CN116303034A

CN116303034A - Automatic test system, method, equipment and medium for network on chip

Info

Publication number: CN116303034A
Application number: CN202310275420.XA
Authority: CN
Inventors: 张晨; 邵海波
Original assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Current assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Priority date: 2023-03-17
Filing date: 2023-03-17
Publication date: 2023-06-23

Abstract

The invention belongs to the field of computers, and particularly relates to an automatic test system, method and equipment readable storage medium of a network on chip. Wherein, the system includes: the basic verification environment module is used for providing a basic verification environment and generating a verification environment of the module to be tested on the basis of the basic verification environment according to the configuration information of the module to be tested; the signal connection module is used for connecting the module to be tested to the verification platform based on the interface information of the module to be tested; the standard test case module is configured to generate a test case based on predetermined parameters of the module to be tested, and execute a test of the module to be tested based on the generated test case. The automatic test system of the network on chip provided by the invention can realize the verification of different modules to be tested by using the same environment, and only the basic environment and the corresponding variables in the basic test case are required to be modified according to the corresponding configuration file. The automatic test can be realized.

Description

Automatic test system, method, equipment and medium for network on chip

Technical Field

The invention belongs to the field of computers, and particularly relates to an automatic test system, method, equipment and readable storage medium of a network on chip.

Background

Along with the increasing complexity of digital systems, many challenges are brought to chip verification work, in order to improve verification efficiency and reduce the risk of degradation of verification quality after work handover, standard verification processes with different sizes and automatic and visual tools are commonly available in the industry to enable the verification work to be more standardized. The NOC (Network on Chip) can realize communication between the modules, and compared with the traditional on-Chip interconnection interface, the NOC has the advantages of good scalability, power consumption, reliability and the like. In the validation process of NOCs, the problems faced are:

1. NOCs are used as on-chip interconnect networks in SoC designs to participate in communication before each module, which also results in that often tens of different types of NOCs are present in the design, which are often configured differently, and involve different address space translations, data path bit widths, etc., which are time consuming if verified individually. How to improve the reusability of test cases is a big problem.

2. On the premise of ensuring the reusability of the test cases, how to test all NOCs in the same verification environment is performed, so that the time spent by verification personnel in building the verification environment is reduced.

3. After the test is completed, how to quickly obtain the system performance and the performance among the ports of the network on chip, and detect and locate the bottleneck of NOC transmission, and reduce the debug time of the verifier is also one of the problems faced.

Therefore, an effective solution is needed to address the above problems.

Disclosure of Invention

In order to solve the above-mentioned problems, the present invention provides an automatic test system for network on chip, comprising:

the basic verification environment module is configured to provide a basic verification environment and generate a verification environment of the module to be tested on the basis of the basic verification environment according to the configuration information of the module to be tested;

the signal connection module is configured to connect the module to be tested to the verification platform based on interface information of the module to be tested;

and the standard test case module is configured to generate a test case based on the preset parameters of the module to be tested and execute the test of the module to be tested based on the generated test case.

In some embodiments of the invention, the system further comprises:

and the data reading module is configured to read the configuration file of the module to be tested and send the content of the read configuration file to each module of the test system.

In some embodiments of the invention, the standard test case module is further configured to:

providing different types of basic test case templates with test variables, and replacing the test variables in the corresponding different types of basic test case templates according to the preset parameters of the module to be tested to form different types of test cases.

In some embodiments of the invention, the system further comprises:

the performance analysis module is configured to count the test result of the module to be tested by the standard test case module, directionally change excitation test data according to a preset strategy according to the test result and feed back the excitation test data to the standard test case module to dynamically simulate the module to be tested.

In some embodiments of the invention, the performance analysis module is further configured to:

and setting the recovery time of the module to be tested according to the test result of the module to be tested in a preset mode, and feeding back the recovery time to the standard test case module to perform dynamic simulation on the module to be tested.

and analyzing specific parameters of the performance of each input/output interface of the module to be tested based on the test result, and outputting the specific parameters to an external file.

In some embodiments of the invention, the system further comprises:

and the performance evaluation module is configured to detect an input/output interface of the module to be tested in real time, respond to the occurrence of transmission blocking of the input/output interface, quickly locate and output a performance bottleneck according to a preset signal.

Another aspect of the present invention also provides a method for automatically testing a network on chip, including:

providing a basic verification environment, and generating a verification environment of the module to be tested on the basis of the basic verification environment according to the configuration information of the module to be tested;

connecting the module to be tested to a verification platform based on interface information of the module to be tested;

and generating a test case based on the preset parameters of the module to be tested, and executing the test of the module to be tested based on the generated test case.

Yet another aspect of the present invention is directed to a computer device comprising:

at least one processor; and

a memory storing computer instructions executable on the processor, which when executed by the processor, perform the steps of the method of any of the above embodiments.

Yet another aspect of the invention also proposes a computer-readable storage medium storing a computer program which, when executed by a processor, implements the steps of the method of any of the above embodiments.

The automatic test system of the network on chip can realize the verification of different modules to be tested by using the same environment, and can realize the automatic test by modifying the basic environment and the corresponding variables in the basic test case according to the corresponding configuration file.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of an automatic test system for network on chip according to an embodiment of the present invention;

fig. 2 is a schematic flow chart of an automatic test method for network on chip according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a computer device according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a computer readable storage medium according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of an implementation of an automatic test system for network on chip according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of an automatic test system for network on chip according to an embodiment of the present invention;

FIG. 7 is a schematic flow chart of a module to be tested accessing a verification platform according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of a performance test flow provided by an embodiment of the present invention;

FIG. 9 is a general verification flow chart of a module to be tested according to an embodiment of the present invention;

fig. 10 is a schematic diagram of interaction of verification environments of modules to be tested according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention will be described in further detail with reference to the accompanying drawings.

The invention aims to solve the problems of low efficiency of a verification test platform or method used in the traditional NOC verification test, as described above, the NOC verification has the problems of various types and numbers of modules, huge test time consumption and low test result analysis efficiency. In order to improve the verification efficiency of the NOC, most of the ways are the reusability of test cases, and the verification environment is also reusable because the interfaces in the NOC are basically universal bus interfaces. After the simulation is completed, the verifier often spends a lot of time performing performance analysis,

as shown in fig. 1, to solve the above-mentioned problems, the present invention provides an automatic test system for network on chip, comprising:

the basic verification environment module 1 is configured to provide a basic verification environment, and generate a verification environment of the module to be tested on the basis of the basic verification environment according to the configuration information of the module to be tested;

a signal connection module 2, the signal connection module 2 being configured to connect a module to be tested to a verification platform based on interface information of the module to be tested;

and the standard test case module 3 is configured to generate a test case based on the preset parameters of the module to be tested, and execute the test of the module to be tested based on the generated test case.

In the invention, the module to be tested is a simulation module of the network on chip to be tested, namely the DUT.

In the invention, a basic verification environment module 1 integrates general environment settings into a basic environment template according to the basic environment template, reserves interfaces for different contents, and perfects the basic environment template according to configuration information of a module to be tested to form a verification environment matched with the module to be tested through the reserved interfaces after determining the module to be tested. When the module to be tested is changed, the configuration file of the module to be tested is directly obtained, and a new verification environment is regenerated based on the basic environment template according to the changed configuration information.

The signal connection module 2 is used for connecting each interface in the module to be tested to the verification platform according to each interface type of the module to be tested and corresponding interface information recorded in the module to be tested configuration file, so as to realize automatic connection of the module to be tested and the verification platform. Namely, the verification environment generated by the basic verification environment module 1 and the simulation corresponding to the module to be tested are connected on the verification platform.

In the embodiment of the invention, a standard test case template for various test mainboards is arranged in a standard test case module 3, parameters related to the test types are formed into a template in a variable mode based on the test types, when the test equipment is used, corresponding test cases are formed by assigning contents, such as address fields, in a configuration file of the module to be tested to corresponding variables, and the test cases are operated on a verification platform, so that verification test of the module to be tested is realized.

In some embodiments of the present invention, the standard test case module 3 provides standard test cases of multiple test types, that is, general parts of the test cases of various types are used as standard test case contents, the contents of the test cases which change with each other according to different modules to be tested are replaced by variables or preset data structures, and after the modules to be tested are determined, the corresponding configuration information is assigned to the corresponding variables according to the configuration information of the modules to be tested, so that the test cases are formed rapidly.

Furthermore, through the basic verification environment module 1 and the standard test case module 3, corresponding test environments and test cases can be quickly established for different modules to be tested, the test cases can be automatically executed, and verification tests of the modules to be tested can be quickly completed.

In some embodiments of the invention, the system further comprises:

and the data reading module 4 is configured to read the configuration file of the module to be tested and send the content of the read configuration file to each module of the test system.

In the embodiment of the present invention, the data reading module 4 is configured to parse a configuration file of a module to be tested, and send information required by an automatic test system of a network on chip provided by the present invention to each module.

In some embodiments of the present invention, the standard test case module 3 is further configured to:

In some embodiments of the invention, the system further comprises:

and the performance analysis module 5 is configured to count the test result of the module to be tested by the standard test case module, directionally change excitation test data according to a preset strategy according to the test result, and feed back the excitation test data to the standard test case module 3 to dynamically simulate the module to be tested.

In some embodiments of the present invention, the performance analysis module 5 is further configured to:

In this embodiment, the performance analysis module 5 is configured to analyze execution results of various cases of the standard test case module 3, adjust excitation data and set recovery time in a desired test case according to the test result, and feed back the adjustment result to the standard test case module 3 for dynamic adjustment to implement dynamic simulation.

Further, the performance analysis module is further configured to output the corresponding analysis result in the form of an analysis report as a corresponding external file.

In some embodiments of the invention, the system further comprises:

and the performance evaluation module 6 is configured to detect an input/output interface of the module to be tested in real time, respond to the occurrence of transmission blocking of the input/output interface, and quickly locate and output a performance bottleneck according to a preset signal.

In this embodiment, the performance evaluation module 6 monitors each input/output interface of the module to be tested, and analyzes the cause of the problem affecting the performance of the input/output interface through the key words of the interface protocol when the corresponding input/output interface is abnormal, such as blocking, so as to help the tester to quickly locate the performance bottleneck.

Examples:

fig. 6 is a schematic diagram of a verification environment composition structure of an automatic test system for network on chip according to an embodiment of the present invention. Comprising the following steps:

the basic authentication environment module 1. In the verification process of the functional module corresponding to the network on chip, a corresponding verification environment is often required to be created according to the function of the DUT. While the interface of the DUT is a generic protocol interface and its main functions are the same. Therefore, a basic verification environment can be created in advance, an input interface is reserved, the reserved input interface is used for acquiring a configuration file through the configuration file reading module, and the corresponding verification environment of the DUT is formed through information such as the number of interfaces, the types of the interfaces, the clock frequency and the like of the DUT in the configuration file. The basic verification environment can improve the reusability of the test environment, and the invention builds the verification environment of the NOC by using UVM.

Standard test case module 3. The basic test case templates for providing various test cases for testing the DUT in a preset structure body mode according to test variables caused by different DUTs in the test cases comprise address conversion test cases, performance analysis test cases and the like. For example, in an address conversion test case, a dynamic array of an address domain space is defined in advance, a start address and a stop address of a DUT before and after conversion are set as variables, the test case only comprises address conversion tests and checks of all address domains, and after simulation is started, the number and the addresses of the address domains are obtained by reading configuration file information, and the test case is supplemented to complete the test. Certain test cases may be selectively added or deleted in the testing of the optional features. For example: in the read-write test, if the NOC is obtained from the configuration file and the interface does not support burst transmission, a test case containing burst transmission is not added.

A signal connection module 2. Because the DUT interface type and number are not fixed, creating a script file automatically accesses the top layer into the VIPs in the environment based on the DUT interface signals. The connection process then connects the DUT interface protocol signals through a regular match. If an undefined signal appears in the matching process, the signal is vacated and then manually perfected, and the flow chart is shown in fig. 7.

A data reading module 4. The data reading module needs to read the content of the configuration file and input the configuration file into the environment before the simulation starts, so as to perfect the information such as VIP, clock, test case and the like in the environment.

And a performance analysis module 5. In the test case, data are sent out and time is calculated under the condition that reading and writing are separated and reading and writing are carried out simultaneously, after the test is finished, the test performance is always needed to be given, time is wasted in manual calculation, log files are printed and are not intuitive enough, therefore, the invention counts the test performance results, and according to whether parameters such as out_of_ order, outstanding and MPS are supported in the environment, whether read-write channels are combined or not and the like, specific parameters of ideal performance of all input and output ports of the network on chip and ideal performance parameters of the whole channel are obtained, the test state of the DUT in the current test scene is obtained through a performance analysis component, the performance results are output in an external file after the test state is compared with the ideal test results, later debugging is facilitated, and a detailed flow chart is shown in FIG. 8.

A performance evaluation component 6. The performance analysis component is used for detecting the network-on-chip key component signals of the component in real time, the performance evaluation component is used for detecting the data input port and the data output port in real time, capturing the key signals when the transmission is blocked, rapidly positioning the performance bottleneck, adaptively changing the input of the test case according to the current scene, and reducing the debugging time of the verification personnel. For example: in the AXI test process, the system bottleneck is positioned by judging which end of the master end or the slave end has the effective signal pulled down first, and input data of the test case is dynamically adjusted. Further, the implementation flow of the present embodiment is shown in fig. 10, which is a flowchart of the implementation of the present invention. The details are as follows:

defining a configuration file: the configuration information includes basic information of the NOC, such as address domain mapping relation, interface number, clock frequency, and other configuration information.

The DUT is connected to the environment. And acquiring the path of the DUT in the environment by adding a file list, and connecting the path of the DUT file into the verification environment preset above according to the interface information of the top layer of the DUT after the script tool acquires the path of the DUT file.

And configuring a verification environment and test cases. In a verification environment, a default emulation mode is typically performed. After the simulation is started, the content of the configuration file defined in the step (1) is read through the DPI-C interface. After the data in the JSON file is obtained, the verification environment is adjusted in response, and preset information is given to the test case, and the JSON file reading in the invention is exemplified, and part of the data reading functions are as follows.

Simulation is completed and the result is derived: the invention establishes JSON file in advance and reserves the content to be filled, and calls C function to write data into external test after the simulation is finished so as to reduce the complexity of writing the data C code.

In summary, as shown in fig. 10, after the simulation starts, the UVM verification environment corresponding to the DUT capable of being dynamically configured selectively sends the data in the configuration file component to the verification case component (to obtain the excitation of the DUT), the verification platform component (to modify the platform configuration), and the performance analysis tool component (to compare results) through the data reading 1, 2, and 3 components, so as to implement the dynamic configuration of the environment. In the performance test process, the performance evaluation component detects the DUT and feeds back the result to the performance test component, and then feeds back to the test case end, and the performance test is dynamically performed, so that the performance parameters of each data port and the whole channel are obtained. And finally, the evaluation result and the actual result are written into an external file through a data writing-out component by a test performance output component.

The automatic test system of the network on chip provided by the invention can realize the following technical effects:

(1) when testing a plurality of DUTs, the same environment test can be simply and efficiently used, the waste of personnel and time caused by repeatedly constructing a verification environment is avoided, and the verification personnel can spend more time on the verification of the test points.

(2) After the test is finished, the test data are uniformly written into an external file, so that a large number of repeated calculation of a verifier is avoided. The verification efficiency is improved.

(3) The data is stored in a more universal mode by using the configuration file and the performance analysis file, so that unified management is facilitated, and the method is also visual enough in the performance analysis process.

(4) In the later maintenance process, the invention is based on UVM, and has good compatibility when being modified, which is almost the same as the traditional verification environment.

As shown in fig. 2, another aspect of the present invention further proposes an automatic test method for a network on chip, including:

step S1, providing a basic verification environment, and generating a verification environment of a module to be tested on the basis of the basic verification environment according to configuration information of the module to be tested;

step S2, connecting the module to be tested to a verification platform based on interface information of the module to be tested;

and S3, generating a test case based on the preset parameters of the module to be tested, and executing the test of the module to be tested based on the generated test case.

In some embodiments of the invention, the method further comprises:

and reading the configuration file of the module to be tested, and sending the content of the read configuration file to each module of the test system.

In some embodiments of the invention, the method further comprises:

and the statistical standard test case module directionally changes excitation test data according to the test result of the module to be tested and a preset strategy, and feeds back the excitation test data to the standard test case module to dynamically simulate the module to be tested.

In some embodiments of the invention, the method further comprises:

and detecting the input/output interface of the module to be tested in real time, responding to the transmission blocking of the input/output interface, and rapidly positioning and outputting the performance bottleneck according to a preset signal.

As shown in fig. 3, a further aspect of the present invention further proposes a computer device, including:

at least one processor 21; and

a memory 22, said memory 22 storing computer instructions 23 executable on said processor 21, said instructions 23 when executed by said processor 21 implementing a network-on-chip automatic test method comprising:

As shown in fig. 4, still another aspect of the present invention further proposes a computer readable storage medium 401, the computer readable storage medium 401 storing a computer program 402, the computer program 402 when executed by a processor implementing a method for automatically testing a network on chip, including:

Finally, it should be noted that, as will be appreciated by those skilled in the art, all or part of the procedures in implementing the methods of the embodiments described above may be implemented by a computer program for instructing relevant hardware, where the program may be stored in a computer readable storage medium, and the program may include the procedures of the embodiments of the methods described above when executed. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), a random-access memory (RAM), or the like. Embodiments of the computer program may achieve the same or similar effects as any of the method embodiments previously described.

In addition, typically, the devices, apparatuses and the like disclosed in the embodiments of the present invention may be various electronic terminal apparatuses, for example, mobile phones, personal Digital Assistants (PDAs), tablet computers (PADs), smart televisions, and the like, and may also be large-sized terminal apparatuses, for example, servers, etc., so the protection scope disclosed in the embodiments of the present invention should not be limited to a specific type of devices, apparatuses and the like. The client disclosed by the embodiment of the invention can be applied to any one of the electronic terminal devices in the form of electronic hardware, computer software or a combination of the electronic hardware and the computer software.

Furthermore, the method disclosed according to the embodiment of the present invention may also be implemented as a computer program executed by a CPU, which may be stored in a computer-readable storage medium. When executed by a CPU, performs the functions defined above in the methods disclosed in the embodiments of the present invention.

Furthermore, the above-described method steps and system units may also be implemented using a controller and a computer-readable storage medium storing a computer program for causing the controller to implement the above-described steps or unit functions.

Further, it should be appreciated that the computer-readable storage medium (e.g., memory) described herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. By way of example, and not limitation, nonvolatile memory can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM), which acts as external cache memory. By way of example, and not limitation, RAM may be available in a variety of forms such as synchronous RAM (DRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The storage devices of the disclosed aspects are intended to comprise, without being limited to, these and other suitable types of memory.

Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

The various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein may be implemented or performed with the following components designed to perform the functions described herein: a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP and/or any other such configuration.

The steps of a method or algorithm described in connection with the disclosure herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.

In one or more exemplary designs, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one location to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a general purpose or special purpose computer or general purpose or special purpose processor. Further, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, digital Versatile Disc (DVD), floppy disk, blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

Claims

1. An automatic test system for a network on chip, comprising:

2. The system of claim 1, further comprising:

3. The system of claim 1, wherein the standard test case module is further configured to:

4. The system of claim 1, further comprising:

5. The system of claim 4, wherein the performance analysis module is further configured to:

6. The system of claim 4, wherein the performance analysis module is further configured to:

7. The system of claim 1, further comprising:

8. An automatic test method for a network on chip, comprising:

9. A computer device, comprising:

at least one processor; and

a memory storing computer instructions executable on the processor, which when executed by the processor, perform the steps of the method of claim 8.

10. A computer readable storage medium storing a computer program which, when executed by a processor, implements the steps of the method of claim 8.