CN102385547A - Method and system for verifying timing sequence calibration function of dynamic random access memory (DRAM) controller - Google Patents
Method and system for verifying timing sequence calibration function of dynamic random access memory (DRAM) controller Download PDFInfo
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Abstract
The invention is applied to the technical field of electronics, which provides a method and a system for verifying a timing sequence calibration function of a dynamic random access memory (DRAM) controller. The method comprises steps of performing static delay according to preset static delay value which is random value or traverse value in designated range; generating a test case event describing operations executed by a data transmission bus connected with the DRAM controller; generating a control event according to the test case event; monitoring and obtaining a monitoring event which includes an order part and a data part; and obtaining accurate timing sequence calibration of the DRAM controller when the order part and the data part in the monitoring event are respectively identical with an order part and a data part in the control event. By means of the preset static delay value generated in random or traversal mode in the designated range, the timing sequence calibration function of the DRAM controller is verified, thereby achieving the purpose of verifying the timing sequence calibration function as comprehensive as possible and obtaining complete verification.
Description
Technical field
The invention belongs to electronic technology field, relate in particular to a kind of verification method and system of dram controller timing verification function.
Background technology
Development along with the processor technology; Front Side Bus to memory bandwidth require increasingly high, therefore also just increasingly high for the frequency requirement of internal memory, when clocked memory improves; Obtain to stablize proper data and just must the sequential of coherent signal carry out stricter control when reading and writing data; Because the uncertain time delay of sequential of static state possibly cause the data write mistake, when internally depositing into capable write operation when bus frequency is higher; The sequential of coherent signal is by dynamic RAM (Dynamic random access memory; DRAM) controller produces, and need not carry out the verification operation of static time delay to coherent signal, so the static time delay verification operation of coherent signal mainly is when read data, to carry out.
Verifying function mainly is the uncertain time delay of sequential of removing the static state on the mainboard; Whether the timing verification operation to dram controller correctly is on the mainboard of reality, to debug checking at present; If on the actual mainboard behind the timing verification EO; Dram controller can normal read-write, but then thinks timing verification function correct execution.But in practical application, the mainboard situation has nothing in common with each other, can't with the mainboard that might use all test fully, so the situation coverage rate of actual verification is very low.
Summary of the invention
The purpose of the embodiment of the invention is to provide a kind of verification method of dram controller timing verification function; Be intended to solve that the mainboard situation has nothing in common with each other in the practical application of prior art; Can't with the mainboard that might use all test fully, so the very low problem of situation coverage rate of actual verification.
The embodiment of the invention is achieved in that a kind of verification method of dram controller timing verification function, and said method comprises the steps:
Carry out static time delay by preset static time delay value, said static time delay value is random value or the traversal value in specified scope;
The generation test case affairs that performed operation is described to the data transmission bus that is connected with dram controller;
According to said test case affairs, produce control affairs, said control affairs comprises command component and data division;
The monitoring affairs are obtained in monitoring, and said monitoring affairs comprise command component and data division;
Command component and the data division of said control affairs with the monitoring affairs compared; When the command component in the said monitoring affairs and data division respectively with said control affairs in command component when identical with data division, then the dram controller timing verification is correct.
The embodiment of the invention also provides a kind of verification system of dram controller timing verification function, and said system comprises DRAM unit, time delay unit, test case generation unit, driver element, dram controller, monitoring means and the unit of keeping the score:
Said time delay unit, each that is used for the strobe pulse of the data line of DRAM interface and data line is carried out static time-delay according to preset static time delay value, and said static time delay value is random value or the traversal value in specified scope;
Said test case generation unit is used to produce to the data transmission bus that is connected with dram controller performed operation and describes the test case affairs;
Said driver element; Be used for test case affairs,, and produce control affairs to said dram controller transmitting control commands according to the test case generation unit generation that receives; And to the said unit transmission control affairs of keeping the score, said control affairs comprises command component and data division;
Said dram controller is used to receive the control command of said driver element, and according to said order said DRAM unit is operated accordingly;
Said monitoring means; Be used for obtaining the command component that said dram controller sends to the DRAM unit through monitoring said data transmission bus; And according to the operation address in the order; The data division of the monitoring affairs that obtain in the corresponding address from said DRAM unit, and said monitoring affairs are sent to the unit of keeping the score;
The said unit of keeping the score is used to receive control affairs and the said monitoring means transmitting supervisory affairs that said driver element sends, and said control affairs and the command component and the data division of monitoring in the affairs are compared.
In embodiments of the present invention; Through the static time delay value of the generation that perhaps in specified scope, travels through at random in specified scope; And then dram controller timing verification function verified reached the purpose of as far as possible comprehensively verifying verifying function, checking fully.
Description of drawings
Fig. 1 is the process flow diagram of realization of the verification method of the dram controller timing verification function that provides of the embodiment of the invention one;
Fig. 2 is the process flow diagram of realization of the verification method of the dram controller timing verification function that provides of the embodiment of the invention two;
Fig. 3 is the structural drawing of the verification system of the dram controller timing verification function that provides of the embodiment of the invention.
Embodiment
In order to make the object of the invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with accompanying drawing and embodiment.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
In embodiments of the present invention, through be created in the specified scope at random or travel through static time delay value, dram controller timing verification function is verified, reached the purpose of as far as possible comprehensively verifying verifying function.
The embodiment of the invention provides a kind of verification method of dram controller timing verification function, and said method comprises the steps:
Carry out static time delay by preset static time delay value, said static time delay value is random value or the traversal value in specified scope;
The generation test case affairs that performed operation is described to the data transmission bus that is connected with dram controller;
According to said test case affairs, produce control affairs, said control affairs comprises command component and data division;
The monitoring affairs are obtained in monitoring, and said monitoring affairs comprise command component and data division;
Command component and the data division of said control affairs with the monitoring affairs compared; When the command component in the said monitoring affairs and data division respectively with said control affairs in command component when identical with data division, then the dram controller timing verification is correct.
The embodiment of the invention also provides a kind of verification system of dram controller timing verification function, and said system comprises DRAM unit, time delay unit, test case generation unit, driver element, dram controller, monitoring means and the unit of keeping the score:
Said time delay unit, each that is used for the strobe pulse of the data line of DRAM interface and data line is carried out static time-delay according to preset static time delay value, and said static time delay value is random value or the traversal value in specified scope;
Said test case generation unit is used to produce the test case affairs that performed operation is described to the data transmission bus that is connected with dram controller;
Said driver element; Be used for test case affairs,, and produce control affairs to said dram controller transmitting control commands according to the test case generation unit generation that receives; And to the said unit transmission control affairs of keeping the score, said control affairs comprises command component and data division;
Said dram controller is used to receive the control command of said driver element, and according to said order said DRAM unit is operated accordingly;
Said monitoring means; Be used for obtaining the command component that said dram controller sends to the DRAM unit through monitoring said data transmission bus; And according to the operation address in the order; The data division of the monitoring affairs that obtain in the corresponding address from said DRAM unit, and said monitoring affairs are sent to the unit of keeping the score;
The said unit of keeping the score is used to receive control affairs and the said monitoring means transmitting supervisory affairs that said driver element sends, and said control affairs and the command component and the data division of monitoring in the affairs are compared.
Below in conjunction with specific embodiment realization of the present invention is described in detail:
Embodiment one
Fig. 1 shows the verification method of the dram controller timing verification function that the embodiment of the invention one provides, and this method comprises the steps:
In step S101, carry out static time delay by preset static time delay value, this static state time delay value is random value or the traversal value in specified scope.
In step S102, produce the test case affairs that performed operation is described to the data transmission bus that is connected with dram controller.
In embodiments of the present invention, bus comprises register bus and data transmission bus.
In embodiments of the present invention, each test case affairs all comprises order and data two parts, and the operation that is used to describe this bus is read or write, and how many addresses of read-write is etc.
In step S103, according to above-mentioned test case affairs, produce control affairs, this control affairs comprises command component and data division.
In step S104, the monitoring affairs are obtained in monitoring, and these monitoring affairs comprise command component and data division.
In step S105; Command component and the data division of control affairs with the monitoring affairs compared; When the command component in the above-mentioned monitoring affairs and data division respectively with above-mentioned control affairs in command component when identical with data division, then the dram controller timing verification is correct.
In embodiments of the present invention, through carrying out static time delay by preset static time delay value, static time delay value is random value or the traversal value in specified scope; And produce control affairs and monitoring affairs, thereby command component and the data division of control affairs with the monitoring affairs compared, the command component in monitoring affairs and data division respectively with control affairs in command component when identical with data division; Then the dram controller timing verification is correct; Reached the purpose of full test verifying function as far as possible, verify very abundant, in addition; The operation of timing verification operation and reading and writing data all can contrast automatically, and is simple and convenient.
Embodiment two
Fig. 2 shows the verification method of the dram controller timing verification function that the embodiment of the invention two provides, and this method comprises the steps:
In step S201, produce the static time delay value that is provided with in advance.
In step S202, carry out static time delay by preset static time delay value, this static state time delay value is random value or the traversal value in specified scope.
In step S203, start the timing verification operation of dram controller, whether the operation of monitoring timing verification correctly finishes.
In step S204, when correct end of monitoring timing verification operation, produce the test case affairs that performed operation is described to the data transmission bus that is connected with dram controller.
In step S205, according to the test case affairs, produce control affairs, control affairs comprises command component and data division.
In embodiments of the present invention; When the test case affairs are write operation; The test case affairs directly as control affairs, when the test case affairs are read operation, are combined as control affairs with the command component in the test case affairs with by the data that data transmission bus is read.
In step S206, the monitoring affairs are obtained in monitoring, and these monitoring affairs comprise command component and data division.
In step S207; Command component and the data division of control affairs with the monitoring affairs compared; When the command component in the above-mentioned monitoring affairs and data division respectively with above-mentioned control affairs in command component when identical with data division, then the dram controller timing verification is correct.
In embodiments of the present invention, when the dram controller verification operation correctly finishes, begin to verify whether verification operation is correct, improve the accuracy of checking.
Embodiment three
Fig. 3 shows the verification system of the dram controller timing verification function that the embodiment of the invention provides, and this system comprises: time delay unit 31, test case generation unit 32, driver element 33, dram controller 34, monitoring means 35, keep the score unit 36 and DRAM unit 37.
Each of the data line in the 31 pairs of DRAM interfaces in time delay unit and the strobe pulse of data line is carried out static time-delay according to preset static time delay value, and this static state time delay value is random value or the traversal value in specified scope.
Test case generation unit 32 produces the test case affairs that the performed operation of data transmission bus that is connected with dram controller 34 is described.
In embodiments of the present invention, be connected through bus between driver element 33 and the dram controller 34, this bus comprises register bus and data transmission bus.
In embodiments of the present invention; Each test case affairs all comprises order and data two parts, and the test case affairs are the descriptions to the performed operation of the data transmission bus that is connected with dram controller, for example; The operation that can describe this bus is read or is write, and how many addresses of read-write is etc.
The test case affairs that driver element 33 produces according to the test case generation unit that receives 32; To dram controller 34 transmitting control commands; And produce control affairs, and send control affairs to the unit 36 of keeping the score, this control affairs comprises command component and data division.
In embodiments of the present invention, if when the test case affairs that driver element 33 receives are write operation, driver element 33 can directly send to the unit 36 of keeping the score as control affairs with the test case affairs.
When if the test case affairs that driver element 33 receives are read operation, driver element 33 can combine to be transferred to the unit 36 of keeping the score as control affairs with the command component in the test case affairs with by the data that data transmission bus is read.
In embodiments of the present invention; Driver element 33 is through the register of the register bus configuration dram controller 34 of dram controller 34; Start the timing verification operation of dram controller 34; Monitoring means 35 is through reading the register of dram controller 34 at this moment, and whether the operation of monitoring timing verification correctly finishes.
After the correct end of sequential verification operation; Monitoring means 35 obtains the command component that dram controller 34 sends to DRAM unit 37 through the Monitoring Data transfer bus; And according to the operation address in the order; Obtain the data division of monitoring affairs in the corresponding address from DRAM unit 37, and said monitoring affairs are sent to the unit 36 of keeping the score.
Keep the score unit 36 receives the monitoring affairs that control affairs that driver elements 33 send and monitoring means 35 send, and above-mentioned control affairs and command component and data division in the monitoring affairs are compared.
In embodiments of the present invention; Through adding a time delay unit at the DRAM interface; Be created in the specified scope at random or the time delay value of the static state that produces of traversal; And produce control affairs through driver element and obtain the monitoring affairs with monitoring means, command component and the data division of control affairs with the monitoring affairs compared, the command component in monitoring affairs and data division respectively with control affairs in command component when identical with data division; Then the dram controller timing verification is correct, and the purpose checking that has reached full test verifying function as far as possible is very abundant.In addition, the operation of verification operation and reading and writing data all can contrast automatically, and is simple and be easy to debugging, and further, when verifying function need adjust in the chip of back, the verification environment need not to do any change, verification method portable good.
Embodiment four
In embodiments of the present invention, can also in the verification system of the dram controller timing verification function among the embodiment three, increase time delay generator 38, time delay generator 38 produces static time delay value, and is transferred to time delay unit 31.
The static time delay that time delay unit 31 produces according to time delay generator 38 is carried out the time-delay of static state to each of the strobe pulse of the data line in the DRAM interface and data line.
In embodiments of the present invention, write static time delay value to time delay unit 31 through time delay generator 38, very convenient.
To sum up; Through carrying out static time delay by preset static time delay value; Static time delay value is random value or traversal value in specified scope, and produces control affairs and monitoring affairs, thereby command component and the data division of control affairs with the monitoring affairs compared; When the command component of monitoring in the affairs and data division respectively with control affairs in command component when identical with data division; Then dram controller timing verification function is correct, has reached the purpose of full test verifying function as far as possible, verifies very abundant.In addition, the operation of verification operation and reading and writing data all can contrast automatically, and is simple and convenient.
The above is merely preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of within spirit of the present invention and principle, being done, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1. the verification method of a dram controller timing verification function is characterized in that, said method comprises the steps:
Carry out static time delay by preset static time delay value, said static time delay value is random value or the traversal value in specified scope;
The generation test case affairs that performed operation is described to the data transmission bus that is connected with dram controller;
According to said test case affairs, produce control affairs, said control affairs comprises command component and data division;
The monitoring affairs are obtained in monitoring, and said monitoring affairs comprise command component and data division;
Command component and the data division of said control affairs with the monitoring affairs compared; When the command component in the said monitoring affairs and data division respectively with said control affairs in command component when identical with data division, then the timing verification of dram controller is correct.
2. the method for claim 1 is characterized in that, also comprises the steps: before the step of the said generation test case affairs that performed operation is described to the data transmission bus that is connected with dram controller
Start the timing verification operation of dram controller, monitor said timing verification operation and whether correctly finish, when correct end of monitoring timing verification operation, carry out the step of the test case affairs of said description.
3. the method for claim 1 is characterized in that, and is said according to said test case affairs, and the step that produces control affairs specifically comprises:
When the test case affairs are write operation, with the test case affairs directly as control affairs;
When the test case affairs are read operation, combine as control affairs with the command component in the test case affairs with by the data that data transmission bus is read.
4. the method for claim 1 is characterized in that, also comprises the steps: before the step of the static time delay value of said generation
Produce the static time delay value that is provided with in advance.
5. the verification system of a dram controller timing verification function is characterized in that, said system comprises time delay unit, test case generation unit, driver element, dram controller, monitoring means, keep the score unit and DRAM unit:
Said time delay unit is used for that each of the strobe pulse of the data line of DRAM interface and data line is carried out static state according to preset static time delay value and delays time, and said static time delay value is random value or the traversal value in specified scope;
Said test case generation unit is used to produce the test case affairs that the performed operation of data transmission bus that is connected with said dram controller is described;
Said driver element; Be used for test case affairs,, and produce control affairs to said dram controller transmitting control commands according to the test case generation unit generation that receives; And to the said unit transmission control affairs of keeping the score, said control affairs comprises command component and data division;
Said dram controller is used to receive the control command of said driver element, and according to said order said DRAM unit is operated accordingly;
Said monitoring means; Be used for obtaining the command component that said dram controller sends to the DRAM unit through monitoring said data transmission bus; And according to the operation address in the order; Obtain the data division of monitoring affairs in the corresponding address from said DRAM unit, and said monitoring affairs are sent to the unit of keeping the score;
The said unit of keeping the score is used to receive control affairs and the said monitoring means transmitting supervisory affairs that said driver element sends, and said control affairs and the command component and the data division of monitoring in the affairs are compared.
6. system as claimed in claim 5 is characterized in that said system also comprises the time delay generator, is used to produce static time delay value, and is transferred to said time delay unit.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106383762A (en) * | 2016-08-31 | 2017-02-08 | 西安紫光国芯半导体有限公司 | Verification method used for DRAM (Dynamic Random Access Memory) controller |
| CN109960616A (en) * | 2017-12-22 | 2019-07-02 | 龙芯中科技术有限公司 | The adjustment method and system of processor-based memory parameters |
| CN111367569A (en) * | 2018-12-26 | 2020-07-03 | 合肥杰发科技有限公司 | Memory calibration system and method and readable storage medium |
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| CN101118788A (en) * | 2007-07-19 | 2008-02-06 | 中兴通讯股份有限公司 | Memory controller automatization testing method and apparatus |
| CN101458971A (en) * | 2008-12-02 | 2009-06-17 | 炬力集成电路设计有限公司 | Test system and method for built-in memory |
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| CN1767072A (en) * | 2004-09-09 | 2006-05-03 | 三星电子株式会社 | Error detecting memory module and method |
| CN101118788A (en) * | 2007-07-19 | 2008-02-06 | 中兴通讯股份有限公司 | Memory controller automatization testing method and apparatus |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106383762A (en) * | 2016-08-31 | 2017-02-08 | 西安紫光国芯半导体有限公司 | Verification method used for DRAM (Dynamic Random Access Memory) controller |
| CN106383762B (en) * | 2016-08-31 | 2019-01-15 | 西安紫光国芯半导体有限公司 | A kind of verification method for dram controller |
| CN109960616A (en) * | 2017-12-22 | 2019-07-02 | 龙芯中科技术有限公司 | The adjustment method and system of processor-based memory parameters |
| CN111367569A (en) * | 2018-12-26 | 2020-07-03 | 合肥杰发科技有限公司 | Memory calibration system and method and readable storage medium |
| CN111367569B (en) * | 2018-12-26 | 2023-04-28 | 合肥杰发科技有限公司 | Memory calibration system and method and readable storage medium |
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