CN101118788A - Memory controller automatization testing method and apparatus - Google Patents
Memory controller automatization testing method and apparatus Download PDFInfo
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Abstract
The present invention discloses a method and a device for testing the automation of a memory and a controller, and the method includes the steps as follows. Firstly, memory models are set up; series numbers are distributed to a variety of memories; and the parameters of each memory is cleared up; secondly, the types and the parameter of the memory can be selected through checking on the current supportive types and serial numbers of memories; through the configuration of an exchange bus and checking on the current configurations of the exchange bus, the parameters of the memory are transmitted to the exchange bus; last, considering the selected types of memory, the requisite initialization and the testing samples are executed to complete the test on current configurations of the memory. The present invention overcomes the shortcoming of the prior art in difficult realization of full coverage in the testing of a SOC storage system; realizes the automatic test on the storage system; saves the workload of a testing coding; and improves the testing efficiency.
Description
Technical field
The present invention relates to the Memory Controller field, relate in particular to a kind of memory controller automatization testing method and device.
Background technology
The target of SOC (System on Chip, embedded system) chip design at present is more special-purpose, is not general.Its requires just to share, minimum cost cost, the highest integrated level.With it be the product of core therefore will be can faster listing, the cost reason is low, function is abundanter, volume is littler, power consumption is lower.
The hardware components of SOC comprises processor/microprocessor, storer and external device and I/O port, graphics controller etc.Embedded system is different from general computer processing system, and it does not possess jumbo storage medium as hard disk.Software section comprises operating system software (requiring in real time and multi-job operation) and application programming.Application program is being controlled the running and the behavior of system; And operating system is being controlled the reciprocation of application programming and hardware.
SOC (System on Chip, embedded system) generally has Memory Controller in the chip design, to support the storer of polytype and configuration, typical storage class has SDRAM (synchronous DRAM), DDR SDRAM (Double Data Rate synchronous DRAM), NAND FLASH (Sheffer stroke gate flash memory), NOR FLASH (rejection gate flash memory), SRAM (static RAM) etc.With the SDRAM chip below the 512Mb capacity, commercial chip type is above tens of kinds.
Suppose that a chip supports the choosing of 4 DRAM (dynamic RAM) sheet, and support the SDRAM chips of 30 kinds of dissimilar and configurations,, want structure at least for the function of verifying memory controller intactly
Individual test case is in order to cover, and the complexity of the coding that brings, debugging and test is unacceptable, and is not easy to realize test automation and test result statistics.
In sum, a kind of technical scheme that solves the memory controller automatization test of current needs.
Summary of the invention
Technical matters to be solved by this invention provides a kind of memory controller automatization testing method and device, has overcome the shortcoming that all standing is difficult to realize in the SOC storage system test of the prior art, realizes the robotization of storage system test.
In order to address the above problem, the invention provides a kind of memory controller automatization proving installation, it is characterized in that, comprise, switch fabric module, type of memory module, configuration interface, query interface, wherein,
Switch fabric module is used for memory bus to the exchange of the connection between the type of memory module;
The type of memory module, the parameter that is used to store test case, numbering and the storer of various memory emulation models;
Configuration interface is used to dispose described switch fabric module, and to the inspection of the current configuration of described switch fabric module;
Query interface is used for the parameter of all storeies of current support and the inquiry of numbering, and to the inquiry of the configuration parameter of switch fabric module;
Select the parameter of storage class and storer by described query interface, and the storage class selected and the parameter of storer are issued to described switch fabric module by described configuration interface, carry out required initialization and test case at the storage class of selecting, carry out the test of storer.
Further, said apparatus also can comprise, described switch fabric module comprises switching matrix configuration parameter module, the configuration that described switching matrix configuration parameter module is used to deposit current switch fabric module comprises validity check result, the switching bus ready state of the configuration of the quantity of memory bus, every memory bus, current configuration;
In the described type of memory module, all corresponding independently described numbering of the storer of each type;
The described scope of examination of described configuration interface comprises described numbering, highway width, addressing range, mapping conflict, address conflict, the type comflict of every memory bus correspondence.
Further, said apparatus can comprise that also described configuration interface comprises configuration read-write interface, configuration parameter inspection module, switching matrix repository, configuration handshake module, error handling processing module, wherein,
Dispose read-write interface, be used for the interface of described proving installation and software section, by described configuration read-write interface, software is realized control and the monitoring to described proving installation;
Configuration parameter is checked module, is used for described proving installation to joining the validity checking of parameter under the software;
The switching matrix repository is used to write down the parameter list of all memory models of the current support of described proving installation;
The configuration handshake module is used for auxiliary described proving installation and finishes the various synchronous of described configuration read-write interface;
The error handling processing module is used for being responsible for catching the various mistakes that the parameter process of issuing occurs, and concentrates and to report described proving installation.
Further, said apparatus can comprise that also described configuration parameter checks that module comprises, test macro status checking module, model existence are checked module, model parameter validity check module, model collaborative work inspection module, wherein,
Test macro status checking module is used for being responsible for the self check of described proving installation, checks whether described proving installation is ready;
Whether the model existence checks module to be used for checking whether the memory model to issuing the parameter appointment is that described proving installation is supported, necessary being in described proving installation;
Model parameter validity check module is used to be responsible for finish and plants the inspection that model issues the other parts of parameter to single, comprises whether various parameters cross the border, whether collaborative work between the parameter;
Module is checked in the model collaborative work, and whether collaborative work is checked to be used for being responsible for multiple model to issuing.
Further, said apparatus also can comprise, described configuration handshake module, and the complexity according to described proving installation support memory model adopts different Handshake Protocols to realize synchronously.
Further, said apparatus also can comprise, also comprises the read-write interface of described configuration interface and described query interface, is used for the read-write operation of described configuration interface and described query interface; The mechanism that the configuration of described configuration interface and described query interface is shaken hands by asynchronous interlocking realizes.
Further, said apparatus can comprise that also described configuration handshake module adopts two semaphores to realize that interlocking is synchronous;
The read-write interface of described configuration interface and described query interface comprises PLI/VPI/DPI interface or the proprietary interface of eda tool.
The present invention also provides a kind of method of memory controller automatization test, may further comprise the steps,
A, to the storer modeling, be various types of memory allocation numberings, the parameter of putting each storer in order;
B, the type and the numbering of storer by the current support of inquiry, the type of selection memory and the parameter of storer, and, and to the inspection of the configuration of current switching bus, the parameter of described storer is issued to described switching bus by the configuration switching bus;
C, at the type of the storer of selecting, carry out required initialization and test case, finish test to the storer of current configuration.
Further, said method also can comprise, among the described step a, also comprises the configuration parameter of the memory bus that the current chip of arrangement is supported;
The described of various types of memory allocation is numbered independently;
The parameter of described storer comprises storage class, accessing time sequence parameter, row address width, column address width, bank number, access mode, capacity, type of bus protocol, frequency of operation;
The configuration parameter of memory bus comprises bus number, addressing space, accessing time sequence parameter, access mode.
Further, said method also can comprise, further comprise among the described step b,
Whether ready, if do not have readyly, then wait for if inquiring about described switching bus;
Otherwise, inquire about the current configuration of described switching bus and whether make a mistake, if then carry out described step b or stop test; Otherwise, execution in step c.
Compared with prior art, use the method for the invention and device, reached the test automation effect, saved test coding work amount, improved testing efficiency.
Description of drawings
Fig. 1 is the system chart of memory controller automatization proving installation in the specific embodiment of the invention;
Fig. 2 is the process flow diagram of memory controller automatization testing method in the specific embodiment of the invention;
Fig. 3 is the functional block diagram of the switching matrix of memory controller automatization proving installation in the specific embodiment of the invention;
Fig. 4 is the functional block diagram of the configuration interface of memory controller automatization proving installation in the specific embodiment of the invention;
Fig. 5 is the system chart of the instantiation of memory controller automatization proving installation in the specific embodiment of the invention.
Embodiment
Below in conjunction with accompanying drawing the specific embodiment of the invention is described further.
The specific embodiment of the invention is mainly used in the RTL prototype verification of digital IC design field, especially has the large-scale Design of Digital Circuit of storage system, as SOC system etc.
As shown in Figure 1, the memory controller automatization proving installation comprises switch fabric module, type of memory module, configuration interface, query interface in the specific embodiment of the invention, wherein,
The quantity of the memory bus of user's definable correspondence.
Type of memory module 104, the parameter that is used to store test case, numbering and the storer of various memory emulation models;
In order to distinguish dissimilar storeies, all corresponding one of the storer of each type is independently numbered; The parameter of storer comprises time sequence parameter and bus parameter etc.
The described scope of examination comprises described numbering, highway width, addressing range, mapping conflict, address conflict, type comflict of every memory bus correspondence etc.
Select the parameter of storage class and storer by described query interface, and the storage class selected and the parameter of storer are issued to described switch fabric module by described configuration interface, carry out required initialization and test case at the storage class of selecting, carry out the test of storer.
Core algorithm in the specific embodiment of the invention is all type of memory and the memory bus configuration of supporting by the current proving installation of real-time inquiry, by directly or ergodic algorithm at random storer various be configured into the action attitudes switch and test, thereby reach automatic test, increase the purpose of testing efficiency.
The method of memory controller automatization test may further comprise the steps in the specific embodiment of the invention that Fig. 2 describes,
Being numbered independently of every type memory allocation.
The parameter of storer comprises storage class, accessing time sequence parameter, row address width, column address width, BANK (memory bank) quantity, access mode, capacity, type of bus protocol, frequency of operation etc.
The configuration parameter of memory bus comprises bus number, addressing space, accessing time sequence parameter, access mode etc.
By above operation, finish the structure proving installation.
The type and the numbering of the storer by inquiring about current support are selected the type and the configuration thereof of suitable storer.
Whether step 130, inquiry switching bus be ready, if do not have readyly, then waits for execution in step 130; Otherwise, execution in step 140;
Whether step 140, the current configuration of the described switching bus of inquiry make a mistake, if then execution in step 120, otherwise, execution in step 150;
Issue configuration and make a mistake, then can execution in step 120, or stop test.
Whether step 150, inquiry switching bus be ready, if do not have readyly, then waits for execution in step 150; Otherwise, execution in step 160;
The configuration of the storer that step 170, statistics have covered, execution in step 120.
Adopt suitable algorithm to add up the configuration of the storer that has covered.
Select to stop test or continue test according to overlay strategy, if select to continue test, then execution in step 120.
The invention will be further described below in conjunction with instantiation.
The building process of hardware components is as follows:
The first step as shown in Figure 4, makes up the type of memory module;
According to concrete needs, select various memory emulation models.Generally can adopt DENALI model, producer's model or oneself coding to create;
Put bus configuration, time sequence parameter and the internal register configuration information of various models in order.Typical bus configuration generally comprises: the memory data bus width (is counted with bit, common has 8,16,32,64 etc.), the memory bus addressable capacity (is counted with byte, common have a 256KB, 512KB, 2MB, 16MB, 32MB, 64MB etc.), the storage chip data-bus width (is counted with bit, common has 4,8,16,32 etc.), (with byte counting, common have a 256KB to the storage chip capacity, 512KB, 2MB, 16MB, 32MB, 64MB etc.), storage class is (as SDRAM, DDR SDRAM, NAND Flash, NOR Flash etc.), power consumption model is (as Low Power, High Performance etc.) etc.;
Time sequence parameter comprises the crucial accessing time sequence parameter of storage chip, and generally arranged key signal Time Created, key signal retention time, bus direction of transfer flip-flop transition etc.With SDRAM is example, crucial accessing time sequence parameter comprises that RAS postpones (can obtain from the chip handbook), CAS and postpones (can obtain from the chip handbook, common have 1,2,2.5,3 etc.), precharge delay (can obtain from the chip handbook), refresh delay (common have 32ms, 64ms etc.), operating frequency range etc.;
The internal register configuration information comprises the explanation of the configurable value of storage chip internal register.With SDRAM is example, the burst-length/type that generally has the CAS of support to postpone, supports, support write operation type, support low-power consumption characteristic etc.
In second step, as shown in Figure 3, make up switch fabric module;
A kind of mode that switch fabric module is realized is that each storage class is carried out bus reconstruct, for the part that does not need reconstruct, can be directly connected on the corresponding memory model, as data bus, clock etc.; For the bus that needs reconstruct, need be to each part of bus, as BANK control, address wire, clock enable, sheet choosing etc., carry out corresponding reconstruct according to current configuration.
As shown in Figure 4, switch fabric module 401 comprises switching matrix configuration parameter module;
Switching matrix configuration parameter module is used for the temporary of various information that switch fabric module need realize that Fig. 3 reconstruct is required, realizes going up and can adopt Verilog array (simple information) or VPI to expand (complex information).
In the 3rd step,, make up configuration interface as Fig. 4, shown in Figure 5;
Configuration interface comprises configuration read-write interface 301, configuration parameter inspection module 302, switching matrix repository 307, configuration handshake module 308, error handling processing module 309.
Dispose read-write interface 301, be used to realize the interface of proving installation and software section, by configuration read-write interface 301, software can be realized control and the monitoring to device; Generally can adopt VPI to realize, also can adopt the proprietary interface of eda tool to realize that what adopt among the embodiment is TB MEM interface 402, the configuration read-write interface also is the basic component part of query interface 404;
Configuration parameter is checked module 302, be used for proving installation to joining the validity checking of parameter under the software, comprising, test macro status checking module 303, model existence are checked module 304, model parameter validity check module 305, model collaborative work inspection module 306;
Test macro status checking module 303 is used for being responsible for the self check of proving installation, checks whether described proving installation is ready available; Whether the model existence checks module 304 to be used for checking whether the memory model to issuing the parameter appointment is that device is supported, necessary being in device; Whether model parameter validity check module 305 is used to be responsible for finish and plants the inspection that model issues the other parts of parameter to single, comprises whether various parameters cross the border, can collaborative work between the parameter etc.; Module 306 is checked in the model collaborative work, is used for being responsible for whether the multiple model that issues can be checked in collaborative work.
Error handling processing module 309 is used for being responsible for catching the various mistakes that the parameter process of issuing occurs, and concentrates and to report described proving installation.
In the 4th step, as shown in Figure 4, make up query interface 404.
The read-write interface of configuration interface 403 and query interface 404 is used for the read-write operation of described configuration interface and described query interface, can adopt the PLI/VPI/DPI interface to realize, also can adopt the proprietary interface of eda tool, as TB MEM interface 402 etc.; The configuration of configuration interface 403 and query interface 404 is shaken hands and can be adopted the mechanism of asynchronous interlocking to realize.
Software section is described is use to this proving installation, its employed various parameters all should keep with hardware components in list consistent, a kind of possible software processes step is as follows:
Step 600, obtain the storage class of the current support of proving installation and all kinds of parameters of each storage class, comprise bus configuration, time sequence parameter, running parameter etc. by query interface;
Step 610, select the suitable storage class and the stored parameter of storer, and by configuration interface with configuration distributing to switch fabric module, typical configuration comprises: storage class, capacity, highway width, time sequence parameter, type of bus protocol, frequency of operation etc.;
Whether step 620, proving installation inspection issue configuration legal, if illegal, then notify the test control program reason of makeing mistakes, and wait for new configuration; If legal, then switching matrix is switched to corresponding duty, and notice test control program proving installation is ready, execution in step 630;
Step 630, test control program are carried out required initialization and test case at the storage class of selecting;
The storage class that step 640, test control program will have been selected places sleep pattern (storer as for the DRAM type then is configured to self-refresh mode with them);
Step 650, as required, execution in step 600 or withdraw from test.
The above; only for the preferable embodiment of the present invention, but protection scope of the present invention is not limited thereto, and anyly is familiar with the people of this technology in the disclosed technical scope of the present invention; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of claim.
Claims (10)
1. a memory controller automatization proving installation is characterized in that, comprise, and switch fabric module, type of memory module, configuration interface, query interface, wherein,
Switch fabric module is used for memory bus to the exchange of the connection between the type of memory module;
The type of memory module, the parameter that is used to store test case, numbering and the storer of various memory emulation models;
Configuration interface is used to dispose described switch fabric module, and to the inspection of the current configuration of described switch fabric module;
Query interface is used for the parameter of all storeies of current support and the inquiry of numbering, and to the inquiry of the configuration parameter of switch fabric module;
Select the parameter of storage class and storer by described query interface, and the storage class selected and the parameter of storer are issued to described switch fabric module by described configuration interface, carry out required initialization and test case at the storage class of selecting, carry out the test of storer.
2. device as claimed in claim 1 is characterized in that,
Described switch fabric module comprises switching matrix configuration parameter module, the configuration that described switching matrix configuration parameter module is used to deposit current switch fabric module comprises validity check result, the switching bus ready state of the configuration of the quantity of memory bus, every memory bus, current configuration;
In the described type of memory module, all corresponding independently described numbering of the storer of each type;
The described scope of examination of described configuration interface comprises described numbering, highway width, addressing range, mapping conflict, address conflict, the type comflict of every memory bus correspondence.
3. device as claimed in claim 2 is characterized in that, described configuration interface comprises configuration read-write interface, configuration parameter inspection module, switching matrix repository, configuration handshake module, error handling processing module, wherein,
Dispose read-write interface, be used for the interface of described proving installation and software section, by described configuration read-write interface, software is realized control and the monitoring to described proving installation;
Configuration parameter is checked module, is used for described proving installation to joining the validity checking of parameter under the software;
The switching matrix repository is used to write down the parameter list of all memory models of the current support of described proving installation;
The configuration handshake module is used for auxiliary described proving installation and finishes the various synchronous of described configuration read-write interface;
The error handling processing module is used for being responsible for catching the various mistakes that the parameter process of issuing occurs, and concentrates and to report described proving installation.
4. device as claimed in claim 3 is characterized in that,
Described configuration parameter checks that module comprises, test macro status checking module, model existence are checked module, model parameter validity check module, model collaborative work inspection module, wherein,
Test macro status checking module is used for being responsible for the self check of described proving installation, checks whether described proving installation is ready;
Whether the model existence checks module to be used for checking whether the memory model to issuing the parameter appointment is that described proving installation is supported, necessary being in described proving installation;
Model parameter validity check module is used to be responsible for finish and plants the inspection that model issues the other parts of parameter to single, comprises whether various parameters cross the border, whether collaborative work between the parameter;
Module is checked in the model collaborative work, and whether collaborative work is checked to be used for being responsible for multiple model to issuing.
5. device as claimed in claim 3 is characterized in that, described configuration handshake module, and the complexity according to described proving installation support memory model adopts different Handshake Protocols to realize synchronously.
6. as claim 4 or 5 described devices, it is characterized in that, also comprise the read-write interface of described configuration interface and described query interface, be used for the read-write operation of described configuration interface and described query interface; The mechanism that the configuration of described configuration interface and described query interface is shaken hands by asynchronous interlocking realizes.
7. device as claimed in claim 6 is characterized in that, described configuration handshake module adopts two semaphores to realize that interlocking is synchronous;
The read-write interface of described configuration interface and described query interface comprises PLI/VPI/DPI interface or the proprietary interface of eda tool.
8. the method for a memory controller automatization test may further comprise the steps,
A, to the storer modeling, be various types of memory allocation numberings, the parameter of putting each storer in order;
B, the type and the numbering of storer by the current support of inquiry, the type of selection memory and the parameter of storer, and, and to the inspection of the configuration of current switching bus, the parameter of described storer is issued to described switching bus by the configuration switching bus;
C, at the type of the storer of selecting, carry out required initialization and test case, finish test to the storer of current configuration.
9. method as claimed in claim 8 is characterized in that, among the described step a, also comprises the configuration parameter of the memory bus that the current chip of arrangement is supported;
The described of various types of memory allocation is numbered independently;
The parameter of described storer comprises storage class, accessing time sequence parameter, row address width, column address width, bank number, access mode, capacity, type of bus protocol, frequency of operation;
The configuration parameter of memory bus comprises bus number, addressing space, accessing time sequence parameter, access mode.
10. method as claimed in claim 9 is characterized in that, further comprises among the described step b,
Whether ready, if do not have readyly, then wait for if inquiring about described switching bus;
Otherwise, inquire about the current configuration of described switching bus and whether make a mistake, if then carry out described step b or stop test; Otherwise, execution in step c.
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