CN109522194B - Automatic pressure test system and method for AXI protocol slave equipment interface - Google Patents
Automatic pressure test system and method for AXI protocol slave equipment interface Download PDFInfo
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Abstract
The invention discloses an automatic pressure test system for an AXI protocol slave device interface, which comprises an excitation generation module, a cache queue module, a data receiving module, an excitation and result storage module, a result comparison module and a module to be tested. The technical scheme of the invention directly simulates the extreme condition that a plurality of main devices access simultaneously at one end of the interface of the slave device, and has the advantages of high configurability and sufficient verification coverage rate.
Description
Technical Field
The invention belongs to the field of simulation test, and particularly relates to an automatic pressure test system and method for an AXI protocol slave device interface.
Background
AXI is the most widely used on-chip bus protocol with high performance, high bandwidth and low delay in SoC chips at present, and it realizes the mutual separation of address/control and data signals, forms five mutually independent channels of write address, write data, write receipt, read address and read data, and can meet the requirements of high-performance and high-complexity on-chip system design.
In practical application, devices mounted on an AXI bus are divided into two types, namely a master device and a slave device, where the master device is responsible for initiating a read/write request, and the slave device is responsible for receiving the read/write request and responding. The two devices realize communication between the internal and the bus through a master device interface and a slave device interface respectively. Because the current SoC chip has a larger and larger scale and more complex functions, there may be a plurality of master devices and slave devices on the chip, and if a plurality of master devices such as a processor and a DMA perform read-write access to a certain slave device at the same time, the bus interface of the slave device is in a high-voltage state at this time. The high-voltage state has several characteristics from the equipment side, firstly, the read-write requests are very dense, and valid signals of different requests do not have intervals; secondly, the type of the read-write request is irregular; thirdly, the requests of different main devices correspond to different IDs; fourth, the ready signal from the master may not always be active because the interface of the master itself may also be busy. In such extreme cases, the slave interface may affect the functionality of the entire chip if it is malfunctioning.
At present, a conventional test method for an AXI protocol slave device interface only aims at a basic transmission function, and can ensure that a single master device and a single slave device can normally communicate with each other, but cannot verify whether the slave device interface can normally work in a high-voltage environment. If a real verification environment comprising a plurality of master devices and one slave device is adopted, the defects of poor configurability, long simulation time and the like exist.
Disclosure of Invention
Aiming at the technical problem, the invention provides an automatic pressure test system and method for an AXI protocol slave device interface, which solve the problem that the conventional verification method cannot prove whether the AXI slave device interface can normally work in a high-pressure environment.
An automatic pressure test system aiming at an AXI protocol slave equipment interface comprises an excitation generating module, a buffer queue module, a data receiving module, an excitation and result storage module, a result comparison module and a module to be tested,
the excitation generating module is used for generating excitation signals of three channels of a write address, write data and a read address;
the buffer queue module is used for simulating outranging buffer in a slave device interface and receiving generated excitation signals, and the generated excitation signals comprise a first write address buffer queue, a second write address buffer queue and a read address buffer queue;
the data receiving module is used for communicating with a write receipt and a read data channel of the module to be tested and receiving a write request receipt and read data sent by the module to be tested according to the requirements of an AXI protocol;
the excitation and result storage module is used for storing the data written into the module to be tested by the excitation generation module and the data read out from the module to be tested and transmitting the data written into the module to be tested and the data read out from the module to be tested to the result comparison module;
the result comparison module is used for comparing the data written into the module to be tested with the data read out from the module to be tested and judging whether the module to be tested works normally or not;
and the module to be tested is provided with a functional module of the AXI interface and is used for simulating the data reading and writing conditions of the slave equipment.
Further, the excitation generation module continuously sends read-write requests, a valid signal of a channel is continuously effective in each request, the next request is sent until a ready signal of the module to be tested is high, the valid between two adjacent requests is not pulled down under the condition of continuously sending the requests, and the valid of the corresponding channel is pulled down only when the cache queue in the cache queue module is in a full state, so that the requests are stopped being sent;
the ID and burst _ type signals of the write address channel and the read address channel generated by the excitation generation module are random values.
Further, the read enable of the first write address cache queue in the cache queue module is controlled by valid and ready signals of a write-back execution channel;
the read enable of the read address buffer queue is controlled by valid and ready signals of a read data channel;
the read enabling of the second write address buffer queue is controlled by valid and ready signals of a data writing channel;
the empty and full signals are generated by combinational logic, and data writing and reading adopt asynchronous logic.
Further, the break and rread signals sent by the data receiving module are random values.
Further, before comparing the data written into the module to be tested with the data read out from the module to be tested, the result comparison module compares whether the number of read-write requests sent by the excitation generation module is the same as the number of received read-write responses of the module to be tested.
The invention also provides an automatic pressure test method for the slave equipment interface of the AXI protocol, which comprises the following steps:
s1, an excitation generating step, wherein an excitation generating module generates excitation signals of three channels of a write address, write data and a read address;
s2, a data caching step, wherein a caching queue module simulates outranging caching in a slave device interface, and receives generated excitation signals, wherein the excitation signals comprise a first writing address caching queue, a second writing address caching queue and a reading address caching queue;
s3, a data receiving step, in which a data receiving module communicates with a write receipt and a read data channel of a module to be tested and receives a write request receipt and read data sent by the module to be tested according to the requirements of an AXI protocol;
s4, an excitation and result storage step, wherein the excitation and result storage module stores the data written into the module to be tested and the data read out from the module to be tested, and transmits the data written into the module to be tested and the data read out from the module to be tested to the result comparison module;
and S5, comparing the result, wherein the result comparing module compares the data written into the module to be tested with the data read out from the module to be tested, and judges whether the module to be tested works normally.
Further, in step S1, the excitation generation module continuously sends read/write requests, and in each request, the valid signal of the channel is continuously valid, and the next request is sent until the ready signal of the module to be tested is high, and in the case of continuously sending requests, the valid between two adjacent requests is not pulled down, and only when the cache queue in the cache queue module is in a "full" state, the valid of the corresponding channel is pulled down, and the request sending is stopped;
the ID and burst _ type signals of the write address channel and the read address channel generated by the excitation generation module are random values.
Further, in step S2, the read enable of the first write address cache queue in the cache queue module is controlled by the valid and ready signals of the write-back execution channel;
the read enable of the read address buffer queue is controlled by valid and ready signals of a read data channel;
the read enabling of the second write address buffer queue is controlled by valid and ready signals of a data writing channel;
the empty and full signals are generated by combinational logic, and data writing and reading adopt asynchronous logic.
Further, the break and rread signals sent by the data receiving module are random values.
Further, in step S5, before the result comparison module compares the data written into the module to be tested with the data read from the module to be tested, it first compares whether the number of read-write requests sent by the excitation generation module is the same as the number of read-write responses received from the module to be tested.
The technical scheme of the invention directly simulates the extreme condition that a plurality of main devices access simultaneously at one end of the interface of the slave device, and has the advantages of high configurability and sufficient verification coverage rate.
Drawings
FIG. 1 is a schematic block diagram of an automated stress testing system for an AXI protocol slave interface of the present invention;
FIG. 2 is an exemplary timing diagram of a write address channel in the present invention;
FIG. 3A is a diagram illustrating a first write address buffer queue connection according to the present invention;
FIG. 3B is a diagram illustrating a second write address buffer queue connection according to the present invention;
FIG. 3C is a diagram illustrating a read address buffer queue connection according to the present invention;
FIG. 4 illustrates the logic for generating a buffered empty/full signal according to the present invention;
FIG. 5 illustrates the asynchronous write logic of the cache of the present invention;
FIG. 6 is a flow chart of a method of the present invention using an automated pressure testing system.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, the automatic pressure test system for an AXI protocol slave device interface includes an excitation generating module 1, a buffer queue module 2, a data receiving module 3, an excitation and result storing module 4, a result comparing module 5 and a module to be tested 6, where the module to be tested 6 includes a functional module with an AXI interface for simulating data read-write conditions of a slave device
(1) Excitation generating module 1
The module is responsible for generating excitation signals of three channels of a write address, a write data and a read address. The module can continuously send read-write requests, the valid signal of a channel can be continuously effective in each request, the next request can not be sent until the ready signal of the slave device is high, the valid between two adjacent requests can not be pulled down under the condition of continuously sending the requests, only when the cache queue module 2 is in a full state, the outranging capability of the slave device interface is shown to reach the limit, at the moment, the valid of the corresponding channel can be pulled down, and the request sending is stopped. As shown in fig. 2, a buffer queue module continues to send requests as long as the module is not full. The ID and burst _ type signals of the writing address channel and the reading address channel are random values, different IDs simulate different main devices, and random burst _ type indicates that access of single read-write and burst read-write types occurs randomly. Addresses issued by these two channels will guarantee traversal from the device address space. And the data writing channel sends out data according to the writing address, the data is a random value, and the ID of the data writing channel is consistent with the ID of the writing address channel.
(2) Buffer queue module 2
The module is responsible for emulating the outranging cache in the slave interface, which is configurable in depth. The device comprises three buffer queues, namely a first write address buffer queue, a second write address buffer queue and a read address buffer queue. The specific connection is shown in fig. 3A-3C.
The read enable of the first write address cache queue is controlled by the valid and ready signals of the write-back execution channel, which means that the number of requests in the first write address cache queue is reduced by one every time a write request is received from the device. If the write address cache 1 is in a "full" state, the excitation generation module 1 stops sending the write address request.
Similarly, the read enable of the read address buffer queue is controlled by the valid and ready signals of the read data channel, which means that the number of requests in the read address buffer is reduced by one every time a read request is received from the device. If the read address buffer is in a "full" state, the excitation generation module 1 stops sending the read address request.
The read enable of the second write address buffer queue is controlled by valid and ready signals of the write data channel, which means that the excitation generating module 1 will read the request and update the signals in the write data channel as long as there is a request in the buffer, and if the second write address buffer queue is in an "empty" state, the excitation generating module 1 will stop sending write data.
To implement the timing shown in fig. 2, the cache employed in the present invention is based on the conventional design method and is modified in a series of ways, including: firstly, the empty and full signals are generated by changing the combined logic; and secondly, asynchronous logic is adopted for data writing and reading. FIG. 4 shows the logic for generating the empty-full signal, and the reason why no sequential logic is used is that if the empty-full signal is output from the register, the stimulus generation module 1 will pull valid low in the next cycle when the "full" state is detected, which corresponds to a request being issued. Using combinational logic, which is equivalent to advancing the generation of the empty-full signal by one cycle, ensures that valid is pulled low immediately after the last request is issued. FIG. 5 shows data write logic employing latches. In the cache applied by the invention, the write data is asynchronously written into the latch, while the read data does not pass through the register and is directly output by the combinational logic, so that the valid and the data of the write data channel in the excitation generating module 1 need to be synchronously updated, and the read data is directly output by the combinational logic, so that the read port data of the cache can be ensured to be the next request to be read all the time; and the asynchronous writing function ensures that the written data can be reflected to the read port without delay when the cache is written for the first time.
(3) Data receiving module 3
The module is responsible for communicating with a write receipt and a read data channel of the module to be tested and receiving a write request receipt and read data sent by the module to be tested according to the requirements of an AXI protocol. The break and the rread signals sent by the module are random values and are mostly 0, which means that the master device is mostly in a busy state and cannot receive data. Therefore, whether the slave device interface can work normally under the condition that the ready signal feedback of the master device is not obtained at a later time can be verified.
(4) Excitation and result storage module 4
The module is responsible for storing the data written into the module to be tested 6 by the excitation generating module 1 and the data read out from the module to be tested 6 and outputting the data to the result comparison module 5 for comparison.
(5) Result comparison module 5
The module is responsible for comparing the written data with the read data and judging whether the module to be tested 6 works normally or not. Before the consistency of the write-in data and the read-out data is compared, whether the number of read-write requests sent by the excitation generating module 1 is the same as the number of read-write responses received by the module to be tested needs to be compared, the overall test results of the five channels are preliminarily judged according to the results, and the debugging efficiency is improved.
In addition, the invention can also set up a timeout exit mechanism for the three channels of the write address, the write data and the read address respectively, so that even if the slave device interface has a problem, for example, a ready signal is not given late, the whole verification environment can be normally ended without continuing waiting. The time limit for the timeout exit may be matched.
The present invention also provides a method of using an automated pressure testing system, as shown in FIG. 6, comprising the steps of:
s1, an excitation generating step, wherein an excitation generating module generates excitation signals of three channels of a write address, write data and a read address;
s2, a data caching step, wherein a caching queue module simulates outranging caching in a slave device interface, and receives generated excitation signals, wherein the excitation signals comprise a first writing address caching queue, a second writing address caching queue and a reading address caching queue;
s3, a data receiving step, in which a data receiving module communicates with a write receipt and a read data channel of a module to be tested and receives a write request receipt and read data sent by the module to be tested according to the requirements of an AXI protocol;
s4, an excitation and result storage step, wherein the excitation and result storage module stores the data written into the module to be tested and the data read out from the module to be tested, and transmits the data written into the module to be tested and the data read out from the module to be tested to the result comparison module;
and S5, comparing the result, wherein the result comparing module compares the data written into the module to be tested with the data read out from the module to be tested, and judges whether the module to be tested works normally.
It is to be understood that the above examples are illustrative only for the purpose of clarity of description and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are intended to be within the scope of the invention.
Claims (10)
1. An automatic pressure test system aiming at an AXI protocol slave device interface is characterized by comprising an excitation generating module, a buffer queue module, a data receiving module, an excitation and result storage module, a result comparison module and a module to be tested, wherein,
the excitation generating module is used for generating excitation signals of three channels of a write address, write data and a read address;
the buffer queue module is used for simulating outranging buffer in a slave device interface and receiving generated excitation signals, and the generated excitation signals comprise a first write address buffer queue, a second write address buffer queue and a read address buffer queue;
the data receiving module is used for communicating with a write receipt and a read data channel of the module to be tested and receiving a write request receipt and read data sent by the module to be tested according to the requirements of an AXI protocol;
the excitation and result storage module is used for storing the data written into the module to be tested by the excitation generation module and the data read out from the module to be tested and transmitting the data written into the module to be tested and the data read out from the module to be tested to the result comparison module;
the result comparison module is used for comparing the data written into the module to be tested with the data read out from the module to be tested and judging whether the module to be tested works normally or not;
and the module to be tested is provided with a functional module of the AXI interface and is used for simulating the data reading and writing conditions of the slave equipment.
2. The automated pressure testing system of claim 1, wherein the excitation generating module continuously sends read and write requests, and in each request, the valid signal of a channel is continuously valid until the ready signal of the module to be tested is high, and then sends the next request, and in the case of continuously sending requests, the valid between two adjacent requests is not pulled down, and only when the cache queue in the cache queue module is in a "full" state, the valid of the corresponding channel is pulled down, and the request sending is stopped;
the ID and burst _ type signals of the write address channel and the read address channel generated by the excitation generation module are random values.
3. The automated pressure test system of claim 1, wherein read enable of the first write address cache queue in the cache queue module is controlled by valid and ready signals of a write back execution channel;
the read enable of the read address buffer queue is controlled by valid and ready signals of a read data channel;
the read enabling of the second write address buffer queue is controlled by valid and ready signals of a data writing channel;
the empty and full signals are generated by combinational logic, and data writing and reading adopt asynchronous logic.
4. The automated pressure testing system of claim 1, wherein the break and rread signals emitted by the data receiving module are random values.
5. The automated pressure testing system of claim 1, wherein the result comparison module compares whether the number of read/write requests issued by the excitation generation module is the same as the number of read/write responses received from the module under test before comparing the data written to the module under test with the data read from the module under test.
6. An automated stress testing method for an AXI protocol slave interface using the automated stress testing system of any of claims 1-5, comprising the steps of:
s1, an excitation generating step, wherein an excitation generating module generates excitation signals of three channels of a write address, write data and a read address;
s2, a data caching step, wherein a caching queue module simulates outranging caching in a slave device interface, and receives generated excitation signals, wherein the excitation signals comprise a first writing address caching queue, a second writing address caching queue and a reading address caching queue;
s3, a data receiving step, in which a data receiving module communicates with a write receipt and a read data channel of a module to be tested and receives a write request receipt and read data sent by the module to be tested according to the requirements of an AXI protocol;
s4, an excitation and result storage step, wherein the excitation and result storage module stores the data written into the module to be tested and the data read out from the module to be tested, and transmits the data written into the module to be tested and the data read out from the module to be tested to the result comparison module;
and S5, comparing the result, wherein the result comparing module compares the data written into the module to be tested with the data read out from the module to be tested, and judges whether the module to be tested works normally.
7. The method according to claim 6, wherein in step S1, the excitation generating module continuously sends read/write requests, and in each request, the valid signal of a channel is continuously valid until the ready signal of the module to be tested is high, and then sends the next request, and in the case of continuously sending requests, the valid signal between two adjacent requests is not pulled down, and only when the buffer queue in the buffer queue module is in "full" state, the valid signal of the corresponding channel is pulled down, and the sending of the request is stopped;
the ID and burst _ type signals of the write address channel and the read address channel generated by the excitation generation module are random values.
8. The automated stress testing method of claim 6, wherein the read enable of the first write address cache queue in the cache queue module in step S2 is controlled by valid and ready signals written back to the execution channel;
the read enable of the read address buffer queue is controlled by valid and ready signals of a read data channel;
the read enabling of the second write address buffer queue is controlled by valid and ready signals of a data writing channel;
the empty and full signals are generated by combinational logic, and data writing and reading adopt asynchronous logic.
9. The automated pressure testing method of claim 6, wherein the break and rread signals emitted by the data receiving module are random values.
10. The automated pressure testing method of claim 6, wherein in step S5, the result comparison module compares whether the number of read/write requests issued by the excitation generation module is the same as the number of read/write responses received by the module under test before comparing the data written into the module under test with the data read from the module under test.
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| CN110737552B (en) * | 2019-08-29 | 2022-06-21 | 瑞芯微电子股份有限公司 | SFC interface testing equipment and method based on FPGA |
| CN113533941B (en) * | 2021-09-15 | 2022-03-01 | 北京国科天迅科技有限公司 | Chip interface testing method and device, computer equipment and storage medium |
| CN118643776A (en) * | 2024-08-12 | 2024-09-13 | 山东云海国创云计算装备产业创新中心有限公司 | Pressure test method and device for target chip, storage medium and program product |
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