CN117878138A - Silicon carbide semiconductor epitaxial wafer, preparation method thereof and silicon carbide semiconductor device - Google Patents
Silicon carbide semiconductor epitaxial wafer, preparation method thereof and silicon carbide semiconductor device Download PDFInfo
- Publication number
- CN117878138A CN117878138A CN202311691089.6A CN202311691089A CN117878138A CN 117878138 A CN117878138 A CN 117878138A CN 202311691089 A CN202311691089 A CN 202311691089A CN 117878138 A CN117878138 A CN 117878138A
- Authority
- CN
- China
- Prior art keywords
- silicon carbide
- epitaxial layer
- film
- silicon
- carbide epitaxial
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 341
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 334
- 239000004065 semiconductor Substances 0.000 title claims abstract description 82
- 238000002360 preparation method Methods 0.000 title claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 96
- 238000000034 method Methods 0.000 claims abstract description 33
- 238000006243 chemical reaction Methods 0.000 claims abstract description 25
- 229910052799 carbon Inorganic materials 0.000 claims description 53
- 229910021645 metal ion Inorganic materials 0.000 claims description 53
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 52
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 44
- 229910052710 silicon Inorganic materials 0.000 claims description 44
- 239000010703 silicon Substances 0.000 claims description 44
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 37
- 239000007788 liquid Substances 0.000 claims description 31
- 229920005591 polysilicon Polymers 0.000 claims description 31
- 239000007789 gas Substances 0.000 claims description 27
- -1 titanium ions Chemical class 0.000 claims description 25
- 239000012495 reaction gas Substances 0.000 claims description 14
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 13
- 229910052757 nitrogen Inorganic materials 0.000 claims description 13
- 239000007791 liquid phase Substances 0.000 claims description 11
- 150000002500 ions Chemical class 0.000 claims description 7
- 229910001430 chromium ion Inorganic materials 0.000 claims description 6
- 150000004820 halides Chemical class 0.000 claims description 6
- 229910052742 iron Inorganic materials 0.000 claims description 6
- XEEYBQQBJWHFJM-UHFFFAOYSA-N iron Substances [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims description 6
- 239000000376 reactant Substances 0.000 claims description 6
- 229910001456 vanadium ion Inorganic materials 0.000 claims description 6
- 125000004432 carbon atom Chemical group C* 0.000 claims description 5
- 229910001385 heavy metal Inorganic materials 0.000 claims description 5
- 150000002894 organic compounds Chemical class 0.000 claims description 5
- 239000012808 vapor phase Substances 0.000 claims description 5
- 239000011261 inert gas Substances 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 239000010936 titanium Substances 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- LCKIEQZJEYYRIY-UHFFFAOYSA-N Titanium ion Chemical compound [Ti+4] LCKIEQZJEYYRIY-UHFFFAOYSA-N 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 239000011733 molybdenum Substances 0.000 claims description 3
- 230000007423 decrease Effects 0.000 claims description 2
- 239000013589 supplement Substances 0.000 claims description 2
- 239000013078 crystal Substances 0.000 abstract description 12
- 239000007787 solid Substances 0.000 abstract description 8
- 230000007547 defect Effects 0.000 description 17
- 238000010586 diagram Methods 0.000 description 16
- 239000013067 intermediate product Substances 0.000 description 12
- 230000000694 effects Effects 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000000407 epitaxy Methods 0.000 description 5
- SLLGVCUQYRMELA-UHFFFAOYSA-N chlorosilicon Chemical compound Cl[Si] SLLGVCUQYRMELA-UHFFFAOYSA-N 0.000 description 4
- 238000004943 liquid phase epitaxy Methods 0.000 description 4
- 239000002243 precursor Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 239000000155 melt Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 2
- 238000004090 dissolution Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000009830 intercalation Methods 0.000 description 2
- 230000002687 intercalation Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000006911 nucleation Effects 0.000 description 2
- 238000010899 nucleation Methods 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 150000001721 carbon Chemical class 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 150000002902 organometallic compounds Chemical class 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 230000001131 transforming effect Effects 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 239000002023 wood Substances 0.000 description 1
Abstract
The application provides a silicon carbide semiconductor epitaxial wafer and a preparation method thereof, and a silicon carbide semiconductor device. The first silicon carbide epitaxial layer is arranged on the silicon carbide substrate; the second silicon carbide epitaxial layer is arranged on the first silicon carbide epitaxial layer; wherein the dislocation density of the first silicon carbide epitaxial layer is less than the dislocation density of the silicon carbide substrate. Specifically, the dislocation density of the first silicon carbide epitaxial layer in the method is smaller than that of the silicon carbide substrate, and the first silicon carbide epitaxial layer is adopted as the growth surface of the second silicon carbide epitaxial layer, so that the probability of extension or conversion of crystal dislocation of the silicon carbide substrate to the second silicon carbide epitaxial layer is greatly reduced, the yield of an epitaxial wafer can be remarkably improved, and a solid foundation is laid for the subsequent improvement of the yield and reliability of the silicon carbide semiconductor device.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a silicon carbide semiconductor epitaxial wafer, a preparation method thereof and a silicon carbide semiconductor device.
Background
Silicon carbide (SiC) is a typical representative of a third generation wide bandgap semiconductor material, and a SiC-based power device has excellent performances of high frequency, high power, low power consumption, high temperature resistance, high voltage resistance, radiation resistance and the like, and is a key 'core' of a new energy automobile, an extra-high voltage power grid, rail transit, an optical Fu Fengneng inverter and a next generation communication technology. At present, all SiC power devices are built based on SiC epitaxial layers, and SiC epitaxial production is an intermediate link of an SiC semiconductor industry chain and plays a role in supporting the top and bottom. Since the epitaxial defect directly affects the electrical property and reliability of the back-end device, the control of the epitaxial defect is always a core topic in the development of the epitaxial mass production process.
Because the Stacking fault energy of the SiC crystal is low, stacking fault defects (SF) are easier to form in the material during the crystal growth and epitaxy of the 4H-SiC. Literature data shows that the epitaxial SF defect can become a leakage channel of the SiC power device, so that leakage current is greatly increased, reverse withstand voltage is reduced by more than 20%, and therefore, suppression of SF defect formation in an epitaxial layer is important for improving the chip yield and reliability.
Disclosure of Invention
The application provides a silicon carbide semiconductor epitaxial wafer, a preparation method thereof and a silicon carbide semiconductor device, which can solve the problem that an epitaxial layer is easier to form stacking fault defects in the epitaxial process.
In order to solve the technical problems, a first technical scheme adopted by the application is as follows: provided is a silicon carbide semiconductor epitaxial wafer comprising: a silicon carbide substrate; the first silicon carbide epitaxial layer is arranged on the silicon carbide substrate; the second silicon carbide epitaxial layer is arranged on the first silicon carbide epitaxial layer; wherein the dislocation density of the first silicon carbide epitaxial layer is less than the dislocation density of the silicon carbide substrate.
In order to solve the technical problems, a second technical scheme adopted by the application is as follows: there is provided a silicon carbide semiconductor device comprising the silicon carbide semiconductor epitaxial wafer as set forth in any one of the above.
In order to solve the technical problem, a third technical scheme adopted in the application is as follows: the preparation method of the silicon carbide semiconductor epitaxial wafer comprises the following steps: providing a silicon carbide substrate; forming a first silicon carbide epitaxial layer on the silicon carbide substrate by growth, wherein the first silicon carbide epitaxial layer is formed by liquid phase epitaxial growth of a carbon film and a silicon film; and growing a second silicon carbide epitaxial layer on the first silicon carbide epitaxial layer.
In order to solve the technical problem, a fourth technical scheme adopted in the application is as follows: the preparation method of the silicon carbide semiconductor epitaxial wafer comprises the following steps: providing a silicon carbide substrate; forming a first silicon carbide epitaxial layer on the silicon carbide substrate; forming a second silicon carbide epitaxial layer on the first silicon carbide epitaxial layer; wherein the dislocation density of the first silicon carbide epitaxial layer is less than the dislocation density of the silicon carbide substrate.
Compared with the prior art, the silicon carbide semiconductor epitaxial wafer has the beneficial effects that in the silicon carbide semiconductor epitaxial wafer, the dislocation density of the first silicon carbide epitaxial layer is smaller than that of the silicon carbide substrate, and the first silicon carbide epitaxial layer is adopted as the growth surface of the second silicon carbide epitaxial layer, so that the probability of extending or converting crystal dislocation of the silicon carbide substrate to the second silicon carbide epitaxial layer is greatly reduced, compared with the traditional method of directly epitaxially growing the silicon carbide epitaxial layer on the surface of the silicon carbide substrate, the stacking fault density of epitaxially growing the second silicon carbide epitaxial layer on the first silicon carbide epitaxial layer is reduced by more than 40%, the yield of the epitaxial layer is remarkably improved, and a solid foundation is laid for the yield and reliability of a follow-up silicon carbide semiconductor device.
Drawings
For a clearer description of the technical solutions in the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art, wherein:
fig. 1 is a schematic structural diagram of an embodiment of a silicon carbide semiconductor epitaxial wafer provided in the present application;
fig. 2 is a schematic flow chart of an embodiment of a method for preparing a silicon carbide semiconductor epitaxial wafer provided in the present application;
FIG. 3 is a flowchart illustrating an embodiment of the step S2 in FIG. 2;
fig. 4 is a schematic diagram of an intermediate product of the silicon carbide semiconductor epitaxial wafer provided in the present application after step S1;
fig. 5 is a schematic diagram of an intermediate product of the silicon carbide semiconductor epitaxial wafer provided in the present application after step S21;
fig. 6 is a schematic diagram of an intermediate product of the silicon carbide semiconductor epitaxial wafer provided in the present application in step S22;
fig. 7 is a schematic diagram of an intermediate product of the silicon carbide semiconductor epitaxial wafer provided in the present application in step S22;
fig. 8 is a schematic diagram of an intermediate product of the silicon carbide semiconductor epitaxial wafer provided in the present application in step S22;
fig. 9 is a schematic diagram of an intermediate product of the silicon carbide semiconductor epitaxial wafer provided in the present application after step S22;
fig. 10 is a schematic structural diagram of a silicon carbide semiconductor epitaxial wafer provided in the present application after step S3.
Description of the reference numerals:
silicon carbide semiconductor epitaxial wafer-100; a silicon carbide substrate-10; a first silicon carbide epitaxial layer-20; a second silicon carbide epitaxial layer-30; carbon film-40; liquid silicon film-50; a polysilicon film-60; si-C melt-70;
a first thickness-H1; a second thickness-H2; third thickness-H3.
Detailed Description
The following description of the technical solutions in the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
The terms "first," "second," "third," and the like in this application are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", and "a third" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise. All directional indications (such as up, down, left, right, front, back … …) in the embodiments of the present application are merely used to explain the relative positional relationship, movement, etc. between the components in a particular gesture (as shown in the drawings), and if the particular gesture changes, the directional indication changes accordingly. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
With current SiC epitaxy generally employing a (0001) bias<11-20>An off-axis SiC substrate of 4 ° is taken as an example of an epitaxial substrate, and in the related art, a step flow growth method is introduced through the off-axis substrateThe formula greatly reduces the formation of SF defects in epitaxy, which is a significant technological advance in SiC epitaxy. Later technicians continuously improve the defects of the epitaxial SF by means of high-temperature hydrogen etching of the substrate, slow-speed buffer layer growth and the like to reduce the density to 1ea/cm 2 Left and right. But the SF density is continuously reduced to 0.3ea/cm 2 There is still a need for new technological breakthroughs below.
The occurrence rate of SF defects in epitaxial mass production is greatly reduced by adopting a step flow growth mode, but a small amount of in-grown SF defects still form. Research on the mechanism of formation of such SF defects remains an important research direction for SiC crystal defect theory. In general, epitaxial SF defects are classified into a Shockley type and a Frank type stacking fault, and crystal growth theory indicates that these two SF defects are directly related to abnormal evolution of a step state at a surface dislocation of a substrate, and two-dimensional nucleation at the surface dislocation of the substrate at the beginning of growth tends to be the origin of the stacking fault.
In order to solve the problems, the method adopts an optimized substrate surface treatment process to inhibit abnormal nucleation at the dislocation of the substrate so as to effectively inhibit the epitaxial SF defect.
The present application is described in detail below with reference to the accompanying drawings and examples.
Referring to fig. 1, fig. 1 is a schematic structural diagram of an embodiment of a silicon carbide semiconductor epitaxial wafer provided in the present application.
Specifically, the present application provides a silicon carbide semiconductor epitaxial wafer 100, and the silicon carbide semiconductor epitaxial wafer 100 includes a silicon carbide substrate 10, a first silicon carbide epitaxial layer 20, and a second silicon carbide epitaxial layer 30. Wherein a first silicon carbide epitaxial layer 20 is disposed on a silicon carbide substrate 10; the second silicon carbide epitaxial layer 30 is disposed on the first silicon carbide epitaxial layer 20; the first silicon carbide epitaxial layer 20 acts as an intercalation between the silicon carbide substrate 10 and the second silicon carbide epitaxial layer 30.
Wherein the dislocation density of the first silicon carbide epitaxial layer 20 is less than the dislocation density of the silicon carbide substrate 10.
Among them, the silicon carbide substrate 10 may be a 4H-SiC substrate or a 6H-SiC substrate, and 4H-SiC substrate is preferable in this application because it has higher bulk mobility and has smaller anisotropy.
In some embodiments, the (0001) plane (i.e., the growth plane) of the silicon carbide substrate 10 has an angular off-orientation of 2 ° -6 ° along the <11-20> direction. For example, the (0001) plane of the silicon carbide substrate 10 has an off-orientation angle of 2 ° along the <11-20> direction; alternatively, the (0001) plane of the silicon carbide substrate 10 has an off-orientation angle of 4 ° along the <11-20> direction; alternatively, the (0001) plane of the silicon carbide substrate 10 has an off-orientation angle of 6 ° along the <11-20> direction. The first silicon carbide epitaxial layer 20 is not limited herein as long as it can be formed better on the silicon carbide substrate 10.
Wherein the dislocation density of the first silicon carbide epitaxial layer 20 is less than the dislocation density of the silicon carbide substrate 10, the first silicon carbide epitaxial layer 20 acts as an intercalation between the silicon carbide substrate 10 and the second silicon carbide epitaxial layer 30.
Specifically, the first silicon carbide epitaxial layer 20 with smaller dislocation density is formed between the silicon carbide substrate 10 and the second silicon carbide epitaxial layer 30 to serve as the growth surface of the second silicon carbide epitaxial layer 30, so that the probability that crystal dislocation of the silicon carbide substrate 10 extends or is converted to the second silicon carbide epitaxial layer 30 can be greatly reduced, compared with the conventional method that the second silicon carbide epitaxial layer 30 is directly epitaxially grown on the surface of the silicon carbide substrate 10, the stacking fault density of the second silicon carbide epitaxial layer 30 is epitaxially grown on the first silicon carbide epitaxial layer 20 can be reduced by more than 40%, the yield of the second silicon carbide epitaxial layer 30 is remarkably improved, and a solid foundation is laid for the yield and reliability of a follow-up silicon carbide semiconductor device.
In one embodiment, in the silicon carbide semiconductor epitaxial wafer 100, the thickness ratio of the silicon carbide substrate 10, the first silicon carbide epitaxial layer 20, and the second silicon carbide epitaxial layer 30 is: 290-500: 0.05 to 0.5:5 to 100.
Specifically, the ratio of the thickness of the first silicon carbide epitaxial layer 20 to the total thickness of the silicon carbide semiconductor epitaxial wafer 100 cannot be too large, which may result in serious wafer warpage and increased internal stress. Of course, the proportion of the thickness of the first silicon carbide epitaxial layer 20 to the total thickness of the silicon carbide semiconductor epitaxial wafer 100 should not be too small to effectively block dislocation propagation in the substrate.
In one embodiment, the first silicon carbide epitaxial layer 20 has a thickness of 50-500nm. Accordingly, the thickness of the silicon carbide substrate 10 and the thickness of the second silicon carbide epitaxial layer 30 may be designed according to the above-described ratio.
In one embodiment, the first silicon carbide epitaxial layer 20 is also doped with metal ions. Specifically, during the preparation of the first silicon carbide epitaxial layer 20, the doped metal ions may help to perform a melting-assisting effect on the carbon film formed in the precursor process, thereby helping to epitaxially form the first silicon carbide epitaxial layer 20 on the growth surface of the silicon carbide substrate 10. For example, the doping concentration of the metal ions may range from 1E19 to 1E21/cm3, for example 1E20/cm3.
In some embodiments, the metal ions include at least one of titanium ions, chromium ions, vanadium ions, and iron ions. Wherein the source of metal ions may be formed from the vapor phase halides or organic compounds of the corresponding metals.
In one embodiment, the type of metal ions doped in the first silicon carbide epitaxial layer 20 is one, and the doping concentration of metal ions gradually decreases in the direction of the first silicon carbide epitaxial layer 20 toward the second silicon carbide epitaxial layer 30, since the atomic density of metal ions in the first silicon carbide epitaxial layer 20 is higher than that of other components.
In one embodiment, the first silicon carbide epitaxial layer 20 is doped with a plurality of metal ions, wherein the metal ions are classified according to their atomic densities, and the plurality of metal ions include heavy metal ions and light metal ions, and the doping concentration of the heavy metal ions is greater than that of the light metal ions in the region of the first silicon carbide epitaxial layer 20 near the silicon carbide substrate 10 because the atomic densities of the heavy metal ions are greater than that of the light metal ions.
In one embodiment, the first silicon carbide epitaxial layer 20 is also doped with nitrogen ions. Specifically, co-doping of the metal ions and the nitrogen ions may play a role in adjusting the lattice constant of the first silicon carbide epitaxial layer 20, thereby reducing the stacking fault density of the second silicon carbide epitaxial layer 30 epitaxially grown on the first silicon carbide epitaxial layer 20 and significantly improving the yield of the second silicon carbide epitaxial layer 30.
In one embodiment, the nitrogen ions in the first silicon carbide epitaxial layer 20 have a first doping concentration; nitrogen ions in the second silicon carbide epitaxial layer 30 have a second doping concentration; the first doping concentration is greater than the second doping concentration.
In one embodiment, the first doping concentration ranges from 1E18 to 1E19, and the second doping concentration ranges from 1E15 to 2E16. The design can be specifically carried out according to actual needs.
Specifically, in the silicon carbide semiconductor epitaxial wafer 100 provided by the application, the first silicon carbide epitaxial layer 20 with the dislocation density smaller than that of the silicon carbide substrate 10 is formed between the silicon carbide substrate 10 and the second silicon carbide epitaxial layer 30 to serve as the growth surface of the second silicon carbide epitaxial layer 30, so that the probability that crystal dislocation of the silicon carbide substrate 10 extends to or is converted into the second silicon carbide epitaxial layer 30 can be greatly reduced, the yield of the second silicon carbide epitaxial layer 30 is remarkably improved, and a solid foundation is laid for the yield and reliability of subsequent silicon carbide semiconductor devices. In addition, by doping the metal ions and the nitrogen ions in the first silicon carbide epitaxial layer 20, the metal ions can contribute to a melting-assisting effect on the carbon film formed in the precursor process, thereby contributing to the formation of the first silicon carbide epitaxial layer 20, and the co-doping of the metal ions and the nitrogen ions can play a role in adjusting the lattice constant of the first silicon carbide epitaxial layer 20, thereby contributing to a reduction in the stacking fault density of the second silicon carbide epitaxial layer 30 epitaxially grown on the first silicon carbide epitaxial layer 20, and significantly improving the yield of the second silicon carbide epitaxial layer 30.
Referring to fig. 2 and 10, fig. 2 is a schematic flow chart of an embodiment of a method for preparing a silicon carbide semiconductor epitaxial wafer provided in the present application; FIG. 3 is a flowchart illustrating an embodiment of the step S2 in FIG. 2; fig. 4 is a schematic diagram of an intermediate product of the silicon carbide semiconductor epitaxial wafer provided in the present application after step S1; fig. 5 is a schematic diagram of an intermediate product of the silicon carbide semiconductor epitaxial wafer provided in the present application after step S21; fig. 6 is a schematic diagram of an intermediate product of the silicon carbide semiconductor epitaxial wafer provided in the present application in step S22; fig. 7 is a schematic diagram of an intermediate product of the silicon carbide semiconductor epitaxial wafer provided in the present application in step S22; fig. 8 is a schematic diagram of an intermediate product of the silicon carbide semiconductor epitaxial wafer provided in the present application in step S22; fig. 9 is a schematic diagram of an intermediate product of the silicon carbide semiconductor epitaxial wafer provided in the present application after step S22; fig. 10 is a schematic structural diagram of a silicon carbide semiconductor epitaxial wafer provided in the present application after step S3.
Specifically, the present application further provides a method for preparing the silicon carbide semiconductor epitaxial wafer 100, including:
step S1: a silicon carbide substrate 10 is provided.
Referring to fig. 4, where silicon carbide substrate 10 may be a 4H-SiC substrate or a 6H-SiC substrate, the 4H-SiC substrate is preferred in this application because it has higher bulk mobility and has less anisotropy.
In some embodiments, the growth face of the silicon carbide substrate 10 has an angular off-orientation of 2 ° -6 ° along the <11-20> direction. In the present embodiment, the growth face of the silicon carbide substrate 10 has an angular misalignment orientation of 4 ° along the <11-20> direction, and the growth face of the silicon carbide substrate 10 is a silicon (Si) face.
Step S2: a first silicon carbide epitaxial layer 20 is grown on a silicon carbide substrate 10.
Wherein the dislocation density of the first silicon carbide epitaxial layer 20 is less than the dislocation density of the silicon carbide substrate 10.
Wherein, in order to make the dislocation density of the first silicon carbide epitaxial layer 20 smaller than that of the silicon carbide substrate 10, the first silicon carbide epitaxial layer 20 is formed of a carbon film and a silicon film by liquid phase epitaxial growth.
Specifically, by forming the first silicon carbide epitaxial layer 20 with a dislocation density smaller than that of the silicon carbide substrate 10 on the silicon carbide substrate 10 to serve as a growth surface of the second silicon carbide epitaxial layer 30 formed in a subsequent process, the probability of extending or converting crystal dislocation of the silicon carbide substrate 10 into the second silicon carbide epitaxial layer 30 can be greatly reduced, the yield of the second silicon carbide epitaxial layer 30 is remarkably improved, and a solid foundation is laid for subsequently improving the yield and reliability of the silicon carbide semiconductor device.
Referring to fig. 3, in an embodiment, step S2 includes:
step S21: a carbon film 40 is formed on the silicon carbide substrate 10.
In one embodiment, before step S21, the method further includes: and under a third preset condition, introducing a fourth reaction gas into the reaction chamber to perform high-temperature treatment on the silicon carbide substrate 10 placed in the reaction chamber.
The third preset condition is to raise the temperature in the reaction cavity to more than 1600 ℃; the fourth reactive gas comprising an inert gas, e.g. H 2 And/or HCl gas.
Specifically, the silicon carbide substrate 10 provided in step S1 is placed in a reaction chamber of an epitaxial furnace, heated to 1600 ℃ or higher, and the surface (including the growth surface) of the silicon carbide substrate 10 is etched in an inert atmosphere to remove the dirt and processing damage layer on the wafer surface of the silicon carbide substrate 10, so as to provide a clean and flat growth surface for the subsequently formed film.
Referring to fig. 5, in an embodiment, step S21 specifically includes: a reaction gas is introduced into the reaction chamber at a preset temperature range and a preset pressure range to treat the silicon carbide substrate 10 for a preset time, thereby forming the carbon film 40 on the growth surface of the silicon carbide substrate 10.
Wherein the preset temperature range is 1350-1550 ℃ and the preset pressure range is 100-1000 mbar; the reaction gas is inert gas (such as argon or helium) and the preset time range is 5-10min.
Specifically, the temperature in the reaction chamber is reduced from more than 1600 ℃ to 1350-1550 ℃, the silicon carbide substrate 10 is annealed at high temperature for 5-10min in an inert gas atmosphere, and the pressure in the reaction chamber is set to be 100-1000 mbar, so that a carbon film 40 with specific orientation is formed on the growth surface of the silicon carbide substrate 10. This carbon film 40 uniformly covering the growth surface of the silicon carbide substrate 10 provides a deposition surface for the next step in forming a flat and smooth silicon film.
In some embodiments, the second thickness H2 of the carbon film 40 ranges from 10-50nm, for example, may be 10nm, 20nm, 30nm, 40nm, 50nm, or the like, without limitation. Specifically, the carbon film 40 having a certain thickness is used to provide a sufficient carbon source for a silicon film to be formed later.
Step S22: a liquid silicon film 50 is formed on the surface of the carbon film 40, and the liquid silicon film 50 dissolves the carbon film 40 and grows by liquid phase epitaxy to form the first silicon carbide epitaxial layer 20.
Referring to fig. 6 and 7, in an embodiment, step S22 specifically includes: forming a polysilicon film 60 having a first thickness H1 on the carbon film 40; the polysilicon film 60 is subjected to a high temperature treatment to melt the polysilicon film 60 to form the liquid silicon film 50.
Wherein the ratio of the first thickness H1 to the second thickness H2 is 50:1-150:1. in the embodiment of the application, the first thickness H1 is 1000-5000nm. Specifically, the thickness of the polysilicon film 60 cannot be too large, so that the carbon film 40 after dissolution cannot provide a sufficient carbon source for the liquid silicon film 50 formed after dissolution of the polysilicon film 60.
The polysilicon film can be formed by vacuum plating technology or vapor deposition technology.
Of course, the order of forming the carbon film 40 and the polysilicon film 60 may be replaced, and specifically, in another embodiment, step S2 includes: forming a polysilicon film 60 on the silicon carbide substrate 10; forming a carbon film 40 on the surface of the polysilicon film 60; the high temperature process melts the polysilicon film 60 to form the liquid silicon film 50, and the liquid silicon film 50 dissolves the carbon film 40 and grows in liquid phase epitaxy to form the first silicon carbide epitaxial layer 20.
In one embodiment, the step of forming the polysilicon film 60 having the first thickness H1 on the carbon film 40 includes:
referring to fig. 6, under a first preset condition, a first reaction gas including a silicon source gas is introduced into the reaction chamber to form a polysilicon film 60 having a first thickness H1 on the carbon film 40.
Wherein the first preset condition is to continuously cool the temperature in the reaction cavity after the step S21 to the temperature range of 1100-1300 ℃, and introduce SiH4 and SiHCl into the furnace 3 And/or SiH 2 Cl 2 And a first reactive gas containing a silicon source to deposit a polysilicon film 60 having a first thickness H1 on the surface of the carbon film 40.
In one embodiment, the step of performing a high temperature treatment on the polysilicon film 60 to melt the polysilicon film 60 to form the liquid silicon film 50 includes:
referring to fig. 7, the polycrystalline silicon film 60 is subjected to a high temperature process at a preset temperature range and a preset pressure range to melt the polycrystalline silicon film 60 to form a liquid silicon film 50.
Wherein, in the step, the preset temperature range is 1500-1600 ℃ and the preset pressure range is 800-1500 mbar. Specifically, the wafer temperature is raised to 1500-1600 ℃, and the pressure range is set to 800-1500 mbar. So that the solid polysilicon film 60 melts to form the liquid silicon film 50, and the liquid silicon film 50 dissolves the carbon film 40 and grows by liquid phase epitaxy to form the first silicon carbide epitaxial layer 20.
In one embodiment, the first reactive gas further includes a vapor phase halide or organic compound having metal ions to dope the metal ions in the polysilicon film 60 when forming the polysilicon film 60, the doped metal ions may help to assist in the melting of the carbon film 40 formed in the precursor process.
Referring to fig. 8, the liquid silicon film 50 is dissolved to form the carbon film 40 after step S21, and at the same time, the metal ions in the liquid silicon film 50 can increase the solubility of carbon atoms in the melt to form a si—c melt 70 rich in silicon, and a single crystal first silicon carbide epitaxial layer 20 is epitaxially grown on the surface of the silicon carbide substrate 10 in a liquid phase epitaxy mode and a step-flow growth mode using the si—c melt 70 rich in silicon as a reactant.
In some embodiments, the metal ions include at least one of titanium ions, chromium ions, vanadium ions, iron ions, and molybdenum ions.
In one embodiment, the first reactant gas further comprises NH 3 . Specifically, NH is introduced during formation of the polysilicon film 60 3 When the polysilicon film 60 is formed, the polysilicon film 60 is doped with nitrogen ions, and the co-doping of metal ions and nitrogen ions can play a role of adjusting the lattice constant of the first silicon carbide epitaxial layer 20 formed by the subsequent process, so that the stacking fault density of the second silicon carbide epitaxial layer 30 epitaxially grown on the first silicon carbide epitaxial layer 20 is reduced, and the yield of the second silicon carbide epitaxial layer 30 is remarkably improved.
Specifically, in step S22, a silicon source gas (SiH4、SiHCl 3 And/or SiH 2 Cl 2 Etc.), gas phase halides or metal-organic compounds containing metal ions (Ti, cr, V, fe, etc.), and NH 3 To deposit a layer of N and metal ion doped polysilicon film 60 on the surface of the carbon film 40. And in this embodiment, the first reactant gas further comprises H 2 And H is 2 The gas flow rate of (2) is 60-130 slm; the flow rate of the silicon source gas is 50-150 sccm; the doping concentration of metal ions in the polysilicon film 60 is 1E 18-1E 20/cm 3 The doping concentration of N is 1E 18-1E 19/cm 3 。
In one embodiment, the step of dissolving the carbon film 40 in the liquid silicon film 50 and forming the first silicon carbide epitaxial layer 20 by liquid phase epitaxial growth includes:
a second reaction gas containing a carbon source gas is introduced into the reaction chamber to replenish carbon atoms in the liquid silicon film 50, thereby forming the first silicon carbide epitaxial layer 20 having the third thickness H3 by liquid phase epitaxial growth.
Wherein the carbon source gas comprises CH 4 、C 3 H 8 And/or C 2 H 4 And (3) waiting for gas.
Referring to fig. 9, specifically, a carbon source gas is introduced into the reaction chamber, carbon atoms generated by the cracking of the carbon source gas are dissolved in the si—c melt 70 and diffuse toward the epitaxial interface to supplement the carbon atoms required for epitaxy, and the first silicon carbide epitaxial layer 20 is continuously grown upward, which eventually forms the first silicon carbide epitaxial layer 20 having the third thickness H3. The dislocation density (TSD, TED, BPD) in the first silicon carbide epitaxial layer 20 is reduced to less than 40% of the original 4H-SiC substrate while the doping type is co-doped with N ions and metal ions, with a lattice parameter slightly greater than that of the original silicon carbide substrate 10.
In an embodiment, the third thickness H3 is 50-500nm, for example, the third thickness H3 may be 50nm, 100nm, 200nm, 300nm, 400nm, 50nm, or the like, which is not limited herein, and specifically, the first silicon carbide epitaxial layer 20 having the third thickness H3 is used to provide a growth surface for the subsequently formed second silicon carbide epitaxial layer 30, so as to reduce the probability of crystal dislocation of the silicon carbide substrate 10 extending or transforming into the second silicon carbide epitaxial layer 30.
In one embodiment, the second reactant gas further comprises a vapor phase halide or organic compound having a second metal ion; wherein the second metal ion includes at least one of titanium ion, chromium ion, vanadium ion, iron ion, and wood ion.
Specifically, doping with the second metal ions may help to provide a fluxing effect on the carbon film 40 as the liquid silicon film 50 dissolves the carbon film 40. In addition, although both the first metal ion and the second metal ion contribute to the melting-assisting effect on the carbon film 40, doping the second metal ion at the time of forming the liquid silicon film 50 cannot replace doping the first metal ion in forming the polysilicon film 60, and doping unevenness is likely to be caused because the liquid silicon film 50 in the liquid phase has a diffusion effect, so that the first metal ion is doped in the polysilicon film 60, and the metal ion is more uniformly distributed in the polysilicon film 60 than the second metal ion is doped at the time of forming the liquid silicon film 50.
Step S3: a second silicon carbide epitaxial layer 30 is grown on the first silicon carbide epitaxial layer 20.
In one embodiment, before step S3, the method further includes: and (3) terminating the introduction of the carbon source gas into the reaction chamber, and introducing a third reaction gas into the reaction chamber under a second preset condition to remove the liquid silicon film 50 remained on the surface of the first silicon carbide epitaxial layer 20.
The second preset condition is to raise the temperature in the reaction cavity after the step S2 to be more than 1650 ℃.
Wherein the third reaction gas may be H 2 And/or HCl gas. Specifically, the supply of the carbon source into the reaction chamber is stopped, the wafer formed in the step S2 is heated to 1650 ℃ or higher, and H is used 2 And/or HCl etching removes the residual liquid silicon film 50 from the surface of the first silicon carbide epitaxial layer 20 to expose the first silicon carbide epitaxial layer 20.
In one embodiment, step S3 specifically includes: under a fourth preset condition, a fifth reaction gas is introduced into the reaction chamber to form a second silicon carbide epitaxial layer 30 on the surface of the first silicon carbide epitaxial layer 20.
Wherein the fourth preset condition is thatThe temperature range in the reaction chamber is set to 1550-1700 ℃, the pressure range is set to 50-300 mbar, and the fifth reaction gas comprises SiH 4 、SiHCl 3 SiH (SiH) 2 Cl 2 At least one of the gases, and C 3 H 8 、C 2 H 4 At least one of the gases.
Referring to FIG. 10, in particular, siH is introduced into the reaction chamber 4 、SiHCl 3 And/or SiH 2 Cl 2 Gas and C 3 H 8 And/or C 2 H 4 And (3) preparing a second silicon carbide epitaxial layer 30 on the surface of the first silicon carbide epitaxial layer 20 by a CVD method to finally form the silicon carbide semiconductor epitaxial wafer 100 structure, wherein the epitaxial growth pressure in the step is 50-300 mbar, the temperature range is 1550-1700 ℃, and the long speed is 1.5-150 m/h. Since the defect density in the first silicon carbide epitaxial layer 20 is greatly reduced compared with the PVT method SiC silicon carbide substrate 10, the probability of formation of stacking fault defects is greatly reduced by CVD growth of the second silicon carbide epitaxial layer 30 based on the surface of the first silicon carbide epitaxial layer 20.
Specifically, according to the preparation method of the silicon carbide semiconductor epitaxial wafer 100 provided by the application, the first silicon carbide epitaxial layer 20 formed by the carbon film 40 and the liquid silicon film 50 through liquid phase epitaxial growth is formed on the silicon carbide substrate 10 to serve as the growth surface of the second silicon carbide epitaxial layer 30, so that the probability that crystal dislocation of the silicon carbide substrate 10 extends to or is converted into the second silicon carbide epitaxial layer 30 can be greatly reduced, the yield of the second silicon carbide epitaxial layer 30 is remarkably improved, and a solid foundation is laid for subsequently improving the yield and reliability of silicon carbide semiconductor devices. In addition, by doping metal ions and nitrogen ions when preparing the first silicon carbide epitaxial layer 20, the metal ions can help to have a melting-assisting effect on the carbon film 40 formed in the precursor process, thereby helping to form the first silicon carbide epitaxial layer 20, and co-doping of the metal ions and nitrogen ions can have an effect of adjusting the lattice constant of the first silicon carbide epitaxial layer 20, thereby helping to reduce the stacking fault density of the second silicon carbide epitaxial layer 30 epitaxially grown on the first silicon carbide epitaxial layer 20, and significantly improving the yield of the second silicon carbide epitaxial layer 30.
The present application also provides a silicon carbide semiconductor device (not shown), where the silicon carbide semiconductor device includes the silicon carbide semiconductor epitaxial wafer 100 provided in any of the foregoing embodiments, or the silicon carbide semiconductor device is formed by the preparation method of the silicon carbide semiconductor epitaxial wafer 100 provided in any of the foregoing embodiments.
In some embodiments, the silicon carbide semiconductor device may be a planar gate semiconductor device or a trench gate semiconductor device. The planar gate semiconductor device and the trench gate semiconductor device are formed based on the silicon carbide semiconductor epitaxial wafer 100 provided in any of the embodiments of the present application, and other structures in the device are substantially the same as those in the prior art, and are not described herein.
Specifically, the silicon carbide semiconductor device provided by the application adopts the silicon carbide semiconductor epitaxial wafer 100 as the outer edge structure of the device, so that the stacking fault density of the second silicon carbide epitaxial layer 30 can be remarkably reduced, the yield of the second silicon carbide epitaxial layer 30 is improved, and a solid foundation is laid for subsequently improving the yield and reliability of the silicon carbide semiconductor device.
The foregoing description is only of embodiments of the present application, and is not intended to limit the scope of the patent application, and all equivalent structures or equivalent processes using the descriptions and the contents of the present application or other related technical fields are included in the scope of the patent application.
Claims (22)
1. A silicon carbide semiconductor epitaxial wafer, comprising:
a silicon carbide substrate;
the first silicon carbide epitaxial layer is arranged on the silicon carbide substrate;
the second silicon carbide epitaxial layer is arranged on the first silicon carbide epitaxial layer;
wherein the dislocation density of the first silicon carbide epitaxial layer is less than the dislocation density of the silicon carbide substrate.
2. The silicon carbide semiconductor epitaxial wafer of claim 1, wherein the first silicon carbide epitaxial layer is doped with metal ions.
3. The silicon carbide semiconductor epitaxial wafer of claim 2, wherein the metal ions comprise at least one of titanium ions, chromium ions, vanadium ions, and iron ions.
4. A silicon carbide semiconductor epitaxial wafer according to claim 2 or 3, wherein the kind of the metal ions doped in the first silicon carbide epitaxial layer is one, and the doping concentration of the metal ions gradually decreases in the direction of the first silicon carbide epitaxial layer toward the second silicon carbide epitaxial layer.
5. A silicon carbide semiconductor epitaxial wafer according to claim 2 or claim 3 wherein the metal ions doped in said first silicon carbide epitaxial layer are of a plurality of species, wherein a plurality of said metal ions comprise heavy metal ions and light metal ions, and wherein said first silicon carbide epitaxial layer is adjacent to a region of said silicon carbide substrate, said heavy metal ions having a doping concentration greater than that of said light metal ions.
6. The silicon carbide semiconductor epitaxial wafer of claim 2, wherein the first silicon carbide epitaxial layer and the second silicon carbide epitaxial layer are further doped with nitrogen ions.
7. The silicon carbide semiconductor epitaxial wafer of claim 6, wherein nitrogen ions in the first silicon carbide epitaxial layer have a first doping concentration; nitrogen ions in the second silicon carbide epitaxial layer have a second doping concentration;
the first doping concentration is greater than the second doping concentration.
8. The silicon carbide semiconductor epitaxial wafer of claim 7, wherein the first doping concentration ranges from 1E17 to 1E19 and the second doping concentration ranges from 1E14 to 1E18.
9. The silicon carbide semiconductor epitaxial wafer of claim 1, wherein the silicon carbide substrate, the first silicon carbide epitaxial layer, and the second silicon carbide epitaxial layer have a thickness ratio of: 290-500: 0.05 to 0.5:5 to 100.
10. The silicon carbide semiconductor epitaxial wafer of claim 9, wherein the first silicon carbide epitaxial layer has a thickness of 50-500nm.
11. A silicon carbide semiconductor device comprising the silicon carbide semiconductor epitaxial wafer of any one of claims 1 to 10.
12. The preparation method of the silicon carbide semiconductor epitaxial wafer is characterized by comprising the following steps of:
providing a silicon carbide substrate;
forming a first silicon carbide epitaxial layer on the silicon carbide substrate by growth, wherein the first silicon carbide epitaxial layer is formed by liquid phase epitaxial growth of a carbon film and a silicon film;
and growing a second silicon carbide epitaxial layer on the first silicon carbide epitaxial layer.
13. The preparation method of the silicon carbide semiconductor epitaxial wafer is characterized by comprising the following steps of:
providing a silicon carbide substrate;
forming a first silicon carbide epitaxial layer on the silicon carbide substrate;
forming a second silicon carbide epitaxial layer on the first silicon carbide epitaxial layer;
wherein the dislocation density of the first silicon carbide epitaxial layer is less than the dislocation density of the silicon carbide substrate.
14. The method of preparing as claimed in claim 13, wherein the step of growing a first silicon carbide epitaxial layer on the silicon carbide substrate comprises:
forming a carbon film on the silicon carbide substrate;
and forming a liquid silicon film on the surface of the carbon film, wherein the liquid silicon film dissolves the carbon film and forms the first silicon carbide epitaxial layer through liquid phase epitaxial growth.
15. The method according to claim 14, wherein the step of forming a liquid silicon film on the surface of the carbon film includes:
forming a polysilicon film having a first thickness on the carbon film;
and carrying out high-temperature treatment on the polycrystalline silicon film so as to enable the polycrystalline silicon film to be melted to form the liquid silicon film.
16. The method of manufacturing according to claim 15, wherein the step of forming a polysilicon film having a first thickness on the carbon film includes:
and under a first preset condition, introducing a first reaction gas comprising a silicon source gas into the reaction cavity to form a polycrystalline silicon film with the first thickness on the carbon film.
17. The method of claim 16, wherein the first reactant gas further comprises a vapor phase halide or organic compound having a first metal ion;
wherein the first metal ion includes at least one of titanium ion, chromium ion, vanadium ion, iron ion, and molybdenum ion.
18. The method of preparing according to claim 14, wherein the step of dissolving the carbon film in the liquid silicon film and forming the first silicon carbide epitaxial layer by liquid phase epitaxial growth comprises:
and introducing a second reaction gas containing carbon source gas into the reaction cavity to supplement carbon atoms in the liquid silicon film, so that the first silicon carbide epitaxial layer is formed by liquid phase epitaxial growth.
19. The method of claim 18, wherein the second reactant gas further comprises a vapor phase halide or organic compound having a second metal ion;
wherein the second metal ion includes at least one of titanium ion, chromium ion, vanadium ion, iron ion, and molybdenum ion.
20. The method of preparing as claimed in claim 14, wherein before growing the second silicon carbide epitaxial layer on the first silicon carbide epitaxial layer, further comprising:
and stopping introducing carbon source gas into the reaction cavity, and introducing third reaction gas into the reaction cavity under a second preset condition to remove the liquid silicon film remained on the surface of the first silicon carbide epitaxial layer.
21. The method of preparing as claimed in claim 13, wherein the step of growing a first silicon carbide epitaxial layer on the silicon carbide substrate comprises:
forming a polysilicon film on the silicon carbide substrate;
forming a carbon film on the surface of the polysilicon film;
and (3) performing high-temperature treatment to enable the polycrystalline silicon film to be melted to form a liquid silicon film, wherein the liquid silicon film dissolves the carbon film and forms the first silicon carbide epitaxial layer through liquid phase epitaxial growth.
22. The method of producing according to claim 13, further comprising, before the step of forming the carbon film on the silicon carbide substrate:
under a third preset condition, introducing a fourth reaction gas into the reaction cavity to perform high-temperature treatment on the silicon carbide substrate placed in the reaction cavity;
wherein the fourth reaction gas is an inert gas.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311691089.6A CN117878138A (en) | 2023-12-09 | 2023-12-09 | Silicon carbide semiconductor epitaxial wafer, preparation method thereof and silicon carbide semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311691089.6A CN117878138A (en) | 2023-12-09 | 2023-12-09 | Silicon carbide semiconductor epitaxial wafer, preparation method thereof and silicon carbide semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117878138A true CN117878138A (en) | 2024-04-12 |
Family
ID=90583704
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311691089.6A Pending CN117878138A (en) | 2023-12-09 | 2023-12-09 | Silicon carbide semiconductor epitaxial wafer, preparation method thereof and silicon carbide semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117878138A (en) |
-
2023
- 2023-12-09 CN CN202311691089.6A patent/CN117878138A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8927396B2 (en) | Production process of epitaxial silicon carbide single crystal substrate | |
| TWI404123B (en) | Selective epitaxial formation of semiconductor films | |
| CN111029246B (en) | Method for reducing triangular defects in SiC epitaxial layer | |
| WO2011126145A1 (en) | Process for producing epitaxial single-crystal silicon carbide substrate and epitaxial single-crystal silicon carbide substrate obtained by the process | |
| JP5865777B2 (en) | Method for manufacturing silicon carbide epitaxial wafer | |
| US10026610B2 (en) | Silicon carbide semiconductor device manufacturing method | |
| JP2003168689A (en) | Heterojunction bipolar transistor and its manufacturing method | |
| JP2013014469A (en) | Sic epitaxial substrate and method for manufacturing the same | |
| US11114295B2 (en) | Epitaxial silicon carbide single crystal wafer and process for producing the same | |
| CN111681947B (en) | Epitaxial method for reducing stacking fault defects of epitaxial wafer and application thereof | |
| TW201432793A (en) | Method for manufacturing silicon carbide semiconductor substrate and method for manufacturing silicon carbide semiconductor device | |
| JP6702268B2 (en) | Epitaxial wafer manufacturing method | |
| CN114496724A (en) | SiC epitaxial wafer and method for producing SiC epitaxial wafer | |
| JP2002539327A (en) | Method and apparatus for forming a metal oxide on a substrate surface by chemical vapor deposition | |
| JP2911694B2 (en) | Semiconductor substrate and method of manufacturing the same | |
| JP2022020995A (en) | Manufacturing method of silicon carbide epitaxial wafer | |
| CN117878138A (en) | Silicon carbide semiconductor epitaxial wafer, preparation method thereof and silicon carbide semiconductor device | |
| JP4283478B2 (en) | Method for growing SiC single crystal on electronic device substrate | |
| JP2003209059A (en) | Epitaxial silicon single crystal wafer and method of manufacturing the same | |
| KR20230132455A (en) | Method for manufacturing epitaxial wafers | |
| JP2011023502A (en) | Silicon carbide semiconductor device, method of manufacturing the same, and method of manufacturing silicon carbide epitaxial substrate | |
| JP2004281591A (en) | Semiconductor epitaxial wafer, its manufacturing method, semiconductor device, and its manufacturing method | |
| JP3494467B2 (en) | Method of forming semiconductor thin film | |
| WO2012090268A1 (en) | Monocrystalline silicon carbide epitaxial substrate, method for producing same, and monocrystalline sic device | |
| CN111293037B (en) | P-type SiC epitaxy and growth method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination |