CN117873258B - LDO without off-chip capacitor and self-adaptive substrate driving circuit thereof - Google Patents
LDO without off-chip capacitor and self-adaptive substrate driving circuit thereof Download PDFInfo
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Abstract
The invention discloses an off-chip capacitor-free LDO and a self-adaptive substrate driving circuit thereof, relates to a system for adjusting electric variables or magnetic variables, and provides a scheme for solving the problem of poor PSRR lifting in the prior art. The LDO is preceded by a P buffer stage for buffering the control input of the power tube in a feedback control loop and forming a feed-forward path between the control input of the power tube and the power supply ripple. The self-adaptive substrate driving circuit is applied to the LDO, and is used for sampling the output voltage and power supply ripple of the LDO and then injecting the sampled output voltage and power supply ripple into the bottom end of a power tube substrate of the LDO with self-adaptive gain; the circuit state used for following the LDO carries out ripple cancellation with self-adaptive feedforward, and self-adaptive adjustment of feedforward gain is realized. The advantage is that the effect of improving PSRR is achieved by adding a feedforward path to minimize the influence of g m. On the other hand, considering the influence of the gds in the power tube, the sampled power is injected into the substrate end of the power tube by the self-adaptive gain, and the self-adaptive regulation function is realized.
Description
Technical Field
The present invention relates to a system for adjusting an electric variable or a magnetic variable, and more particularly, to an off-chip capacitor-free LDO and an adaptive substrate driving circuit thereof.
Background
A low dropout linear regulator (Low Dropout Regulator, LDO for short).
In recent years, system on chip (Soc) has become more and more important due to the ability to integrate high-speed digital modules, high dynamic range analog modules and radio frequency modules to achieve high efficiency requirements. While a Power Management Unit (PMU) is an integral part, conventional PMUs are typically composed of a switching converter and LDOs, which are typically used to clean up ripple of the switching converter due to their excellent ripple rejection capability, providing clean power to noise sensitive blocks.
However, as switching frequency increases, LDOs need to maintain high Power Supply Rejection Ratio (PSRR) in the mid-high frequency band (Mhz), while off-chip capacitor-free LDOs remove external capacitance in order to reduce area and increase integration, which undoubtedly results in degradation of PSRR because output power supply ripple cannot bypass to ground through external large capacitance.
In the mid-high frequency range, the PSRR of LDOs is mainly limited by two factors: drain-source transconductance g ds and gate-source transconductance g m of the power tube; however, the work in the prior art mainly focuses on g m of the power tube and ignores the effect of g ds, which results in a less than optimal PSRR improvement. In addition, an additional summing circuit is needed to inject the sampled power supply ripple into the LDO body circuit, which consumes more power and increases the complexity of the circuit.
Disclosure of Invention
The present invention is directed to an off-chip capacitor-free LDO and an adaptive substrate driving circuit thereof, so as to solve the above-mentioned problems of the prior art.
The invention discloses an off-chip capacitor-free LDO, which is provided with a P buffer stage in front, wherein the P buffer stage is used for buffering the control input of a power tube in a feedback control loop and enabling a feedforward path to be formed between the control input of the power tube and a power supply ripple.
The invention relates to an off-chip capacitor-free LDO and a self-adaptive substrate driving circuit thereof, which specifically have the following structure:
the non-inverting input end of the error amplifier is connected with the feedback voltage, the inverting input end of the error amplifier is connected with the first reference voltage, and the output end of the error amplifier is connected with the grid electrode of the first MOS tube;
The source electrode of the first MOS tube is connected with the grid node, and the drain electrode of the first MOS tube is grounded;
the source electrode of the second MOS tube is connected with the power supply ripple wave, the drain electrode of the second MOS tube is connected with the grid electrode node, and the grid electrode of the second MOS tube is connected with the power supply ripple wave after passing through a low-pass filter;
the source electrode of the power tube is connected with the power supply ripple, the drain electrode of the power tube is connected with the RC output stage in series and then grounded, and the grid electrode of the power tube is connected with the grid electrode node; the node voltage between the drain electrode of the power tube and the RC output stage is the output voltage;
One end of the first feedback resistor is connected with the output voltage, and the other end of the first feedback resistor is grounded through the second feedback resistor and is used as the output of the first reference voltage to be fed back to the error amplifier;
the P buffer stage consists of a first MOS tube and a second MOS tube, and the second MOS tube is used for forming the feedforward path;
the feedback control loop consists of a first feedback resistor, an error amplifier, a first MOS tube and a power tube.
A miller capacitance is connected in series between the output voltage and the output of the error amplifier, the miller capacitance being used to provide miller compensation.
The first MOS tube, the second MOS tube and the power tube are PMOS tubes.
Setting an adaptive substrate driving circuit, sampling output voltage and power supply ripple, and injecting the sampled output voltage and power supply ripple into the substrate end of the power tube with adaptive gain; the self-adaptive substrate driving circuit is used for carrying out ripple cancellation in a following circuit state through self-adaptive feedforward, and self-adaptive adjustment of feedforward gain is realized.
The specific structure of the self-adaptive substrate driving circuit is as follows:
One end of the first resistor is connected with the power supply ripple, and the other end of the first resistor is connected with the first node;
one end of the second resistor is connected with the first node, and the other end of the second resistor is connected with the mirror image node;
The non-inverting input end of the second transconductance amplifier is connected with the first node, the inverting input end of the second transconductance amplifier is connected with the second reference voltage, and the output end of the second transconductance amplifier is connected with the substrate node;
The substrate end of the power tube is connected with a substrate node;
the source electrode of the first mirror tube is connected with the power supply ripple, the drain electrode of the first mirror tube is connected with the mirror node, the grid electrode of the first mirror tube is connected with the grid electrode node, and the substrate end of the first mirror tube is connected with the substrate node;
the source electrode of the second mirror tube is connected with the power supply ripple, the drain electrode of the second mirror tube is connected with the reference node, the grid electrode of the second mirror tube is connected with the grid electrode node, and the substrate end of the second mirror tube is connected with the second node;
The source electrode of the third MOS tube is connected with the power supply ripple, the drain electrode of the third MOS tube is connected with the second node, and the grid electrode of the third MOS tube is connected with the second node;
The second node is connected in series with a current source and then grounded;
the source electrode of the fourth MOS tube is grounded, the drain electrode of the fourth MOS tube is connected with the mirror image node, and the grid electrode of the fourth MOS tube is connected with the feedback node;
The source electrode of the fifth MOS tube is grounded, the drain electrode of the fifth MOS tube is connected with a reference node, and the grid electrode of the fifth MOS tube is connected with a feedback node;
The non-inverting input end of the second transconductance amplifier is connected with the reference node, the inverting input end of the second transconductance amplifier is connected with the output voltage, and the output end of the second transconductance amplifier is connected with the feedback node.
The first mirror tube, the second mirror tube and the third MOS tube are PMOS tubes, and the fourth MOS tube and the fifth MOS tube are NMOS tubes.
The W/L size ratio of the power tube to the first mirror tube is 1:1200; wherein W/L is the width-to-length ratio of the internal dimensions of the MOS tube.
The fourth MOS tube and the fifth MOS tube have the same size.
The self-adaptive substrate driving circuit is applied to the LDO, and the output voltage and the power supply ripple of the LDO are sampled and then injected into the power tube substrate end of the LDO with self-adaptive gain; the circuit state used for following the LDO carries out ripple cancellation with self-adaptive feedforward, and self-adaptive adjustment of feedforward gain is realized.
The LDO without the off-chip capacitor has the advantages that g m influence of power supply ripple on LDO output is reduced to the minimum by adding the feedforward path, and PSRR is improved. On the other hand, the influence of g ds in the power tube is considered, the sampled power is injected into the substrate end of the power tube by the self-adaptive gain, and the self-adaptive feedforward ripple cancellation method has a self-adaptive adjustment function and self-adaptively adjusts the feedforward gain along with the state of the circuit. Under the condition that no additional summing circuit is needed, the optimal PSRR lifting effect is guaranteed under the full load condition and at each process angle, so that compared with the traditional scheme, the method has stronger robustness, the circuit is relatively simplified, and the power consumption is saved.
The self-adaptive substrate driving circuit has the advantage that the applied LDO realizes the beneficial effects.
Drawings
Fig. 1 is a schematic structural diagram of the LDO according to the present invention.
Fig. 2 is a schematic diagram of the structure of the adaptive substrate driving circuit according to the present invention.
FIG. 3 is a schematic diagram showing the PSRR improving effect of the LDO according to the present invention.
Reference numerals:
An H1-P buffer stage and an H2-self-adaptive substrate driving circuit;
M1-first MOS tube, M2-second MOS tube, M3-third MOS tube, M4-fourth MOS tube, M5-fifth MOS tube;
the power supply comprises an MP-power tube, an Mr 1-first mirror tube and an Mr 2-second mirror tube;
ro-output resistor, R1-first resistor, R2-second resistor, rf 1-first feedback resistor, rf 2-second feedback resistor;
co-output capacitance, cm-Miller capacitance;
an EA-error amplifier, an OTA 1-first transconductance amplifier, an OTA 2-second transconductance amplifier;
Vin-power supply ripple, vo-output voltage, vfb-feedback voltage, vref 1-first reference voltage, vref 2-second reference voltage;
vg-gate node, vy-substrate node, V1-first node, V2-second node, vx-mirror node, va-reference node, vb-feedback node.
Detailed Description
As shown in FIG. 1, the specific structure of the LDO of the present invention is as follows:
The non-inverting input end of the error amplifier EA is connected with the feedback voltage Vfb, the inverting input end of the error amplifier EA is connected with the first reference voltage Vref1, and the output end of the error amplifier EA is connected with the grid electrode of the first MOS tube M1.
The source electrode of the first MOS tube M1 is connected with the grid node Vg, and the drain electrode of the first MOS tube M1 is grounded.
The source electrode of the second MOS tube M2 is connected with the power supply ripple Vin, the drain electrode of the second MOS tube M2 is connected with the grid electrode node Vg, and the grid electrode of the second MOS tube M2 is connected with the power supply ripple Vin after passing through a low-pass filter.
The source electrode of the power tube Mp is connected with the power supply ripple Vin, the drain electrode of the power tube Mp is connected with the RC output stage in series and then grounded, and the grid electrode of the power tube Mp is connected with the grid electrode node Vg. The node voltage between the drain of the power transistor Mp and the RC output stage is the output voltage Vo.
One end of the first feedback resistor Rf1 is connected to the output voltage Vo, and the other end is grounded through the second feedback resistor Rf2 and fed back to the error amplifier EA as an output of the first reference voltage Vref 1.
The P buffer stage H1 consists of a first MOS tube M1 and a second MOS tube M2, and the second MOS tube M2 is used for forming the feedforward path.
The feedback control loop consists of a first feedback resistor Rf1, an error amplifier EA, a first MOS tube M1 and a power tube Mp.
A miller capacitance Cm is connected in series between the output voltage Vo and the output of the error amplifier EA, said miller capacitance Cm being used to provide miller compensation.
The first MOS tube M1, the second MOS tube M2 and the power tube Mp are PMOS tubes.
An adaptive substrate driving circuit H2 is arranged, and the output voltage Vo and the power supply ripple Vin are sampled and then injected into the substrate end of the power tube Mp with adaptive gain.
As shown in fig. 2, the specific structure of the adaptive substrate driving circuit H2 in the present invention is:
one end of the first resistor R1 is connected with the power supply ripple Vin, and the other end of the first resistor R1 is connected with the first node V1.
One end of the second resistor R2 is connected with the first node V1, and the other end is connected with the mirror image node Vx.
The non-inverting input end of the second transconductance amplifier OTA2 is connected with the first node V1, the inverting input end of the second transconductance amplifier OTA2 is connected with the second reference voltage Vref2, and the output end of the second transconductance amplifier OTA2 is connected with the substrate node Vy.
The substrate end of the power tube Mp is connected with the substrate node Vy.
The source electrode of the first mirror image tube Mr1 is connected with the power supply ripple Vin, the drain electrode of the first mirror image tube Mr1 is connected with the mirror image node Vx, the grid electrode of the first mirror image tube Mr1 is connected with the grid electrode node Vg, and the substrate end of the first mirror image tube Mr1 is connected with the substrate node Vy.
The source electrode of the second mirror image tube Mr2 is connected with the power supply ripple Vin, the drain electrode of the second mirror image tube Mr2 is connected with the reference node Va, the grid electrode of the second mirror image tube Mr2 is connected with the grid electrode node Vg, and the substrate end of the second mirror image tube Mr2 is connected with the second node V2.
The source electrode of the third MOS tube M3 is connected with the power supply ripple Vin, the drain electrode of the third MOS tube M3 is connected with the second node V2, and the grid electrode of the third MOS tube M3 is connected with the second node V2.
The second node V2 is connected in series to a current source and then grounded.
The source electrode of the fourth MOS tube M4 is grounded, the drain electrode of the fourth MOS tube M4 is connected with the mirror image node Vx, and the grid electrode of the fourth MOS tube M4 is connected with the feedback node Vb.
The source electrode of the fifth MOS tube M5 is grounded, the drain electrode of the fifth MOS tube M5 is connected with the reference node Va, and the grid electrode of the fifth MOS tube M5 is connected with the feedback node Vb.
The non-inverting input end of the first transconductance amplifier OTA1 is connected with the reference node Va, the inverting input end of the first transconductance amplifier OTA1 is connected with the output voltage Vo, and the output end of the first transconductance amplifier OTA1 is connected with the feedback node Vb.
The first mirror image tube Mr1, the second mirror image tube Mr2 and the third MOS tube M3 are PMOS tubes, and the fourth MOS tube M4 and the fifth MOS tube M5 are NMOS tubes.
The W/L size ratio of the power tube MP to the first mirror image tube Mr1 is 1:1200. Wherein W/L is the width-to-length ratio of the internal dimensions of the MOS tube. The fourth MOS tube M4 and the fifth MOS tube M5 have the same size.
The working principle of the LDO without the off-chip capacitor and the self-adaptive substrate driving circuit thereof in the invention is as follows:
The high gain error amplifier EA ensures high current accuracy, the output voltage Vo and the error amplifier EA output are connected across the miller capacitance Cm to separate the primary and secondary poles. The main pole is placed at the EA output end of the error amplifier, so that stability is ensured. The P buffer stage H1 formed by the first MOS tube M1 and the second MOS tube M2 pushes the pole of the grid electrode of the power tube MP to the outside of the bandwidth. In addition, the grid electrode of the second MOS tube M2 is connected with an RC network to form a low-pass filter, so that a grid electrode direct current working point of the second MOS tube M2 in a static state is ensured. The grid electrode of the second MOS tube M2 in the middle-high frequency range is equivalent to being short-circuited to the ground, the second MOS tube M2 is a common-gate amplifier for the power supply ripple Vin, and is injected into the grid electrode of the power tube Mp after being amplified, so that the effect of eliminating the influence of inter-gate-source transconductance g m of the power tube Mp to achieve the effect of improving PSRR is achieved.
The PSRR lifting effect is shown in fig. 2, and compared with a scheme without any feedforward path, the PSRR can effectively lift 15dB in the 1Mhz frequency band by the method of embedding the feedforward path.
The self-adaptive substrate driving circuit H2 utilizes the characteristic that the transistor is a four-terminal device, and achieves the effect of eliminating the transconductance gds between the drain and the source of the power tube Mp by sampling the power supply ripple Vin and acquiring the output voltage Vo and then injecting the output voltage Vo into the substrate end of the power tube Mp through self-adaptive gain. As shown in fig. 2, after adding the adaptive substrate driving circuit H2, PSRR can be further increased by 25dB in the 1Mhz band. Under the cooperation of the P buffer stage H1 and the self-adaptive substrate driving circuit H2, the 40dB lifting effect can be achieved, and the P buffer stage H1 is remarkably improved compared with the traditional FFRC scheme.
The first mirror tube Mr1 and the second mirror tube Mr2 are mirror tubes of the power tube Mp respectively, and the grid electrodes of the three tubes are in common point to the grid electrode node Vg. The first transconductance amplifier OTA1 makes the direct current voltage of the reference node Va follow the output voltage Vo, so as to ensure that the current of two branches flowing through the fourth MOS transistor M4 and the fifth MOS transistor M5 is proportional to the load current. The first resistor R1 and the second resistor R2 are voltage dividing resistors, and the consistency of direct current levels of the mirror node Vx and the reference node Va is guaranteed. The third MOS transistor M3 is connected in a diode manner, and provides the dc level at the substrate end of the second mirror tube Mr2, and is a current source to ground based on the second node V2, so that the ac impedance of the second node V2 is large, and therefore the ac amplitude of the second node V2 can be considered to completely follow the power ripple Vin.
According to kirchhoff's law, KVL node equations are listed for the mirror node Vx, the reference node Va, and the first node V1, respectively, and solved to obtain:
；
Where g ds2 is the inter-drain-source transconductance of the second mirror tube Mr2, and g mb2 is the inter-liner-source transconductance of the second mirror tube Mr 2. Since the second mirror image tube Mr2 and the power tube Mp are in mirror image proportion relationship, g mb2 and g ds are also in preset proportion relationship. Therefore, the information of the transconductance g ds between the drain and the source can be sampled at the substrate node Vy, the substrate node Vy is directly connected to the substrate end of the power tube Mp, and the feedforward ripple is injected to realize cancellation, so that the effect of further improving the PSRR is achieved. The ripple gain can adaptively change along with the change of the load current and the working state of the power tube, and has strong robustness.
It will be apparent to those skilled in the art from this disclosure that various other changes and modifications can be made which are within the scope of the invention as defined in the appended claims.
Claims (7)
1. An off-chip capacitor-free LDO, characterized by a P-buffer stage (H1) arranged in front of the LDO, the P-buffer stage (H1) being configured to buffer a control input of a power transistor (Mp) in a feedback control loop and to form a feed-forward path between the control input of the power transistor (Mp) and a power supply ripple (Vin);
The non-inverting input end of the Error Amplifier (EA) is connected with the feedback voltage (Vfb), the inverting input end of the Error Amplifier (EA) is connected with the first reference voltage (Vref 1), and the output end of the Error Amplifier (EA) is connected with the grid electrode of the first MOS tube (M1);
The source electrode of the first MOS tube (M1) is connected with a grid node (Vg), and the drain electrode of the first MOS tube (M1) is grounded;
The source electrode of the second MOS tube (M2) is connected with the power supply ripple wave (Vin), the drain electrode of the second MOS tube (M2) is connected with the grid electrode node (Vg), and the grid electrode of the second MOS tube (M2) is connected with the power supply ripple wave (Vin) after passing through a low-pass filter;
The source electrode of the power tube (Mp) is connected with the power supply ripple wave (Vin), the drain electrode of the power tube (Mp) is connected with the RC output stage in series and then grounded, and the grid electrode of the power tube (Mp) is connected with the grid electrode node (Vg); the node voltage between the drain of the power tube (Mp) and the RC output stage is the output voltage (Vo);
One end of the first feedback resistor (Rf 1) is connected with the output voltage (Vo), and the other end of the first feedback resistor (Rf 1) is grounded through the second feedback resistor (Rf 2) and is used as the output of the first reference voltage (Vref 1) to be fed back to the Error Amplifier (EA);
The P buffer stage (H1) consists of a first MOS tube (M1) and a second MOS tube (M2), and the second MOS tube (M2) is used for forming the feedforward path;
the feedback control loop consists of a first feedback resistor (Rf 1), an Error Amplifier (EA), a first MOS tube (M1) and a power tube (Mp);
Setting an adaptive substrate driving circuit (H2), sampling the output voltage (Vo) and the power supply ripple (Vin), and injecting the sampled output voltage (Vo) and the power supply ripple (Vin) to the substrate end of the power tube (Mp) with adaptive gain; the self-adaptive substrate driving circuit (H2) is used for carrying out ripple cancellation by self-adaptive feedforward according to the state of the circuit, so as to realize self-adaptive adjustment of feedforward gain;
The specific structure of the self-adaptive substrate driving circuit (H2) is as follows:
One end of the first resistor (R1) is connected with the power supply ripple (Vin), and the other end of the first resistor is connected with the first node (V1);
one end of the second resistor (R2) is connected with the first node (V1), and the other end of the second resistor is connected with the mirror image node (Vx);
The non-inverting input end of the second transconductance amplifier (OTA 2) is connected with the first node (V1), the inverting input end of the second transconductance amplifier (OTA 2) is connected with the second reference voltage (Vref 2), and the output end of the second transconductance amplifier (OTA 2) is connected with the substrate node (Vy);
The substrate end of the power tube (Mp) is connected with a substrate node (Vy);
The source electrode of the first mirror image tube (Mr 1) is connected with the power supply ripple (Vin), the drain electrode of the first mirror image tube (Mr 1) is connected with the mirror image node (Vx), the grid electrode of the first mirror image tube (Mr 1) is connected with the grid electrode node (Vg), and the substrate end of the first mirror image tube (Mr 1) is connected with the substrate node (Vy);
The source electrode of the second mirror image tube (Mr 2) is connected with the power supply ripple (Vin), the drain electrode of the second mirror image tube (Mr 2) is connected with the reference node (Va), the grid electrode of the second mirror image tube (Mr 2) is connected with the grid electrode node (Vg), and the substrate end of the second mirror image tube (Mr 2) is connected with the second node (V2);
The source electrode of the third MOS tube (M3) is connected with the power supply ripple wave (Vin), the drain electrode of the third MOS tube (M3) is connected with the second node (V2), and the grid electrode of the third MOS tube (M3) is connected with the second node (V2);
The second node (V2) is connected in series with a current source and then grounded;
the source electrode of the fourth MOS tube (M4) is grounded, the drain electrode of the fourth MOS tube (M4) is connected with the mirror image node (Vx), and the grid electrode of the fourth MOS tube (M4) is connected with the feedback node (Vb);
The source electrode of the fifth MOS tube (M5) is grounded, the drain electrode of the fifth MOS tube (M5) is connected with the reference node (Va), and the grid electrode of the fifth MOS tube (M5) is connected with the feedback node (Vb);
The non-inverting input end of the first transconductance amplifier (OTA 1) is connected with the reference node (Va), the inverting input end of the first transconductance amplifier (OTA 1) is connected with the output voltage (Vo), and the output end of the first transconductance amplifier (OTA 1) is connected with the feedback node (Vb).
2. The LDO of claim 1, wherein a miller capacitance (Cm) is connected in series between the output voltage (Vo) and the output of the Error Amplifier (EA), said miller capacitance (Cm) being configured to provide miller compensation.
3. The non-off-chip capacitor type LDO of claim 2, wherein the first MOS tube (M1), the second MOS tube (M2) and the power tube (Mp) are PMOS tubes.
4. The non-on-chip capacitor type LDO of claim 1, wherein the first mirror tube (Mr 1), the second mirror tube (Mr 2) and the third MOS tube (M3) are PMOS tubes, and the fourth MOS tube (M4) and the fifth MOS tube (M5) are NMOS tubes.
5. The LDO of claim 4, wherein the W/L size ratio of the power transistor (Mp) and the first mirror transistor (Mr 1) is 1:1200; wherein W/L is the width-to-length ratio of the internal dimensions of the MOS tube.
6. The non-off-chip capacitor type LDO of claim 4, wherein the fourth MOS transistor (M4) and the fifth MOS transistor (M5) are the same size.
7. An adaptive substrate driving circuit applied to the LDO of any of claims 1-4, sampling the output voltage (Vo) and the power supply ripple (Vin) of the LDO, and injecting the sampled output voltage (Vo) and the power supply ripple (Vin) into a power transistor (Mp) substrate end of the LDO with adaptive gain; the circuit state used for following the LDO carries out ripple cancellation with self-adaptive feedforward, and self-adaptive adjustment of feedforward gain is realized.
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| CN114415771A (en) * | 2022-01-10 | 2022-04-29 | 桂林电子科技大学 | Low-ripple off-chip capacitor digital LDO circuit |
| CN114967811A (en) * | 2022-06-10 | 2022-08-30 | 电子科技大学 | Off-chip capacitor LDO (low dropout regulator) capable of improving PSR (power supply rejection) performance |
| CN116719382A (en) * | 2023-08-09 | 2023-09-08 | 成都通量科技有限公司 | High PSR's off-chip capacitor LDO circuit |
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