CN109194326B - Circuit for improving power supply rejection ratio of linear stabilized power supply - Google Patents
Circuit for improving power supply rejection ratio of linear stabilized power supply Download PDFInfo
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- CN109194326B CN109194326B CN201811170682.5A CN201811170682A CN109194326B CN 109194326 B CN109194326 B CN 109194326B CN 201811170682 A CN201811170682 A CN 201811170682A CN 109194326 B CN109194326 B CN 109194326B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L1/00—Stabilisation of generator output against variations of physical values, e.g. power supply
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L5/00—Automatic control of voltage, current, or power
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Abstract
The invention relates to a circuit for improving the power supply rejection ratio of a linear stabilized power supply, which is formed by connecting an error amplifier EA, an output power tube MP, feedback resistors R1 and R2, a Miller compensation capacitor Cc, an output load impedance ZL, a buffer Mpb, a power supply feedforward transistor Mpc, a bias transistor Mpbi, a bias current IB, a filter capacitor Cf and a filter resistor Rt. The invention has simple and reasonable structural design, cuts off the signal feedforward path from the output end of the error amplifier EA to the power output end Vo through the miller compensation capacitor Cc, but keeps the signal feedback path from the power output end Vo to the output end of the error amplifier EA through the miller compensation capacitor Cc, and couples the alternating current signal 1:1 on the power supply to the grid electrode of the power tube, thereby ensuring that the output power tube MP has no amplification effect on the alternating current signal on the power supply, effectively improving the minimum value of the power supply rejection ratio of the linear stabilized power supply, and reducing the influence of power supply jitter on the output of the linear stabilized power supply.
Description
Technical Field
The invention belongs to the field of analog integrated circuits, and particularly relates to a circuit for improving the power supply rejection ratio of a linear stabilized power supply.
Background
The linear voltage-stabilizing power supply circuit is widely used in a power supply system of a chip system with excellent voltage-stabilizing performance, reduces the overall power supply quantity of the system, provides required power supply voltage for different modules or circuits, and simultaneously avoids noise or jitter between the non-communication modules from interfering with each other through a power supply. The linear stabilized voltage power supply circuit is one of the most widely used analog circuits, and improves the power supply rejection ratio of the linear stabilized voltage power supply circuit, so that the influence of power supply jitter on a load circuit is very practical.
Fig. 2 shows a typical conventional linear regulated power supply circuit structure, which is composed of an error amplifier EA, an output power tube MP, feedback networks R1 and R2, a miller compensation capacitor Cc, and an output load impedance ZL. As the frequency increases, the power supply rejection ratio Vo/VDD decreases gradually due to the decrease in the gain of the feedback loop, and the minimum power supply rejection ratio also causes the entire circuit to lose its power supply jitter rejection effect due to the decrease in the impedance of the miller compensation capacitor Cc at high frequencies. The minimum value of the power supply rejection ratio may be generally expressed as:
wherein gmp is transconductance of the power tube MP, ZL is load impedance of the linear stabilized power supply; typically, the value of gmp ZL is much greater than 1 at the minimum frequency of PSRR, and therefore the above equation may be approximately equal to 1, indicating that near this frequency, the linear regulated power supply has no suppressing effect on jitter or noise on the power supply.
According to the linear stabilized power supply adopting the miller compensation capacitor Cc, as the frequency is increased, the impedance of the miller compensation capacitor Cc is reduced, so that the first-stage output and the second-stage output of the linear stabilized voltage are short-circuited together, and as a result, the power supply rejection ratio is close to 0dB when the power supply rejection ratio is the lowest, and jitter near the frequency on the power supply is easily transferred to an output end, so that the load circuit of the linear stabilized power supply is influenced.
Disclosure of Invention
The invention aims to solve the problems in the background technology center, and provides the circuit for improving the power supply rejection ratio of the linear stabilized power supply, which has simple and reasonable structural design and can effectively improve the minimum value of the power supply rejection ratio of the linear stabilized power supply, reduce the influence of power supply jitter on the output of the linear stabilized power supply.
The technical scheme of the invention is as follows:
the circuit for improving the power supply rejection ratio of the linear stabilized power supply is formed by connecting an error amplifier EA, an output power tube MP, feedback resistors R1 and R2, a Miller compensation capacitor Cc, an output load impedance ZL, a buffer Mpb, a power supply feedforward transistor Mpc, a bias transistor Mpbi, a bias current IB, a filter capacitor Cf and a filter resistor Rt;
one end of the output load impedance ZL is grounded, and the other end of the output load impedance ZL is connected with the power output end Vo; one end of the feedback resistor R2 is grounded, and the other end of the feedback resistor R2 is connected with one end of the feedback resistor R1; the other end of the resistor R1 is connected with the power output end Vo; the inverting input end of the error amplifier EA is connected with a reference power supply Vref, the non-inverting input end of the error amplifier EA is connected with a connection point of the feedback resistor R1 and the feedback resistor R2, and the output end of the error amplifier EA is connected with the grid electrode of the output power tube MP; the source electrode of the output power tube MP is connected with the power supply VDD, and the drain electrode of the output power tube MP is connected with the power supply output end Vo; the grid electrode of the buffer Mpb is connected with the power supply output end Vo, the drain electrode is grounded, and the source electrode is connected with the drain electrode of the power supply feedforward transistor Mpc; the source electrode of the power feedforward transistor Mpc is connected with a power supply VDD, the grid electrode of the power feedforward transistor Mpc is connected with the filter resistor Rt and is connected with the grid electrode of the bias transistor Mpbi through the filter resistor Rt; the source electrode of the bias transistor Mpbi is connected with a power supply VDD, and the drain electrode of the bias transistor Mpbi is connected with one end of the bias current IB; the other end of the bias current IB is grounded; one end of the miller compensation capacitor Cc is connected to a connection point between the output end of the error amplifier EA and the gate of the output power transistor MP, and the other end of the miller compensation capacitor Cc is connected to a connection point between the source of the buffer Mpb and the source of the power feedforward transistor Mpc; one end of the filter capacitor Cf is grounded, and the other end of the filter capacitor Cf is connected to a connection point between the filter resistor Rt and the gate of the power feedforward transistor Mpc.
The beneficial effects are that:
the circuit for improving the power supply rejection ratio of the linear stabilized power supply is simple and reasonable in structural design, a signal feedforward path from the output end of the error amplifier EA to the output end Vo of the power supply through the miller compensation capacitor Cc is cut off, but a signal feedback path from the output end Vo of the power supply to the output end of the error amplifier EA through the miller compensation capacitor Cc is reserved, and an alternating current signal 1:1 on the power supply is coupled to the grid electrode of the power tube, so that the output power tube MP has no amplification effect on the alternating current signal on the power supply, the minimum value of the power supply rejection ratio of the linear stabilized power supply can be effectively improved, and the influence of power supply jitter on the output of the linear stabilized power supply is reduced;
the specific advantages are realized in the following aspects:
(1) By adopting the method of the first-stage buffer Mpb, the path from the first-stage output to the second-stage output (the output end of the first stage refers to the output end of EA, and the output end of the second stage is the output end Vo of LDO) is cut off while the effect of the Miller compensation capacitor Cc is kept;
(2) The jitter on the power supply is coupled to the grid electrode of the output power tube MP through the amplification action of the power supply feedforward transistor Mpc and the coupling action of the capacitor Cc at high frequency, so that the amplification action of the power supply jitter at high frequency of the output power tube MP is reduced.
Drawings
FIG. 1 is a circuit diagram of a circuit for increasing the power supply rejection ratio of a linear stabilized power supply in accordance with the present invention;
fig. 2 is a schematic diagram of a typical linear voltage-stabilized power supply circuit in the prior art.
Detailed Description
As shown in FIG. 1, the circuit for improving the power supply rejection ratio of the linear stabilized power supply is composed of an error amplifier EA, an output power tube MP, feedback resistors R1 and R2, a Miller compensation capacitor Cc, an output load impedance ZL, a buffer Mpb, a power supply feedforward transistor Mpc, a bias transistor Mpbi, a bias current IB, a filter capacitor Cf and a filter resistor Rt which are connected.
One end of the output load impedance ZL is grounded, and the other end of the output load impedance ZL is connected with the power output end Vo; one end of the feedback resistor R2 is grounded, and the other end of the feedback resistor R2 is connected with one end of the feedback resistor R1; the other end of the resistor R1 is connected with the power output end Vo; the inverting input end of the error amplifier EA is connected with a reference power supply Vref, the non-inverting input end of the error amplifier EA is connected with a connection point of the feedback resistor R1 and the feedback resistor R2, and the output end of the error amplifier EA is connected with the grid electrode of the output power tube MP; the source electrode of the output power tube MP is connected with the power supply VDD, and the drain electrode is connected with the power supply output end Vo; the grid electrode of the buffer Mpb is connected with the power supply output end Vo, the drain electrode of the buffer Mpb is grounded, the source electrode of the buffer Mpb is connected with the drain electrode of the power supply feedforward transistor Mpc, the source electrode of the power supply feedforward transistor Mpc is connected with the power supply VDD, the grid electrode of the power supply feedforward transistor Mpc is connected with the filter resistor Rt and is connected with the grid electrode of the bias transistor Mpbi through the filter resistor Rt, the source electrode of the bias transistor Mpbi is connected with the power supply VDD, the drain electrode of the bias transistor Mpbi is connected with one end of the bias current IB, and the other end of the bias current IB is grounded; one end of the miller compensation capacitor Cc is connected to a connection point between the output end of the error amplifier EA and the gate of the output power transistor MP, and the other end of the miller compensation capacitor Cc is connected to a connection point between the source of the buffer Mpb and the source of the power feedforward transistor Mpc; one end of the filter capacitor Cf is grounded, and the other end is connected to a connection point between the filter resistor Rt and the gate of the power feed-forward transistor Mpc.
The working principle of the invention is as follows:
on the basis of the conventional circuit, as shown in fig. 1, on one hand, the voltage output end Vo is connected with the miller compensation capacitor Cc through the buffer Mpb, so that a feedforward path from the output of the error amplifier EA to the output Vo through the miller compensation capacitor Cc is cut off, but a feedback path from the voltage output end Vo to the output end of the error amplifier EA is reserved, so that the miller compensation effect of the miller compensation capacitor Cc is reserved; on the other hand, at high frequency, due to the filtering action of the filter capacitor Cf and the filter resistor Rt, the gate of the power supply feedforward transistor Mpc is approximately ac, the source of the power supply feedforward transistor Mpc is the power supply ac input, because the buffer Mpb and the power supply feedforward transistor Mpc have the same dc current (the dc current of which is determined by the bias voltage VB generated by the bias current IB and the bias transistor Mpbi), if the buffer Mpb and the power supply feedforward transistor Mpc have the same size, they will have the same transconductance, and thus the gain of VBUF from the power supply VDD to the connection point VBUF between the source of the buffer Mpb and the drain of the power supply feedforward transistor Mpc through the power supply feedforward transistor Mpc is 1;
by combining the above two points, at high frequency, the ac voltage at the source-drain connection point VBUF of the buffer Mpb and the output terminal Vo1 of the power feedforward transistor Mpc is vo+vdd (Vo, VDD represent the ac signal at the output terminal Vo and the power supply VDD, respectively), so it can be deduced that the power supply rejection ratio PSRR at this time will be equal to 0 (in reality, due to the capacitance Cgd between the gate and the drain of the output power transistor MP and the resistance between the source and the drain, there is still an ac signal transmitted from the power supply VDD to the power supply output terminal Vo, resulting in the output ac signal being not 0, but this signal is very small, which is far smaller than the ac signal at the output terminal in the conventional circuit).
The invention has simple and reasonable structural design, cuts off the signal feedforward path from the output end of the error amplifier EA to the power output end Vo through the miller compensation capacitor Cc, but keeps the signal feedback path from the power output end Vo to the output end of the error amplifier EA through the miller compensation capacitor Cc, and couples the alternating current signal on the power supply to the grid electrode of the power tube through the power feedforward transistor Mpc and the miller compensation capacitor Cc1:1, thereby ensuring that the output power tube MP has no amplification effect on the alternating current signal on the power supply, effectively improving the minimum value of the power supply rejection ratio of the linear stabilized power supply, and reducing the influence of power supply jitter on the output of the linear stabilized power supply.
Claims (1)
1. The circuit for improving the power supply rejection ratio of the linear stabilized power supply is characterized by comprising an error amplifier EA, an output power tube MP, feedback resistors R1 and R2, a Miller compensation capacitor Cc, an output load impedance ZL, a buffer Mpb, a power supply feedforward transistor Mpc, a bias transistor Mpbi, a bias current IB, a filter capacitor Cf and a filter resistor Rt which are connected;
one end of the output load impedance ZL is grounded, and the other end of the output load impedance ZL is connected with the power output end Vo;
one end of the feedback resistor R2 is grounded, and the other end of the feedback resistor R2 is connected with one end of the feedback resistor R1;
the other end of the resistor R1 is connected with the power output end Vo;
the inverting input end of the error amplifier EA is connected with a reference power supply Vref, the non-inverting input end of the error amplifier EA is connected with a connection point of the feedback resistor R1 and the feedback resistor R2, and the output end of the error amplifier EA is connected with the grid electrode of the output power tube MP;
the source electrode of the output power tube MP is connected with the power supply VDD, and the drain electrode of the output power tube MP is connected with the power supply output end Vo;
the grid electrode of the buffer Mpb is connected with the power supply output end Vo, the drain electrode is grounded, and the source electrode is connected with the drain electrode of the power supply feedforward transistor Mpc;
the source electrode of the power feedforward transistor Mpc is connected with a power supply VDD, the grid electrode of the power feedforward transistor Mpc is connected with the filter resistor Rt and is connected with the grid electrode of the bias transistor Mpbi through the filter resistor Rt;
the source electrode of the bias transistor Mpbi is connected with a power supply VDD, and the drain electrode of the bias transistor Mpbi is connected with one end of the bias current IB;
the other end of the bias current IB is grounded;
one end of the miller compensation capacitor Cc is connected to a connection point between the output end of the error amplifier EA and the gate of the output power transistor MP, and the other end of the miller compensation capacitor Cc is connected to a connection point between the source of the buffer Mpb and the source of the power feedforward transistor Mpc;
one end of the filter capacitor Cf is grounded, and the other end of the filter capacitor Cf is connected to a connection point of the filter resistor Rt and the grid electrode of the power feedforward transistor Mpc;
the alternating current signals 1:1 on the power supply are coupled to the grid electrode of the output power tube.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811170682.5A CN109194326B (en) | 2018-10-09 | 2018-10-09 | Circuit for improving power supply rejection ratio of linear stabilized power supply |
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| CN201811170682.5A CN109194326B (en) | 2018-10-09 | 2018-10-09 | Circuit for improving power supply rejection ratio of linear stabilized power supply |
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| CN109194326B true CN109194326B (en) | 2023-11-03 |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110502053B (en) * | 2019-08-28 | 2020-12-18 | 南京凯鼎电子科技有限公司 | Linear voltage regulator with high power supply voltage rejection ratio |
| CN112684844B (en) * | 2019-10-18 | 2022-08-16 | 圣邦微电子（北京）股份有限公司 | Low dropout regulator |
| CN110794910B (en) * | 2019-11-14 | 2021-08-13 | 芯原微电子(上海)股份有限公司 | Low dropout voltage regulator circuit and method thereof |
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| CN208424340U (en) * | 2018-10-09 | 2019-01-22 | 成都信息工程大学 | A kind of circuit improving linear stabilized power supply power supply rejection ratio |
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| US6690147B2 (en) * | 2002-05-23 | 2004-02-10 | Texas Instruments Incorporated | LDO voltage regulator having efficient current frequency compensation |
| US20040124909A1 (en) * | 2002-12-31 | 2004-07-01 | Haider Nazar Syed | Arrangements providing safe component biasing |
| US7502719B2 (en) * | 2007-01-25 | 2009-03-10 | Monolithic Power Systems, Inc. | Method and apparatus for overshoot and undershoot errors correction in analog low dropout regulators |
| US7583133B2 (en) * | 2008-01-25 | 2009-09-01 | Texas Instruments Incorporated | Self-oscillating regulated low-ripple charge pump and method |
| GB0912745D0 (en) * | 2009-07-22 | 2009-08-26 | Wolfson Microelectronics Plc | Improvements relating to DC-DC converters |
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| CN101078943A (en) * | 2007-05-15 | 2007-11-28 | 北京中星微电子有限公司 | Voltage controlled current source and low voltage difference regulated power supply installed with same |
| CN108052153A (en) * | 2018-01-26 | 2018-05-18 | 成都市海芯微纳电子科技有限公司 | The LDO linear voltage regulators of New-type CMOS structure |
| CN208424340U (en) * | 2018-10-09 | 2019-01-22 | 成都信息工程大学 | A kind of circuit improving linear stabilized power supply power supply rejection ratio |
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