CN208424340U - A kind of circuit improving linear stabilized power supply power supply rejection ratio - Google Patents
A kind of circuit improving linear stabilized power supply power supply rejection ratio Download PDFInfo
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- CN208424340U CN208424340U CN201821629859.9U CN201821629859U CN208424340U CN 208424340 U CN208424340 U CN 208424340U CN 201821629859 U CN201821629859 U CN 201821629859U CN 208424340 U CN208424340 U CN 208424340U
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Abstract
The utility model relates to a kind of circuits for improving linear stabilized power supply power supply rejection ratio, are connected and are formed by error amplifier EA, output power pipe MP, feedback resistance R1 and R2, miller compensation capacitor Cc, output load impedance ZL, buffer Mpb, power supply feedforward transistor Mpc, biasing transistor Mpbi, bias current IB, filter capacitor Cf, filter resistance Rt.The design of the utility model structure is simple, reasonable, the signal feedforward path that error amplifier EA output end passes through miller compensation capacitor Cc to power output end Vo is cut off, but retains power output end Vo and pass through the signal feedback network of miller compensation capacitor Cc to error amplifier EA output end, couple the AC signal 1:1 on power supply to the grid of power tube, to allow output power pipe MP there is no amplification to the AC signal on power supply, the minimum value of linear stabilized power supply power supply rejection ratio can be effectively improved, the influence that power jitter exports linear stabilized power supply is reduced.
Description
Technical field
The utility model belongs to field of analog integrated circuit, and in particular to a kind of raising linear stabilized power supply power supply rejection ratio
Circuit.
Background technique
Linear voltage-stabilized power supply circuit is subtracted by wide hair in the power supply system of chip system with its excellent voltage regulation performance
The power supply quantity of few system entirety, provides required supply voltage for different module or circuit, while avoiding obstructed module
Between noise or shake interfered with each other by power supply.Linear voltage-stabilized power supply circuit is to use one of widest analog circuit,
Its power supply rejection ratio is improved, so that reducing influence of the power jitter to load circuit has very practical meaning.
It is illustrated in figure 2 existing typical linear voltage-stabilized power supply circuit structure, by error amplifier EA, output power pipe
MP, feedback network R1, R2, miller compensation capacitor Cc, output load impedance ZL composition.With the increase of frequency, power supply inhibits
It is gradually reduced than Vo/VDD meeting because of the gain reduction of feedback control loop, the power supply rejection ratio at minimum can also be because of miller compensation
Capacitor Cc is reduced in the impedance of high frequency treatment, and entire circuit is caused to lose the inhibiting effect to power jitter.Power supply rejection ratio
Minimum value can be expressed substantially are as follows:
Gmp is the mutual conductance of power tube MP in above formula, and ZL is the load impedance of linear stabilized power supply；Under normal conditions, exist
At the minimum value frequency of PSRR, the value of gmp*ZL is all bigger than 1 many, therefore above formula can be approximately equal to 1, show attached in this frequency
Closely, linear stabilized power supply on power supply shake or noise there is no inhibiting effect.
This linear stabilized power supply using miller compensation capacitor Cc, with the increase of frequency, miller compensation capacitor Cc's
Impedance reduces, and is shorted together so that the linear voltage stabilization voltage first order is exported with second level output, as a result its power supply rejection ratio
Close to 0dB when minimum, the shake on power supply near this frequency will be easy to be transmitted to output end, bear to linear stabilized power supply
Circuit is carried to impact.
Summary of the invention
The utility model proposes a kind of structure design letter to solve the problems, such as that background above technique center exists
It is single, reasonable, the minimum value of linear stabilized power supply power supply rejection ratio can be effectively improved, it is defeated to linear stabilized power supply to reduce power jitter
The circuit of the raising linear stabilized power supply power supply rejection ratio of influence out.
The technical solution of the utility model is as follows:
The circuit of above-mentioned raising linear stabilized power supply power supply rejection ratio, by error amplifier EA, output power pipe MP, anti-
Feed resistance R1 and R2, miller compensation capacitor Cc, output load impedance ZL, buffer Mpb, power supply feedforward transistor Mpc, biasing are brilliant
Body pipe Mpbi, bias current IB, filter capacitor Cf, filter resistance Rt connection composition；
The one end output load impedance ZL ground connection, the other end connect power output end Vo；The one end the feedback resistance R2
Ground connection, the other end connect the one end the feedback resistance R1；The resistance R1 other end connects power output end Vo；The error is put
The inverting input terminal of big device EA connects reference power supply Vref, and the non-inverting input terminal of the error amplifier EA is connected to the feedback
The tie point of resistance R1 and feedback resistance R2, the output end of the error amplifier EA connect the grid of the output power pipe MP
Pole；The source electrode of the output power pipe MP connects power vd D, drain electrode connection power output end Vo；The grid of the buffer Mpb
Power output end Vo, grounded drain are connected, source electrode connects the drain electrode of the power supply feedforward transistor Mpc；The power supply feedforward is brilliant
The source electrode of body pipe Mpc connects power vd D, and the grid connection filter resistance Rt is simultaneously described partially by the filter resistance Rt connection
Set the grid of transistor Mpbi；The source electrode of the biasing transistor Mpbi connects power vd D, and drain electrode connects the bias current IB
One end；The bias current IB other end ground connection；Described one end miller compensation capacitor Cc is connected to the error amplifier EA's
The tie point of the grid of output end and the output power pipe MP, the other end of the miller compensation capacitor Cc are connected to described slow
Rush the tie point of the source electrode of device Mpb and the source electrode of power supply feedforward transistor Mpc；The one end filter capacitor Cf ground connection, separately
One end is connected to the tie point of the grid of the filter resistance Rt and power supply feedforward transistor Mpc.
The utility model has the advantages that
The circuit structure design that the utility model improves linear stabilized power supply power supply rejection ratio is simple, reasonable, has cut off accidentally
Poor amplifier EA output end passes through the signal feedforward path of miller compensation capacitor Cc to power output end Vo, but retains power supply output
Hold Vo by the signal feedback network of miller compensation capacitor Cc to error amplifier EA output end, by the AC signal 1 on power supply:
1 is coupled to the grid of power tube, so that output power pipe MP be allowed not have amplification to the AC signal on power supply, can effectively mention
The minimum value of High Linear regulated power supply power supply rejection ratio reduces the influence that power jitter exports linear stabilized power supply；
Specific advantage is embodied in following several respects:
(1) by using the method for first-level buffer device Mpb, while remaining miller compensation capacitor Cc effect, cutting
Being output to the access that the second level exports from the first order, (output of the first order refers to that the output end of EA, the output end of the second level are LDO
Output end vo)；
(2) high frequency when by power supply feedover transistor Mpc amplification and capacitor Cc coupling, will be on power supply
Dithered coupling to output power pipe MP grid, to the amplification of power jitter when reducing output power pipe MP high frequency.
Detailed description of the invention
Fig. 1 is the circuit diagram for the circuit that the utility model improves linear stabilized power supply power supply rejection ratio；
Fig. 2 is existing typical linear voltage-stabilized power supply circuit structural schematic diagram.
Specific embodiment
As shown in Figure 1, the utility model improve linear stabilized power supply power supply rejection ratio circuit, by error amplifier EA,
Output power pipe MP, feedback resistance R1 and R2, miller compensation capacitor Cc, output load impedance ZL, buffer Mpb, power supply feedforward
Transistor Mpc, biasing transistor Mpbi, bias current IB, filter capacitor Cf, filter resistance Rt connection composition.
The one end output load impedance ZL ground connection, the other end connect power output end Vo；The one end feedback resistance R2 ground connection,
The other end connects the one end feedback resistance R1；The resistance R1 other end connects power output end Vo；The reverse phase of error amplifier EA
Input terminal connects reference power supply Vref, and the non-inverting input terminal of error amplifier EA is connected to feedback resistance R1 and feedback resistance R2
Tie point, error amplifier EA output end connection output power pipe MP grid；The source electrode of output power pipe MP connects
Meet power vd D, drain electrode connection power output end Vo；The grid of buffer Mpb connects power output end Vo, buffer Mpb
Grounded drain, the drain electrode of the source electrode connection power supply feedforward transistor Mpc of buffer Mpb, which feedovers transistor Mpc
Source electrode connects power vd D, and the grid connection filter resistance Rt of power supply feedforward transistor Mpc is simultaneously inclined by filter resistance Rt connection
The grid of transistor Mpbi is set, the source electrode of biasing transistor Mpbi connects power vd D, and the drain electrode of biasing transistor Mpbi connects
Connect the one end bias current IB, bias current IB other end ground connection；The one end miller compensation capacitor Cc is connected to error amplification
The tie point of the grid of the output end and output power pipe MP of device EA, the other end of miller compensation capacitor Cc are connected to buffer
The tie point of the source electrode of source electrode and power supply feedforward the transistor Mpc of Mpb；The one end filter capacitor Cf ground connection, the other end are connected to
The tie point of the grid of filter resistance Rt and power supply feedforward transistor Mpc.
Working principle of the utility model is:
As shown in Figure 1, on the one hand voltage output end Vo is mended by buffer Mpb and Miller on the basis of traditional circuit
It repays capacitor Cc to be connected, has cut off the output of error amplifier EA by miller compensation capacitor Cc to the feedforward path for exporting Vo, but
The feedback network of voltage output end Vo to error amplifier EA output end is remained, to remain the close of miller compensation capacitor Cc
Strangle compensating action；On the other hand, high frequency when due to filter capacitor Cf, filter resistance Rt filter action, power supply feedover transistor
The grid of Mpc is approximately AC deposition, and the source electrode of power supply feedforward transistor Mpc is capable AC input, because of buffer Mpb and electricity
Transistor Mpc is feedovered on same access in source, and (its DC current is by bias current IB and biasing for DC current having the same
The bias voltage VB that transistor Mpbi is generated is determined), if buffer Mpb is of the same size with power supply feedforward transistor Mpc,
They pass through the source electrode and electricity of power supply feedforward transistor Mpc to buffer Mpb by mutual conductance having the same, thus from power vd D
The gain of the drain junction VBUF of source feedforward transistor Mpc is 1；
In summary two o'clock, when high frequency, the drain junction of source electrode and power supply feedforward the transistor Mpc of buffer Mpb
The alternating voltage of the output end vo 1 of VBUF and EA is that (vo, vdd are respectively represented on output end vo and power vd D vo+vdd
AC signal), it is possible thereby to derive that power supply rejection ratio PSRR at this time will be equal to 0 (due to output power pipe MP's in reality
Capacitor Cgd between grid and drain electrode and the resistance effect between source electrode and drain electrode, still suffer from AC signal from power vd D
It is transmitted to power output end Vo, leading to output end AC signal is not 0, but this signal is very small, defeated much smaller than in traditional circuit
The AC signal of outlet).
The design of the utility model structure is simple, reasonable, has cut off error amplifier EA output end and has passed through miller compensation capacitor
The signal feedforward path of Cc to power output end Vo, but retain power output end Vo and amplified by miller compensation capacitor Cc to error
AC signal on power supply is passed through power supply feedforward transistor Mpc and miller compensation electricity by the signal feedback network of device EA output end
Hold Cc1:1 and be coupled to the grid of power tube, so that output power pipe MP be allowed not have amplification, energy to the AC signal on power supply
The minimum value of linear stabilized power supply power supply rejection ratio is effectively improved, the influence that power jitter exports linear stabilized power supply is reduced.
Claims (1)
1. a kind of circuit for improving linear stabilized power supply power supply rejection ratio, which is characterized in that by error amplifier EA, output power
Pipe MP, feedback resistance R1 and R2, miller compensation capacitor Cc, output load impedance ZL, buffer Mpb, power supply feedforward transistor
Mpc, biasing transistor Mpbi, bias current IB, filter capacitor Cf, filter resistance Rt connection composition；
The one end output load impedance ZL ground connection, the other end connect power output end Vo；The one end feedback resistance R2 ground connection,
The other end connects the one end the feedback resistance R1；The resistance R1 other end connects power output end Vo；The error amplifier
The inverting input terminal of EA connects reference power supply Vref, and the non-inverting input terminal of the error amplifier EA is connected to the feedback resistance
The tie point of R1 and feedback resistance R2, the output end of the error amplifier EA connect the grid of the output power pipe MP；Institute
State the source electrode connection power vd D of output power pipe MP, drain electrode connection power output end Vo；The grid of the buffer Mpb connects
Power output end Vo, grounded drain, source electrode connect the drain electrode of the power supply feedforward transistor Mpc；The power supply feedforward transistor
The source electrode of Mpc connects power vd D, and grid connects the filter resistance Rt and by the filter resistance Rt connection biasing crystalline substance
The grid of body pipe Mpbi；The source electrode of the biasing transistor Mpbi connects power vd D, and drain electrode connects the bias current IB mono-
End；The bias current IB other end ground connection；Described one end miller compensation capacitor Cc is connected to the defeated of the error amplifier EA
The tie point of the grid of outlet and the output power pipe MP, the other end of the miller compensation capacitor Cc are connected to the buffering
The tie point of the source electrode of the source electrode of device Mpb and power supply feedforward transistor Mpc；The one end filter capacitor Cf ground connection is another
End is connected to the tie point of the grid of the filter resistance Rt and power supply feedforward transistor Mpc.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821629859.9U CN208424340U (en) | 2018-10-09 | 2018-10-09 | A kind of circuit improving linear stabilized power supply power supply rejection ratio |
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| CN201821629859.9U CN208424340U (en) | 2018-10-09 | 2018-10-09 | A kind of circuit improving linear stabilized power supply power supply rejection ratio |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109194326A (en) * | 2018-10-09 | 2019-01-11 | 成都信息工程大学 | A kind of circuit improving linear stabilized power supply power supply rejection ratio |
| CN110502053A (en) * | 2019-08-28 | 2019-11-26 | 南京凯鼎电子科技有限公司 | Linear voltage regulator is compared in high power supply voltage inhibition |
| CN115542996A (en) * | 2022-11-28 | 2022-12-30 | 中晟微电子(南京)有限公司 | Low dropout regulator with high power supply rejection ratio and control method thereof |
| US20230266783A1 (en) * | 2022-02-22 | 2023-08-24 | Credo Technology Group Ltd | Voltage Regulator with Supply Noise Cancellation |
-
2018
- 2018-10-09 CN CN201821629859.9U patent/CN208424340U/en active Active
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109194326A (en) * | 2018-10-09 | 2019-01-11 | 成都信息工程大学 | A kind of circuit improving linear stabilized power supply power supply rejection ratio |
| CN109194326B (en) * | 2018-10-09 | 2023-11-03 | 成都铱通科技有限公司 | Circuit for improving power supply rejection ratio of linear stabilized power supply |
| CN110502053A (en) * | 2019-08-28 | 2019-11-26 | 南京凯鼎电子科技有限公司 | Linear voltage regulator is compared in high power supply voltage inhibition |
| US20230266783A1 (en) * | 2022-02-22 | 2023-08-24 | Credo Technology Group Ltd | Voltage Regulator with Supply Noise Cancellation |
| US11789478B2 (en) * | 2022-02-22 | 2023-10-17 | Credo Technology Group Limited | Voltage regulator with supply noise cancellation |
| CN115542996A (en) * | 2022-11-28 | 2022-12-30 | 中晟微电子(南京)有限公司 | Low dropout regulator with high power supply rejection ratio and control method thereof |
| CN115542996B (en) * | 2022-11-28 | 2023-03-24 | 中晟微电子(南京)有限公司 | Low dropout regulator with high power supply rejection ratio and control method thereof |
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