CN117858583A

CN117858583A - Display device

Info

Publication number: CN117858583A
Application number: CN202311214123.0A
Authority: CN
Inventors: 崔允瑄; 崔原硕
Original assignee: Samsung Display Co Ltd
Current assignee: Samsung Display Co Ltd
Priority date: 2022-10-07
Filing date: 2023-09-20
Publication date: 2024-04-09

Abstract

A display device includes a substrate, a circuit layer, and a light emitting element layer. The circuit layer includes a plurality of pixel drivers corresponding to a plurality of emission regions of a display region of a substrate and electrically connected to a plurality of light emitting elements of the light emitting element layer, a plurality of data lines transmitting a plurality of data signals to the plurality of pixel drivers, a plurality of first dummy lines disposed in the display region and extending in a first direction crossing the plurality of data lines, and a plurality of second dummy lines extending in a second direction parallel to the plurality of data lines and adjacent to the plurality of data lines on one side in the first direction. A subset of vias through which the first and second dummy lines among the plurality of vias are electrically connected overlaps one of the plurality of emission regions, and another subset of vias among the plurality of vias is disposed in a non-emission region between the plurality of emission regions.

Description

Display device

Cross Reference to Related Applications

The present application claims priority and benefit of korean patent application No. 10-2022-0128976 filed on 10 month 7 of 2022 and korean patent application No. 10-2023-0026025 filed on 27 of 2023, which are incorporated herein by reference in their entirety.

Technical Field

The present disclosure relates to a display device.

Background

With the development of information society, the demand for display devices for displaying images is increasing in various forms. For example, the display device is applied to various electronic devices such as a smart phone, a digital camera, a notebook computer, a navigation device, and a smart television.

The display device may include a display panel emitting light for displaying an image and a driver supplying a signal or power for driving the display panel.

At least one surface of the display device may be referred to as a display surface on which an image may be displayed. The display surface may include a display area in which an emission area emitting light for displaying an image is provided and a non-display area provided around the display area.

The display device may include data lines disposed in the display region and transmitting data signals to pixel drivers respectively corresponding to the emission regions, and display driving circuits respectively supplying the data signals to the data lines.

It will be appreciated that this background section is intended to provide, in part, a useful background for understanding the technology. However, this background section may also include ideas, concepts or cognizances not as part of the knowledge or understanding by those in the relevant art prior to the corresponding effective application date of the subject matter disclosed herein.

Disclosure of Invention

The display device may include data supply lines electrically connected to output terminals of the display driving circuits, respectively, and disposed in the non-display region. In the case where the data supply lines are electrically connected to the data lines, respectively, it is difficult to reduce the width of the non-display region because the number of the data supply lines increases as the number of the data lines increases in order to increase the size or improve the resolution.

In other embodiments, if the width of the non-display area is reduced in order to increase the proportion of the display area in the display surface of the display device, the distance between the data supply lines is reduced, thus resulting in a short defect.

Aspects of the present disclosure provide a display device in which the width of a non-display region may be reduced without reducing resolution or causing short-circuit defects.

However, aspects of the present disclosure are not limited to one aspect set forth herein. The above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referencing the detailed description of the present disclosure given below.

According to aspects of the present disclosure, there is provided a display device, which may include a substrate including: a main region including a display region including a plurality of emission regions and a non-display region disposed around the display region; and a sub-region protruding from one side of the main region. The display device may include: a circuit layer disposed on the substrate; and a light emitting element layer disposed on the circuit layer and including a plurality of light emitting elements in the plurality of emission regions. The circuit layer may include: a plurality of pixel drivers corresponding to the plurality of emission regions and electrically connected to the plurality of light emitting elements; a plurality of data lines transmitting a plurality of data signals to the plurality of pixel drivers; a plurality of first dummy lines disposed in the display region and extending in a first direction crossing the plurality of data lines; and a plurality of second dummy lines extending in a second direction parallel to the plurality of data lines and adjacent to the plurality of data lines on one side in the first direction. A subset of vias from among the plurality of vias through which the plurality of first dummy lines and the plurality of second dummy lines are electrically connected may overlap one of the plurality of emission regions, and another subset of vias from among the plurality of vias may be disposed in a non-emission region between the plurality of emission regions.

The display device may further include: and a display driving circuit disposed on the substrate in the sub-region and supplying a plurality of data driving signals corresponding to the plurality of data signals of the plurality of data lines of the circuit layer. The circuit layer may further include: a plurality of demultiplexer (demux) circuits disposed in a demultiplexer region of the non-display region adjacent to the sub-region, and electrically connected between the display driving circuit and the plurality of data lines. One of the plurality of demultiplexer circuits may comprise: an input terminal electrically connected to the display driving circuit; and a first output terminal and a second output terminal electrically connected to two of the plurality of data lines, respectively.

The demultiplexer region may include: a demultiplexer intermediate region located in the middle; a first demultiplexer-side region adjacent to a folded portion of an edge of the substrate; and a second demultiplexer-side region disposed between the demultiplexer intermediate region and the first demultiplexer-side region. The plurality of demultiplexer circuits may include: a first demultiplexer circuit provided in the first demultiplexer-side region; and a second demultiplexer circuit provided in the second demultiplexer-side region. The circuit layer may further include a plurality of data supply lines electrically connected to a plurality of output terminals of the display driving circuit. A first data supply line among the plurality of data supply lines may extend from the sub-region to the second demultiplexer-side region and may be electrically connected to an input terminal of the first demultiplexer circuit via an input detour line provided in the display region, and a second data supply line among the plurality of data supply lines may extend from the sub-region to the second demultiplexer-side region and may be electrically connected to an input terminal of the second demultiplexer circuit.

A demultiplexer adjacent region of the display region adjacent to the demultiplexer region may include: displaying an intermediate region adjacent to the demultiplexer intermediate region; a first display side region adjacent to the first demultiplexer side region; and a second display side region adjacent to the second demultiplexer side region. The input detour may include: a first detour line provided in the second display side region, extending in the second direction, and electrically connected to the first data supply line; a second detour line provided in the second display side region and the first display side region, the second detour line extending in the first direction and electrically connected to the first detour line; and a third detour line provided in the first display side region, extending toward the first demultiplexer side region in the second direction, and electrically connected to the second detour line. The plurality of first dummy lines may include the second detour line, and the plurality of second dummy lines may include the first detour line and the third detour line.

The circuit layer may further include first and second power lines disposed in the sub-region and the non-display region and transmitting first and second power for driving the plurality of light emitting elements, respectively; and a plurality of first power auxiliary lines disposed in the display region, extending in the first direction, and electrically connected to the first power lines. The plurality of first dummy lines may further include a plurality of first auxiliary lines electrically connected to the second power line. The plurality of second dummy lines may further include a plurality of second auxiliary lines electrically connected to the second power supply line.

The display region may further include a general region disposed between the demultiplexer adjacent region and the non-display region in the second direction. The general area may include: a universal middle region adjacent to the display middle region; a first general side region adjacent to the first display side region; and a second common side region adjacent to the second display side region. The first detour line may extend in the second direction between the first data supply line and the second detour line, the second detour line may extend in the first direction between the first detour line and the third detour line, and the third detour line may extend in the second direction between the first demultiplexer-side region and the second detour line. The plurality of second auxiliary lines may include: a plurality of general auxiliary lines extending between both ends of the display area in the second direction; a first extension auxiliary line spaced apart from an end of the first detour line in the second direction and extending to the second common side region; and a second extension auxiliary line spaced apart from an end of the third detour line in the second direction and extending to the first general side region.

The plurality of data lines may include: a first data line and a second data line electrically connected to a first output terminal and a second output terminal of the first demultiplexer circuit, respectively, and disposed in the first display side region and the first common side region; and third and fourth data lines electrically connected to the first and second output terminals of the second demultiplexer circuit, respectively, and disposed in the second display side region and the second common side region. Each of the first and third data lines may be adjacent to one of the plurality of general auxiliary lines on the one side in the first direction, the second data line may be adjacent to the third detour line and the second extension auxiliary line on the one side in the first direction, and the fourth data line may be adjacent to the first detour line and the first extension auxiliary line on the one side in the first direction.

The plurality of vias may include: a first detour connection hole through which the first detour line and the second detour line are electrically connected; a second detour connection hole through which the second detour line and the third detour line are electrically connected; and a plurality of auxiliary connection holes through which the plurality of first auxiliary lines and the plurality of second auxiliary lines may be electrically connected.

The plurality of auxiliary connection holes may include a plurality of first auxiliary connection holes overlapping the plurality of common auxiliary lines, the first and second detour connection holes may be disposed in the non-emission region, and each of the plurality of first auxiliary connection holes may overlap one of the emission regions.

The plurality of auxiliary connection holes may further include: a second auxiliary connection hole provided in the first general side region and overlapping the second extension auxiliary line; and a third auxiliary connection hole provided in the second general side region and overlapping the first extension auxiliary line. The second auxiliary connection hole and the third auxiliary connection hole may be disposed in the non-emission region.

The first extension auxiliary line and the second extension auxiliary line may be electrically connected to the second power line in the non-display region.

The plurality of auxiliary connection holes may include a plurality of first auxiliary connection holes overlapping the plurality of common auxiliary lines, each of the first and second detour connection holes may overlap one of the emission regions, and the plurality of first auxiliary connection holes may be disposed in the non-emission region.

The first detour connection holes overlapping with the adjacent second detour lines in the second direction, respectively, may be provided in a first oblique line direction intersecting the first direction and the second direction. The second detour connection holes overlapping with the second detour line adjacent thereto in the second direction may be provided in a second oblique line direction symmetrical to the first oblique line direction.

Each of the plurality of pixel drivers may be electrically connected to one of the plurality of data lines via a data connection hole. Each of the first data line and the second data line may include: a first main extension extending in the second direction; and a first sub-protrusion protruding from the first main extension portion and overlapping the data connection hole. The general auxiliary line adjacent to the first data line among the plurality of general auxiliary lines may include: a second main extension extending in the second direction; a second sub-protrusion protruding from the second main extension portion and facing the first sub-protrusion of the first data line; and a third sub-protrusion facing the first main extension portion of the first data line and overlapping with one of the plurality of auxiliary connection holes. The third detour line adjacent to the second data line may include: a third main extension extending in the second direction; a fourth sub-protrusion protruding from the third main extension portion and facing the first sub-protrusion of the second data line; and a fifth sub-protrusion protruding from the third main extension portion, facing the first main extension portion of the second data line, and overlapping the second detour connection hole.

The second extension auxiliary line adjacent to the second data line may include: a fourth main extension extending in the second direction; and a sixth sub-protrusion protruding from the fourth main extension portion and facing the first sub-protrusion of the second data line. The fourth main extension portion may be electrically connected to the second power line in the non-display region.

The second extension auxiliary line adjacent to the second data line may further include: a seventh sub-protrusion protruding from the fourth main extension portion, facing the first main extension portion of the second data line, and overlapping with another auxiliary connection hole among the plurality of auxiliary connection holes.

According to aspects of the present disclosure, there is provided a display device, which may include a substrate including: a main region, which may include a display region including a plurality of emission regions, and a non-display region disposed around the display region; and a sub-region protruding from one side of the main region. The display device may include: a circuit layer disposed on the substrate; a light emitting element layer disposed on the circuit layer and including a plurality of light emitting elements in the plurality of emission regions; and a display driving circuit disposed on the substrate in the sub-region and supplying a data driving signal corresponding to the data signal of the data line of the circuit layer. The circuit layer may include: a plurality of pixel drivers corresponding to the plurality of emission regions and electrically connected to the plurality of light emitting elements; a plurality of data lines transmitting a plurality of data signals to the plurality of pixel drivers; a plurality of first dummy lines disposed in the display region and extending in a first direction crossing the plurality of data lines; a plurality of second dummy lines extending in a second direction parallel to the plurality of data lines and adjacent to the plurality of data lines on one side in the first direction; a plurality of demultiplexer circuits disposed in a demultiplexer region of the non-display region adjacent to the sub-region; a plurality of data supply lines electrically connected to a plurality of output terminals of the display driving circuit; first and second power supply lines disposed in the sub-region and the non-display region and transmitting first and second power for driving the plurality of light emitting elements, respectively; and a plurality of first power auxiliary lines disposed in the display region, extending in the first direction, and electrically connected to the first power lines. The demultiplexer region may include: a demultiplexer intermediate region located in the middle; a first demultiplexer-side region adjacent to a folded portion of an edge of the substrate; and a second demultiplexer-side region disposed between the demultiplexer intermediate region and the first demultiplexer-side region. A demultiplexer adjacent region of the display region adjacent to the demultiplexer region may include: displaying an intermediate region adjacent to the demultiplexer intermediate region; a first display side region adjacent to the first demultiplexer side region; and a second display side region adjacent to the second demultiplexer side region. The plurality of demultiplexer circuits may include: a first demultiplexer circuit provided in the first demultiplexer-side region; and a second demultiplexer circuit provided in the second demultiplexer-side region. A first data supply line among the plurality of data supply lines may extend from the sub-region to the second demultiplexer-side region, and may be electrically connected to an input terminal of the first demultiplexer circuit via an input detour line provided in the display region. A second data supply line among the plurality of data supply lines may extend from the sub-region to the second demultiplexer-side region and may be electrically connected to an input terminal of the second demultiplexer circuit. The input detour may include: a first detour line provided in the second display side region, extending in the second direction, and electrically connected to the first data supply line; a second detour line provided in the second display side region and the first display side region, the second detour line extending in the first direction and electrically connected to the first detour line; and a third detour line provided in the first display side region, extending toward the first demultiplexer side region in the second direction, and electrically connected to the second detour line. The plurality of first dummy lines may include the second detour line and a plurality of first auxiliary lines. The plurality of second dummy lines may include the first detour line, the third detour line, and a plurality of second auxiliary lines. The plurality of first auxiliary lines and the plurality of second auxiliary lines may be electrically connected to the second power line. The first detour connection hole through which the first detour line and the second detour line may be electrically connected may overlap one of the plurality of emission regions. The second detour connection hole through which the third detour line and the second detour line can be electrically connected may overlap the other one of the emission regions. A plurality of auxiliary connection holes through which the plurality of first auxiliary lines and the plurality of second auxiliary lines may be electrically connected may be provided in the non-emission region between the emission regions.

The display region may further include a general region disposed between the demultiplexer adjacent region and the non-display region in the second direction. The general area may include: a universal middle region adjacent to the display middle region; a first general side region adjacent to the first display side region; and a second common side region adjacent to the second display side region. The first detour line may extend in the second direction between the first data supply line and the second detour line. The second detour line may extend in the first direction between the first detour line and the third detour line. The third detour line may extend in the second direction between the first demultiplexer-side region and the second detour line. The plurality of second auxiliary lines may include: a plurality of general auxiliary lines extending between both ends of the display area in the second direction; a first extension auxiliary line spaced apart from an end of the first detour line in the second direction and extending to the second common side region; a second extension auxiliary line spaced apart from an end of the third detour line in the second direction and extending to the first common side region. The plurality of data lines may include: first and second data lines electrically connected to the first demultiplexer circuit and disposed in the first display side region and the first common side region; and third and fourth data lines electrically connected to the second demultiplexer circuit and disposed in the second display side region and the second common side region. Each of the first data line and the third data line may be adjacent to one of the plurality of general auxiliary lines on the one side in the first direction. The second data line may be adjacent to the third detour line and the second extension auxiliary line on the one side in the first direction. The fourth data line may be adjacent to the first detour line and the first extension auxiliary line on the one side in the first direction.

Each of the plurality of pixel drivers may be electrically connected to one of the plurality of data lines via a data connection hole. Each of the first data line and the second data line may include: a first main extension extending in the second direction; and a first sub-protrusion protruding from the first main extension portion and overlapping the data connection hole. The general auxiliary line adjacent to the first data line among the plurality of general auxiliary lines may include: a second main extension extending in the second direction; a second sub-protrusion protruding from the second main extension portion and facing the first sub-protrusion of the first data line; and a third sub-protrusion facing the first main extension portion of the first data line and overlapping with one of the plurality of auxiliary connection holes. The third detour line adjacent to the second data line may include: a third main extension extending in the second direction; a fourth sub-protrusion protruding from the third main extension portion and facing the first sub-protrusion of the second data line; and a fifth sub-protrusion protruding from the third main extension portion, facing the first main extension portion of the second data line, and overlapping the second detour connection hole. The second extension auxiliary line adjacent to the second data line may include: a fourth main extension extending in the second direction; and a sixth sub-protrusion protruding from the fourth main extension portion and facing the first sub-protrusion of the second data line. The fourth main extension portion may be electrically connected to the second power line in the non-display region.

Effects of the present disclosure are not limited to the above-described effects, and various other effects are included in the specification.

Drawings

These and/or other aspects will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:

fig. 1 is a schematic perspective view of a display device according to an embodiment;

FIG. 2 is a schematic plan view of the display device of FIG. 1;

FIG. 3 is a schematic cross-sectional view of an example of a plane cut along line A-A' of FIG. 2;

FIG. 4 is a schematic plan view of the main and sub-regions of the display device of FIG. 1;

FIG. 5 is a schematic plan view of an example of portion B of FIG. 4;

fig. 6 is a schematic plan view illustrating an example of the data line, the first dummy line, the second dummy line, and the first power auxiliary line provided in part C of fig. 4 and 5;

fig. 7 is a schematic diagram of an equivalent circuit of an example of the first demultiplexer (demultiplexer) circuit unit of fig. 5;

FIG. 8 is a schematic timing diagram illustrating the data driving signal and the demultiplexer control signal of FIG. 7;

fig. 9 is a schematic diagram of an equivalent circuit of an example of a pixel driver of a circuit layer;

fig. 10 is a schematic plan view of two pixel drivers disposed in part F of fig. 6;

Fig. 11 is a schematic plan view of the semiconductor layer and the first conductive layer of fig. 10;

fig. 12 is a schematic plan view of the semiconductor layer, first conductive layer, second conductive layer, and third conductive layer of fig. 10;

FIG. 13 is a schematic cross-sectional view of an example of a plane cut along line G-G' of FIG. 10;

fig. 14 is a schematic plan view showing an example of an emission region provided in part C of fig. 4 and 5;

fig. 15 is a schematic plan view showing an emission region and a via hole provided in part C of fig. 4 and 5 in a display device according to an embodiment;

fig. 16 is a schematic plan view showing an emission region and a via hole provided in part D of fig. 4 in the display device according to the embodiment of fig. 15;

fig. 17 is a schematic plan view showing an emission region and a via hole provided in part C of fig. 4 and 5 in a display device according to another embodiment;

fig. 18 is a schematic plan view showing data lines, first dummy lines, second dummy lines, and vias provided in part C of fig. 4 and 5 in a display device according to still another embodiment;

fig. 19 is a schematic plan view illustrating data lines, first dummy lines, second dummy lines, and vias disposed in part D of fig. 4 in the display device according to the embodiment of fig. 18;

Fig. 20 is a schematic plan view showing data lines, first dummy lines, second dummy lines, and vias disposed in a portion D of fig. 4 in a display device according to still another embodiment;

fig. 21 is a schematic plan view illustrating data lines, first dummy lines, second dummy lines, and vias disposed in part E of fig. 4 in the display device according to the embodiment of fig. 20; and

fig. 22 is a schematic plan view illustrating data lines, first dummy lines, second dummy lines, and vias disposed in a portion E of fig. 4 in a display device according to another embodiment.

Detailed Description

Embodiments will now be described more fully hereinafter with reference to the accompanying drawings. However, embodiments may be time-limited in different forms and should not be construed as limiting. Like reference numerals refer to like components throughout this disclosure. In the drawings, the thickness of layers and regions may be exaggerated for clarity.

Portions that are not relevant to the description may not be provided in order to describe embodiments of the present disclosure.

As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It will also be understood that when a layer or substrate is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. In contrast, when an element is referred to as being "directly on" another element, there may be no intervening elements present.

Further, the phrase "in a plan view" means when the target portion is viewed from above, and the phrase "in a schematic cross-sectional view" means when a schematic cross-section taken by vertically cutting the target portion is viewed from the side. The term "overlapping" or "overlapping" means that a first object may be above or below a second object or to one side of the second object, and vice versa. In addition, the term "overlapping" may include layers, stacks, facing or facing, extending throughout, covering or partially covering, or any other suitable term as would be appreciated and understood by one of ordinary skill in the art. The expression "non-overlapping" may include meanings such as "spaced", "separated" or "offset" as well as any other suitable equivalent terms as would be appreciated and understood by one of ordinary skill in the art. The terms "facing" and "facing" may mean that a first object may be directly or indirectly opposite a second object. In the case where the third object is interposed between the first object and the second object, the first object and the second object may be understood to be indirectly opposed to each other although still facing each other.

For ease of description, spatially relative terms "below … …," "below … …," "lower," "above … …," or "upper" and the like may be used herein to describe one element or component's relationship to another element or component as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, where the apparatus shown in the figures is turned over, elements positioned "below" or "beneath" another apparatus could be oriented "above" the other apparatus. Thus, the illustrative term "under … …" may include both upper and lower positions. The device may also be oriented in other directions and the spatially relative terms may therefore be construed differently depending on the orientation.

It will be further understood that the terms "comprises (comprises, comprising)", "having (has, have, having)", and/or "comprising (includes, including)", when used, may specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of other features, integers, steps, operations, elements, components, and/or groups thereof.

It will be understood that in the description, when an element (or region, layer or section, etc.) is referred to as being "on," "connected to," or "coupled to" another element, it can be directly on, connected or coupled to the other element or intervening elements may be present between the element and the other element.

It will be understood that the terms "connected" or "coupled" may include physical connections or physical couplings or electrical connections or couplings.

It will be understood that, although the terms "first," "second," or "third," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element or for convenience in description and illustration thereof. For example, when a "first element" is discussed in the description, it can be termed a "second element" or a "third element," and the "second element" and the "third element" can be named in a similar manner without departing from the teachings herein.

The terms "about," "approximately," or "substantially" as used herein include the stated values in view of the measurements in question and errors associated with the particular amounts of the measurements (e.g., limitations of the measurement system), and are intended to be within the acceptable ranges of deviation from the particular values as determined by one of ordinary skill in the art. For example, "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10% or ±5% of the stated value.

In the description and claims, for the purposes of their meaning and explanation, the term "and/or" is intended to include any combination of the terms "and" or ". For example, "a and/or B" may be understood to mean "A, B or a and B". The terms "and" or "may be used in a combined or separate sense and are to be understood as being equivalent to" and/or ". In the description and claims, for the purposes of their meaning and explanation, the phrase "at least one (seed/person)" in … … is intended to include the meaning of "at least one (seed/person) selected from the group of … …". For example, "at least one (seed/person) of a and B" may be understood to mean "A, B or a and B".

Unless defined or indicated otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Fig. 1 is a schematic perspective view of a display device 10 according to an embodiment. Fig. 2 is a schematic plan view of the display device 10 of fig. 1. Fig. 3 is a schematic cross-sectional view of an example of a plane cut along line A-A' of fig. 2.

Referring to fig. 1, a display device 10 is a device for displaying a moving image or a still image. The display device 10 may be used as a display screen in portable electronic devices such as mobile phones, smart phones, tablet Personal Computers (PCs), smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable Multimedia Players (PMPs), navigation devices, and Ultra Mobile PCs (UMPCs), and in various products such as televisions, notebook computers, monitors, billboards, and internet of things (IoT) devices.

The display device 10 may be a light emitting display device such as an organic light emitting display device using an organic light emitting diode, a quantum dot light emitting display device including a quantum dot light emitting layer, an inorganic light emitting display device including an inorganic semiconductor, or a micro or nano light emitting display device using a micro or nano light emitting diode. The case where the display device 10 is an organic light emitting display device will be described below. However, the present disclosure is not limited to this case, and is also applicable to a display device including an organic insulating material, an organic light emitting material, and a metal material.

The display device 10 may be formed flat, but the present disclosure is not limited thereto. For example, the display device 10 may include curved portions formed at left and right ends and having a constant or varying curvature. The display device 10 may be formed to be flexible such that the display device 10 may be bent, folded, and/or curled.

The display device 10 may include a display panel 100, a display driving circuit 200, and a circuit board 300.

The display panel 100 may include a display area DA in which a plurality of emission areas EA (see fig. 2) for displaying images are arranged (set).

For example, the substrate 110 (see fig. 3) of the display panel 100 may include a main area MA including a display area DA and a non-display area NDA disposed around the display area DA, and a sub-area SBA protruding from one side of the main area MA in the second direction DR 2.

The display driving circuit 200 may be provided as an integrated circuit and mounted in the sub-area SBA. The display driving circuit 200 may supply a data driving signal corresponding to the data line DL (see fig. 5) of the display panel 100.

The circuit board 300 may be bonded to signal pads SPD (see fig. 4) provided on the edge of the sub-region SBA.

In fig. 1 and 4, the sub-area SBA is unfolded parallel to the main area MA. On the other hand, in fig. 2 and 3, a part of the sub-region SBA is folded.

Referring to fig. 2, the display area DA may be shaped like a rectangular plane having a short side in a first direction DR1 and a long side in a second direction DR2 crossing the first direction DR 1. Each corner where the short side extending in the first direction DR1 meets the long side extending in the second direction DR2 may be rounded with a predetermined or selected curvature, or may be a right angle. The planar shape of the display area DA is not limited to a quadrangular shape, but may be another polygonal shape, a circular shape, and/or an elliptical shape.

The display area DA may occupy a large portion of the main area MA. The display area DA may be disposed at the center of the main area MA.

The display area DA may include a plurality of emission areas EA arranged side by side with each other. The display area DA may further include non-emission areas NEA between the emission areas EA.

The emission areas EA may be arranged side by side with each other in the first and second directions DR1 and DR 2.

Each of the emission areas EA may have a diamond-shaped planar shape or a rectangular planar shape. However, this is only an example, and the planar shape of each of the emission areas EA according to the embodiment is not limited to the shape shown in fig. 2. For example, in a plan view, the emission area EA may also have a polygonal shape, a circular shape, or an elliptical shape other than a quadrangular shape.

The emission areas EA may include a first emission area EA1 that emits light of a first color in a predetermined or selected wavelength band, a second emission area EA2 that emits light of a second color in a wavelength band lower than the wavelength band of the first color, and a third emission area EA3 that emits light of a third color in a wavelength band lower than the wavelength band of the second color.

For example, the light of the first color may be red light in a wavelength band of about 600nm to about 750 nm. The light of the second color may be green light in a wavelength band of about 480nm to about 560 nm. The light of the third color may be blue light in a wavelength band of about 370nm to about 460 nm.

As shown in fig. 2, the first and third emission areas EA1 and EA3 may be alternately disposed in the first direction DR1 or the second direction DR 2. The second emission areas EA2 may be arranged side by side with each other in the first direction DR1 or the second direction DR 2.

A plurality of pixels PX displaying respective brightness and colors may be provided by the emission area EA. Each of the pixels PX may be a base unit that displays various colors including white at a predetermined or selected brightness.

For example, each of the pixels PX may be composed of at least one first emission area EA1, at least one second emission area EA2, and at least one third emission area EA3 adjacent to each other.

Each of the pixels PX may display a color and a luminance of a mixture of light emitted from at least one first, at least one second, and at least one third emission area EA1, EA2, and EA3 adjacent to each other.

Although the emission areas EA have the same area in fig. 2, this is only an example. In another example, the third emission area EA3 may have a largest area, and the second emission area EA2 may have a smallest area.

Although the emission areas EA are arranged side by side in the first and second directions DR1 and DR2 in fig. 2, this is only an example. In another example, the second emission area EA2 may be adjacent to the first and third emission areas EA1 and EA3 in a diagonal direction crossing the first and second directions DR1 and DR 2.

Referring to fig. 3, the display panel 100 of the display device 10 may include a substrate 110 including a main region MA and a sub-region SBA, a circuit layer 120 disposed on the substrate 110, and a light emitting element layer 130 disposed on the circuit layer 120.

The circuit layer 120 may include pixel drivers PXD (see fig. 9) respectively corresponding to the emission areas EA and data lines DL (see fig. 5) transmitting the data signals Vdata (see fig. 9) to the pixel drivers PXD.

The light emitting element layer 130 may include light emitting elements LEL (see fig. 13) corresponding to the emission regions EA, respectively. The light emitting elements LEL may be electrically connected to the pixel drivers PXD of the circuit layer 120, respectively.

The display panel 100 of the display device 10 may further include a sealing layer 140 covering the light emitting element layer 130, and a sensor electrode layer 150 disposed on the sealing layer 140.

The substrate 110 may be made of an insulating material such as a polymer resin. For example, the substrate 110 may be made of polyimide. The substrate 110 may be a flexible substrate that may be bent, folded, and/or rolled.

In other embodiments, the substrate 110 may be made of an insulating material such as glass.

The sealing layer 140 may be disposed on the circuit layer 120, correspond to the main region MA, and cover the light emitting element layer 130. The sealing layer 140 may include a structure in which two or more inorganic layers and at least one organic layer are alternately stacked with each other.

The sensor electrode layer 150 may be disposed on the sealing layer 140, and may correspond to the main area MA. The sensor electrode layer 150 may include a touch electrode for sensing a touch of a person or an object.

The display device 10 may further include a cover window (not shown) disposed on the sensor electrode layer 150. The cover window may be attached to the sensor electrode layer 150 by a transparent adhesive member such as an Optically Clear Adhesive (OCA) film or Optically Clear Resin (OCR). The cover window may be an inorganic material such as glass, or may be an organic material such as a plastic or polymeric material. The cover window may protect the sensor electrode layer 150, the sealing layer 140, the light emitting element layer 130, and the circuit layer 120 from electrical and physical impacts on the display surface.

The display device 10 may further include an anti-reflection member (not shown) disposed between the sensor electrode layer 150 and the cover window. The anti-reflection member may be a polarizing film or a color filter. The anti-reflection member may block external light reflected by the sensor electrode layer 150, the sealing layer 140, the light emitting element layer 130, the circuit layer 120, and interfaces therebetween, thereby preventing a decrease in the visibility of an image of the display device 10.

The display device 10 according to the embodiment may further include a touch driving circuit 400 for driving the sensor electrode layer 150.

The touch driving circuit 400 may be provided as an integrated circuit.

The touch driving circuit 400 may be mounted on the circuit board 300 bonded to the signal pads SPD, and thus may be electrically connected to the sensor electrode layer 150.

In other embodiments, as with the display driving circuit 200, the touch driving circuit 400 may be mounted on the second sub-region SB2 (see fig. 4) of the substrate 110.

The touch driving circuit 400 may transmit touch driving signals to a plurality of driving electrodes included in the sensor electrode layer 150, receive touch sensing signals of a plurality of touch nodes via the plurality of sensing electrodes, respectively, and detect an amount of charge change in the mutual capacitance based on the touch sensing signals.

For example, the touch driving circuit 400 may determine whether a touch or proximity of a user has occurred based on a touch sensing signal of each of the touch nodes. The user's touch may indicate that an object such as a user's finger or pen directly touches the front surface of the display device 10. The proximity of the user may indicate that an object, such as a user's finger or pen, hovers over the front surface of the display device 10.

Fig. 4 is a schematic plan view of the main area MA and the sub-area SBA of the display device 10 of fig. 1.

Referring to fig. 4, the sub-region SBA may include a folded region BA that may be converted into a folded shape, and first and second sub-regions SB1 and SB2 connected to both sides of the folded region BA.

The first sub-region SB1 may be disposed between the main region MA and the folded region BA. One side of the first sub-area SB1 may be connected to the non-display area NDA of the main area MA, and the other side of the first sub-area SB1 may be connected to the folded area BA.

The second sub-region SB2 may be spaced apart from the main region MA with the inflection region BA interposed therebetween, and the second sub-region SB2 may be disposed on the lower surface of the substrate 110 by the inflection region BA converted into an inflection shape. For example, the second sub-region SB2 may overlap the main region MA in the thickness direction DR3 of the substrate 110 due to the bent region BA converted into a bent shape.

One side of the second sub-region SB2 may be connected to the folded region BA.

The signal pads SPD and the display drive circuit 200 may be disposed in the second sub-region SB 2.

The display driving circuit 200 may generate signals and voltages for driving the pixel driver PXD (see fig. 9) of the display area DA.

The display driving circuit 200 may be provided as an integrated circuit and mounted on the second sub-region SB2 of the substrate 110 by a Chip On Glass (COG) method, a Chip On Plastic (COP) method, or an ultrasonic bonding method. However, the present disclosure is not limited thereto. For example, the display driving circuit 200 may also be mounted on the circuit board 300 by a Chip On Film (COF) method.

The circuit board 300 may be attached and electrically connected to the signal pads SPD of the second sub-region SB2 using an anisotropic conductive film or a low resistance, high reliability material such as self-assembled anisotropic conductive paste (SAP).

The pixel driver PXD and the display driving circuit 200 of the display area DA may receive digital video data, timing signals, and driving voltages from the circuit board 300.

The circuit board 300 may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a flip chip film.

According to an embodiment, the non-display area NDA may include a demultiplexer (demultiplexer) area DXA formed in a portion adjacent to the sub-area SBA. The demultiplexer region DXA may be disposed adjacent to an edge of the display region DA in the second direction DR2 (which is adjacent to the sub-region SBA).

In the demultiplexer region DXA, a demultiplexer circuit unit (demultiplexer circuit) DMC (see fig. 5) electrically connected between the data line DL (see fig. 5) of the display region DA and the display driving circuit 200 of the sub-region SBA may be provided.

The demultiplexer region DXA may include a demultiplexer intermediate region XMA located in the middle in the first direction DR1, a first demultiplexer side region XSA1 adjacent to a bent portion of an edge of the substrate 110 (see fig. 3), and a second demultiplexer side region XSA2 disposed between the demultiplexer intermediate region XMA and the first demultiplexer side region XSA1.

The demultiplexer region DXA may include two second demultiplexer-side regions XSA2 and two first demultiplexer-side regions XSA1 disposed at both sides of the demultiplexer intermediate region XMA in the first direction DR 1.

The display area DA may include a demultiplexer adjacent area DAA adjacent to the demultiplexer area DXA.

The demultiplexer adjacent region DAA may include a display middle region DMDA adjacent to the demultiplexer middle region XMA in the second direction DR2, a first display side region DSDA1 adjacent to the first demultiplexer side region XSA1 in the second direction DR2, and a second display side region DSDA2 adjacent to the second demultiplexer side region XSA2 in the second direction DR 2. In the demultiplexer adjacent region DAA, an input detour IDEL (see fig. 5) of the first demultiplexer circuit unit DMC1 (see fig. 5) electrically connected to the first demultiplexer-side region XSA1 may be provided.

The display area DA may further include a general area GA disposed between the demultiplexer adjacent area DAA and the non-display area NDA in the second direction DR 2.

The general area GA may include a general middle area GMA adjacent to the display middle area DMDA in the second direction DR2, a first general side area GSA1 adjacent to the first display side area DSDA1 in the second direction DR2, and a second general side area GSA2 adjacent to the second display side area DSDA2 in the second direction DR 2.

The non-display area NDA may further include a scan driving circuit area SCDA disposed adjacent to at least one edge of the display area DA in the first direction DR 1.

The circuit layer 120 (see fig. 3) may include a scan driving circuit (not shown) disposed in the scan driving circuit area SCDA. The scan driving circuit may supply scan signals to the scan lines extending in the first direction DR1 in the display area DA, respectively.

For example, the display driving circuit 200 or the circuit board 300 may supply a scan control signal to the scan driving circuit based on the digital video data and the timing signal.

The circuit board 300 may supply a predetermined or selected constant voltage for generating the scan signal to the scan driving circuit.

Although the scan driving circuit area SCDA is a portion of the non-display area NDA adjacent to both edges of the display area DA in the first direction DR1 in fig. 4, this is only an example. For example, although not shown separately, the scan driving circuit area SCDA may also be a portion of the non-display area NDA adjacent to at least one side of the display area DA in the first direction DR1, or may be provided as a separate area overlapping with a portion of the display area DA.

Fig. 5 is a schematic plan view of an example of a portion B of fig. 4. Fig. 6 is a schematic plan view showing an example of the data line DL, the first dummy line DML1, the second dummy line DML2, and the first power auxiliary line VDAL provided in the portion C of fig. 4 and 5.

Referring to fig. 5, the circuit layer 120 (see fig. 3) of the display device 10 (see fig. 1) according to an embodiment may include: the pixel drivers PXD (see fig. 9), respectively corresponding to the emission areas EA and respectively electrically connected to the light emitting elements LEL (see fig. 9) of the light emitting element layer 130 (see fig. 3); a data line DL transmitting a data signal Vdata (see fig. 9) to the pixel driver PXD; a first dummy line DML1 disposed in the display area DA (see fig. 4) and extending in a first direction DR1 crossing the data line DL; a second dummy line DML2 extending in a second direction DR2 parallel to the data lines DL and respectively adjacent to the data lines DL; and a demultiplexer circuit unit DMC disposed in a demultiplexer region DXA of the non-display region NDA (see fig. 4), adjacent to the sub-region SBA, and electrically connected between the display driving circuit 200 and the data line DL.

The circuit layer 120 may further include data supply lines DSPL electrically connected to output terminals of the display driving circuit 200, respectively.

The demultiplexer circuit unit DMC may be arranged in the demultiplexer area DXA in a first direction DR 1.

The demultiplexer circuit unit DMC may include a first demultiplexer circuit unit DMC1 disposed in the first demultiplexer-side area XSA1 and a second demultiplexer circuit unit DMC2 disposed in the second demultiplexer-side area XSA 2.

The demultiplexer circuit unit DMC may further include a third demultiplexer circuit unit DMC3 provided in the demultiplexer intermediate region XMA.

One of the demultiplexer circuit units DMC (e.g., the first demultiplexer circuit unit DMC 1) may include a first output terminal AOP (see fig. 7) and a second output terminal BOP (see fig. 7) electrically connected to an input terminal DIP (see fig. 7) of the display driving circuit 200 and to two of the data lines DL (e.g., DL1 and DL2 in fig. 5 and 7), respectively, via one of the data supply lines DSPL (e.g., DSPL1 in fig. 5 and 7).

The data lines DL may include first and second data lines DL1 and DL2 disposed in the first display side area DSDA1 and the first general side area GSA1, and third and fourth data lines DL3 and DL4 disposed in the second display side area DSDA2 and the second general side area GSA 2.

The data lines DL may further include fifth and sixth data lines DL5 and DL6 disposed in the display middle area DMDA and the general middle area GMA.

The first and second data lines DL1 and DL2 disposed in the first display-side area DSDA1 and the first general-purpose side area GSA1 may be electrically connected to the first and second output terminals AOP and BOP of the first demultiplexer circuit unit DMC1 disposed in the first demultiplexer-side area XSA1, respectively.

The third data line DL3 and the fourth data line DL4 disposed in the second display-side area DSDA2 and the second common-side area GSA2 may be electrically connected to the first output terminal and the second output terminal of the second demultiplexer circuit unit DMC2 disposed in the second demultiplexer-side area XSA2, respectively.

The fifth data line DL5 and the sixth data line DL6 disposed in the display middle area DMDA and the general middle area GMA may be electrically connected to the first output terminal and the second output terminal of the third demultiplexer circuit unit DMC3 disposed in the demultiplexer middle area XMA, respectively.

The data supply lines DSPL may include a first data supply line DSPL1 transmitting data driving signals corresponding to the data signals of the first and second data lines DL1 and DL2 disposed in the first display side area DSDA1, a second data supply line DSPL2 transmitting data driving signals corresponding to the data signals of the third and fourth data lines DL3 and DL4 disposed in the second display side area DSDA2, and a third data supply line DSPL3 transmitting data driving signals corresponding to the data signals of the fifth and sixth data lines DL5 and DL6 disposed in the display middle area DMDA.

The first data supply line DSPL1 among the data supply lines DSPL may extend from the sub-region SBA to the second demultiplexer-side region XSA2, and may be electrically connected to an input terminal of the first demultiplexer circuit unit DMC1 via an input detour line IDEL provided in the display region DA.

The second data supply line DSPL2 among the data supply lines DSPL may extend from the sub-region SBA to the second demultiplexer-side region XSA2 and may be connected to an input terminal of the second demultiplexer circuit unit DMC 2.

The third data supply line DSPL3 among the data supply lines DSPL may extend from the sub-region SBA to the demultiplexer intermediate region XMA and may be connected to an input terminal of the third demultiplexer circuit unit DMC 3.

The input detour IDEL may include a first detour DETL1 disposed in the second display side area DSDA2, extending in the second direction DR2, and electrically connected to the first data supply line DSPL1, a second DETL2 extending in the first direction DR1 in the second display side area DSDA2 and the first display side area DSDA1, and electrically connected to the first DETL1, and a third DETL3 disposed in the first display side area DSDA1, extending in the second direction DR2 toward the first demultiplexer side area XSA1, and electrically connected to the second DETL 2.

The circuit layer 120 may further include an input connection line ICNL which is disposed in the first demultiplexer-side region XSA1 and electrically connects the third DETL3 of the input det line IDEL and the input terminal of the first demultiplexer circuit unit DMC 1.

The first DETL1 may extend in the second direction DR2 between the first data supply line DSPL1 of the second demultiplexer-side area XSA2 and the second DETL2.

The second DETL2 may extend in the first direction DR1 between the first DETL1 and the third DETL3.

The third DETL3 may extend in the second direction DR2 between the first demultiplexer-side area XSA1 and the second DETL2. The third DETL3 may be electrically connected to the input connection line ICNL of the first demultiplexer-side area XSA 1.

Referring to fig. 6, the second DETL2 may be electrically connected to the first DETL1 via the first deth 1 and may be electrically connected to the third DETL3 via the second DECH 2.

The first dummy line DML1 may include a second DETL2 of the input det line IDEL.

The first dummy line DML1 may include a first auxiliary line ASL1 to which the second power ELVSS (see fig. 9) is applied, in addition to the second DETL2.

The second dummy line DML2 may include a first DETL1 and a third DETL3 of the input detel DETL.

The second dummy line DML2 may include a second auxiliary line ASL2 to which the second power ELVSS is applied, in addition to the first DETL1 and the third DETL3 dets.

As shown in fig. 5, the circuit layer 120 of the display device 10 according to the embodiment may further include a first power line VDSPL and a second power line VSSPL disposed in the sub-region SBA and the non-display region NDA and transmitting a first power ELVDD (see fig. 9) and a second power ELVSS for driving the light emitting element LEL, respectively.

The first auxiliary line ASL1 of the first dummy line DML1 and the second auxiliary line ASL2 of the second dummy line DML2 may be electrically connected to the second power supply line VSSPL.

In other words, the first dummy line DML1 may include the second DETL2 of the input DETL and the first auxiliary line ASL1, the first auxiliary line ASL1 being a portion other than the second DETL2 and electrically connected to the second power supply line VSSPL.

The second dummy line DML2 may include first and third DETL1 and DETL3 of the input detel DETL and a second auxiliary line ASL2, and the second auxiliary line ASL2 is a portion other than the first and third DETL1 and DETL3 and electrically connected to the second power supply line VSSPL.

As shown in fig. 5 and 6, the second auxiliary line ASL2 may include a general auxiliary line GASL extending between both ends of the display area DA in the second direction DR2, a first extension auxiliary line EASL1 spaced apart from an end of the first DETL1 in the second direction DR2 and extending to the second general side area GSA2, and a second extension auxiliary line EASL2 spaced apart from an end of the third DETL3 in the second direction DR2 and extending to the first general side area GSA 1.

Each of the first data lines DL1 electrically connected to the first demultiplexer circuit unit DMC1 and disposed in the first display-side area DSDA1 may be adjacent to one general auxiliary line GASL on one side (e.g., right side in fig. 6) in the first direction DR1, and each of the second data lines DL2 may be adjacent to the third DETL3 and the second extension auxiliary line EASL2 on one side in the first direction DR 1. Here, some of the pixel drivers PXD electrically connected to the first data line DL1 may be disposed between the common auxiliary line GASL and the first data line DL1 adjacent to each other. Some other pixel drivers PXD electrically connected to the second data line DL2 may be disposed between the third DETL3 and the second extension auxiliary line EASL2 adjacent to each other and the second data line DL 2.

In other words, each of the first data lines DL1 may face the common auxiliary line GASL with some pixel drivers PXD connected to the first data lines DL1 interposed between the common auxiliary line GASL and the first data lines DL 1. Each of the second data lines DL2 may face the third DETL3 and the second extension auxiliary line EASL2 with some other pixel drivers PXD connected to the second data lines DL2 interposed between the third DETL3 and the second extension auxiliary line EASL2 and the second data lines DL 2.

Each of the third data lines DL3, which are electrically connected to the second demultiplexer circuit unit DMC2 and are disposed in the second display side area DSDA2, may be adjacent to another general auxiliary line GASL, and each of the fourth data lines DL4 may be adjacent to the first DETL1 and the first extension auxiliary line EASL1.

Each of the fifth data line DL5 and the sixth data line DL6 electrically connected to the third demultiplexer circuit unit DMC3 and disposed in the display middle area DMDA may be adjacent to the common auxiliary line GASL.

The circuit layer 120 of the display device 10 according to the embodiment may include a via for electrical connection between the first dummy line DML1 and the second dummy line DML 2.

According to an embodiment, some of the vias (subset of vias) may overlap one of the emission areas EA, and other vias (another subset of vias) may be disposed in the non-emission areas NEA between the emission areas EA. This will be described later with reference to fig. 14 to 17.

The via may include a first detour connection hole DECH1 for electrical connection between the first DETL1 and the second DETL2, a second detour connection hole DECH2 for electrical connection between the second DETL2 and the third DETL3, and an auxiliary connection hole ASCH for electrical connection between the first auxiliary line ASL1 and the second auxiliary line ASL2 (see fig. 16).

According to an embodiment, the first detour connection holes DECH1 provided in the second display side area DSDA2 and respectively overlapping with the second detour lines DETL2 adjacent thereto in the second direction DR2 may be arranged in the first diagonal direction DD1 intersecting the first direction DR1 and the second direction DR 2.

The second detour connection holes DECH2 provided in the first display-side area DSDA1 and respectively overlapping with the second detour lines DETL2 adjacent thereto in the second direction DR2 may be arranged in the second diagonal direction DD2 symmetrical to the first diagonal direction DD 1.

According to an embodiment, auxiliary connection holes ASCH (see fig. 16) may be provided in the general area GA and the display middle area DMDA.

For example, in the first general side area GSA1 connected to the first display side area DSDA1 in the second direction DR2, the auxiliary connection holes ASCH may be arranged in the second diagonal direction DD2 parallel to the arrangement direction of the second detour connection holes DECH2 of the first display side area DSDA1, or may be arranged in the third diagonal direction DD3 (see fig. 16) having a steeper slope than that of the second diagonal direction DD 2.

In the second general-purpose side region GSA2 connected to the second display-side region DSDA2 in the second direction DR2, the auxiliary connection holes ASCH may be arranged in a first diagonal direction DD1 parallel to the arrangement direction of the first detour connection holes DECH1 of the second display-side region DSDA2, or may be arranged in a fourth diagonal direction DD4 having a steeper slope than that of the first diagonal direction DD 1.

In this case, it can be easily inferred whether the first bypass connection hole DECH1, the second bypass connection hole DECH2, and the auxiliary connection hole ASCH are normally arranged through the arrangement direction of the first bypass connection hole DECH1, the arrangement direction of the second bypass connection hole DECH2, and the arrangement direction of the auxiliary connection hole ASCH.

Fig. 7 is a schematic diagram of an equivalent circuit of an example of the first demultiplexer circuit unit DMC1 of fig. 5. Fig. 8 is a schematic timing diagram illustrating the data driving signal DDRS and the demultiplexer control signals CLA and CLB of fig. 7.

Referring to fig. 7, one of the first demultiplexer circuit units DMC1 among the demultiplexer circuit units DMC (see fig. 5) may include: an input terminal DIP electrically connected to the display driving circuit 200 (see fig. 5) and inputted with one data driving signal DDRS; a first output terminal AOP outputting a higher priority data signal corresponding to the data driving signal DDRS during a higher priority output period AT (see fig. 8); and a second output terminal BOP outputting a lower priority data signal corresponding to the data driving signal DDRS during a lower priority output period BT (see fig. 8) after the higher priority data signal AT.

The first demultiplexer circuit unit DMC1 may further include a first demultiplexer transistor TDM1 electrically connected between the input terminal DIP and the first output terminal AOP, and a second demultiplexer transistor TDM2 electrically connected between the input terminal DIP and the second output terminal BOP.

The circuit layer 120 (see fig. 3) of the display device 10 (see fig. 1) according to the embodiment may further include a first output connection line electrically connecting the first output terminal AOP of each first demultiplexer circuit unit DMC1 and the first data line DL1 and a second output connection line electrically connecting the second output terminal BOP of each first demultiplexer circuit unit DMC1 and the second data line DL 2.

The circuit layer 120 may further include a first demultiplexer control line DXCL1 electrically connected to the gate electrode of the first demultiplexer transistor TDM1 and a second demultiplexer control line DXCL2 electrically connected to the gate electrode of the second demultiplexer transistor TDM 2.

Referring to fig. 7 and 8, each image frame (i-1 st, i) th frame may include a higher priority output period AT and a lower priority output period BT.

The first demultiplexer control signal CLA of the first demultiplexer control line DXCL1 may be output AT a turn-on level during the higher priority data signal AT, and the second demultiplexer control signal CLB of the second demultiplexer control line DXCL2 may be output AT a turn-on level during the lower priority data signal BT.

In this case, during the higher priority data signal AT, the first demultiplexer transistor TDM1 may be turned on to allow the data driving signal DDRS to output the data signal as the first data line DL1 via the first output terminal AOP. During the lower priority data signal BT, the second demultiplexer transistor TDM2 may be turned on to allow the data driving signal DDRS to output the data signal as the second data line DL2 via the second output terminal BOP.

For example, the data driving signal DDRS may be time-divided into a higher priority data signal AT and a lower priority data signal BT by the demultiplexer circuit unit DMC.

The equivalent circuit and timing diagram of each of the second and third demultiplexer circuit units DMC2 and DMC3 may be substantially the same as those of the first demultiplexer circuit unit DMC1 shown in fig. 7 and 8, except that the first and second output terminals AOP and BOP in the second demultiplexer circuit unit DMC2 (see fig. 5) are electrically connected to the third and fourth data lines DL3 (see fig. 5) and DL4 (see fig. 5), respectively, and the first and second output terminals AOP and BOP in the third demultiplexer circuit unit DMC3 (see fig. 5) are electrically connected to the fifth and sixth data lines DL5 (see fig. 5) and DL6 (see fig. 5), respectively. Accordingly, redundant descriptions of the equivalent circuits and timing charts of each of the second and third demultiplexer circuit units DMC2 and DMC3 will be omitted.

Fig. 9 is a schematic diagram of an equivalent circuit of an example of the pixel driver PXD of the circuit layer 120 (see fig. 3).

The circuit layer 120 may include pixel drivers PXD respectively corresponding to the emission areas EA (see fig. 2) and respectively electrically connected to the light emitting elements LEL of the light emitting element layer 130 (see fig. 3).

Referring to fig. 9, one of the pixel drivers PXD of the circuit layer 120 may include a driving transistor DT, one or more switching elements ST1 to ST6, and a capacitor C1. The switching elements ST1 to ST6 may include a first transistor ST1 (switching transistor), a second transistor ST2, a third transistor ST3, a fourth transistor ST4, a fifth transistor ST5, and a sixth transistor ST6.

The circuit layer 120 may further include a scan write line GWL transmitting the scan write signal GW to the pixel driver PXD, a gate control line GCL transmitting the gate control signal GC to the pixel driver PXD, a scan initialization line GIL transmitting the scan initialization signal GI to the pixel driver PXD, an emission control line ECL transmitting the emission control signal EC to the pixel driver PXD, a gate initialization voltage line VGIL transmitting the first initialization voltage Vgint to the pixel driver PXD, an anode initialization voltage line fail transmitting the second initialization voltage vant to the pixel driver PXD, and a first power line VDL transmitting the first power ELVDD to the pixel driver PXD.

The scan writing line GWL may be electrically connected to a gate electrode of each of the first transistor ST1 and the second transistor ST 2. The scan initialization line GIL may be electrically connected to a gate electrode of the third transistor ST 3. The gate control line GCL may be electrically connected to a gate electrode of the fourth transistor ST 4. The emission control line ECL may be electrically connected to a gate electrode of each of the fifth transistor ST5 and the sixth transistor ST6.

The driving transistor DT may be connected in series to the light emitting element LEL between the first power line VDL and the second power line VSL.

The first electrode of the driving transistor DT may be connected to the first power line VDL via a fifth transistor ST 5.

The first electrode of the driving transistor DT may be connected to the data line DL via the second transistor ST 2.

A second electrode of the driving transistor DT may be connected to the light emitting element LEL via a sixth transistor ST 6.

The capacitor C1 may be connected between the first power line VDL and the gate electrode of the driving transistor DT. For example, the gate electrode of the driving transistor DT may be connected to the first power line VDL via a capacitor C1.

Accordingly, in case that the data signal of the data line DL is transmitted to the first electrode of the driving transistor DT, the driving transistor DT may generate a drain-source current corresponding to the data signal. The drain-source current of the driving transistor DT may be supplied as a driving current to the light emitting element LEL.

The light emitting element LEL may emit light having a luminance corresponding to a driving current generated by the driving transistor DT.

The light emitting element LEL may include an anode AND (see fig. 13) AND a cathode CTD (see fig. 13) facing each other AND a light emitting layer EML (see fig. 13) between the anode AND the cathode CTD.

For example, the light emitting element LEL may be an organic light emitting diode having a light emitting layer made of an organic light emitting material. In other embodiments, the light emitting element LEL may be an inorganic light emitting element having a light emitting layer made of an inorganic semiconductor. In other embodiments, the light emitting element LEL may be a quantum dot light emitting element having a quantum dot light emitting layer. In other embodiments, the light emitting element LEL may be a micro light emitting diode.

The capacitor Cel connected in parallel with the light emitting element LEL may be a parasitic capacitance between the anode and the cathode.

The first transistor ST1 may be connected between the gate electrode of the driving transistor DT and the second electrode of the driving transistor DT.

The first transistor ST1 may include a plurality of sub-transistors connected in series. For example, the first transistor ST1 may include a first sub-transistor ST11 and a second sub-transistor ST12.

The first electrode of the first sub-transistor ST11 may be connected to the second electrode of the driving transistor DT, the second electrode of the first sub-transistor ST11 may be connected to the first electrode of the second sub-transistor ST12, and the second electrode of the second sub-transistor ST12 may be connected to the gate electrode of the driving transistor DT.

In this case, the potential of the gate electrode of the driving transistor DT can be prevented from being changed by the leakage current caused by the first transistor ST1 in the off state.

The second transistor ST2 is connected between the first electrode of the driving transistor DT and the data line DL.

A gate electrode of each of the first transistor ST1 and the second transistor ST2 is connected to the scan write line GWL.

In the case where the scan write signal GW is supplied via the scan write line GWL, the first transistor ST1 and the second transistor ST2 are turned on, and the gate electrode and the second electrode of the driving transistor DT become the same potential via the turned-on first transistor ST 1. The data signal of the data line DL may be supplied to the first electrode of the driving transistor DT via the turned-on second transistor ST 2.

Here, in case that a voltage difference between the first electrode and the gate electrode of the driving transistor DT is greater than a threshold voltage, the driving transistor DT may be turned on, and thus a drain-source current may be generated between the first electrode and the second electrode of the driving transistor DT.

The third transistor ST3 is connected between the gate electrode of the driving transistor DT and the gate initialization voltage line VGIL. A gate electrode of the third transistor ST3 may be connected to the scan initialization line GIL.

The third transistor ST3 may include a plurality of sub-transistors connected in series. For example, the third transistor ST3 may include a third sub-transistor ST31 and a fourth sub-transistor ST32.

The first electrode of the third sub-transistor ST31 may be connected to the gate electrode of the driving transistor DT, the second electrode of the third sub-transistor ST31 may be connected to the first electrode of the fourth sub-transistor ST32, and the second electrode of the fourth sub-transistor ST32 may be connected to the gate initialization voltage line VGIL.

In this case, the potential of the gate electrode of the driving transistor DT can be prevented from being changed by the leakage current caused by the third transistor ST3 in the off state.

In case of supplying the scan initialization signal GI via the scan initialization line GIL, the third transistor ST3 may be turned on. At this time, the gate electrode of the driving transistor DT may be connected to the gate initialization voltage line VGIL via the turned-on third transistor ST 3. Accordingly, the potential of the gate electrode of the driving transistor DT may be initialized to the first initialization voltage Vgint of the gate initialization voltage line VGIL.

The fourth transistor ST4 may be connected between the anode of the light emitting element LEL and the anode initialization voltage line tail. The gate electrode of the fourth transistor ST4 may be connected to the gate control line GCL.

In the case of supplying the gate control signal GC via the gate control line GCL, the fourth transistor ST4 may be turned on. At this time, the anode of the light emitting element LEL may be connected to the anode initialization voltage line vat via the fourth transistor ST4 that is turned on. Accordingly, the potential of the anode of the light emitting element LEL may be initialized to the second initialization voltage vant of the anode initialization voltage line VAIL.

The fifth transistor ST5 may be connected between the first electrode of the driving transistor DT and the first power line VDL.

The sixth transistor ST6 may be connected between the second electrode of the driving transistor DT and the anode of the light emitting element LEL.

A gate electrode of each of the fifth transistor ST5 and the sixth transistor ST6 may be connected to the emission control line ECL.

In case of supplying the emission control signal EC via the emission control line ECL, the fifth transistor ST5 and the sixth transistor ST6 may be turned on, and the driving transistor DT and the light emitting element LEL may be connected in series between the first power line VDL and the second power line VSL. Accordingly, the driving current of the driving transistor DT may be supplied to the light emitting element LEL, and the light emitting element LEL may emit light based on the driving current.

As shown in fig. 9, the driving transistor DT and the switching elements ST1 to ST6 included in the pixel driver PXD may all be provided as P-type Metal Oxide Semiconductor Field Effect Transistors (MOSFETs).

In other embodiments, the driving transistor DT included in the pixel driver PXD and some of the switching elements ST1 to ST6 may be provided as P-type MOSFETs, and other transistors may be provided as N-type MOSFETs. In this case, the switching element provided as a P-type MOSFET and the switching element provided as an N-type MOSFET may include active layers of different semiconductor materials. Accordingly, the width of the pixel driver PXD can be reduced by the stacked structure, which can be advantageous for improving resolution.

Fig. 10 is a schematic plan view of two pixel drivers PXD (see fig. 9) provided in a portion F of fig. 6. Fig. 11 is a schematic plan view of the semiconductor layer SEL and the first conductive layer CDL1 of fig. 10. Fig. 12 is a schematic plan view of the semiconductor layer SEL, the first conductive layer CDL1, the second conductive layer CDL2, and the third conductive layer CDL3 of fig. 10. Fig. 13 is a schematic cross-sectional view of an example of a plane cut along line G-G' of fig. 10.

Referring to fig. 10 to 13, the circuit layer 120 may include a semiconductor layer SEL on the substrate 110, a buffer layer 121 disposed between the substrate 110 and the semiconductor layer SEL, a first gate insulating layer 122 covering the semiconductor layer SEL, a first conductive layer CDL1 on the first gate insulating layer 122, a second gate insulating layer 123 covering the first conductive layer CDL1, a second conductive layer CDL2 on the second gate insulating layer 123, an interlayer insulating layer 124 covering the second conductive layer CDL2, a third conductive layer CDL3 on the interlayer insulating layer 124, a first planarization layer 125 covering the third conductive layer CDL3, a fourth conductive layer CDL4 on the first planarization layer 125, a second planarization layer 126 covering the fourth conductive layer CDL4, a fifth conductive layer CDL5 on the second planarization layer 126, and a third planarization layer 127 covering the fifth conductive layer CDL 5.

The light emitting element layer 130 may be disposed on the third planarization layer 127.

Referring to fig. 11, the semiconductor layer SEL may include a driving transistor DT and channel portions CHDT, CH11, CH12, CH2, CH31, CH32, CH4, CH5, and CH6, source electrodes SDT, S11, S12, S2, S31, S32, S4, S5, and S6, and drain electrodes DDT, D11, D12, D2, D31, D32, D4, D5, and D6 included in each pixel driver PXD.

The first conductive layer CDL1 may include the driving transistor DT and gate electrodes GDT, G11, G12, G2, G31, G32, G4, G5, and G6 of the first to sixth transistors ST1 to ST 6.

The first conductive layer CDL1 may further include scan lines, i.e., a scan write line GWL, a scan initialization line GIL, an emission control line ECL, and a gate control line GCL, connected to the gate electrodes GDT, G11, G12, G2, G31, G32, G4, G5, and G6 of the driving transistor DT and the first to sixth transistors ST1 to ST 6. The scan writing line GWL, the scan initializing line GIL, the emission control line ECL, and the gate control line GCL may extend in the first direction DR 1.

Referring to fig. 11 and 12, the second conductive layer CDL2 may include a gate initialization voltage line VGIL connected to the drain electrode D32 of the third transistor ST3 and transmitting the first initialization voltage Vgint (see fig. 9) and an anode initialization voltage line VAIL connected to the drain electrode D4 of the fourth transistor ST4 and transmitting the second initialization voltage vant (see fig. 9). The gate initialization voltage line VGIL and the anode initialization voltage line VAIL may extend in the first direction DR 1.

The first power line VDL may include a first power level auxiliary line VDSBL1 extending in the first direction DR1 and a first power vertical auxiliary line VDSBL2 extending in the second direction DR 2.

The second conductive layer CDL2 may further include a first power level auxiliary line VDSBL1.

The third conductive layer CDL3 may include a first power vertical auxiliary line VDSBL2.

The third conductive layer CDL3 may further include a gate initialization voltage auxiliary line VGIAL and an anode initialization voltage auxiliary line vanal.

The gate initialization voltage auxiliary line VGIAL may be electrically connected to the gate initialization voltage line VGIL and may extend in the second direction DR 2.

The anode initialization voltage auxiliary line vanal may be electrically connected to the anode initialization voltage line VAIL and may extend in the second direction DR 2.

The first power vertical auxiliary line VDSBL2 may be electrically connected to the first power horizontal auxiliary line VDSBL1.

As shown in fig. 11, the driving transistor DT may include a channel portion CHDT, source and drain electrodes SDT and DDT connected to both sides of the channel portion CHDT, and a gate electrode GDT overlapping the channel portion CHDT.

The source electrode SDT of the driving transistor DT may be connected to the drain electrode D2 of the second transistor ST2 and the drain electrode D5 of the fifth transistor ST 5.

The drain electrode DDT of the driving transistor DT may be connected to the source electrode S11 of the first sub-transistor ST11 and the source electrode S6 of the sixth transistor ST 6.

The channel portion CHDT, the source electrode SDT, and the drain electrode DDT of the driving transistor DT may be made of a semiconductor layer SEL. The source electrode SDT and the drain electrode DDT may be portions of the semiconductor layer SEL made conductive by doping the semiconductor material with ions or impurities.

The gate electrode GDT of the driving transistor DT may be made of the first conductive layer CDL 1.

The first transistor ST1 may include a first sub-transistor ST11 and a second sub-transistor ST12 connected in series with each other.

The first sub-transistor ST11 may include a channel portion CH11, source and drain electrodes S11 and D11 connected to both sides of the channel portion CH11, and a gate electrode G11 overlapping the channel portion CH11 and formed of a portion of the scan write line GWL.

The source electrode S11 of the first sub-transistor ST11 may be connected to the drain electrode DDT of the driving transistor DT.

The drain electrode D11 of the first sub-transistor ST11 may be connected to the source electrode S12 of the second sub-transistor ST12.

The second sub-transistor ST12 may include a channel portion CH12, source and drain electrodes S12 and D12 connected to both sides of the channel portion CH12, and a gate electrode G12 overlapping the channel portion CH12 and formed of a protruding portion of the scan writing line GWL.

The source electrode S12 of the second sub-transistor ST12 may be connected to the drain electrode D11 of the first sub-transistor ST 11.

The drain electrode D12 of the second sub-transistor ST12 may be connected to the source electrode S31 of the third sub-transistor ST 31.

The gate electrodes G11 and G12 of the first and second sub-transistors ST11 and ST12 may be different portions of the scan write line GWL made of the first conductive layer CDL 1.

The gate electrode GDT of the driving transistor DT may be connected to the first connection electrode CE1 via the first contact hole CT1, and the first connection electrode CE1 may be connected to the drain electrode D12 of the second sub-transistor ST12 via the second contact hole CT 2.

The first connection electrode CE1 may be made of the third conductive layer CDL 3.

The second transistor ST2 may include a channel portion CH2, source and drain electrodes S2 and D2 connected to both sides of the channel portion CH2, and a gate electrode G2 overlapping the channel portion CH2 and formed of another portion of the scan write line GWL.

The source electrode S2 of the second transistor ST2 may be connected to the second connection electrode CE2 via the fourth contact hole CT 4.

The drain electrode D2 of the second transistor ST2 may be connected to the source electrode SDT of the driving transistor DT and the drain electrode D5 of the fifth transistor ST 5.

The channel portion CH2, the source electrode S2, and the drain electrode D2 of the second transistor ST2 may be made of a semiconductor layer SEL. The source electrode S2 and the drain electrode D2 may be portions of the semiconductor layer SEL made conductive by doping a semiconductor material with ions or impurities.

The gate electrode G2 of the second transistor ST2 may be a portion of the scan write line GWL made of the first conductive layer CDL 1.

The second connection electrode CE2 may be made of the third conductive layer CDL 3.

The third transistor ST3 may include a third sub-transistor ST31 and a fourth sub-transistor ST32 connected in series with each other.

The third sub-transistor ST31 may include a channel portion CH31, source and drain electrodes S31 and D31 connected to both sides of the channel portion CH31, and a gate electrode G31 overlapping the channel portion CH 31.

The source electrode S31 of the third sub-transistor ST31 may be connected to the drain electrode D12 of the second sub-transistor ST 12.

The drain electrode D31 of the third sub-transistor ST31 may be connected to the source electrode S32 of the fourth sub-transistor ST32.

The fourth sub-transistor ST32 may include a channel portion CH32, source and drain electrodes S32 and D32 connected to both sides of the channel portion CH32, and a gate electrode G32 overlapping the channel portion CH 32.

The drain electrode D32 of the fourth sub-transistor ST32 may be connected to the gate initialization voltage auxiliary line VGIAL via the second initialization contact hole VICH 2.

The channel portion CH31, the source electrode S31, and the drain electrode D31 of the third sub-transistor ST31, and the channel portion CH32, the source electrode S32, and the drain electrode D32 of the fourth sub-transistor ST32 may be made of a semiconductor layer SEL. The source electrodes S31 and S32 and the drain electrodes D31 and D32 of the third and fourth sub-transistors ST31 and ST32 may be portions of the semiconductor layer SEL made conductive by doping a semiconductor material with ions or impurities.

The gate electrodes G31 and G32 of the third and fourth sub-transistors ST31 and ST32 may be different portions of the scan initialization line GIL made of the first conductive layer CDL 1.

As shown in fig. 12, the circuit layer 120 (see fig. 13) may further include a shielding electrode SHE overlapping at least a portion of the source electrode S31 of the fourth sub-transistor ST 32.

The shielding electrode SHE may be made of the second conductive layer CDL 2.

The shielding electrode SHE may be connected to each of the first power vertical auxiliary lines VDSBL2 via the third contact hole CT 3.

The shielding electrode SHE may further overlap a portion of the drain electrode D11 of the first sub-transistor ST 11.

Each of the first power vertical auxiliary lines VDSBL2 may be connected to the first power horizontal auxiliary line VDSBL1 via a fifth contact hole CT 5.

As shown in fig. 11, the fourth transistor ST4 may include a channel portion CH4, source and drain electrodes S4 and D4 connected to both sides of the channel portion CH4, and a gate electrode G4 overlapping the channel portion CH4 and formed of a portion of the gate control line GCL.

The source electrode S4 of the fourth transistor ST4 may be connected to the drain electrode D6 of the sixth transistor ST 6.

The drain electrode D4 of the fourth transistor ST4 may be connected to the anode initialization voltage auxiliary line vanal via the fourth initialization contact hole VACH 2.

The channel portion CH4, the source electrode S4, and the drain electrode D4 of the fourth transistor ST4 may be made of a semiconductor layer SEL. The source electrode S4 and the drain electrode D4 may be portions of the semiconductor layer SEL made conductive by doping a semiconductor material with ions or impurities.

The gate electrode G4 of the fourth transistor ST4 may be a portion of the gate control line GCL made of the first conductive layer CDL 1.

The fifth transistor ST5 may include a channel portion CH5, source and drain electrodes S5 and D5 connected to both sides of the channel portion CH5, and a gate electrode G5 overlapping the channel portion CH5 and formed of a portion of the emission control line ECL.

The source electrode S5 of the fifth transistor ST5 may be connected to each of the first power vertical auxiliary lines VDSBL2 via a sixth contact hole CT 6.

The drain electrode D5 of the fifth transistor ST5 may be connected to the source electrode SDT of the driving transistor DT.

The sixth transistor ST6 may include a channel portion CH6, source and drain electrodes S6 and D6 connected to both sides of the channel portion CH6, and a gate electrode G6 overlapping the channel portion CH6 and formed of another portion of the emission control line ECL.

The source electrode S6 of the sixth transistor ST6 may be connected to the drain electrode DDT of the driving transistor DT.

The drain electrode D6 of the sixth transistor ST6 may be connected to the source electrode S4 of the fourth transistor ST4, and may be connected to the third connection electrode CE3 via the seventh contact hole CT 7.

As shown in fig. 12, the third connection electrode CE3 may be made of a third conductive layer CDL 3.

As shown in fig. 11, the channel portion CH5, the source electrode S5, and the drain electrode D5 of the fifth transistor ST5 may be made of a semiconductor layer SEL. The source electrode S5 and the drain electrode D5 may be portions of the semiconductor layer SEL made conductive by doping a semiconductor material with ions or impurities.

The channel portion CH6, the source electrode S6, and the drain electrode D6 of the sixth transistor ST6 may be made of a semiconductor layer SEL. The source electrode S6 and the drain electrode D6 may be portions of the semiconductor layer SEL made conductive by doping a semiconductor material with ions or impurities.

The gate electrodes G5 and G6 of the fifth and sixth transistors ST5 and ST6 may be different portions of the emission control line ECL made of the first conductive layer CDL 1.

As shown in fig. 12, the capacitor C1 (see fig. 9) may be provided by the first capacitor electrode CAE1 and the second capacitor electrode CAE2 overlapping each other.

Here, the first capacitor electrode CAE1 may be a portion of the gate electrode GDT of the driving transistor DT made of the first conductive layer CDL 1.

The second capacitor electrode CAE2 may be a portion of the first power level auxiliary line VDSBL1 made of the second conductive layer CDL 2.

The second connection electrode CE2 is connected to the source electrode S2 of the second transistor ST2 via the fourth contact hole CT 4.

Referring to fig. 10, the fourth conductive layer CDL4 of the circuit layer 120 (see fig. 13) may include a first power auxiliary line VDAL and a second DETL2 extending in the first direction DR 1.

As shown in fig. 6, since the second DETL2 is a part of the first dummy line DML1, the fourth conductive layer CDL4 may include the first power auxiliary line VDAL and the first dummy line DML1.

As shown in fig. 6, the first dummy line DML1 includes a second DETL2 of the input DETL and a first auxiliary line ASL1, the first auxiliary line ASL1 being a portion other than the second DETL2 and to which the second power ELVSS is applied.

The first dummy lines DML1 and the first power auxiliary lines VDAL may be alternately disposed in the second direction DR 2.

As shown in fig. 10, the fourth conductive layer CDL4 may further include a fourth connection electrode CE4 and a fifth connection electrode CE5.

The fourth connection electrode CE4 may be connected to the second connection electrode CE2 via a tenth contact hole CT 10.

The fifth connection electrode CE5 may be electrically connected to the third connection electrode CE3 via the eighth contact hole CT 8.

The first power auxiliary line VDAL may be electrically connected to each of the first power vertical auxiliary lines VDSBL2 of the third conductive layer CDL3 via the eleventh contact hole CT 11.

The fifth conductive layer CDL5 may include a data line DL and a second dummy line DML2.

The data lines DL include a first data line DL1 and a second data line DL2 disposed in a first display side area DSDA1 (see fig. 4).

The second dummy lines DML2 respectively adjacent to the data lines DL may include first and third DETL1 and DETL3 and second auxiliary lines ASL2 for each input DETL, the second auxiliary lines ASL2 being portions other than the first and third DETL1 and DETL3 and to which the second power ELVSS is applied.

The second auxiliary line ASL2 may include a general auxiliary line GASL extending between both ends of the display area DA (see fig. 4) in the second direction DR2, a first extension auxiliary line EASL1 spaced apart from one end of the first DETL1, and a second extension auxiliary line EASL2 spaced apart from one end of the third DETL 3.

The first data line DL1 may be adjacent to the general auxiliary line GASL on one side in the first direction DR 1.

The second data line DL2 may be adjacent to the third DETL3 and the second extension auxiliary line EASL2 on one side in the first direction DR 1.

Each of the data lines DL may be electrically connected to the fourth connection electrode CE4 via the data connection hole DTCH.

Accordingly, the source electrode S2 of the second transistor ST2 may be electrically connected to each of the data lines DL via the second and fourth connection electrodes CE2 and CE4.

The fifth conductive layer CDL5 may further include a sixth connection electrode CE6.

The sixth connection electrode CE6 may be electrically connected to the fifth connection electrode CE5 via a ninth contact hole CT 9.

The fifth connection electrode CE5 may be electrically connected to the third connection electrode CE3, and the third connection electrode CE3 may be electrically connected to the source electrode S4 of the fourth transistor ST4 and the drain electrode D6 of the sixth transistor ST 6.

The sixth connection electrode CE6 may be electrically connected to the source electrode S4 of the fourth transistor ST4 and the drain electrode D6 of the sixth transistor ST6 via the third connection electrode CE3 and the fifth connection electrode CE5.

The sixth connection electrode CE6 may be electrically connected to the anode AND (see fig. 13) of the light emitting element LEL (see fig. 13) via an anode contact hole ANCT (see fig. 13) penetrating the third planarization layer 127 (see fig. 13).

In the first display-side area DSDA1, the third DETL3 may be electrically connected to the second DETL2 via a second deth connection hole DECH2 penetrating the second planarization layer 126 (see fig. 13).

Referring to fig. 10 to 13, the circuit layer 120 may include a semiconductor layer SEL on the substrate 110, a first gate insulating layer 122 covering the semiconductor layer SEL, a first conductive layer CDL1 on the first gate insulating layer 122, a second gate insulating layer 123 covering the first conductive layer CDL1, a second conductive layer CDL2 on the second gate insulating layer 123, an interlayer insulating layer 124 covering the second conductive layer CDL2, a third conductive layer CDL3 on the interlayer insulating layer 124, a first planarization layer 125 covering the third conductive layer CDL3, a fourth conductive layer CDL4 on the first planarization layer 125, a second planarization layer 126 covering the fourth conductive layer CDL4, a fifth conductive layer CDL5 on the second planarization layer 126, and a third planarization layer 127 covering the fifth conductive layer CDL 5.

The circuit layer 120 may further include a buffer layer 121 disposed between the substrate 110 and the semiconductor layer SEL.

The buffer layer 121 may be designed to protect the circuit layer 120 and the light emitting element layer 130 from moisture introduced through the substrate 110, and may be made of at least one inorganic layer.

For example, the buffer layer 121 may be a multilayer in which one or more inorganic layers selected from a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked with each other.

The semiconductor layer SEL may be disposed on the buffer layer 121, and may be made of a silicon semiconductor such as polysilicon, monocrystalline silicon, low-temperature polycrystalline silicon, or amorphous silicon.

The semiconductor layer SEL may include a driving transistor DT provided in each pixel driver PXD (see fig. 9) and channel portions CHDT, CH11, CH12, CH2, CH31, CH32, CH4, CH5, and CH6 (see fig. 11) of the switching elements ST1 to ST 6.

The semiconductor layer SEL may further include source electrodes SDT, S11, S12, S2, S31, S32, S4, S5, and S6 (see fig. 11) and drain electrodes DDT, D11, D12, D2, D31, D32, D4, D5, and D6 (see fig. 11) of the driving transistor DT and the switching elements ST1 to ST 6.

Portions of the semiconductor layer SEL corresponding to the source electrodes SDT, S11, S12, S2, S31, S32, S4, S5, and S6 (see fig. 11) and the drain electrodes DDT, D11, D12, D2, D31, D32, D4, D5, and D6 (see fig. 11) of the driving transistor DT and the switching elements ST1 to ST6 may be doped with ions or impurities to have conductivity.

On the other hand, portions of the semiconductor layer SEL corresponding to the channel portions CHDT, CH11, CH12, CH2, CH31, CH32, CH4, CH5, and CH6 (see fig. 11) of the driving transistor DT and the switching elements ST1 to ST6 may be undoped due to the gate electrodes GDT, G11, G12, G2, G31, G32, G4, G5, and G6, and may maintain semiconductor characteristics that generate channels serving as channels through which carriers move according to potential differences.

The first gate insulating layer 122 may be made of an inorganic layer disposed on the buffer layer 121 and covering the semiconductor layer SEL.

For example, the first gate insulating layer 122 may be made of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and/or an aluminum oxide layer.

The first conductive layer CDL1 may be disposed on the first gate insulating layer 122.

The first conductive layer CDL1 may include the driving transistor DT and the gate electrodes GDT, G11, G12, G2, G31, G32, G4, G5, and G6 of the switching elements ST1 to ST6 provided in each pixel driver PXD.

The first conductive layer CDL1 may further include a scan write line GWL, a scan initialization line GIL, a gate control line GCL, and an emission control line ECL connected to the gate electrodes G11, G12, G2, G31, G32, G4, G5, and G6 of the first to sixth transistors ST1 to ST6 in each pixel driver PXD and extending in the first direction DR 1.

The first conductive layer CDL1 may be a single layer or a plurality of layers made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof.

The second gate insulating layer 123 may be made of an inorganic layer disposed on the first gate insulating layer 122 and covering the first conductive layer CDL 1.

For example, the second gate insulating layer 123 may be made of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and/or an aluminum oxide layer.

The second conductive layer CDL2 may be disposed on the second gate insulating layer 123.

The second conductive layer CDL2 may include a shielding electrode SHE (see fig. 12), a first power level auxiliary line VDSBL1 (see fig. 12), a gate initialization voltage line VGIL (see fig. 12), and an anode initialization voltage line valid (see fig. 12).

The second conductive layer CDL2 may be a single layer or a plurality of layers made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof.

The interlayer insulating layer 124 may be made of an inorganic layer disposed on the second gate insulating layer 123 and covering the second conductive layer CDL 2.

For example, the interlayer insulating layer 124 may be made of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and/or an aluminum oxide layer.

The third conductive layer CDL3 may be disposed on the interlayer insulating layer 124.

The third conductive layer CDL3 may include a first connection electrode CE1 (see fig. 12), a second connection electrode CE2 (see fig. 12), a third connection electrode CE3 (see fig. 12), a first power vertical auxiliary line VDSBL2 (see fig. 12), a gate initialization voltage line VGIL (see fig. 12), and an anode initialization voltage line fail.

Referring to fig. 11, 12 and 13, each of the pixel drivers PXD (see fig. 9) may include a first contact hole CT1, a second contact hole CT2, a third contact hole CT3, a fourth contact hole CT4, a fifth contact hole CT5, a sixth contact hole CT6 and a seventh contact hole CT7.

The first contact hole CT1 may be designed to connect the first connection electrode CE1 and the gate electrode GDT of the driving transistor DT.

The first contact hole CT1 may correspond to a portion of the gate electrode GDT of the driving transistor DT, and may penetrate the second gate insulating layer 123 and the interlayer insulating layer 124. Accordingly, the first connection electrode CE1 made of the third conductive layer CDL3 may be electrically connected to the gate electrode GDT of the driving transistor DT made of the first conductive layer CDL1 via the first contact hole CT 1.

The second contact hole CT2 may be designed to connect any one of the drain electrode D12 of the second sub-transistor ST12 and the source electrode S31 of the third sub-transistor ST31 to the first connection electrode CE1. The drain electrode D12 of the second sub-transistor ST12 and the source electrode S31 of the third sub-transistor ST31 may be connected to each other.

The second contact hole CT2 may correspond to a portion of any one of the drain electrode D12 of the second sub-transistor ST12 and the source electrode S31 of the third sub-transistor ST31, and may penetrate the first gate insulating layer 122, the second gate insulating layer 123, and the interlayer insulating layer 124. Accordingly, the first connection electrode CE1 made of the third conductive layer CDL3 may be electrically connected to the drain electrode D12 of the second sub-transistor ST12 and the source electrode S31 of the third sub-transistor ST31 made of the semiconductor layer SEL via the second contact hole CT 2.

The gate electrode GDT of the driving transistor DT may be electrically connected to the drain electrode D12 of the second sub-transistor ST12 and the source electrode S31 of the third sub-transistor ST31 via the first contact hole CT1, the second contact hole CT2, and the first connection electrode CE 1.

The third contact hole CT3 may be designed to connect the shielding electrode SHE and each of the first power vertical auxiliary lines VDSBL2.

The third contact hole CT3 may correspond to a portion of each of the first power vertical auxiliary lines VDSBL2, and may penetrate the interlayer insulating layer 124. Accordingly, the shielding electrode SHE made of the second conductive layer CDL2 may be electrically connected to each of the first power vertical auxiliary lines VDSBL2 made of the third conductive layer CDL3 via the third contact hole CT 3.

The fourth contact hole CT4 may be designed to connect the second connection electrode CE2 and the source electrode S2 of the second transistor ST 2.

The fourth contact hole CT4 may correspond to a portion of the source electrode S2 of the second transistor ST2, and may penetrate the first gate insulating layer 122, the second gate insulating layer 123, and the interlayer insulating layer 124. Accordingly, the second connection electrode CE2 made of the third conductive layer CDL3 may be electrically connected to the source electrode S2 of the second transistor ST2 made of the semiconductor layer SEL via the fourth contact hole CT 4.

The fifth contact hole CT5 may be designed to connect each of the first power horizontal auxiliary line VDSBL1 and the first power vertical auxiliary line VDSBL 2.

The fifth contact hole CT5 may correspond to a portion of the first power level auxiliary line VDSBL1 and may penetrate the interlayer insulating layer 124. Accordingly, each of the first power vertical auxiliary lines VDSBL2 made of the third conductive layer CDL3 may be electrically connected to the first power horizontal auxiliary line VDSBL1 made of the second conductive layer CDL2 via the fifth contact hole CT 5.

The sixth contact hole CT6 may be designed to connect each of the first power vertical auxiliary lines VDSBL2 with the source electrode S5 of the fifth transistor ST 5.

The sixth contact hole CT6 may correspond to a portion of the source electrode S5 of the fifth transistor ST5, and may penetrate the first gate insulating layer 122, the second gate insulating layer 123, and the interlayer insulating layer 124. Accordingly, each of the first power vertical auxiliary lines VDSBL2 made of the third conductive layer CDL3 may be electrically connected to the source electrode S5 of the fifth transistor ST5 made of the semiconductor layer SEL via the sixth contact hole CT 6.

The seventh contact hole CT7 may be designed to connect the third connection electrode CE3 and the drain electrode D6 of the sixth transistor ST 6.

The seventh contact hole CT7 may correspond to a portion of the drain electrode D6 of the sixth transistor ST6, and may penetrate the first gate insulating layer 122, the second gate insulating layer 123, and the interlayer insulating layer 124. Accordingly, the third connection electrode CE3 made of the third conductive layer CDL3 may be electrically connected to the drain electrode D6 of the sixth transistor ST6 made of the semiconductor layer SEL via the seventh contact hole CT 7.

The third conductive layer CDL3 may have a multilayer structure including a metal layer having low resistance properties and metal layers having ion diffusion preventing properties and disposed on upper and lower surfaces of the metal layer, respectively.

For example, the third conductive layer CDL3 may have a stacked structure of metal layers, and each of the metal layers of the third conductive layer CDL3 may be made of at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

Specifically, the metal layer having low resistance properties may be made of at least one of aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), and copper (Cu).

The metal layer having ion diffusion preventing properties may be made of titanium (Ti).

For example, the third conductive layer CDL3 may have a stacked structure of titanium (Ti)/aluminum (Al)/titanium (Ti) (Ti/Al/Ti).

The first planarization layer 125 covering the third conductive layer CDL3 may be made of an organic layer including, for example, an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

The fourth conductive layer CDL4 may be disposed on the first planarization layer 125.

As shown in fig. 10, the fourth conductive layer CDL4 may include a first power auxiliary line VDAL, a first dummy line DML1, a fourth connection electrode CE4, and a fifth connection electrode CE5.

The first dummy line DML1 includes a second DETL2 and a first auxiliary line ASL1.

The fourth conductive layer CDL4 may be a single layer or a plurality of layers made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof.

As with the third conductive layer CDL3, the fourth conductive layer CDL4 may have a stacked structure of metal layers, and each of the metal layers of the third conductive layer CDL3 may be made of at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

For example, the fourth conductive layer CDL4 may have a stacked structure of titanium (Ti)/aluminum (Al)/titanium (Ti) (Ti/Al/Ti).

The second planarization layer 126 covering the fourth conductive layer CDL4 may be made of an organic layer such as an acryl-based resin, an epoxy resin, a phenol resin, a polyamide resin, and/or a polyimide resin.

A fifth conductive layer CDL5 may be disposed on the second planarization layer 126.

As shown in fig. 10, the fifth conductive layer CDL5 may include a data line DL, a second dummy line DML2, and a sixth connection electrode CE6.

The second dummy line DML2 may include a first DETL1, a third DETL3, and a second auxiliary line ASL2.

The fifth conductive layer CDL5 may be a single layer or a plurality of layers made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof.

As shown in fig. 13, the third planarization layer 127 covering the fifth conductive layer CDL5 may be made of an organic layer including, for example, an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, and/or a polyimide resin.

Referring to fig. 10 and 13, each pixel driver PXD (see fig. 9) may further include an eighth contact hole CT8, a ninth contact hole CT9, a tenth contact hole CT10, and an eleventh contact hole CT11.

The eighth contact hole CT8 may be designed to connect the third connection electrode CE3 and the fifth connection electrode CE5.

The eighth contact hole CT8 may correspond to a portion of the third connection electrode CE3 and may penetrate the first planarization layer 125. Accordingly, the fifth connection electrode CE5 may be electrically connected to the third connection electrode CE3 via the eighth contact hole CT 8.

The ninth contact hole CT9 may be designed to connect the fifth connection electrode CE5 and the sixth connection electrode CE 6.

The ninth contact hole CT9 may correspond to a portion of the fifth connection electrode CE5, and may penetrate the second planarization layer 126. Accordingly, the sixth connection electrode CE6 may be electrically connected to the fifth connection electrode CE5 via the ninth contact hole CT 9.

The tenth contact hole CT10 may be designed to connect the fourth connection electrode CE4 and the second connection electrode CE2.

The tenth contact hole CT10 may correspond to a portion of the second connection electrode CE2 and may penetrate the first planarization layer 125. Accordingly, the fourth connection electrode CE4 may be electrically connected to the second connection electrode CE2 via the tenth contact hole CT 10.

The data connection hole DTCH may be designed to electrically connect each of the fourth connection electrode CE4 and the data line DL.

The data connection hole DTCH may correspond to a portion of the fourth connection electrode CE4, and may penetrate the second planarization layer 126. Accordingly, each of the data lines DL may be electrically connected to the fourth connection electrode CE4 via the data connection hole DTCH.

As shown in fig. 13, the light emitting element layer 130 may be disposed on the third planarization layer 127 of the circuit layer 120.

For example, the light emitting element layer 130 may include: an anode AND disposed on the third planarization layer 127, corresponding to the emission areas EA, respectively, AND electrically connected to the pixel drivers PXD, respectively (see fig. 9); a pixel defining layer PDL, which may be disposed on the third planarization layer 127, corresponds to the non-emission area NEA between the emission areas EA AND covers the edge of the anode AND; the light emitting layers EML respectively correspond to the emission areas EA AND are respectively disposed on the anode AND; and a cathode CTD corresponding to the emission area EA and may be disposed on the pixel defining layer PDL and the light emitting layer EML.

The cathode CTD may be electrically connected to the second power supply line VSSPL (see fig. 5).

Each of the anode electrodes AND may be connected to the sixth connection electrode CE6 via an anode contact hole ANCT penetrating the third planarization layer 127.

Accordingly, each of the anode electrodes AND may be electrically connected to the pixel driver PXD via the seventh contact hole CT7, the third connection electrode CE3, the eighth contact hole CT8, the fifth connection electrode CE5, the ninth contact hole CT9, the sixth connection electrode CE6, AND the anode contact hole ANCT.

The pixel defining layer PDL may be made of an organic layer.

The light emitting layer EML may include an organic light emitting material.

Although not shown separately, at least a first common layer (not shown) including a hole transport material may be disposed between the anode AND the light emitting layer EML.

A second common layer (not shown) including at least an electron transport material may be disposed between the emission layer EML and the cathode CTD.

The cathode CTD may correspond to the entire display area DA (see fig. 2).

Although not shown separately, the cathode electrode CTD may be connected to the second power line VSSPL in the non-display area NDA (see fig. 2).

Accordingly, the light emitting element layer 130 may include a plurality of light emitting elements LEL, which respectively correspond to the emission regions EA, AND each of the plurality of light emitting elements LEL includes anode AND cathode electrodes CTD facing each other AND a light emitting layer EML interposed between the anode AND cathode electrodes CTD.

The light emitting element layer 130 may be covered with a sealing layer 140 for blocking permeation of oxygen or moisture.

The sealing layer 140 may cover the light emitting element layer 130, and may have a structure in which at least one inorganic layer and at least one organic layer are alternately stacked with each other.

For example, the sealing layer 140 may include a first inorganic layer 141 covering the cathode CTD and made of an inorganic insulating material, an organic layer 142 disposed on the first inorganic layer 141 and made of an organic insulating material, and a second inorganic layer 143 covering the organic layer 142 and made of an inorganic insulating material.

Fig. 14 is a schematic plan view showing an example of the emission area EA provided in the portion C of fig. 4 and 5.

Referring to fig. 14, the emission area EA of the display device 10 (see fig. 1) according to the embodiment may include a first emission area EA1, a second emission area EA2, and a third emission area EA3.

The first and third emission areas EA1 and EA3 may be alternately arranged in each of the first and second directions DR1 and DR 2.

The second emission area EA2 may be adjacent to the first emission area EA1 or the third emission area EA3 in the first diagonal direction DD1 or the second diagonal direction DD 2.

The second emission areas EA2 may be arranged side by side in each of the first and second directions DR1 and DR 2.

The non-emission area NEA may be disposed around each of the emission areas EA.

Fig. 15 is a schematic plan view showing the emission area EA and the via provided in the portion C of fig. 4 and 5 in the display device 10 (see fig. 1) according to the embodiment. Fig. 16 is a schematic plan view showing the emission area EA and the via provided in the portion D of fig. 4 in the display device 10 according to the embodiment of fig. 15.

Referring to fig. 15 and 16, the display device 10 according to the embodiment includes a via for electrical connection between the first dummy line DML1 and the second dummy line DML 2.

Some of the via holes via may overlap one of the emission areas EA, and other via holes may be disposed in the non-emission area NEA.

As described above with reference to fig. 5 and 6, according to an embodiment, the first dummy line DML1 may include a second DETL2 input into the det line for electrically connecting the first demultiplexer circuit unit DMC1 and the first data supply line DSPL1, and a first auxiliary line ASL1 electrically connected to the second power supply line VSSPL to receive the second power ELVSS (see fig. 9).

The second dummy line DML2 may include a first DETL1 and a third DETL3 of the input detel DETL and a second auxiliary line ASL2 electrically connected to the second power line VSSPL to receive the second power ELVSS.

The second auxiliary line ASL2 may include a general auxiliary line GASL extending between both ends of the display area DA in the second direction DR2, a first extension auxiliary line EASL1 spaced apart from an end of the first DETL1 in the second direction DR2, and a second extension auxiliary line EASL2 spaced apart from an end of the third DETL3 in the second direction DR 2.

Accordingly, as shown in fig. 15, the via hole via may include a first detour connection hole DECH1 for electrical connection between the second DETL2 and the first DETL1 detour, and a second detour connection hole DECH2 for electrical connection between the second DETL2 and the third DETL3 detour.

As shown in fig. 16, the via hole may further include an auxiliary connection hole ASCH for electrical connection between the first auxiliary line ASL1 and the second auxiliary line ASL2.

The auxiliary connection hole ASCH may include a first auxiliary connection hole ASCH1 overlapping the common auxiliary line GASL, a second auxiliary connection hole ASCH2 disposed in the first common side region GSA1 and overlapping the second extension auxiliary line EASL2, and a third auxiliary connection hole ASCH3 disposed in the second common side region GSA2 and overlapping the first extension auxiliary line EASL 1.

According to an embodiment, the first and second detour connection holes DECH1 and DECH2 among the via holes via may be disposed in the non-emission area NEA.

In this case, each of the first auxiliary connection holes ASCH1 among the auxiliary connection holes ASCH may overlap one of the emission areas EA.

The second DETL2 extends in the first direction DR1 between the first DETL1 and the third DETL3, and the first deth 1 and the second DECH2 deth are disposed at both ends of the second DETL 2.

Therefore, the visibility of the end portions at both ends of the second det 2 and the visibility of the first det connection hole DECH1 and the second det connection hole DECH2 are improved due to the interaction therebetween. Accordingly, the image quality of the demultiplexer adjacent region DAA (see fig. 4) becomes different from that of the general region GA (see fig. 4), thereby deteriorating the display quality of the display device 10.

However, according to the embodiment, since the first and second detour connection holes DECH1 and DECH2 are disposed in the non-emission area NEA, the visibility of the first and second detour connection holes DECH1 and DECH2 may be reduced.

Since the first and second detour connection holes DECH1 and DECH2 are disposed in the non-emission region NEA, the light emitting element LEL (see fig. 13) of each of the emission regions EA may not overlap with the first and second detour connection holes DECH1 or DECH 2. Therefore, it is possible to prevent the light emitting direction of the light emitting element LEL from becoming different due to the influence of the step difference caused by the first detour connection hole DECH1 and the second detour connection hole DECH 2.

Therefore, degradation of the display quality of the display device 10 due to the input detour IDEL can be reduced.

The first extension auxiliary line EASL1 among the second auxiliary lines ASL2 may be disposed in parallel with the first DETL1 in the second direction DR2 and may be spaced apart from an end of the first DETL 1.

The second extension auxiliary line EASL2 among the second auxiliary lines ASL2 may be disposed in parallel with the third DETL3 in the second direction DR2 and may be spaced apart from an end of the third DETL 3.

Since each of the second extension auxiliary lines EASL2 of the first display-side area DSDA1 and each of the first extension auxiliary lines EASL1 of the second display-side area DSDA2 cross one or more second DETL2 DETL, it is difficult to overlap them with the auxiliary connection hole ASCH.

Therefore, according to the first embodiment, the auxiliary connection hole ASCH may not be provided in the first display-side area DSDA1 and the second display-side area DSDA2, but may be provided in the display middle area DMDA and the general area GA.

As shown in fig. 16, in the first general side area GSA1, auxiliary connection holes ASCH1 and ASCH2, which overlap with the first auxiliary lines ASL1 adjacent thereto, respectively, in the second direction DR2 may be arranged in the third diagonal direction DD 3.

For example, the auxiliary connection holes ASCH of the first general side region GSA1 may include first auxiliary connection holes ASCH1 and second auxiliary connection holes ASCH2 arranged in the third diagonal direction DD3 and alternating with each other.

In the second common side region GSA2, auxiliary connection holes ASCH1 and ASCH3, which overlap the first auxiliary lines ASL1 adjacent thereto, respectively, in the second direction DR2 may be arranged in the fourth oblique line direction DD 4.

For example, the auxiliary connection holes ASCH of the second common side region GSA2 may include first auxiliary connection holes ASCH1 and third auxiliary connection holes ASCH3 arranged in the fourth diagonal direction DD4 and alternating with each other.

Fig. 17 is a schematic plan view showing an emission area EA and a via provided in part C of fig. 4 and 5 in the display device 10 (see fig. 1) according to another embodiment.

The display device according to the embodiment of fig. 17 may be identical to the embodiment of fig. 15, except that the first auxiliary connection hole ASCH1 among the via holes via may be disposed in the non-emission area NEA and each of the first and second detour connection holes DECH1 and DECH2 may overlap one of the emission areas EA. Accordingly, redundant description will be omitted below.

The first and second detour connection holes DECH1 and DECH2 may be disposed at both ends of the second detour line DETL2 in the demultiplexer adjacent region DAA (see fig. 4), but one or more first auxiliary connection holes ASCH1 may be disposed in each of the first auxiliary lines ASL1 of the display region DA (see fig. 2). Accordingly, the number of the first auxiliary connection holes ASCH1 may be greater than the total number of the first and second bypass connection holes DECH1 and DECH2 disposed in the demultiplexer adjacent region DAA.

Thus, according to the embodiment of fig. 17, a relatively large number of the first auxiliary connection holes ASCH1 may be provided in the non-emission area NEA (see fig. 2), instead of a relatively small number of the first and second bypass connection holes DECH1 and DECH2. As a result, the visibility of the first auxiliary connection hole ASCH1 may be reduced. It is possible to prevent the light emitting direction of the light emitting element LEL (see fig. 13) from becoming different due to the influence of the step difference caused by the first auxiliary connection hole ASCH 1. Therefore, this can reduce degradation of the display quality of the display device 10 due to the via hole via.

Fig. 18 is a schematic plan view showing the data line DL, the first dummy line DML1, the second dummy line DML2, and the via hole via provided in the portion C of fig. 4 and 5 in the display device 10 (see fig. 1) according to still another embodiment. Fig. 19 is a schematic plan view showing the data line DL, the first dummy line DML1, the second dummy line DML2, and the via hole via provided in the portion D of fig. 4 in the display device 10 according to the embodiment of fig. 18.

Referring to fig. 18 and 19, the display device 10 according to the embodiment of fig. 18 may be substantially the same as the embodiment shown in fig. 15 and 16 or the embodiment shown in fig. 17, except that each of the data line DL and the second dummy line DML2 may not include a pair of sub-protrusions protruding toward each adjacent pixel driver PXD (see fig. 9) and symmetrical to each other, but may include only the sub-protrusion SPR1 overlapping the data connection hole DTCH, the sub-protrusion SPR2, SPR4 or SPR6 facing the data connection hole DTCH, the sub-protrusion SPR3 or SPR7 overlapping the auxiliary connection hole ASCH, and the sub-protrusion SPR5 overlapping the first bypass connection hole DECH1 or the second bypass connection hole DECH 2. Accordingly, redundant description will be described below.

According to the embodiment of fig. 18, each of the first and second data lines DL1 and DL2 disposed in the first display-side area DSDA1 (see fig. 4) and the first general-purpose side area GSA1 may include a first main extension MEX1 extending in the second direction DR2 and a first sub-protrusion SPR1 protruding from the first main extension MEX1 and overlapping the data connection hole DTCH of each adjacent pixel driver PXD.

The general auxiliary line GASL adjacent to each of the first data lines DL1 may include a second main extension MEX2 extending in the second direction DR2 and a second sub-protrusion SPR2 protruding from the second main extension MEX2 and facing the first sub-protrusion SPR1 of the first data line DL 1.

In the general area GA (see fig. 4), each general auxiliary line GASL may further include a third sub-protrusion SPR3 protruding from the second main extension MEX2 and overlapping the first auxiliary connection hole ASCH 1.

In the first general side area GSA1, the first auxiliary connection hole ASCH1 may be disposed in the third sub-protrusion SPR3 of the general auxiliary line GASL.

The first auxiliary connection hole ASCH1 may be arranged in the second diagonal direction DD 2.

Each of the third DETL3 adjacent to the second data line DL2 may include a third main extension MEX3 extending in the second direction DR2, a fourth sub-protrusion SPR4 protruding from the third main extension MEX3 and facing the first sub-protrusion SPR1 of the second data line DL2, and a fifth sub-protrusion SPR5 facing the first main extension MEX1 of the second data line DL2 and overlapping the second detour connection hole DECH2 among the auxiliary connection holes ASCH.

The fifth sub-protrusion SPR5 may protrude toward one pixel driver PXD adjacent to an intersection of an end of the second DETL2 and one third DETL 3.

Each of the second extension auxiliary lines EASL2 adjacent to the second data line DL2 may include a fourth main extension MEX4 extending in the second direction DR2 and a sixth sub-protrusion SPR6 protruding from the fourth main extension MEX4 and facing the first sub-protrusion SPR1 of the second data line DL 2.

In the general area GA, each of the second extension auxiliary lines EASL2 may further include a seventh sub-protrusion SPR7 protruding from the fourth main extension part MEX4 and overlapping the second auxiliary connection hole ASCH 2.

In the first general side area GSA1, the second auxiliary connection hole ASCH2 may be arranged in the second diagonal direction DD 2. The arrangement direction of the first auxiliary connection holes ASCH1 may be parallel to the arrangement direction of the second auxiliary connection holes ASCH 2.

The second display-side area DSDA2 and the second common-side area GSA2 may be substantially the same as the first display-side area DSDA1 and the first common-side area GSA1 except that the second display-side area DSDA2 and the second common-side area GSA2 may include the third data line DL3 and the fourth data line DL4 instead of the first data line DL1 and the second data line DL2 and include the first DETL1 instead of the third DETL 3. The second display-side region DSDA2 and the second common-side region GSA2 may be substantially similar to the first display-side region DSDA1 and the first common-side region GSA1, the third data line DL3 and the fourth data line DL4 may be similar to the first data line DL1 and the second data line DL2, and the first det 1 may be similar to the third det 3. Therefore, redundant description will be omitted.

As described above, according to the embodiment of fig. 18, each of the data line DL and the second dummy line DML2 may include only the sub-protrusion overlapping the via. Accordingly, the number of sub-protrusions may be reduced as compared with a case where each of the data line DL and the second dummy line DML2 includes a pair of sub-protrusions protruding toward each adjacent pixel driver PXD and symmetrical to each other. Accordingly, since the resistance of each of the data line DL and the second dummy line DML2 may decrease as the number of sub-protrusions decreases, RC delay may be reduced.

Fig. 20 is a schematic plan view showing a data line DL, a first dummy line DML1, a second dummy line DML2, and a via hole via provided in a portion D of fig. 4 in a display device 10 (see fig. 1) according to still another embodiment. Fig. 21 is a schematic plan view showing the data line DL, the first dummy line DML1, the second dummy line DML2, and the via hole via provided in the portion E of fig. 4 in the display device 10 according to the embodiment of fig. 20.

Referring to fig. 20 and 21, the display device 10 according to the embodiment of fig. 20 may be substantially the same as the embodiment shown in fig. 15 and 16 or the embodiment shown in fig. 17, except that the auxiliary connection hole ASCH may not include the second auxiliary connection hole ASCH2 (see fig. 16) and the third auxiliary connection hole ASCH3 (see fig. 16) and the first and second extension auxiliary lines EASL1 and EASL2 may be connected to the second power line VSSPL (see fig. 5) in the non-display area NDA. Accordingly, redundant description will be omitted hereinafter.

According to an embodiment, the auxiliary connection hole ASCH may include only the first auxiliary connection hole ASCH1 overlapping the general auxiliary line GASL.

The first and second extension auxiliary lines EASL1 and EASL2 may not be electrically connected to the first auxiliary line ASL1, but may be directly electrically connected to the second power line VSSPL in the non-display area NDA.

In this case, due to the mesh structure of the general auxiliary line GASL and the first auxiliary line ASL1, the resistance of the line for transmitting the second power ELVSS (see fig. 9) may be reduced, while the heat generation is reduced due to the reduction in the number of auxiliary connection holes ASCH.

Fig. 22 is a schematic plan view showing the data line DL, the first dummy line DML1, the second dummy line DML2, and the via hole via provided in the portion E of fig. 4 in the display device 10 (see fig. 1) according to another embodiment.

Referring to fig. 22, the display device 10 according to the embodiment of fig. 22 may be substantially the same as the embodiment shown in fig. 20 and 21, except that each of the data line DL and the second dummy line DML2 may include only a sub-protrusion overlapping the via hole via instead of a pair of sub-protrusions protruding toward each adjacent pixel driver PXD (see fig. 9) and symmetrical to each other. Therefore, redundant description will be omitted later.

According to the embodiment of fig. 22, the auxiliary connection hole ASCH may include only the first auxiliary connection hole ASCH1 overlapping the general auxiliary line GASL. Accordingly, each of the first and second extension auxiliary lines EASL1 and EASL2 may not include the seventh sub-protrusion SPR7 (see fig. 19) overlapped with the second auxiliary connection hole ASCH2 (see fig. 19) or the third auxiliary connection hole ASCH3 (see fig. 19), but may include only the sixth sub-protrusion SPR6 facing the first sub-protrusion SPR 1.

The fourth main extension part MEX4 of each of the first and second extension auxiliary lines EASL1 and EASL2 may extend to the non-display area NDA and may be connected to the second power line VSSPL.

The embodiment according to fig. 22 may be substantially the same as the embodiment shown in fig. 15 and 16 or the embodiment shown in fig. 17, except that each of the data line DL and the second dummy line DML2 may include only the sub-protrusion SPR1 overlapping the data connection hole DTCH (see fig. 18), the sub-protrusion SPR2, SPR4 (see fig. 18) or SPR6 facing the data connection hole DTCH, the sub-protrusion SPR3 overlapping the auxiliary connection hole ASCH, and the sub-protrusion SPR5 (see fig. 18) overlapping the first bypass connection hole DECH1 or the second bypass connection hole DECH 2. Therefore, redundant description will be omitted.

The display device according to an embodiment may include a substrate, a circuit layer on the substrate, a light emitting element layer on the circuit layer, and a display driving circuit supplying a data driving signal corresponding to a data signal of a data line of the circuit layer.

The substrate may include a main region and a sub-region protruding from one side of the main region, and the main region may include a display region in which the emission region is arranged and a non-display region disposed around the display region.

The circuit layer may include pixel drivers respectively corresponding to the emission regions, data lines transmitting data signals to the pixel drivers, first dummy lines disposed in the display region and extending in a first direction crossing the data lines, second dummy lines extending in a second direction parallel to the data lines and respectively adjacent to the data lines, and demultiplexer circuit units disposed in a demultiplexer region (adjacent to the sub-regions) of the non-display region and electrically connected between the display driving circuits and the data lines.

As described above, the display device according to the embodiment may include the demultiplexer circuit unit electrically connected between the display driving circuit and the data line. Each of the demultiplexer circuit units may output a data signal of the data line based on a data driving signal of the display driving circuit. Accordingly, the data driving signals of the display driving circuit may not correspond to the data lines, respectively, but may correspond to the demultiplexer circuit units which are fewer in number than the data lines, respectively. Due to the demultiplexer circuit unit, the data supply lines respectively electrically connected to the output terminals of the display driving circuit may be provided to be fewer in number than the data lines. Accordingly, the width of the arrangement of the data supply lines allocated to the non-display area can be reduced.

Accordingly, the width of the non-display area can be reduced without reducing the number of data lines, thereby eliminating the limitation on resolution due to the width of the non-display area. It is possible to prevent a short defect between data supply lines due to a reduction in the width of the non-display area.

Further, according to an embodiment, some of the vias for electrical connection between the first dummy line and the second dummy line may overlap one of the emission regions, and other vias are disposed in non-emission regions between the emission regions.

Therefore, the visibility of the via hole can be reduced, and further, the degradation of the display quality due to the via hole can be reduced.

According to an embodiment, the demultiplexer region may include a demultiplexer middle region in the middle, a first demultiplexer side region adjacent to the bent portion of the edge of the substrate, and a second demultiplexer side region disposed between the demultiplexer middle region and the first demultiplexer side region.

In this case, the demultiplexer circuit unit may include a first demultiplexer circuit unit disposed in the first demultiplexer-side region and a second demultiplexer circuit unit disposed in the second demultiplexer-side region.

A first data supply line among the data supply lines may be electrically connected to the first demultiplexer circuit unit via an input detour line disposed in the display region.

On the other hand, a second data supply line among the data supply lines may be connected to the second demultiplexer circuit unit.

As described above, since the first data supply line is electrically connected to the first demultiplexer circuit unit of the first demultiplexer-side region via the input detour, the first data supply line may extend to the second demultiplexer-side region as the second data supply line. Accordingly, the first data supply line may not be disposed in the first demultiplexer-side region adjacent to the bent portion of the substrate. This can reduce the width of the first demultiplexer-side region, thereby further reducing the width of the non-display region.

However, the effects of the present disclosure are not limited to those set forth herein. The above and other effects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains.

Embodiments have been disclosed herein and, although terminology is employed, they are used and described in a generic and descriptive sense only and not for purposes of limitation. In some cases, features, characteristics, and/or elements described in connection with an embodiment may be used alone or in combination with features, characteristics, and/or elements described in connection with other embodiments unless specifically indicated otherwise, as will be apparent to one of ordinary skill in the art. Accordingly, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure.

Claims

1. A display device, wherein the display device comprises:

a substrate, comprising:

a main area comprising:

a display area including a plurality of emission areas; and

a non-display area disposed around the display area; and

a sub-region protruding from one side of the main region;

a circuit layer disposed on the substrate; and

a light emitting element layer disposed on the circuit layer and including a plurality of light emitting elements in the plurality of emission regions, wherein,

the circuit layer includes:

a plurality of pixel drivers corresponding to the plurality of emission regions and electrically connected to the plurality of light emitting elements;

a plurality of data lines transmitting a plurality of data signals to the plurality of pixel drivers;

a plurality of first dummy lines disposed in the display region and extending in a first direction crossing the plurality of data lines; and

a plurality of second dummy lines extending in a second direction parallel to the plurality of data lines, and adjacent to the plurality of data lines on one side in the first direction,

a subset of vias among the plurality of vias through which the plurality of first dummy lines and the plurality of second dummy lines are electrically connected overlap one of the plurality of emission regions, and

Another subset of vias among the plurality of vias is disposed in a non-emissive region between the plurality of emissive regions.

2. The display device according to claim 1, wherein the display device further comprises:

a display driving circuit disposed on the substrate in the sub-region, and supplying a plurality of data driving signals corresponding to the plurality of data signals of the plurality of data lines of the circuit layer, wherein,

the circuit layer further includes: a plurality of demultiplexer circuits disposed in a demultiplexer region adjacent to the sub-region of the non-display region, and electrically connected between the display driving circuit and the plurality of data lines,

one of the plurality of demultiplexer circuits comprises:

an input terminal electrically connected to the display driving circuit; and

a first output terminal and a second output terminal electrically connected to two of the plurality of data lines, respectively,

the demultiplexer region includes:

a demultiplexer intermediate region located in the middle;

a first demultiplexer-side region adjacent to a folded portion of an edge of the substrate; and

A second demultiplexer-side region disposed between the demultiplexer intermediate region and the first demultiplexer-side region,

the plurality of demultiplexer circuits includes:

a first demultiplexer circuit provided in the first demultiplexer-side region; and

a second demultiplexer circuit provided in the second demultiplexer-side region,

the circuit layer further includes:

a plurality of data supply lines electrically connected to a plurality of output terminals of the display driving circuit;

first and second power supply lines disposed in the sub-region and the non-display region, and transmitting first and second power for driving the plurality of light emitting elements, respectively; and

a plurality of first power auxiliary lines disposed in the display region, extending in the first direction, and electrically connected to the first power lines,

a first data supply line among the plurality of data supply lines extends from the sub-region to the second demultiplexer-side region, and is electrically connected to an input terminal of the first demultiplexer circuit via an input detour line provided in the display region,

A second data supply line among the plurality of data supply lines extends from the sub-region to the second demultiplexer-side region and is electrically connected to an input terminal of the second demultiplexer circuit, the display region including:

a demultiplexer adjacent region adjacent to the demultiplexer region; and

a common area disposed between the demultiplexer adjacent area and the non-display area in the second direction,

the demultiplexer adjacent region includes:

displaying an intermediate region adjacent to the demultiplexer intermediate region;

a first display side region adjacent to the first demultiplexer side region; and

a second display side area adjacent to the second demultiplexer side area,

the general area includes:

a universal middle region adjacent to the display middle region;

a first general side region adjacent to the first display side region; and

a second common side region adjacent to the second display side region,

the input detour line includes:

a first detour line provided in the second display side region, the first detour line extending in the second direction and being electrically connected to the first data supply line;

A second detour line provided in the second display side region and the first display side region, the second detour line extending in the first direction and electrically connected to the first detour line; and

a third detour line provided in the first display side region, the third detour line extending in the second direction toward the first demultiplexer side region and being electrically connected to the second detour line,

the plurality of first dummy lines includes:

the second detour line; and

a plurality of first auxiliary lines electrically connected to the second power lines,

the plurality of second dummy lines includes:

the first detour line and the third detour line; and

a plurality of second auxiliary lines electrically connected to the second power lines,

the first detour line extends in the second direction between the first data supply line and the second detour line,

the second detour line extends in the first direction between the first detour line and the third detour line,

the third detour line extends in the second direction between the first demultiplexer-side region and the second detour line, and

the plurality of second auxiliary lines includes:

A plurality of general auxiliary lines extending between both ends of the display area in the second direction;

a first extension auxiliary line spaced apart from an end of the first detour line in the second direction, and extending to the second common side region; and

a second extension auxiliary line spaced apart from an end of the third detour line in the second direction, and extending to the first common side region, the plurality of data lines including:

a first data line and a second data line electrically connected to a first output terminal and a second output terminal of the first demultiplexer circuit unit, respectively, and disposed in the first display side region and the first common side region; and

a third data line and a fourth data line electrically connected to a first output terminal and a second output terminal of the second demultiplexer circuit unit, respectively, and disposed in the second display side region and the second common side region, each of the first data line and the third data line being adjacent to one of the plurality of common auxiliary lines on the one side in the first direction;

The second data line is adjacent to the third detour line and the second extension auxiliary line on the one side in the first direction,

the fourth data line is adjacent to the first detour line and the first extension auxiliary line on the one side in the first direction, and

the plurality of vias includes:

a first detour connection hole through which the first detour line and the second detour line are electrically connected;

a second detour connection hole through which the second detour line and the third detour line are electrically connected; and

the plurality of first auxiliary lines and the plurality of second auxiliary lines are electrically connected via the plurality of auxiliary connection holes.

3. The display device according to claim 2, wherein,

the plurality of auxiliary connection holes includes a plurality of first auxiliary connection holes overlapping the plurality of general auxiliary lines,

the first and second detour connection holes are disposed in the non-emission region, and

each of the plurality of first auxiliary connection holes overlaps one of the plurality of emission regions.

4. The display device according to claim 3, wherein,

The plurality of auxiliary connection holes further include:

a second auxiliary connection hole provided in the first general side region and overlapping the second extension auxiliary line; and

a third auxiliary connection hole provided in the second common side region and overlapping the first extension auxiliary line, and

the second auxiliary connection hole and the third auxiliary connection hole are disposed in the non-emission region.

5. A display device according to claim 3, wherein the first extension auxiliary line and the second extension auxiliary line are electrically connected to the second power supply line in the non-display region.

6. The display device according to claim 2, wherein,

each of the first and second detour connection holes overlaps one of the plurality of emission regions, and

the plurality of first auxiliary connection holes are disposed in the non-emission region.

7. The display device according to claim 2, wherein,

the first detour connection holes overlapping with the adjacent second detour lines in the second direction are provided in a first oblique line direction intersecting the first direction and the second direction, respectively, and

And second detour connection holes overlapping with adjacent second detour lines in the second direction are provided in a second oblique line direction symmetrical to the first oblique line direction.

8. The display device according to claim 2, wherein,

each of the plurality of pixel drivers is electrically connected to one of the plurality of data lines via a data connection hole,

each of the first data line and the second data line includes:

a first main extension extending in the second direction; and

a first sub-protrusion protruding from the first main extension portion and overlapping the data connection hole,

the common auxiliary line adjacent to the first data line among the plurality of common auxiliary lines includes:

a second main extension extending in the second direction;

a second sub-protrusion protruding from the second main extension portion and facing the first sub-protrusion of the first data line; and

a third sub-protrusion facing the first main extension portion of the first data line and overlapping with one of the plurality of auxiliary connection holes, and

the third detour line adjacent to the second data line includes:

A third main extension extending in the second direction;

a fourth sub-protrusion protruding from the third main extension portion and facing the first sub-protrusion of the second data line; and

and a fifth sub-protrusion protruding from the third main extension portion, the fifth sub-protrusion facing the first main extension portion of the second data line and overlapping the second detour connection hole.

9. The display device according to claim 8, wherein,

the second extension auxiliary line adjacent to the second data line includes:

a fourth main extension extending in the second direction; and

a sixth sub-protrusion protruding from the fourth main extension portion and facing the first sub-protrusion of the second data line, an

The fourth main extension portion is electrically connected to the second power line in the non-display region.

10. The display device of claim 9, wherein the second extension auxiliary line adjacent to the second data line further comprises:

a seventh sub-protrusion protruding from the fourth main extension portion, the seventh sub-protrusion facing the first main extension portion of the second data line and overlapping another auxiliary connection hole among the plurality of auxiliary connection holes.