KR20240049762A - Display apparatus - Google Patents

Abstract

A display device is provided. The display device includes a substrate, a circuit layer, and a light emitting device layer. The circuit layer includes pixel drivers, data lines, first dummy lines extending in a first direction, and second dummy lines adjacent to the data lines. Among the via holes for electrical connection between the first dummy wires and the second dummy wires, some of the via holes each overlap with one of the light emitting areas, and some of the remaining via holes are between the light emitting areas. It is placed in the non-emissive area, which is the spaced apart area.

Description

DISPLAY APPARATUS}

The present invention relates to a display device.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. For example, display devices are applied to various electronic devices such as smartphones, digital cameras, laptop computers, navigation systems, and smart televisions.

A display device may include a display panel that emits light for displaying an image, and a driver that supplies a signal or power to drive the display panel.

At least one surface of the display device may be referred to as a display surface on which an image is displayed. The display surface may include a display area in which light-emitting areas that emit respective lights for image display are arranged, and a non-display area surrounding the display area.

The display device may include data lines disposed in the display area and transmitting data signals to pixel drivers corresponding to the light-emitting regions, and a display driving circuit supplying data signals to each of the data lines.

The display device may include data supply wires that are electrically connected to output terminals of the display driving circuit and are disposed in a non-display area. When the data supply wires are electrically connected to each data wire, as the number of data wires increases for enlargement or resolution improvement, the number of data supply wires also increases, making it difficult to reduce the width of the non-display area. .

Alternatively, when the width of the non-display area is reduced to increase the ratio of the display area of the display surface of the display device, the gap between data supply wires becomes smaller, which may lead to a short circuit defect.

Accordingly, the problem to be solved by the present invention is to provide a display device that can reduce the width of the non-display area without reducing resolution or causing short circuit defects.

The problems of the present invention are not limited to the problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the description below.

A display device according to an embodiment for solving the above problem includes a main area including a display area in which light-emitting areas are arranged, a non-display area arranged around the display area, and a sub-area protruding from one side of the main area. It includes a substrate, a circuit layer disposed on the substrate, and a light-emitting device layer disposed on the circuit layer and including light-emitting devices respectively corresponding to the light-emitting regions. The circuit layer includes pixel drivers corresponding to the light-emitting areas and electrically connected to the light-emitting elements, data wires that transmit data signals to the pixel drivers, and data wires disposed in the display area. first dummy wires extending in a first direction crossing the and second dummy wires extending in a second direction parallel to the data wires and neighboring the data wires on one side of the first direction. . Some of the via holes for electrical connection between the first dummy wires and the second dummy wires overlap one of the light emitting areas, and some of the remaining via holes overlap the light emitting areas. It is placed in the non-emissive area, which is the spaced area between them.

The display device may further include a display driving circuit disposed in the sub-region of the substrate and supplying data driving signals corresponding to data signals of data lines of the circuit layer. The circuit layer may further include demultiplex circuit units disposed in a demultiplex area adjacent to the sub area among the non-display areas and electrically connected between the display driving circuit and the data wires.

One of the demux circuit units includes an input terminal electrically connected to the display driving circuit, and a first output terminal and a second output terminal respectively electrically connected to two of the data wires. It can be included. The one demux circuit unit outputs a priority data signal corresponding to a data driving signal transmitted through the input terminal during the priority output period to the first output terminal, and outputs a priority data signal to the first output terminal during a secondary output period after the priority output period. A lower priority data signal corresponding to the data driving signal transmitted through may be output to the second output terminal.

The demux region includes a central demux middle region, a first demux side region adjacent to a bent portion of an edge of the substrate, and a second demux disposed between the demux middle region and the first demux side region. May include side areas. The demux circuit units may include a first demux circuit unit disposed in the first demux side area, and a second demux circuit unit disposed in the second demux side area. The circuit layer may further include data supply lines electrically connected to output terminals of the display driving circuit, respectively. Among the data supply wires, a first data supply wire extends from the sub-area to the second demux side area and is electrically connected to the input terminal of the first demux circuit unit through an input bypass wire disposed in the display area. You can. Among the data supply wires, a second data supply wire may extend from the sub-region to the second demux side area and be connected to an input terminal of the second demux circuit unit.

Among the display areas, the demultiplex adjacent area adjacent to the demultiplex area includes a display middle area adjacent to the demultiplex area, a first display side area adjacent to the first demultiplex side area, and a second demultiplex side area. It may include an adjacent second display side area. The input bypass wire is a first bypass wire disposed in the second display side area, extending in the second direction, and electrically connected to the first data supply wire, the second display side area, and the first display side area. a second bypass wire extending in the first direction and electrically connected to the first bypass wire, and disposed in the first display side area and extending in the second direction toward the first demux side area, It may include a third bypass wiring electrically connected to the second bypass wiring. The first dummy wires may include the second bypass wire. The second dummy wires may include the first bypass wire and the third bypass wire.

The circuit layer is disposed in the sub-area and the non-display area and is connected to a first power supply line and a second power supply line that respectively deliver the first power and the second power for driving the light-emitting elements, and the display area. It may further include first power auxiliary wires that are disposed, extend in the first direction, and are electrically connected to the first power supply wire. The first dummy wires may further include first auxiliary wires electrically connected to the second power supply wire. The second dummy wires may further include second auxiliary wires electrically connected to the second power supply wire.

The display area may further include a general area disposed between the demultiplexed area and the non-display area in the second direction. The general area may include a general middle area adjacent to the display middle area, a first general side area adjacent to the first display side area, and a second general side area adjacent to the second display side area. The first bypass wiring may extend in the second direction between the first data supply wiring and the second bypass wiring. The second bypass wiring may extend in the first direction between the first bypass wiring and the third bypass wiring. The third bypass wiring may extend in the second direction between the first demux side area and the second bypass wiring. The second auxiliary wires are general auxiliary wires extending between both ends of the display area in the second direction, and are spaced apart from one end of the first bypass wire in the second direction and extend to the second general side area. It may include a first extension auxiliary wire and a second extension auxiliary wire that is spaced apart from one end of the third bypass wire in the second direction and extends to the first general side area.

The data lines are electrically connected to the first output terminal and the second output terminal of the first demux circuit unit, respectively, and are a first data line and a second data line disposed in the first display side area and the first general side area. A third data line and a fourth data line are electrically connected to the first and second output terminals of the second demultiplexer circuit, respectively, and are disposed in the second display side area and the second general side area. may include. Each of the first data wire and the third data wire may be adjacent to one of the general auxiliary wires on one side in the first direction. The second data wire may be adjacent to the third bypass wire and the second extension auxiliary wire on one side in the first direction. The fourth data wire may be adjacent to the first bypass wire and the first extension auxiliary wire on one side in the first direction.

The via holes include a first bypass connection hole for electrical connection between the first bypass wiring and the second bypass wiring, a second bypass connection hole for electrical connection between the second bypass wiring and the third bypass wiring, and the third bypass wiring. It may include auxiliary connection holes for electrical connection between 1 auxiliary wires and the second auxiliary wires.

The auxiliary connection holes may include first auxiliary connection holes that overlap the general auxiliary wires. The first bypass connection hole and the second bypass connection hole may be disposed in the non-emission area. Each of the first auxiliary connection holes may overlap one of the light-emitting areas.

The auxiliary connection holes include a second auxiliary connection hole disposed in the first general side area and overlapping the second extension auxiliary wire, and a third auxiliary connection hole disposed in the second general side area and overlapping the first extension auxiliary wire. It may further include auxiliary connection holes. The second auxiliary connection hole and the third auxiliary connection hole may be disposed in the non-emission area.

The first extension auxiliary wire and the second extension auxiliary wire may be connected to the second power supply wire in the non-display area.

The auxiliary connection holes may include first auxiliary connection holes that overlap the general auxiliary wires. Each of the first bypass connection hole and the second bypass connection hole may overlap with one of the light emitting areas. The first auxiliary connection holes may be disposed in the non-emission area.

The first bypass connection holes, each overlapping with adjacent first bypass wires in the second direction, may be arranged in a first diagonal direction crossing the first direction and the second direction. The second bypass connection holes, each overlapping with the first bypass wires adjacent to each other in the second direction, may be arranged in a second diagonal direction symmetrical to the first diagonal direction.

Each of the pixel drivers may be electrically connected to one of the data wires through a data connection hole. Each of the first data wire and the second data wire may include a first main extension extending in the second direction and a first sub-projection that protrudes from the first main extension and overlaps the data connection hole. You can. A general auxiliary wire adjacent to the first data wire includes a second main extension extending in the second direction, and a second sub-protrusion that protrudes from the second main extension and faces the first sub-projection of the first data wire. It may include a sub protrusion and a third sub protrusion that faces the first main extension of the first data wire and overlaps a first auxiliary connection hole of one of the auxiliary connection holes. A third bypass wire adjacent to the second data wire has a third main extension extending in the second direction, and a third bypass wire that protrudes from the third main extension and faces the first sub-projection of the second data wire. It may include four sub protrusions and a fifth sub protrusion that protrudes from the third main extension, faces the first main extension of the second data wire, and overlaps the second bypass connection hole.

A second extension auxiliary wire adjacent to the second data wire has a fourth main extension extending in the second direction, protrudes from the fourth main extension and faces a first sub-projection of the second data wire. It may include a sixth sub protrusion. The fourth main extension may be connected to the second power supply wire in the non-display area.

Alternatively, a second extension auxiliary wire adjacent to the second data wire protrudes from the fourth main extension, faces the first main extension of the second data wire, and is connected to another one of the auxiliary connection holes. It may further include a seventh sub-protrusion overlapping the hole.

A display device according to an embodiment for solving the above problem includes a main area including a display area in which light-emitting areas are arranged, a non-display area arranged around the display area, and a sub-area protruding from one side of the main area. a substrate comprising, a circuit layer disposed on the substrate, a light-emitting device layer disposed on the circuit layer and including light-emitting elements respectively corresponding to the light-emitting regions, and a circuit layer disposed in the sub-region of the substrate. and a display driving circuit that supplies data driving signals corresponding to data signals of the data lines. The circuit layer includes pixel drivers corresponding to the light-emitting areas and electrically connected to the light-emitting elements, data wires that transmit data signals to the pixel drivers, and data wires disposed in the display area. first dummy wires extending in a first direction intersecting the data wires, second dummy wires extending in a second direction parallel to the data wires and neighboring the data wires on one side of the first direction, and the ratio Demux circuit units disposed in a demux area adjacent to the sub-area in the display area, data supply wires electrically connected to output terminals of the display driving circuit, respectively, and disposed in the sub-area and the non-display area and emitting light. A first power supply wire and a second power supply wire that respectively deliver the first power and the second power for driving the elements, and are disposed in the display area, extend in the first direction, and are electrically connected to the first power supply wire. Includes first power auxiliary wires connected to . The demux region includes a central demux middle region, a first demux side region adjacent to a bent portion of an edge of the substrate, and a second demux disposed between the demux middle region and the first demux side region. Includes side area. Among the display areas, the demultiplex adjacent area adjacent to the demultiplex area includes a display middle area adjacent to the demultiplex area, a first display side area adjacent to the first demultiplex side area, and a second demultiplex side area. and an adjacent second display side area. The demux circuit units include a first demux circuit unit disposed in the first demux side area, and a second demux circuit unit disposed in the second demux side area. Among the data supply wires, a first data supply wire extends from the sub-area to the second demux side area and is electrically connected to the input terminal of the first demux circuit unit through an input bypass wire disposed in the display area. do. Among the data supply wires, a second data supply wire extends from the sub-area to the second demux side area and is connected to an input terminal of the second demux circuit unit. The input bypass wire is a first bypass wire disposed in the second display side area, extending in the second direction, and electrically connected to the first data supply wire, the second display side area, and the first display side area. a second bypass wire extending in the first direction and electrically connected to the first bypass wire, and disposed in the first display side area and extending in the second direction toward the first demux side area, It includes a third bypass wiring electrically connected to the second bypass wiring. The first dummy wires include the second bypass wire and first auxiliary wires. The second dummy wires include the first bypass wire, the third bypass wire, and second auxiliary wires. The first auxiliary wires and the second auxiliary wires are electrically connected to the second power supply wire. A first bypass connection hole for electrical connection between the first bypass wiring and the second bypass wiring overlaps one of the light emitting regions. A second bypass connection hole for electrical connection between the third bypass wiring and the second bypass wiring overlaps with another light emitting region among the light emitting regions. Auxiliary connection holes for electrical connection between the first auxiliary wires and the second auxiliary wires are disposed in a non-light-emitting area, which is a spaced area between the light-emitting areas.

The display area may further include a general area disposed between the demultiplexed area and the non-display area in the second direction. The general area may include a general middle area adjacent to the display middle area, a first general side area adjacent to the first display side area, and a second general side area adjacent to the second display side area. The first bypass wiring may extend in the second direction between the first data supply wiring and the second bypass wiring. The second bypass wiring may extend in the first direction between the first bypass wiring and the third bypass wiring. The third bypass wiring may extend in the second direction between the first demux side area and the second bypass wiring. The second auxiliary wires are general auxiliary wires extending between both ends of the display area in the second direction, and are spaced apart from one end of the first bypass wire in the second direction and extend to the second general side area. It may include a first extension auxiliary wire and a second extension auxiliary wire that is spaced apart from one end of the third bypass wire in the second direction and extends to the first general side area. The data lines include a first data line and a second data line electrically connected to the first demux circuit and disposed in the first display side area and the first general side area, and electrically connected to the second demux circuit. and may include a third data line and a fourth data line connected to the second display side area and the second general side area. Each of the first data wire and the third data wire may be adjacent to one of the general auxiliary wires on one side in the first direction. The second data wire may be adjacent to the third bypass wire and the second extension auxiliary wire on one side in the first direction. The fourth data wire may be adjacent to the first bypass wire and the first extension auxiliary wire on one side in the first direction.

The first extension auxiliary wire and the second extension auxiliary wire may be connected to the second power supply wire in the non-display area.

Each of the pixel drivers may be electrically connected to one of the data wires through a data connection hole. Each of the first data wire and the second data wire may include a first main extension extending in the second direction and a first sub-projection that protrudes from the first main extension and overlaps the data connection hole. You can. A general auxiliary wire adjacent to the first data wire includes a second main extension extending in the second direction, and a second sub-protrusion that protrudes from the second main extension and faces the first sub-projection of the first data wire. It may include a sub protrusion and a third sub protrusion that faces the first main extension of the first data wire and overlaps one of the auxiliary connection holes. A third bypass wire adjacent to the second data wire has a third main extension extending in the second direction, and a third bypass wire that protrudes from the third main extension and faces the first sub-projection of the second data wire. It may include four sub protrusions and a fifth sub protrusion that protrudes from the third main extension, faces the first main extension of the second data wire, and overlaps the second bypass connection hole. A second extension auxiliary wire adjacent to the second data wire has a fourth main extension extending in the second direction, protrudes from the fourth main extension and faces a first sub-projection of the second data wire. It may include a sixth sub protrusion. The fourth main extension may be connected to the second power supply wire in the non-display area.

Specific details of other embodiments are included in the detailed description and drawings.

A display device according to an embodiment includes a substrate, a circuit layer on the substrate, a light emitting element layer on the circuit layer, and a display driving circuit that supplies data driving signals corresponding to data signals of data lines of the circuit layer.

The substrate includes a main area and a sub-area protruding from one side of the main area. The main area includes a display area in which light-emitting areas are arranged, and a non-display area disposed around the display area.

The circuit layer includes pixel drivers corresponding to the light emitting areas, data wires that transmit data signals to the pixel drivers, first dummy wires disposed in the display area and extending in a first direction crossing the data wires, Second dummy wires extending in a second direction parallel to the data wires and neighboring the data wires, and disposed in a demux area adjacent to a sub-area in the non-display area and electrically connected between the display driving circuit and the data wires. Includes connected demux circuits.

As such, the display device according to one embodiment includes demux circuit units electrically connected between the display driving circuit and the data wires. Each of the demux circuit units may output data signals of data lines based on the data driving signal of the display driving circuit. Accordingly, the data driving signals of the display driving circuit may not respectively correspond to data wires, but may each correspond to fewer demux circuit units than the data wires. As a result, the number of data supply wires electrically connected to the output terminals of the display driving circuit can be provided by the demux circuit units in a smaller number than the data wires, so the width allocated to the arrangement of the data supply wires in the non-display area can be reduced.

Accordingly, the width of the non-display area can be reduced without reducing the number of data wires, thereby eliminating resolution limitations due to the width of the non-display area. Additionally, short circuit defects between data supply wires due to a decrease in the width of the non-display area can be prevented.

In addition, according to one embodiment, each of some of the via holes for electrical connection between the first dummy wires and the second dummy wires overlaps one of the light emitting areas, and some of the remaining via holes overlap with one of the light emitting areas. It is disposed in a non-emission area, which is a spaced area between the light emitting areas.

As a result, the visibility of via holes can be reduced, and thus the deterioration of display quality caused by via holes can be reduced.

Additionally, according to one embodiment, the demux region is disposed between a central demux middle region, a first demux side region adjacent to a bent portion of an edge of the substrate, and a demux middle region and the first demux side region. It may include a second demux side area.

In this case, the demux circuit units may include a first demux circuit unit disposed in the first demux side area, and a second demux circuit unit disposed in the second demux side area.

Among the data supply wires, the first data supply wire may be electrically connected to the first demux circuit unit through an input bypass wire disposed in the display area.

On the other hand, the second data supply wire among the data supply wires may be connected to the second demux circuit unit.

In this way, the first data supply wire is electrically connected to the first demux circuit part of the first demux side area through the input bypass wire, and thus, like the second data supply wire, it will extend to the second demux side area. You can. Accordingly, since the first data supply line is not disposed in the first demux side area adjacent to the bent portion of the substrate, the width of the first demux side area can be reduced, thereby further reducing the width of the non-display area. It can be.

Effects according to the embodiments are not limited to the content exemplified above, and further various effects are included in the present specification.

1 is a perspective view showing a display device according to an embodiment.
FIG. 2 is a plan view showing the display device of FIG. 1 .
Figure 3 is a cross-sectional view showing an example of a surface cut along line A-A' of Figure 2.
FIG. 4 is a plan view showing a main area and a sub area of the display device of FIG. 1 .
Figure 5 is a layout diagram showing an example of part B of Figure 4.
FIG. 6 is a plan view showing an example of data wires, first dummy wires, second dummy wires, and first power auxiliary wires arranged in portion C of FIGS. 4 and 5 .
FIG. 7 is an equivalent circuit diagram showing an example of the first demux circuit unit of FIG. 5.
FIG. 8 is a timing diagram showing the data driving signal and demux control signals of FIG. 6.
Figure 9 is an equivalent circuit diagram showing an example of a pixel driver of one of the circuit layers.
FIG. 10 is a plan view showing two pixel drivers arranged in portion F of FIG. 6 .
FIG. 11 is a plan view showing the semiconductor layer and the first conductive layer of FIG. 10.
FIG. 12 is a plan view showing the semiconductor layer, first conductive layer, second conductive layer, and third conductive layer of FIG. 10.
FIG. 13 is a cross-sectional view showing an example of a surface cut along line G-G' of FIG. 10.
FIG. 14 is a plan view showing an example of light emitting areas arranged in portion C of FIGS. 4 and 5.
FIG. 15 is a plan view showing light emitting areas and via holes disposed in portion C of FIGS. 4 and 5 of the display device according to the first embodiment.
FIG. 16 is a plan view showing light emitting areas and via holes disposed in portion D of FIG. 4 of the display device according to the first embodiment.
FIG. 17 is a plan view showing light emitting areas and via holes disposed in portion C of FIGS. 4 and 5 of the display device according to the second embodiment.
FIG. 18 is a plan view showing data wires, first dummy wires, second dummy wires, and via holes arranged in portion C of FIGS. 4 and 5 in the display device according to the third embodiment.
FIG. 19 is a plan view showing data wires, first dummy wires, second dummy wires, and via holes arranged in portion D of FIG. 4 in the display device according to the third embodiment.
FIG. 20 is a plan view showing data wires, first dummy wires, second dummy wires, and via holes arranged in portion D of FIG. 4 in the display device according to the fourth embodiment.
FIG. 21 is a plan view showing data wires, first dummy wires, second dummy wires, and via holes arranged in portion E of FIG. 4 of the display device according to the fourth embodiment.
FIG. 22 is a plan view showing data wires, first dummy wires, second dummy wires, and via holes arranged in portion E of FIG. 4 of the display device according to the fifth embodiment.

The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and will be implemented in various different forms. The present embodiments only serve to ensure that the disclosure of the present invention is complete and that common knowledge in the technical field to which the present invention pertains is not limited. It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims.

When an element or layer is referred to as “on” another element or layer, it includes instances where the element or layer is directly on top of or intervening with the other element. Like reference numerals refer to like elements throughout the specification. The shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining the embodiments are illustrative and the present invention is not limited to the details shown.

Although first, second, etc. are used to describe various components, these components are of course not limited by these terms. These terms are merely used to distinguish one component from another. Therefore, it goes without saying that the first component mentioned below may also be a second component within the technical spirit of the present invention.

Each feature of the various embodiments of the present invention can be combined or combined with each other partially or entirely, and various technical interconnections and operations are possible, and each embodiment can be implemented independently of each other or together in a related relationship. It may be possible.

Hereinafter, specific embodiments will be described with reference to the attached drawings.

1 is a perspective view showing a display device according to an embodiment. FIG. 2 is a plan view showing the display device of FIG. 1 . Figure 3 is a cross-sectional view showing an example of a surface cut along line A-A' of Figure 2.

Referring to FIG. 1, the display device 10 is a device that displays moving images or still images, and is used in mobile phones, smart phones, tablet personal computers, and smart watches. ), watch phones, mobile communication terminals, electronic notebooks, e-books, PMP (portable multimedia players), navigation, UMPC (Ultra Mobile PC), as well as portable electronic devices such as televisions, laptops, monitors, billboards, etc. It can be used as a display screen for various products such as the Internet of Things (IOT).

The display device 10 may include an organic light emitting display device using an organic light emitting diode, a quantum dot light emitting display device including a quantum dot light emitting layer, an inorganic light emitting display device including an inorganic semiconductor, and a micro or nano light emitting diode (micro LED). It may be a light-emitting display device such as a miniature light-emitting display device using a nano LED)). Hereinafter, the description will focus on the fact that the display device 10 is an organic light emitting display device. However, the present invention is not limited to this and can be applied to display devices including organic insulating materials, organic light-emitting materials, and metal materials.

The display device 10 may be formed flat, but is not limited thereto. For example, the display device 10 is formed at the left and right ends and may include a curved portion having a constant curvature or a changing curvature. In addition, the display device 10 may be flexibly formed to be bent, curved, bent, folded, or rolled.

The display device 10 may include a display panel 100, a display driving circuit 200, and a circuit board 300.

The display panel 100 includes a display area DA in which a plurality of light-emitting areas (EA in FIG. 5 ) for displaying an image are arranged.

That is, the substrate (110 in FIG. 3) of the display panel 100 has a main area (MA) including a display area (DA) and a non-display area (NDA) that is a surrounding area of the display area (DA), and a main area (MA) ) may include a sub-area (SBA) protruding from one side in the second direction (DR2).

The display driving circuit 200 may be prepared as an integrated circuit chip (IC) and mounted in the sub-area (SBA). The display driving circuit 200 may supply data driving signals corresponding to data lines (DL in FIG. 5) of the display panel 100.

The circuit board 300 may be bonded to signal pads (SPDs in FIG. 4) disposed at the edge of the sub-area SBA.

1 and 4 show the sub-area (SBA) spread out parallel to the main area (MA). On the other hand, Figure 2 illustrates a state in which a portion of the sub-area SBA is bent.

Referring to FIG. 2 , the display area DA may be formed as a rectangular plane having a short side in the first direction DR1 and a long side in the second direction DR2 that intersects the first direction DR1. A corner where the short side in the first direction DR1 and the long side in the second direction DR2 meet may be rounded to have a predetermined curvature or may be formed at a right angle. The planar shape of the display area DA is not limited to a square, and may be formed in other polygonal, circular, or oval shapes.

The display area DA may occupy most of the main area MA. The display area DA may be placed in the center of the main area MA.

The display area DA may include a plurality of light emitting areas EA arranged in parallel with each other. Additionally, the display area DA may further include a non-emission area NEA, which is a spaced area between the plurality of light emitting areas EA.

The plurality of light emitting areas EA may be arranged parallel to each other in the first direction DR1 and the second direction DR2.

Each of the plurality of light emitting areas EA may have a diamond-shaped planar shape or a rectangular planar shape. However, this is only an example, and the planar shape of the plurality of light emitting areas EA according to one embodiment is not limited to that shown in FIG. 2. That is, the plurality of light emitting areas EA may have a polygonal, circular, or oval planar shape other than a square.

The plurality of light-emitting areas EA include a first light-emitting area EA1 that emits light of a first color in a predetermined wavelength band, and a first light-emitting area EA1 that emits light of a second color in a wavelength band lower than the first color. It may include two light-emitting areas EA2 and third light-emitting areas EA3 that emit light of a third color in a wavelength band lower than that of the second color.

As an example, the first color may be red in a wavelength range of approximately 600 nm to 750 nm. The second color may be green in a wavelength range of approximately 480 nm to 560 nm. The third color may be blue in a wavelength band of approximately 370 nm to 460 nm.

As shown in FIG. 2 , the first emission areas EA1 and the third emission areas EA3 may be alternately arranged in the first direction DR1 or the second direction DR2. Additionally, the second light emitting areas EA2 may be arranged side by side in the first direction DR1 or the second direction DR2.

A plurality of pixels (PX) that display respective luminance and color may be provided by these plurality of light emitting areas (EA). Each of the plurality of pixels (PX) may be a basic unit that displays various colors, including white, at a predetermined luminance.

That is, each of the plurality of pixels (PX) may be composed of at least one first emission area (EA1), at least one second emission area (EA2), and at least one third emission area (EA3) adjacent to each other.

Each of the plurality of pixels (PX) is composed of a mixture of light emitted from each of at least one first emission area (EA1), at least one second emission area (EA2), and at least one third emission area (EA3) adjacent to each other. Color and luminance can be displayed.

Meanwhile, FIG. 2 illustrates a case where a plurality of light emitting areas EA have the same area, but this is only an example. As another example, the third light-emitting area EA3 may have the largest area, and the second light-emitting area EA2 may have the smallest area.

Also, although FIG. 2 illustrates a case where a plurality of light emitting areas EA are arranged side by side in the first direction DR1 and the second direction DR2, this is only an example. As another example, the second light-emitting areas EA2 may be adjacent to the first light-emitting area EA1 and the third light-emitting area EA3 in a diagonal direction that intersects the first direction DR1 and the second direction DR2. there is.

Referring to FIG. 3, the display panel 100 of the display device 10 includes a substrate 110 including a main area (MA) and a sub-area (SBA), and a circuit layer 120 disposed on the substrate 110. , and includes a light emitting device layer 130 disposed on the circuit layer 120.

The circuit layer 120 includes pixel drivers (PXDs in FIG. 9) corresponding to each of the light emitting areas (EA) and data lines (in FIG. 5) that transmit data signals (Vdata in FIG. 9) to the pixel drivers (PXDs). DL) are included.

The light-emitting device layer 130 includes light-emitting devices (LELs in FIG. 13) corresponding to each of the light-emitting areas EA. The light emitting elements (LEL) may be electrically connected to the pixel drivers (PXDs) of the circuit layer 120, respectively.

In addition, the display panel 100 of the display device 10 may further include a sealing layer 140 covering the light emitting device layer 130 and a sensor electrode layer 150 disposed on the sealing layer 140.

The substrate 110 may be made of an insulating material such as polymer resin. For example, the substrate 110 may be made of polyimide. The substrate 110 may be a flexible substrate capable of bending, folding, rolling, etc.

Alternatively, the substrate 100 may be made of an insulating material such as glass.

The sealing layer 140 is disposed on the circuit layer 120, corresponds to the main area MA, and covers the light emitting device layer 130. The sealing layer 140 may include a structure in which two or more inorganic films and at least one organic film are alternately stacked.

The sensor electrode layer 150 may be disposed on the sealing layer 140 and correspond to the main area (MA). The sensor electrode layer 150 may include touch electrodes for detecting the touch of a person or object.

The display device 10 may further include a cover window (not shown) disposed on the sensor electrode layer 150. The cover window may be attached to the sensor electrode layer 150 by a transparent adhesive member such as an optically clear adhesive (OCA) film or an optically clear resin (OCR). The cover window may be inorganic, such as glass, or organic, such as plastic or polymer materials. By this cover window, the sensor electrode layer 150, the sealing layer 140, the light emitting device layer 130, and the circuit layer 120 can be protected from electrical and physical shock on the display surface.

Additionally, the display device 10 may further include an anti-reflection member (not shown) disposed between the sensor electrode layer 150 and the cover window. The anti-reflection member may be a polarizing film or a color filter. External light reflected from the sensor electrode layer 150, the sealing layer 140, the light emitting device layer 130, and the circuit layer 120 and their interfaces is blocked by this anti-reflection member, thereby allowing the display device 10 to This can prevent the visibility of the image from deteriorating.

The display device 10 of one embodiment may further include a touch driving circuit 400 for driving the sensor electrode layer 150.

The touch driving circuit 400 may be prepared as an integrated circuit chip (IC).

The touch driving circuit 400 may be electrically connected to the sensor electrode layer 150 by being mounted on the circuit board 300 bonded to signal pads (SPDs).

Alternatively, the touch driving circuit 400 may be mounted in the second sub-region SB2 of the substrate 110, similar to the display driving circuit 200.

The touch driving circuit 400 applies a touch driving signal to a plurality of driving electrodes provided in the sensor electrode layer 150, receives a touch detection signal from each of a plurality of touch nodes through a plurality of sensing electrodes, and responds to the touch detection signal. Based on this, the change in charge of mutual capacitance can be detected.

That is, the touch driving circuit 400 can determine whether the user has touched the device and whether the user is in proximity, etc., according to the touch detection signal of each of the plurality of touch nodes. The user's touch refers to direct contact of an object, such as the user's finger or a pen, to the front of the display device 10. The user's proximity refers to the positioning of an object, such as the user's finger or pen, away from the front of the display device 10, such as hovering.

FIG. 4 is a plan view showing a main area and a sub area of the display device of FIG. 1 .

Referring to FIG. 4, the sub-area SBA includes a bending area BA that is transformed into a bent shape, and a first sub-area SB1 and a second sub-area SB2 adjoining both sides of the bending area BA. It can be included.

The first sub-area SB1 is an area disposed between the main area MA and the bending area BA. One side of the first sub-area SB1 may be in contact with the non-display area NDA of the main area MA, and the other side of the first sub-area SB1 may be in contact with the bending area BA.

The second sub-area SB2 is spaced apart from the main area MA with the bending area BA in between, and is an area disposed on the lower surface of the substrate 110 by the bending area BA deformed into a bent shape. That is, the second sub-area SB2 may overlap the main area MA in the thickness direction DR3 of the substrate SUB due to the bending area BA transformed into a bent shape.

One side of the second sub-area SB2 may be in contact with the bending area BA. The other side of the second sub-region SB2 may contact a portion of the edge of the substrate 110 .

Signal pads SPD and the display driving circuit 200 may be disposed in the second sub-area SB2.

The display driving circuit 200 may generate signals and voltages for driving the pixel drivers PD in the display area DPA.

The display driving circuit 200 is provided as an integrated circuit (IC) and is formed using a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method in the second sub region (SB2) of the substrate 110. ), but is not limited to this. For example, the display driving circuit 200 may be attached to the circuit board 300 using a chip on film (COF) method.

The circuit board 300 may be attached and electrically connected to the signal pads SPD of the second sub-region SB2 using a low-resistance, high-reliability material such as an anisotropic conductive film or SAP.

The pixel drivers PD in the display area DPA and the display driving circuit 200 may receive digital video data, timing signals, and driving voltages from the circuit board 300 .

The circuit board 300 may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

According to one embodiment, the non-display area NDA includes a demux area DXA consisting of a portion adjacent to the sub area SBA. The demux area DXA may be disposed adjacent to one edge of the display area DA adjacent to the sub-area SBA in the second direction DR2.

In the demux area DXA, demux circuit units (DMC in FIG. 5) are electrically connected between the data wires (DL in FIG. 5) of the display area DA and the display driving circuit 200 in the sub-area SBA. ) can be placed.

The demultiplex area DXA includes a central demultiplex area XMA in the first direction DR1, a first demultiplex side area It may include a second demux side area (XSA2) disposed between (XMA) and the first demux side area (XSA1).

The demux area (DXA) includes two second demux side areas (XSA2) and two first demux side areas (XSA1) disposed on both sides of the first direction (DR1) of the demux middle area (XMA). It can be included.

The display area DA may include a demultiplex area DXA and an adjacent demultiplex area DAA.

The demux adjacent area (DAA) is a display middle area (DMDA) adjacent to the demux middle area (XMA) in the second direction (DR2), and a display middle area (DMDA) adjacent to the first demux side area (XSA1) in the second direction (DR2). It may include a first display side area DSDA1 and a second display side area DSDA2 adjacent to the second demux side area XSA2 in the second direction DR2. An input bypass wire (IDEL in FIG. 5) electrically connected to the first demux circuit unit (DMC1 in FIG. 5) of the first demux side area (XSA1) may be disposed in the demux adjacent area (DAA).

The display area DA may further include a general area GA disposed between the demultiplexed adjacent area DAA and the non-display area NDA in the second direction DR2.

The general area GA is a general middle area GMA adjacent to the display middle area MDMA in the second direction DR2, and a first general side area adjacent to the first display side area DSDA1 in the second direction DR2. It may include (GSA1) and a second general side area (GSA2) adjacent to the second display side area (DSDA2) in the second direction (DR2).

Additionally, the non-display area NDA may further include a scan driving circuit area SCDA disposed adjacent to at least one corner of the display area DA in the first direction DR1.

The circuit layer 120 may include a scan driving circuit (not shown) disposed in the scan driving circuit area (SCDA). The scan driving circuit may supply each scan signal to scan lines in the first direction DR1 disposed in the display area DA.

As an example, the display driving circuit 200 or the circuit board 300 may supply a scan control signal to the scan driving circuit based on digital video data and timing signals.

Additionally, the circuit board 300 may supply a predetermined constant voltage for generating a scan signal to the scan driving circuit.

FIG. 4 illustrates a case where the scan driving circuit area SCDA is a partial area of the non-display area NDA adjacent to both edges of the display area DA in the first direction DR1, but this is only an example. That is, although not separately shown, the scan driving circuit area SCDA may be a portion of the non-display area NDA adjacent to one side of the display area DA in the first direction DR1, and the display area DA It may also be provided as partition areas that overlap parts of .

Figure 5 is a layout diagram showing an example of part B of Figure 4. FIG. 6 is a plan view showing an example of data wires, first dummy wires, second dummy wires, and first power auxiliary wires arranged in portion C of FIGS. 4 and 5 .

Referring to FIG. 5, the circuit layer 120 of the display device 10 according to one embodiment corresponds to the light emitting areas EA, respectively, and the light emitting devices (LELs in FIG. 9) of the light emitting device layer 130. pixel drivers (PXDs in FIG. 9) that are electrically connected to each other, data lines (DL) that transmit data signals (Vdata in FIG. 9) to the pixel drivers (PXDs), and data lines that are disposed in the display area (DA) The first dummy wires DML1 extend in the first direction DR1 crossing the data wires DL, and extend in the second direction DR2 parallel to the data wires DL, respectively. It is disposed in the neighboring second dummy wires DML2 and the demux area DXA adjacent to the sub area SBA in the non-display area NDA and between the display driving circuit 200 and the data wires DL. It includes demux circuits (DMC) that are electrically connected.

The circuit layer 120 may further include data supply lines (DSPL) that are electrically connected to the output terminals of the display driving circuit 200, respectively.

The demux circuit units DMC may be arranged in the first direction DR1 in the demux area DXA.

The demux circuit units (DMC) include a first demux circuit unit (DMC1) disposed in the first demux side area (XSA1) and a second demux circuit unit (DMC2) disposed in the second demux side area (XSA2). It can be included.

The demux circuit units (DMC) may further include a third demux circuit unit (DMC3) disposed in the demux middle area (XMA).

One of the demux circuit units DMC (for example, the first demux circuit unit DMC1) connects one of the data supply lines DSPL (for example, DSPL1 in FIGS. 5 and 7). an input terminal (DIP in FIG. 7) that is electrically connected to the display driving circuit 200 through an input terminal (DIP in FIG. 7), and two data lines (eg, DL1 and DL2 in FIGS. 5 and 7) among the data lines DL, respectively. It may include a first output terminal (AOP1 in FIG. 7) and a second output terminal (BOP1 in FIG. 7) that are electrically connected.

The data lines DL include a first data line DL1 and a second data line DL2 disposed in the first display side area DSDA1 and the first general side area GSA1, and a second display side area ( DSDA2) and a third data line DL3 and a fourth data line DL4 disposed in the second general side area GSA2.

The data lines DL may further include a fifth data line DL5 and a sixth data line DL6 disposed in the display middle area DMDA and the general middle area GMA.

The first data line DL1 and the second data line DL2 disposed in the first display side area DSDA1 and the first general side area GSA1 are connected to the first data line DL1 and the second data line DL2 disposed in the first demux side area XSA1. It may be electrically connected to the first output terminal (AOPL1) and the second output terminal (BOPL1) of the demux circuit unit (DMC1), respectively.

The third data line DL3 and the fourth data line DL4 disposed in the second display side area DSDA2 and the second general side area GSA2 are the second data lines disposed in the second demux side area XSA2. It may be electrically connected to the first and second output terminals of the demux circuit unit (DMC2), respectively.

The fifth and sixth data lines DL5 and DL6 arranged in the display middle area (DMDA) and the general middle area (GMA) are connected to the third demux circuit unit (DMC3) arranged in the demux middle area (XMA). Can be electrically connected to the first output terminal and the second output terminal, respectively.

The data supply lines DSPL are first data lines that transmit data driving signals corresponding to the data signals of the first data line DL1 and the second data line DL2 disposed in the first display side area DSDA1. A second data supply line that transmits a data driving signal corresponding to the data signals of the third data line DL3 and DL4 disposed in the supply line DSPL1 and the second display side area DSDA2. (DSPL2), and a third data supply line (DSPL3) transmitting a data driving signal corresponding to the data signals of the fifth data line (DL5) and the sixth data line (DL6) disposed in the display middle area (DMDA). may include.

Among the data supply lines (DSPL), the first data supply line (DSPL1) extends from the sub area (SBA) to the second demux side area (XSA2) and connects the input bypass line (IDEL) disposed in the display area (DA). It can be electrically connected to the input terminal of the first demux circuit unit (DMC1).

Among the data supply lines DSPL, the second data supply line DSPL2 extends from the sub area SBA to the second demux side area XSA2 and may be connected to the input terminal of the second demux circuit unit DMC2. .

Among the data supply lines DSPL, the third data supply line DSPL3 extends from the sub area SBA to the demux middle area XMA and may be connected to the input terminal of the third demux circuit unit DMC3.

The input bypass line (IDEL) is disposed in the second display side area (DSDA2), extends in the second direction (DR2), and is electrically connected to the first data supply line (DSPL1), a first bypass line (DETL1), a second a second bypass line (DETL2) extending from the display side area (DSDA2) and the first display side area (DSDA1) in the first direction (DR1) and electrically connected to the first bypass line (DETL1), and the first display side It may include a third bypass line (DETL3) disposed in the area (DSDA1), extending in a second direction (DR2) toward the first demux side area (XSA1), and electrically connected to the second bypass line (DETL2). there is.

The circuit layer 120 is disposed in the first demux side area (XSA1) and electrically connects the third bypass wire (DETL3) of the input bypass wire (IDEL) and the input terminal of the first demux circuit unit (DMC1). It may further include an input connection wire (ICNL).

The first bypass line DETL1 may extend in the second direction DR2 between the first data supply line DSPL1 and the second bypass line DETL2 of the second demux side area XSA2.

The second bypass wiring DETL2 may extend in the first direction DR1 between the first bypass wiring DETL1 and the third bypass wiring DETL3.

The third bypass line DETL3 may extend in the second direction DR2 between the first demux side area XSA1 and the second bypass line DETL2. The third bypass wire (DETL3) may be electrically connected to the input connection wire (ICNL) of the first demux side area (XSA1).

Referring to FIG. 6, the second bypass wiring (DETL2) is electrically connected to the first bypass wiring (DETL1) through the first bypass connection hole (DECH1) and the third bypass wiring (DETL1) through the second bypass connection hole (DECH2). It can be electrically connected to the wiring (DETL3).

The first dummy wires DML1 may include the second bypass wire DETL2 of the input bypass wire IDEL.

The first dummy wires DML1 may further include a first auxiliary wire ASL1 to which a second power source (ELVSS in FIG. 9 ) is applied, in addition to the second bypass wire DETL2.

The second dummy wires DML2 may include the first bypass wire DETL1 and the third bypass wire DETL3 of the input bypass wire IDEL.

The second dummy wires DML2 may further include a second auxiliary wire ASL2 to which the second power source ELVSS is applied, in addition to the first bypass wire DETL1 and the third bypass wire DETL3.

As shown in FIG. 5, the circuit layer 120 of the display device 10 according to one embodiment is disposed in the sub area SBA and the non-display area NDA and has a first layer for driving the light emitting elements LEL. It may further include a first power supply line (VDSPL) and a second power supply line (VSSPL) that transmit power (ELVDD in FIG. 9) and second power supply (ELVSS), respectively.

The first auxiliary wires ASL1 of the first dummy wires DML1 and the second auxiliary wires ASL2 of the second dummy wires DML2 may be electrically connected to the second power supply wire VSSPL. .

In other words, the first dummy wires (DML1) are the second bypass wire (DETL2) of the input bypass wire (IDEL), and the remaining first auxiliary wires are electrically connected to the second power supply wire (VSSPL). (ASL1) may be included.

The second dummy wires (DML2) are the first bypass wire (DETL1) and the third bypass wire (DETL3) of the input bypass wire (IDEL), and the remainder excluding them, and are electrically connected to the second power supply wire (VSSPL). It may include second auxiliary wires (ASL2).

As shown in FIGS. 5 and 6, the second auxiliary lines ASL2 are general auxiliary lines GASL extending between both ends of the display area DA in the second direction DR2, and the second auxiliary lines ASL2 are connected to the second direction DR2. ), a first extension auxiliary wiring (EASL1) spaced apart from one end of the first bypass wiring (DETL1) and extending to the second general side area (GSA2), and a third bypass wiring (DETL3) in the second direction (DR2). It may include a second extension auxiliary wire (EASL2) that is spaced apart from one end and extends to the first general side area (GSA1).

Among the first data line DL1 and the second data line DL2 electrically connected to the first demux circuit unit DMC1 and disposed in the first display side area DSDA1, the first data line DL1 is the first data line DL1. It is adjacent to one general auxiliary line (GASL) on one side of the direction DR1 (for example, the right side in FIG. 6), and the second data line DL2 is a third bypass line on one side of the first direction DR1. (DETL3) and the second extension auxiliary wiring (EASL2). Here, some pixel drivers PXDs electrically connected to the first data line DL1 may be disposed between the adjacent general auxiliary line GASL and the first data line DL1. And, between the adjacent third bypass line (DETL3) and the second extension auxiliary line (EASL2) and the second data line (DL2), another part of the pixel driver (PXD) electrically connected to the second data line (DL2) can be placed.

In other words, the first data line DL1 may face the general auxiliary line GASL with some pixel drivers PXD connected to the first data line DL1 interposed therebetween. In addition, the second data line DL2 faces the third bypass line DETL3 and the second extension auxiliary line EASL2 with some other pixel drivers PXD connected to the second data line DL2 in between. You can.

Among the third and fourth data lines DL3 and DL4 that are electrically connected to the second demux circuit part DMC2 and disposed in the second display side area DSDA2, the third data line DL3 is the other one. It is adjacent to the general auxiliary line (GASL), and the fourth data line (DL4) may be adjacent to the first bypass line (DETL1) and the first extension auxiliary line (EASL1).

Each of the fifth data line DL5 and the sixth data line DL6 electrically connected to the third demux circuit unit DMC3 and disposed in the display middle area DMDA may be adjacent to the general auxiliary line GASL. .

The circuit layer 120 of the display device 10 according to one embodiment may include via holes VIAH for electrical connection between the first dummy wires DML1 and the second dummy wires DML2.

According to one embodiment, each of some of the via holes (VIAH) overlaps with one of the light emitting areas (EA), and some of the remaining via holes are spaced apart areas between the light emitting areas (EA). It may be placed in a non-emissive area (NEA). This will be described later with reference to FIGS. 14 to 17.

The via holes (VIAH) are for electrical connection between the first bypass wiring (DETL1) and the second bypass wiring (DETL2), the first bypass connection hole (DECH1), the second bypass wiring (DETL2), and the third bypass wiring (DETL3). It may include a second bypass connection hole (DECH2) for electrical connection between, and auxiliary connection holes (ASCH in FIG. 16) for electrical connection between the first auxiliary wires (ASL1) and the second auxiliary wires (ASL2). there is.

According to one embodiment, the first bypass connection holes DECH1 disposed in the second display side area DSDA2 and each overlapping with the second bypass wiring DETL2 adjacent in the second direction DR2 are connected in the first direction DR2. It may be arranged in a first diagonal direction DD1 that intersects DR1 and the second direction DR2.

The second bypass connection holes DECH2 each overlapping with the second bypass wiring DETL2 adjacent in the second direction DR2 in the first display side area DSDA1 are symmetrical to the first diagonal direction DD1. 2 can be arranged in the diagonal direction (DD2).

According to one embodiment, auxiliary connection holes (ASCH in FIG. 16) may be placed in the general area (GA) and the display middle area (DMDA).

For example, in the first general side area (GSA1) adjacent to the first display side area (DSDA1) in the second direction (DR2), the auxiliary connection holes (ASCH) are connected to the second bypass connection of the first display side area (DSDA1). The holes DECH2 may be arranged in a second diagonal direction DD2, parallel to the arrangement direction, or may be arranged in a third diagonal direction (DD3 in FIG. 16) with a steeper slope than the second diagonal direction DD2.

And, in the second general side area (GSA2) adjacent to the second display side area (DSDA2) in the second direction (DR2), the auxiliary connection holes (ASCH) are connected to the first bypass connection hole of the second display side area (DSDA2). They may be arranged in a first diagonal direction DD1, parallel to the arrangement direction of DECH1, or may be arranged in a fourth diagonal direction DD4 with a steeper slope than the first diagonal direction DD1.

In this way, through the arrangement direction of the first bypass connection holes (DECH1), the arrangement direction of the second bypass connection holes (DECH2), and the arrangement direction of the auxiliary connection holes (ASCH), the first bypass connection hole (DECH1), the second bypass connection hole (DECH1), 2 It can be easily inferred whether the bypass connection hole (DECH2) and the auxiliary connection hole (ASCH) are normally arranged.

FIG. 7 is an equivalent circuit diagram showing an example of the first demux circuit unit of FIG. 5. FIG. 8 is a timing diagram showing the data driving signal and demux control signals of FIG. 6.

Referring to FIG. 7, among the demux circuit units (DMC), the first demux circuit unit (DMC1) is electrically connected to the display driving circuit 200 and has an input terminal (DIP) through which one data driving signal (DDRS) is input. , the first output terminal (AOP) through which the senior data signal corresponding to the data driving signal (DDRS) is output during the senior output period (AT in FIG. 8), and the junior output terminal (BT in FIG. 8) after the senior output period (AT). ) may include a second output terminal (BOP) through which a subordinate data signal corresponding to the data driving signal (DDRS) is output.

In addition, the first demux circuit unit (DMC1) includes a first demux transistor (TDM1) electrically connected between the input terminal (DIP) and the first output terminal (AOP), and the input terminal (DIP) and the second output terminal. It may further include a second demux transistor (TDM2) electrically connected between the (BOP).

The circuit layer 120 of the display device 10 according to an embodiment includes a first output terminal (AOP) of the first demux circuit units (DMC1) and the first data line (DL1). It may further include an output connection wire (AOPL1), a second output connection wire (BOPL1) electrically connecting the second output terminal (BOP) of the first demux circuit units (DMC1) and the second data wire (DL2). You can.

In addition, the circuit layer 120 is electrically connected to the first demux control line (DXCL1), which is electrically connected to the gate electrode of the first demux transistor (TDM1), and the gate electrode of the second demux transistor (TDM2). It may further include second demux control wires DXCL2.

Referring to FIG. 8, each of the video frames ((i-1) ^th Frame and (i) ^th Frame) may include a priority output period (AT) and a junior output period (BT).

During the priority output period (AT), the first demux control signal (CLA) of the first demux control wire (DXCL1) is output at a turn-on level, and during the secondary output period (BT), the first demux control signal (CLA) of the second demux control wire (DXCL2) is output at a turn-on level. The second demux control signal CLB may be output at a turn-on level.

In this way, the first demux transistor (TDM1) is turned on during the priority output period (AT) and the data driving signal (DDRS) is output as a data signal of the first data line (DL1) through the first output terminal (AOP). The second demux transistor (TDM2) is turned on during the secondary output period (BT), so that the data driving signal (DDRS) can be output as a data signal of the second data line (DL2) through the second output terminal (BOP). there is.

That is, the data driving signal DDRS can be time-divided into a priority output period (AT) and a priority output period (BT) by the demux circuit unit (DMC).

The second demux circuit unit (DMC2) has a first output terminal (AOP) and a second output terminal (BOP) electrically connected to the third data line (DL3) and the fourth data line (DL4), respectively, and the third output terminal (AOP) and the second output terminal (BOP) are electrically connected to each other. The mux circuit unit (DMC3) has a second output terminal (AOP) and a second output terminal (BOP), except that the first output terminal (AOP) and the second output terminal (BOP) are electrically connected to the fifth data line (DL5) and the sixth data line (DL6), respectively. Since each of the demux circuit unit (DMC2) and the third demux circuit unit (DMC3) is substantially the same as the equivalent circuit and timing diagram for the first demux circuit unit (DMC1) shown in FIGS. 7 and 8, duplicate descriptions are omitted.

Figure 9 is an equivalent circuit diagram showing an example of a pixel driver of one of the circuit layers.

The circuit layer 120 includes pixel drivers PXDs respectively corresponding to the light emitting areas EA and electrically connected to the light emitting elements LEL of the light emitting device layer 130, respectively.

Referring to FIG. 9, one of the pixel drivers PXD of the circuit layer 120 includes a driving transistor DT, at least one switch element ST1 to ST6, and a capacitor C1. ) may include. At least one switch element (ST1 to ST6) includes a first transistor (ST1: Switch Transistor), a second transistor (ST2), a third transistor (ST3), a fourth transistor (ST4), a fifth transistor (ST5), and It may include a sixth transistor (ST6).

The circuit layer 120 includes a scan write line (GWL) that transmits a scan write signal (GW) to the pixel drivers (PXDs) and a gate control line (GCL) that transmits a gate control signal (GC) to the pixel drivers (PXDs). ), a scan initialization line (GIL) that transmits the scan initialization signal (GI) to the pixel drivers (PXDs), an emission control line (ECL) that transmits an emission control signal (EC) to the pixel drivers (PXDs), a pixel driver A gate initialization voltage line (VGIL) that delivers a first initialization voltage (Vgint) to the PXDs, an anode initialization voltage line (VAIL) that delivers a second initialization voltage (Vaint) to the pixel drivers (PXDs), and a pixel. It may further include a first power line (VDL) that delivers the first power source (ELVDD) to the driving units (PXDs).

The scan write line (GWL) may be electrically connected to the gate electrode of each of the first transistor (ST1) and the second transistor (ST2). The scan initialization line (GIL) may be electrically connected to the gate electrode of the third transistor (ST3). The gate control line (GCL) may be electrically connected to the gate electrode of the fourth transistor (ST4). The emission control line (ECL) may be electrically connected to the gate electrode of each of the fifth transistor (ST5) and the sixth transistor (ST6).

The driving transistor DT may be connected in series with the light emitting element LEL between the first power line VDL and the second power line VSL.

The first electrode of the driving transistor DT may be connected to the first power line VDL through the fifth transistor ST5.

Additionally, the first electrode of the driving transistor DT may be connected to the data line DL through the second transistor ST2.

The second electrode of the driving transistor DT may be connected to the light emitting element LEL through the sixth transistor ST6.

The capacitor C1 may be connected between the first power line VDL and the gate electrode of the driving transistor DT. That is, the gate electrode of the driving transistor DT may be connected to the first power line VDL through the capacitor C1.

Accordingly, when the data signal of the data line DL is applied to the first electrode of the driving transistor DT, the driving transistor DT can generate a drain-source current corresponding to the data signal. The drain-source current of the driving transistor DT may be supplied as the driving current of the light emitting element LEL.

The light emitting element (LEL) may emit light with a brightness corresponding to the driving current generated by the driving transistor (DT).

The light emitting element (LEL) includes an anode electrode (AND in Figure 13) and a cathode electrode (CTD in Figure 13) facing each other, and a light emitting layer (EML in Figure 13) between the anode electrode (AND) and the cathode electrode (CTD). can do.

As an example, the light emitting element (LEL) may be an organic light emitting diode having a light emitting layer made of an organic light emitting material. Alternatively, the light emitting device (LEL) may be an inorganic light emitting device having a light emitting layer made of an inorganic semiconductor. Alternatively, the light emitting device (LEL) may be a quantum dot light emitting device having a quantum dot light emitting layer. Alternatively, the light emitting element (LEL) may be a micro light emitting diode.

The capacitor (Cel) connected in parallel with the light emitting element (LEL) is a parasitic capacitance between the anode electrode and the cathode electrode.

The first transistor ST1 is connected between the gate electrode of the driving transistor DT and the second electrode of the driving transistor DT.

The first transistor ST1 may include a plurality of sub-transistors connected in series. As an example, the first transistor ST1 may include a first sub-transistor ST11 and a second sub-transistor ST12.

The first electrode of the first sub-transistor ST11 is connected to the second electrode of the driving transistor DT, and the second electrode of the first sub-transistor ST11 is connected to the first electrode of the second sub-transistor ST12. The second electrode of the second sub-transistor ST12 may be connected to the gate electrode of the driving transistor DT.

In this way, the potential of the gate electrode of the driving transistor DT can be prevented from changing due to leakage current caused by the first transistor ST1 in the turned-off state.

The second transistor ST2 is connected between the first electrode of the driving transistor DT and the data line DL.

The gate electrodes of each of the first transistor (ST1) and the second transistor (ST2) are connected to the scan write line (GWL).

When the scan write signal (GW) is transmitted through the scan write line (GWL), the first transistor (ST1) and the second transistor (ST2) are turned on, and the driving transistor (DT) is turned on through the turned-on first transistor (ST1). The gate electrode and the second electrode are at the same potential. Then, the data signal of the data line DL is supplied to the first electrode of the driving transistor DT through the turned-on second transistor ST2.

At this time, when the voltage difference between the first electrode and the gate electrode of the driving transistor (DT) becomes greater than the threshold voltage, the driving transistor (DT) turns on to generate a drain-source current between the first electrode and the second electrode of the driving transistor (DT). may occur.

The third transistor ST3 is connected between the gate electrode of the driving transistor DT and the gate initialization voltage line VGIL. The gate electrode of the third transistor ST3 is connected to the scan initialization line GIL.

The third transistor ST3 may include a plurality of sub-transistors connected in series. As an example, the third transistor ST3 may include a third sub-transistor ST31 and a fourth sub-transistor ST32.

The first electrode of the third sub-transistor ST31 is connected to the gate electrode of the driving transistor DT, and the second electrode of the third sub-transistor ST31 is connected to the first electrode of the fourth sub-transistor ST32. , the second electrode of the fourth sub-transistor ST32 may be connected to the gate initialization voltage line VGIL.

In this way, the potential of the gate electrode of the driving transistor DT can be prevented from changing due to leakage current caused by the third transistor ST3 in the turned-off state.

When the scan initialization signal GI is supplied through the scan initialization line GIL, the third transistor ST3 may be turned on. At this time, the gate electrode of the driving transistor DT is connected to the gate initialization voltage line VGIL through the turned-on third transistor ST3, so that the potential of the gate electrode of the driving transistor DT is equal to the gate initialization voltage line VGIL. It may be initialized to the first initialization voltage (Vgint).

The fourth transistor ST4 may be connected between the anode electrode of the light emitting element LEL and the anode initialization voltage line VAIL. The gate electrode of the fourth transistor ST4 may be connected to the gate control line GCL.

When the control scan signal GC is supplied through the gate control line GCL, the fourth transistor ST4 may be turned on. At this time, the anode electrode of the light emitting device (LEL) is connected to the anode initialization voltage line (VAIL) through the turned-on fourth transistor (ST4), so that the potential of the anode electrode of the light emitting device (LEL) is equal to the anode initialization voltage line (VAIL). It can be initialized with an initialization voltage (Vint) of .

The fifth transistor ST5 may be connected between the first electrode of the driving transistor DT and the first power line VDL.

The sixth transistor ST6 may be connected between the second electrode of the driving transistor DT and the anode electrode of the light emitting element LEL.

The gate electrodes of each of the fifth transistor ST5 and ST6 may be connected to the emission control line ECL.

When the emission control signal (EC) is supplied through the emission control line (ECL), the driving transistor (DT) and the light emitting element (LEL) are connected in series between the first power line (VDL) and the second power line (VSL). You can. Accordingly, since the driving current of the driving transistor DT can be supplied to the light emitting element LEL, the light emitting element LEL can emit light based on the driving current.

As shown in FIG. 9 , the driving transistor DT and at least one switch element ST1 to 6 provided in the pixel driver PXD may all be provided as P-type MOSFETs.

Alternatively, some of the driving transistor DT and at least one switch element ST1 to 6 provided in the pixel driver PXD may be provided as a P-type MOSFET, and the remaining portion may be provided as an N-type MOSFET. In this case, the switching elements provided as P-type MOSFETs and the switching elements provided as N-type MOSFETs may include active layers of different semiconductor materials. Therefore, the width of the pixel driver (PXD) can be reduced through the stacked structure, which can be advantageous in improving resolution.

FIG. 10 is a plan view showing two pixel drivers arranged in portion F of FIG. 6 . FIG. 11 is a plan view showing the semiconductor layer and the first conductive layer of FIG. 10. FIG. 12 is a plan view showing the semiconductor layer, first conductive layer, second conductive layer, and third conductive layer of FIG. 10. FIG. 13 is a cross-sectional view showing an example of a surface cut along line G-G' of FIG. 10.

First, as shown in FIG. 13, the circuit layer 120 includes a semiconductor layer (SEL) on the substrate 110, a first conductive layer (CDL1) on the first gate insulating layer 122 covering the semiconductor layer (SEL), A second conductive layer (CDL2) on the second gate insulating layer 123 covering the first conductive layer (CDL1), a third conductive layer (CDL3) on the interlayer insulating layer 124 covering the second conductive layer (CDL2), A fourth conductive layer (CDL4) on the first planarization layer (125) covering the third conductive layer (CDL3), a fifth conductive layer (CDL5) on the second planarization layer (126) covering the fourth conductive layer (CDL4), and It may be provided in a structure including a third planarization layer 127 covering the fifth conductive layer (CDL5).

The light emitting device layer 130 may be disposed on the third planarization layer 127.

Referring to FIG. 11, the semiconductor layer (SEL) is a driving transistor (DT) and the channel portions (CHDT, CH11, CH12, CH2, CH31, CH32, CH4, CH5, CH6), source electrodes (SDT, S11, S12, S2, S31, S32, S4, S5, S6) and drain electrodes (DDT, D11, D12, D2, D31, D32, D4, D5, D6). there is.

The first conductive layer (CDL1) includes the driving transistor (DT) and the gate electrodes (GDT, G11, G12, G2, G31, G32, G4, G5, G6) of each of the first to sixth transistors (ST1 to 6). can do.

In addition, the first conductive layer (CDL1) includes scan lines connected to the gate electrodes (GDT, G11, G12, G2, G31, G32, G4, G5, G6) of the first to sixth transistors (ST1 to 6), That is, it may further include a scan write line (GWL), a scan initialization line (GIL), an emission control line (ECL), and a gate control line (GCL). The scan write line (GWL), scan initialization line (GIL), emission control line (ECL), and gate control line (GCL) extend in the first direction DR1.

Referring to FIG. 12, the second conductive layer (CDL2) is connected to the drain electrode (D32) of the third transistor (ST3), the gate initialization voltage line (VGIL) that transmits the first initialization voltage (Vgint), and the fourth It may include an anode initialization voltage line (VAIL) connected to the drain electrode (D4) of the transistor (ST4) and transmitting a second initialization voltage (Vaint). The gate initialization voltage line VGIL and the anode initialization voltage line VAIL may extend in the first direction DR1.

The first power line (VDL) may include a first power horizontal auxiliary line (VDSBL1) extending in the first direction (DR1) and a first power vertical auxiliary line (VDSBL2) extending in the second direction (DR2). there is.

The second conductive layer (CDL2) may further include a first power horizontal auxiliary line (VDSBL1).

The third conductive layer (CDL3) may include the first power vertical auxiliary line (VDSBL2).

The third conductive layer (CDL3) may further include a gate initialization voltage auxiliary line (VGIAL) and an anode initialization voltage auxiliary line (VAIAL).

The gate initialization voltage auxiliary line (VGIAL) is electrically connected to the gate initialization voltage line (VGIL) and may extend in the second direction (DR2).

The anode initialization voltage auxiliary wiring (VAIAL) may be electrically connected to the anode initialization voltage wiring (VAIL) and extend in the second direction (DR2).

The first power vertical auxiliary wiring (VDSBL2) may be electrically connected to the first power horizontal auxiliary wiring (VDSBL1).

As shown in FIG. 11, the driving transistor DT has a channel part CHDT, a source electrode (SDT) and a drain electrode (DDT) connected to both sides of the channel part (CHDT), and a gate overlapping the channel part (CHDT). It may include an electrode (GDT).

The source electrode (SDT) of the driving transistor (DT) may be connected to the drain electrode (D2) of the second transistor (ST2) and the drain electrode (D5) of the fifth transistor (ST5).

The drain electrode (DDT) of the driving transistor (DT) may be connected to the source electrode (S11) of the first sub-transistor (ST11) and the source electrode (S6) of the sixth transistor (ST6).

The channel portion (CHDT), source electrode (SDT), and drain electrode (DDT) of the driving transistor (DT) may be made of a semiconductor layer (SEL). The source electrode (SDT) and drain electrode (DDT) may be formed of a portion of the semiconductor layer (SEL) made conductive by doping ions or impurities into a semiconductor material.

The gate electrode (GDT) of the driving transistor (DT) may be provided with the first conductive layer (CDL1).

The first transistor ST1 may include a first sub-transistor ST11 and a second sub-transistor ST12 connected in series.

The first sub-transistor (ST11) overlaps the channel portion (CH11), the source electrode (S11) and drain electrode (D11) connected to both sides of the channel portion (CH11), and the channel portion (CH11) and forms a scan write wiring (GWL). It may include a gate electrode (G11) made up of a portion of.

The source electrode S11 of the first sub-transistor ST11 may be connected to the drain electrode DDT of the driving transistor DT.

The drain electrode D11 of the first sub-transistor ST11 may be connected to the source electrode S12 of the second sub-transistor ST12.

The second sub-transistor ST12 overlaps the channel part CH12, the source electrode S12 and the drain electrode D12 connected to both sides of the channel part CH12, and the channel part CH12, and forms a scan write wiring (GWL). ) may include a gate electrode (G12) made of protrusions.

The source electrode S12 of the second sub-transistor ST12 may be connected to the drain electrode D11 of the first sub-transistor ST11.

The drain electrode D12 of the second sub-transistor ST12 may be connected to the source electrode S31 of the third sub-transistor ST31.

The gate electrodes (G11, G12) of each of the first sub-transistor (ST11) and the second sub-transistor (ST12) may be formed as different parts of the scan write line (GWL) provided with the first conductive layer (CDL1).

The gate electrode (GDT) of the driving transistor (DT) is connected to the first connection electrode (CE1) through the first contact hole (CT1), and the first connection electrode (CE1) is connected to the first connection electrode (CE1) through the second contact hole (CT2). 2 It can be connected to the drain electrode (D12) of the sub-transistor (ST12).

The first connection electrode (CE1) may be made of a third conductive layer (CDL3).

The second transistor (ST2) overlaps the channel portion (CH2), the source electrode (S2) and drain electrode (D2) connected to both sides of the channel portion (CH2), and the channel portion (CH2) and forms a scan write line (GWL). It may include a gate electrode (G2) made of another part of.

The source electrode S2 of the second transistor ST2 may be connected to the second connection electrode CE2 through the fourth contact hole CT4.

The drain electrode D2 of the second transistor ST2 may be connected to the source electrode SDT of the driving transistor DT and the drain electrode D5 of the fifth transistor ST5.

The channel portion (CH2), source electrode (S2), and drain electrode (D2) of the second transistor (ST2) may be made of a semiconductor layer (SEL). The source electrode S2 and the drain electrode D2 may be formed of a portion of the semiconductor layer SEL made conductive by doping ions or impurities into a semiconductor material.

The gate electrode G2 of the second transistor ST2 may be formed as a part of the scan write line GWL provided with the first conductive layer CDL1.

The second connection electrode (CE2) may be formed of the third conductive layer (CDL3).

The third transistor ST3 may include a third sub-transistor ST31 and a fourth sub-transistor ST32 connected in series.

The third sub-transistor (ST3) includes a channel portion (CH31), a source electrode (S31) and a drain electrode (D31) connected to both sides of the channel portion (CH31), and a gate electrode (G31) overlapping with the channel portion (CH31). It can be included.

The source electrode S31 of the third sub-transistor ST31 may be connected to the drain electrode D12 of the second sub-transistor ST12.

The drain electrode D31 of the third sub-transistor ST31 may be connected to the source electrode S32 of the fourth sub-transistor ST32.

The fourth sub-transistor (ST32) includes a channel portion (CH32), a source electrode (S32) and a drain electrode (D32) connected to both sides of the channel portion (CH32), and a gate electrode (G32) overlapping with the channel portion (CH32). may include.

The drain electrode D32 of the fourth sub-transistor ST32 may be connected to the gate initialization voltage auxiliary wiring VGIAL through the second initialization contact hole VICH2.

The channel portion (CH31), source electrode (S31), and drain electrode (D31) of the third sub-transistor (ST31), and the channel portion (CH32), source electrode (S32), and drain electrode ( D32) may be made of a semiconductor layer (SEL). The source electrodes (S31, S32) and drain electrodes (D31, D32) of each of the third sub-transistor (ST31) and the fourth sub-transistor (ST32) are made conductive by doping ions or impurities into the semiconductor material of the semiconductor layer (SEL). It can be done with the parts ordered.

The gate electrodes G31 and G32 of the third sub-transistor ST31 and the fourth sub-transistor ST32 may each be formed as different parts of the scan initialization line GIL provided with the first conductive layer CDL1.

As shown in FIG. 12 , the circuit layer 120 may further include a shielding electrode (SHE) that overlaps at least a portion of the source electrode (S31) of the fourth sub-transistor (ST32).

The shielding electrode (SHE) may be provided as a second conductive layer (CDL2).

The shielding electrode (SHE) may be connected to the first power vertical auxiliary wiring (VDSBL2) through the third contact hole (CT3).

The shielding electrode (SHE) may further overlap a portion of the drain electrode (D11) of the first sub-transistor (ST11).

The first power vertical auxiliary wiring (VDSBL2) may be connected to the first power horizontal auxiliary wiring (VDSBL1) through the fifth contact hole (CT5).

As shown in FIG. 11, the fourth transistor ST4 overlaps the channel unit CH4, the source electrode S4 and drain electrode D4 connected to both sides of the channel unit CH4, and the channel unit CH4. and may include a gate electrode (G4) formed as part of the gate control line (GCL).

The source electrode S4 of the fourth transistor ST4 may be connected to the drain electrode D6 of the sixth transistor ST6.

The drain electrode D4 of the fourth transistor ST4 may be connected to the anode initialization auxiliary wiring VAIAL through the fourth initialization contact hole VACH2.

The channel portion (CH4), source electrode (S4), and drain electrode (D4) of the fourth transistor (ST4) may be made of a semiconductor layer (SEL). The source electrode S4 and the drain electrode D4 may be formed of a portion of the semiconductor layer SEL made conductive by doping ions or impurities into a semiconductor material.

The gate electrode G4 of the fourth transistor ST4 may be formed as a part of the gate control line GCL formed of the first conductive layer CDL1.

The fifth transistor (ST5) overlaps the channel portion (CH5), the source electrode (S5) and drain electrode (D5) connected to both sides of the channel portion (CH5), and the channel portion (CH5) and has an emission control line (ECL). It may include a gate electrode (G5) made up of a portion of.

The source electrode S5 of the fifth transistor ST5 may be connected to the first power vertical auxiliary wiring VDSBL2 through the sixth contact hole CT6.

The drain electrode D5 of the fifth transistor ST5 may be connected to the source electrode SDT of the driving transistor DT.

The sixth transistor (ST6) overlaps the channel portion (CH6), the source electrode (S6) and drain electrode (D6) connected to both sides of the channel portion (CH6), and the channel portion (CH6) and has an emission control line (ECL). It may include a gate electrode (G6) made up of another part of.

The source electrode S6 of the sixth transistor ST6 may be connected to the drain electrode DDT of the driving transistor DT.

The drain electrode D6 of the sixth transistor ST6 is connected to the source electrode S4 of the fourth transistor ST4 and can be connected to the third connection electrode CE3 through the seventh contact hole CT7.

As shown in FIG. 12, the third connection electrode (CE3) may be made of a third conductive layer (CDL3).

As shown in FIG. 11, the channel portion CH5, the source electrode S5, and the drain electrode D5 of the fifth transistor ST4 may be made of a semiconductor layer SEL. The source electrode S5 and the drain electrode D5 may be formed of a portion of the semiconductor layer SEL made conductive by doping ions or impurities into a semiconductor material.

The channel portion (CH6), source electrode (S6), and drain electrode (D6) of the sixth transistor (ST6) may be made of a semiconductor layer (SEL). The source electrode S6 and the drain electrode D6 may be formed of a portion of the semiconductor layer SEL made conductive by doping ions or impurities into a semiconductor material.

The gate electrodes G5 and G6 of each of the fifth transistor ST5 and ST6 may be formed as different parts of the emission control line ECL formed of the first conductive layer CDL1.

As shown in FIG. 12, the capacitor C1 may be provided by overlapping the first capacitor electrode CAE1 and the second capacitor electrode CAE2.

Here, the first capacitor electrode CAE1 may be formed as a part of the gate electrode GDT of the driving transistor DT provided with the first conductive layer CDL1.

The second capacitor electrode CAE2 may be formed as a part of the first power horizontal auxiliary line VDSBL1 provided with the second conductive layer CDL2.

The second connection electrode CE2 is connected to the source electrode S2 of the second transistor ST2 through the fourth contact hole CT4.

Referring to FIG. 10 , the fourth conductive layer CDL4 of the circuit layer 120 may include a first power auxiliary wiring VDAL and a second bypass wiring DETL2 extending in the first direction DR1. there is.

As shown in FIG. 6, since the second bypass line DETL2 is a part of the first dummy line DML1, the fourth conductive layer CDL4 is connected to the first power auxiliary line VDAL and the first dummy line DML1. ) may include.

In addition, as shown in FIG. 6, the first dummy wires (DML1) are the second bypass wire (DETL2) of the input bypass wire (IDEL) and the remaining first auxiliary wires to which the second power source (ELVSS) is applied. (ASL1).

The first dummy wires DML1 and the first power auxiliary wire VDAL may be arranged to alternate with each other in the second direction DR2.

As shown in FIG. 10 , the fourth conductive layer CDL4 may further include a fourth connection electrode CE4 and a fifth connection electrode CE5.

The fourth connection electrode (CE4) may be connected to the second connection electrode (CE2) through the tenth contact hole (CT10).

The fifth connection electrode (CE5) may be electrically connected to the third connection electrode (CE3) through the eighth contact hole (CT8).

The first power auxiliary line VDAL may be electrically connected to the first power vertical auxiliary line VDSBL2 of the third conductive layer CDL3 through the 11th contact hole CT11.

The fifth conductive layer CDL5 may include data lines DL and second dummy lines DML2.

The data lines DL include a first data line DL1 and a second data line DL2 disposed in the first display side area DSDA1.

The second dummy wires (DML2) adjacent to the data wires (DL) are the first bypass wire (DETL1) and the third bypass wire (DETL3) of the input bypass wire (IDEL), and the remainder excluding these, and the second power supply ( It may include second auxiliary wires (ASL2) to which ELVSS) is applied.

The second auxiliary lines ASL2 include a general auxiliary line GASL extending between both ends of the display area DA in the second direction DR2 and a first extension auxiliary line spaced apart from one end of the first bypass line DETL1. It may include a wiring EASL1 and a second extension auxiliary wiring EASL2 spaced apart from one end of the third bypass wiring DETL3.

The first data line DL1 may be adjacent to the general auxiliary line GASL on one side in the first direction DR1.

The second data line DL2 may be adjacent to the third bypass line DETL3 and the second connection auxiliary line EASL2 on one side in the first direction DR1.

The data line DL may be electrically connected to the fourth connection electrode CE4 through the data connection hole DTCH.

Accordingly, the source electrode S2 of the second transistor ST2 may be electrically connected to the data line DL through the second connection electrode CE2 and the fourth connection electrode CE4.

The fifth conductive layer (CDL5) may further include a sixth connection electrode (CE6).

The sixth connection electrode (CE6) may be electrically connected to the fifth connection electrode (CE5) through the ninth contact hole (CT9).

The fifth connection electrode (CE5) is electrically connected to the third connection electrode (CE3), and the third connection electrode (CE3) is connected to the source electrode (S4) of the fourth transistor (ST4) and the drain of the sixth transistor (ST6). It may be electrically connected to the electrode D6.

The sixth connection electrode (CE6) connects the source electrode (S4) of the fourth transistor (ST4) and the drain electrode (D6) of the sixth transistor (ST6) through the third connection electrode (CE3) and the fifth connection electrode (CE5). can be electrically connected to.

This sixth connection electrode (CE6) may be electrically connected to the anode electrode (AND in FIG. 13) of the light emitting element (LEL) through an anode contact hole (ANCT in FIG. 13) penetrating the third planarization layer 127. .

In the first display side area DSDA1, the third bypass wiring DETL3 may be electrically connected to the second bypass wiring DETL2 through the second bypass connection hole DECH2 penetrating the second planarization layer 126. there is.

As shown in FIG. 13, the circuit layer 120 includes a semiconductor layer (SEL) on the substrate 110, a first conductive layer (CDL1) on the first gate insulating layer 122 covering the semiconductor layer (SEL), and a first conductive layer (CDL1) on the semiconductor layer (SEL) on the substrate 110. A second conductive layer (CDL2) on the second gate insulating layer 123 covering the conductive layer (CDL1), a third conductive layer (CDL3) on the interlayer insulating layer 124 covering the second conductive layer (CDL2), and a third conductive layer (CDL2) on the second gate insulating layer 123 covering the conductive layer (CDL1). The fourth conductive layer (CDL4) on the first planarization layer (125) covering the conductive layer (CDL3), the fifth conductive layer (CDL5) on the second planarization layer (126) covering the fourth conductive layer (CDL4), and the fifth conductive layer (CDL5) on the first planarization layer (125) covering the conductive layer (CDL3). It may include a third planarization layer 127 covering the conductive layer (CDL5).

The circuit layer 120 may further include a buffer layer 121 disposed between the substrate 110 and the semiconductor layer (SEL).

The buffer layer 121 is intended to protect the circuit layer 120 and the light emitting device layer 130 from moisture penetrating through the substrate 110, and may be made of at least one inorganic film.

As an example, the buffer layer 121 may be made of a multilayer in which one or more inorganic layers of silicon nitride, silicon oxy nitride, silicon oxide, titanium oxide, and aluminum oxide are alternately stacked.

The semiconductor layer (SEL) is disposed on the buffer layer 121 and may be made of a silicon semiconductor such as polycrystalline silicon, single crystalline silicon, low-temperature polycrystalline silicon, and amorphous silicon.

The semiconductor layer (SEL) is a channel unit (CHDT, CH11, CH12, CH2, CH31, CH32, CH4 in FIG. 11) of the driving transistor (DT) and switch elements (ST1 to ST6) provided in the pixel driver (PXD). CH5, CH6) may be included.

In addition, the semiconductor layer (SEL) is a source electrode (SDT, S11, S12, S2, S31, S32, S4, S5, S6 in FIG. 11) and drain of each of the driving transistor (DT) and switch elements (ST1 to ST6). It may further include electrodes (DDT, D11, D12, D2, D31, D32, D4, D5, and D6 in FIG. 11).

Among the semiconductor layer (SEL), the driving transistor (DT) and the switch elements (ST1 to ST6) each have a source electrode (SDT, S11, S12, S2, S31, S32, S4, S5, S6 in FIG. 11) and a drain electrode ( Some other parts corresponding to DDT, D11, D12, D2, D31, D32, D4, D5, and D6) in FIG. 11 may be doped with ions or impurities to have conductivity.

On the other hand, in the semiconductor layer (SEL), the driving transistor (DT) and switch elements (ST1 to ST6) correspond to each channel portion (CHDT, CH11, CH12, CH2, CH31, CH32, CH4, CH5, and CH6 in FIG. 11). One part is not doped by the gate electrode (GDT, G11, G12, G2, G31, G32, G4, G5, and G6 in Figure 11) and maintains the semiconductor characteristic of creating a channel through which carriers move according to the potential difference. You can.

The first gate insulating layer 122 may be formed of an inorganic film disposed on the buffer layer 121 and covering the semiconductor layer (SEL).

For example, the first gate insulating layer 122 may be made of an inorganic layer of a silicon nitride layer, a silicon oxy nitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

The first conductive layer CDL1 is disposed on the first gate insulating layer 122 .

The first conductive layer (CDL1) is a gate electrode (GDT, G11, G12, G2, G31, G32 in FIG. 11, G4, G5, G6) may be included.

In addition, the first conductive layer CDL1 is a gate electrode (G11, G12, G2, G31, G32, G4, G5 in FIG. 11) of each of the first to sixth transistors ST1 to ST6 provided in the pixel driver PXD. , G6) and may further include a scan write line (GWL), a scan initialization line (GIL), a gate control line (GCL), and an emission control line (ECL) connected to the first direction DR1.

The first conductive layer (CDL1) is made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Alternatively, it may be formed as a single layer or multiple layers made of alloys thereof.

The second gate insulating layer 123 may be formed of an inorganic film disposed on the first gate insulating layer 122 and covering the first conductive layer (CDL1).

For example, the second gate insulating layer 123 may be made of an inorganic layer of a silicon nitride layer, a silicon oxy nitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

The second conductive layer CDL2 is disposed on the second gate insulating layer 123.

The second conductive layer (CDL2) includes a shielding electrode (SHE in Figure 12), a first power horizontal auxiliary wire (VDSBL1 in Figure 12), a gate initialization voltage wire (VGIL in Figure 12), and an anode initialization voltage wire (VAIL in Figure 12). ) may include.

The second conductive layer (CDL2) is made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Alternatively, it may be formed as a single layer or multiple layers made of alloys thereof.

The interlayer insulating layer 124 may be formed of an inorganic film disposed on the second gate insulating layer 123 and covering the second conductive layer (CDL2).

For example, the interlayer insulating layer 124 may be made of an inorganic layer of a silicon nitride layer, a silicon oxy nitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

The third conductive layer (CDL3) is disposed on the interlayer insulating layer 124.

The third conductive layer (CDL3) includes a first connection electrode (CE1 in FIG. 12), a second connection electrode (CE2 in FIG. 12), a third connection electrode (CE3 in FIG. 12), and a first power vertical auxiliary wiring (FIG. 12). VDSBL2), a gate initialization voltage line (VGIL in FIG. 12), and an anode initialization voltage line (VAIL in FIG. 12).

Referring to FIGS. 12 and 13, the pixel driver PXD includes a first contact hole (CT1), a second contact hole (CT2), a third contact hole (CT3), a fourth contact hole (CT4), and a third contact hole (CT4). It may include a fifth contact hole (CT5), a sixth contact hole (CT6), and a seventh contact hole (CT7).

The first contact hole (CT1) is for connecting the first connection electrode (CE1) and the gate electrode (GDT) of the driving transistor (DT).

The first contact hole (CT1) corresponds to a portion of the gate electrode (GDT) of the driving transistor (DT) and may penetrate the second gate insulating layer 123 and the interlayer insulating layer 124. Accordingly, the first connection electrode (CE1) made of the third conductive layer (CDL3) is connected to the gate electrode (GDT) of the driving transistor (DT) made of the first conductive layer (CDL1) through the first contact hole (CT1). Can be electrically connected.

The second contact hole (CT2) connects the first connection electrode (CE1) with any one of the drain electrode (D12) of the second sub-transistor (ST12) and the source electrode (S31) of the third sub-transistor (ST31). It is for. The drain electrode D12 of the second sub-transistor ST12 and the source electrode S31 of the third sub-transistor ST31 are connected to each other.

The second contact hole (CT2) corresponds to a portion of either the drain electrode (D12) of the second sub-transistor (ST12) or the source electrode (S31) of the third sub-transistor (ST31), and the first gate insulating layer ( 122), it may penetrate the second gate insulating layer 123 and the interlayer insulating layer 124. Accordingly, the first connection electrode CE1 made of the third conductive layer CDL3 is connected to the drain electrode D12 and the drain electrode of the second sub-transistor ST12 made of the semiconductor layer SEL through the second contact hole CT2. It may be electrically connected to the source electrode (S31) of the third sub-transistor (ST31).

In addition, the gate electrode (GDT) of the driving transistor (DT) is connected to the drain electrode of the second sub-transistor (ST12) through the first contact hole (CT1), the second contact hole (CT2), and the first connection electrode (CE1). It may be electrically connected to (D12) and the source electrode (S31) of the third sub-transistor (ST31).

The third contact hole (CT3) is for connecting the shielding electrode (SHE) and the first power vertical auxiliary wiring (VDSBL2).

The third contact hole (CT3) corresponds to a portion of the first power vertical auxiliary wiring (VDSBL2) and may penetrate the interlayer insulating layer 124. As a result, the shielding electrode (SHE) made of the second conductive layer (CDL2) can be electrically connected to the first power vertical auxiliary wiring (VDSBL2) made of the third conductive layer (CDL3) through the third contact hole (CT3). there is.

The fourth contact hole CT4 is for connecting the second connection electrode CE2 and the source electrode S2 of the second transistor ST2.

The fourth contact hole (CT4) corresponds to a part of the source electrode (S2) of the second transistor (ST2), and the first gate insulating layer 122, the second gate insulating layer 123, and the interlayer insulating layer 124 can penetrate. Accordingly, the second connection electrode CE2 made of the third conductive layer CDL3 is electrically connected to the source electrode S2 of the second transistor ST2 made of the semiconductor layer SEL through the fourth contact hole CT4. It can be connected to .

The fifth contact hole (CT5) is for connecting the first power horizontal auxiliary line (VDSBL1) and the first power vertical auxiliary line (VDSBL2).

The fifth contact hole CT5 corresponds to a portion of the first power horizontal auxiliary wiring VDSBL1 and may penetrate the interlayer insulating layer 124. Accordingly, the first power vertical auxiliary wiring (VDSBL2) made of the third conductive layer (CDL3) is connected to the first power horizontal auxiliary wiring (VDSBL1) made of the second conductive layer (CDL2) through the fifth contact hole (CT5). Can be electrically connected.

The sixth contact hole (CT6) is for connecting the first power vertical auxiliary wiring (VDSBL2) and the source electrode (S5) of the fifth transistor (ST5).

The sixth contact hole CT6 corresponds to a portion of the source electrode S5 of the fifth transistor ST5 and includes the first gate insulating layer 122, the second gate insulating layer 123, and the interlayer insulating layer 124. It can penetrate. Accordingly, the first power vertical auxiliary wiring (VDSBL2) made of the third conductive layer (CDL3) is connected to the source electrode (S5) of the fifth transistor (ST5) made of the semiconductor layer (SEL) through the sixth contact hole (CT6). can be electrically connected to.

The seventh contact hole (CT7) is for connecting the third connection electrode (CE3) and the drain electrode (D5) of the fifth transistor (ST5).

The seventh contact hole (CT7) corresponds to a portion of the drain electrode (D5) of the fifth transistor (ST5) and connects the first gate insulating layer 122, the second gate insulating layer 123, and the interlayer insulating layer 124. It can penetrate. Accordingly, the third connection electrode CE3 made of the third conductive layer CDL3 is electrically connected to the drain electrode D5 of the fifth transistor ST5 made of the semiconductor layer SEL through the seventh contact hole CT7. It can be connected to .

The third conductive layer (CDL3) may have a multi-layer structure including a metal layer with low resistance characteristics and a metal layer with ion diffusion prevention characteristics disposed on the top and bottom surfaces, respectively.

As an example, the third conductive layer (CDL3) may be made of a stacked structure of metal layers, and each of the metal layers of the third conductive layer (CDL3) is molybdenum (Mo), aluminum (Al), chromium (Cr), and gold (Au). ), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

Specifically, the metal layer with low resistance characteristics may be made of any one of aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), and copper (Cu).

The metal layer with ion diffusion prevention properties may be made of titanium (Ti).

That is, the third conductive layer (CDL3) may be prepared in a stacked structure (Ti/Al/Ti) of titanium (Ti)/aluminum (Al)/titanium (Ti).

The first planarization layer 125 covering the third conductive layer (CDL3) is made of acryl resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin ( It may be made of an organic film such as polyimide resin.

The fourth conductive layer CDL4 is disposed on the first planarization layer 125 .

As shown in FIG. 10, the fourth conductive layer (CDL4) may include a first power auxiliary line (VDAL), a first dummy line (DML1), a fourth connection electrode (CE4), and a fifth connection electrode (CE5). You can.

The second dummy wire DML1 may include a second bypass wire DETL2 and a first auxiliary wire ASL1.

The fourth conductive layer (CDL4) is made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Alternatively, it may be made of a single layer or multiple layers of alloys thereof.

Like the third conductive layer (CDL3), the fourth conductive layer (CDL4) may be made of a stacked structure of metal layers, and each of the metal layers of the third conductive layer (CDL3) is molybdenum (Mo), aluminum (Al), and chromium. It may be made of any one of (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

That is, the fourth conductive layer (CDL4) may be prepared in a stacked structure (Ti/Al/Ti) of titanium (Ti)/aluminum (Al)/titanium (Ti).

The second planarization layer 126 covering the fourth conductive layer (CDL4) is made of acryl resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin ( It may be made of an organic film such as polyimide resin.

The fifth conductive layer CDL5 is disposed on the second planarization layer 126 .

As shown in FIG. 10 , the fifth conductive layer CDL5 may include data lines DL, second dummy lines DML2, and a sixth connection electrode CE6.

The second dummy wiring (DML2) includes a first bypass wiring (DETL1), a third bypass wiring (DETL3), and a second auxiliary wiring (ASL2).

The fifth conductive layer (CDL5) is made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Alternatively, it may be made of a single layer or multiple layers of alloys thereof.

As shown in FIG. 13, the third planarization layer 127 covering the fifth conductive layer (CDL5) is made of acryl resin, epoxy resin, phenolic resin, and polyamide resin. It may be made of an organic film such as resin or polyimide resin.

Referring to FIGS. 10 and 13, the pixel driver PXD further includes an eighth contact hole (CT8), a ninth contact hole (CT9), a tenth contact hole (CT10), and an eleventh contact hole (CT11). It can be included.

The eighth contact hole CT8 is for connecting the third connection electrode CE3 and the fifth connection electrode CE5.

The eighth contact hole CT8 corresponds to a portion of the third connection electrode CE3 and may penetrate the first planarization layer 125. Accordingly, the fifth connection electrode (CE5) can be electrically connected to the third connection electrode (CE3) through the eighth contact hole (CT8).

The ninth contact hole CT9 is for connecting the fifth connection electrode CE5 and the sixth connection electrode CE6.

The ninth contact hole CT9 corresponds to a portion of the fifth connection electrode CE5 and may penetrate the second planarization layer 126. Accordingly, the sixth connection electrode (CE6) can be electrically connected to the fifth connection electrode (CE5) through the ninth contact hole (CT9).

The tenth contact hole CT10 is for connecting the fourth connection electrode CE4 and the second connection electrode CE2.

The tenth contact hole CT10 corresponds to a portion of the second connection electrode CE2 and may penetrate the first planarization layer 125 . Accordingly, the fourth connection electrode (CE4) can be electrically connected to the second connection electrode (CE2) through the tenth contact hole (CT10).

The data connection hole (DTCH) is for electrically connecting the fourth connection electrode (CE4) and the data line (DL).

The data connection hole DTCH corresponds to a portion of the fourth connection electrode CE4 and may penetrate the second planarization layer 126. Accordingly, the data line DL can be electrically connected to the fourth connection electrode CE4 through the data connection hole DTCH.

As shown in FIG. 13, the light emitting device layer 130 may be disposed on the third planarization layer 127 of the circuit layer 120.

As an example, the light emitting device layer 130 is disposed on the third planarization layer 127 and includes anode electrodes (AND) that respectively correspond to the light emitting areas (EA) and are electrically connected to the pixel drivers (PXDs), respectively. A pixel definition layer (PDL) disposed on the third planarization layer 127 and corresponding to the non-emissive area (NEA), which is the spaced area between the light emitting areas (EA), and covering the edges of each of the anode electrodes (AND), light emitting Emission layers (EML) respectively corresponding to the areas EA and disposed on the anode electrodes AND, respectively, and corresponding to the emission areas EA and disposed on the pixel definition layer (PDL) and the light emitting layers (EML). It may include a cathode electrode (CTD) disposed.

The cathode electrode (CTD) may be electrically connected to the second power supply line (VSSPL).

The anode electrode (AND) may be electrically connected to the sixth connection electrode (CE6) through the anode contact hole (ANCT) penetrating the third planarization layer (127).

Accordingly, the anode electrode (AND) is connected to the seventh contact hole (CT7), the third connection electrode (CE3), the eighth contact hole (CT8), the fifth connection electrode (CE5), the ninth contact hole (CT9), and the sixth contact hole (CT9). It can be electrically connected to the pixel driver (PXD) through the connection electrode (CE6) and anode contact hole (ANCT).

The pixel defining layer (PDL) may be made of an organic layer.

The light emitting layer (EML) may include an organic light emitting material.

Although not separately shown, a first common layer (not shown) containing at least a hole transport material may be disposed between the anode electrode AND and the light emitting layer EML.

Additionally, a second common layer (not shown) containing at least an electron transport material may be disposed between the emission layer (EML) and the cathode electrode (CTD).

The cathode electrode CTD may correspond to the front surface of the display area DA.

Although not separately shown, the cathode electrode (CTD) may be connected to the second power supply line (VSSPL) in the non-display area (NDA).

Accordingly, the light emitting device layer 130 corresponds to each of the light emitting areas EA and is composed of a structure including an anode electrode (AND) and a cathode electrode (CTD) facing each other, and a light emitting layer (EML) sandwiched between them. It may include light emitting elements (LEL).

The light emitting device layer 130 may be covered with a sealing layer 140 to block penetration of oxygen or moisture.

The sealing layer 140 covers the light emitting device layer 130 and may have a structure in which at least one inorganic layer and at least one organic layer are cross-stacked.

As an example, the sealing layer 140 includes a first inorganic layer 141 that covers the cathode electrode (CTD) and is made of an inorganic insulating material, an organic layer 142 disposed on the first inorganic layer 141 and made of an organic insulating material, and a second inorganic layer 143 that covers the organic layer 142 and is made of an inorganic insulating material.

FIG. 14 is a plan view showing an example of light emitting areas arranged in portion C of FIGS. 4 and 5.

Referring to FIG. 14, the light-emitting areas EA of the display device 10 according to an embodiment may include a first light-emitting area EA1, a second light-emitting area EA2, and a third light-emitting area EA3. You can.

The first emission area EA1 and the third emission area EA3 may be arranged alternately in the first direction DR1 and the second direction DR2, respectively.

The second light emitting area EA2 may be adjacent to the first light emitting area EA1 or the third light emitting area EA3 in the first diagonal direction DR1 or the second diagonal direction DR2.

The second light emitting area EA2 may be arranged in parallel in each of the first direction DR1 and the second direction DR2.

A non-emission area (NEA) may be disposed around each of the emissive areas (EA).

FIG. 15 is a plan view showing light emitting areas and via holes disposed in portion C of FIGS. 4 and 5 of the display device according to the first embodiment. FIG. 16 is a plan view showing light emitting areas and via holes disposed in portion D of FIG. 4 of the display device according to the first embodiment.

15 and 16, the display device 10 according to the first embodiment includes via holes VIAH for electrical connection between the first dummy wires DML1 and the second dummy wires DML2. do.

Each of some of the via holes (VIAH) may overlap with one of the light-emitting areas (EA), and some of the remaining via-holes may be arranged in the non-emission area (NEA).

As described above with reference to FIGS. 5 and 6, according to one embodiment, the first dummy wires DML1 electrically connect the first demux circuit unit DMC1 and the first data supply wire DSPL1. The second bypass wire (DETL2) of the input bypass wire (IDEL) for connection to the first auxiliary wire (ASL1), which is electrically connected to the second power supply wire (VSSPL) and to which the second power source (ELVSS) is applied. It can be included.

The second dummy wires (DML2) are electrically connected to the first bypass wire (DETL1) and the third bypass wire (DETL3) of the input bypass wire (IDEL) and the second power supply wire (VSSPL) to provide a second power supply ( It may include second auxiliary wires (ASL2) to which ELVSS) is applied.

In addition, the second auxiliary wiring (ASL2) is a general auxiliary wiring (GASL) extending between both ends of the second direction (DR2) of the display area (DA), and a first bypass wiring (DETL1) in the second direction (DR2). It may include a first extension auxiliary wire (EASL1) spaced apart from one end, and a second extension auxiliary wire (EASL2) spaced apart from one end of the third bypass wire (DETL3) in the second direction (DR2).

Accordingly, as shown in FIG. 15, the via holes (VIAH) are a first bypass connection hole (DECH1) for electrical connection between the second bypass wiring (DETL2) and the first bypass wiring (DETL1), and the second bypass wiring (DETL1). It may include a second bypass connection hole (DECH2) for electrical connection between the wire (DETL2) and the third bypass wire (DETL3).

In addition, as shown in FIG. 16, the via holes (VIAH) may further include auxiliary connection holes (ASCH) for electrical connection between the first auxiliary wiring (ASL1) and the second auxiliary wiring (ASL2). .

The auxiliary connection holes (ASCH) are first auxiliary connection holes (ASCH1) overlapping with the general auxiliary wiring (GASL), and second auxiliary connection holes (ASCH1) disposed in the first general side area (GSA1) and overlapping with the second extension auxiliary wiring (EASL2). It may include an auxiliary connection hole (ASCH2) and a third auxiliary connection hole (ASCH3) disposed in the second general side area (GSA2) and overlapping the first extension auxiliary wire (EASL1).

According to the first embodiment, the first bypass connection hole (DECH1) and the second bypass connection hole (DECH2) among the via holes (VIAH) may be disposed in the non-emission area (NEA).

In this case, each of the first auxiliary connection holes (ASCH1) among the auxiliary connection holes (ASCH) may overlap with one of the light-emitting areas (EA).

The second bypass wiring (DETL2) extends in the first direction (DR1) between the first bypass wiring (DETL1) and the third bypass wiring (DETL3), and has a first bypass connection hole at both ends of the second bypass wiring (DETL2). (DECH1) and a second bypass connection hole (DECH2) are arranged.

As a result, the visibility of the disconnected portions at both ends of the second bypass wiring (DETL2) and the visibility of the first bypass connection hole (DECH1) and the second bypass connection hole (DECH2) are increased through interaction, so that the demultiplex adjacent As the image quality of the area DAA becomes different from the image quality of the general area GA, the display quality of the display device 10 may deteriorate.

However, according to the first embodiment, as the first bypass connection hole (DECH1) and the second bypass connection hole (DECH2) are disposed in the non-emission area (NEA), the first bypass connection hole (DECH1) and the second bypass connection hole (DECH1) The visibility of the connection hole (DECH2) can be reduced.

In addition, as the first bypass connection hole (DECH1) and the second bypass connection hole (DECH2) are disposed in the non-emission area (NEA), the light emitting element (LEL) of each of the light emitting areas (EA) is connected to the first bypass connection hole (DECH2). It does not overlap with (DECH1) or the second bypass connection hole (DECH2). Accordingly, it is possible to prevent the light emission directions of the light emitting elements LEL from differing due to the influence of the step caused by the first bypass connection hole DECH1 and the second bypass connection hole DECH2.

Accordingly, deterioration in display quality of the display device 10 due to the input bypass wiring (IDEL) can be reduced.

Meanwhile, among the second auxiliary wires ASL2, the first extension auxiliary wire EASL1 is arranged parallel to the first bypass wire DETL1 in the second direction DR2 and is spaced from one end of the first bypass wire DETL1. It can be.

Among the second auxiliary wirings ASL2, the second extension auxiliary wiring EASL2 may be arranged parallel to the third bypass wiring DETL3 in the second direction DR2 and may be spaced apart from one end of the third bypass wiring DETL3. there is.

Since the second extension auxiliary line EASL2 of the first display side area DSDA1 and the first extension auxiliary line EASL1 in the second display side area DSDA2 intersect with one or more second bypass lines DETL2, the auxiliary line It is difficult to overlap with the connection hole (ASCH).

Accordingly, according to the first embodiment, the auxiliary connection holes (ASCH) are not disposed in the first display side area (DSDA1) and the second display side area (DSDA2), but in the display middle area (DMDA) and the general area (GA). ) can be placed in.

As shown in FIG. 16, in the first general side area GSA1, the auxiliary connection holes ASCH1 and ASCH2, respectively overlapping with the first auxiliary wiring ASL1 adjacent in the second direction DR2, are the third auxiliary connection holes ASCH1 and ASCH2. It may be arranged in the diagonal direction (DD3).

That is, the auxiliary connection holes (ASCH) of the first general side area (GSA1) are arranged in the third diagonal direction (DD3) and include first auxiliary connection holes (ASCH1) and second auxiliary connection holes (ASCH2) alternating with each other. It can be included.

In addition, the auxiliary connection holes ASCH1 and ASCH3, respectively overlapping with the first auxiliary wiring ASL1 adjacent to the second direction DR2 in the second general side area GSA2, are formed in the fourth diagonal direction DD4. can be arranged.

That is, the auxiliary connection holes (ASCH) of the second general side area (GSA2) are arranged in the fourth diagonal direction (DD4) and include first auxiliary connection holes (ASCH1) and third auxiliary connection holes (ASCH3) alternating with each other. It can be included.

FIG. 17 is a plan view showing light emitting areas and via holes disposed in portion C of FIGS. 4 and 5 of the display device according to the second embodiment.

Referring to FIG. 17, in the display device of the second embodiment, the first auxiliary connection holes (ASCH1) among the via holes (VIAH) are disposed in the non-emission area (NEA), the first bypass connection hole (DECH1) and the second bypass connection hole (DECH1). Except that each of the connection holes DECH2 overlaps with one of the light emitting areas EA, it is the same as the first embodiment of FIG. 15, so overlapping descriptions will be omitted below.

The first bypass connection hole (DECH1) and the second bypass connection hole (DECH2) are disposed at both ends of the second bypass wiring (DETL2) in the demux adjacent area (DAA), while the first auxiliary connection holes (ASCH1) are indicated as One or more lines are disposed on each of the first auxiliary lines ASL1 in the area DD. Accordingly, the number of first auxiliary connection holes (ASCH1) may be greater than the total number of first bypass connection holes (DECH1) and second bypass connection holes (DECH2) disposed in the demultiplex adjacent area (DAA).

Therefore, according to the second embodiment, instead of the relatively small number of first bypass connection holes (DECH1) and second bypass connection holes (DECH2), a relatively large number of first auxiliary connection holes (ASCH1) are formed in the non-emission area (NEA). ) can be placed in. As a result, the visibility of the first auxiliary connection holes ASCH1 may be lowered. Additionally, the light emission directions of the light emitting elements LEL may be prevented from being different due to the influence of the step of the first auxiliary connection holes ASCH1. Accordingly, deterioration in display quality of the display device 10 due to via holes VIAH can be reduced.

FIG. 18 is a plan view showing data wires, first dummy wires, second dummy wires, and via holes arranged in portion C of FIGS. 4 and 5 in the display device according to the third embodiment. FIG. 19 is a plan view showing data wires, first dummy wires, second dummy wires, and via holes arranged in portion D of FIG. 4 in the display device according to the third embodiment.

Referring to FIGS. 18 and 19 , in the display device 10 according to the third embodiment, each of the data lines DL and the second dummy lines DML2 protrudes toward each of the adjacent pixel drivers PXD. It does not include a pair of mutually symmetrical sub protrusions, but includes a sub protrusion (SPR1) overlapping with the data connection hole (DTCH), sub protrusions (SPR2, SPR4, SPR6) facing the data connection hole (DTCH), and auxiliary connections. Except that it includes only the sub-protrusions (SPR3, SPR7) overlapping with the hole (ASCH) and the sub-protrusion (SPR5) overlapping with the first bypass connection hole (DECH1) or the second bypass connection hole (DECH2). Since it is substantially the same as the first embodiment shown in FIGS. 15 and 16 or the second embodiment shown in FIG. 17, overlapping descriptions will be omitted below.

According to the third embodiment, the first data line DL1 and the second data line DL2 disposed in the first display side area DSDA1 and the first general side area GSA1 each extend in the second direction DR2. It may include a first main extension part (MEX1) extending to and a first sub-projection (SPR1) that protrudes from the first main extension part (MEX1) and overlaps the data connection hole (DTCH) of each of the adjacent pixel drivers. there is.

The general auxiliary wire (GASL) adjacent to the first data wire (DL1) has a second main extension part (MEX2) extending in the second direction (DR2), protrudes from the second main extension part (MEX2), and carries first data It may include a second sub-protrusion SPR2 facing the first sub-protrusion SPR1 of the wiring DL1.

In the general area GA, the general auxiliary line GASL may further include a third sub protrusion SPR3 that protrudes from the second main extension part MEX2 and overlaps the first auxiliary connection hole ASCH1.

In the first general side area (GSA1), the first auxiliary connection holes (ASCH1) may be disposed on the third sub protrusion (SPR3) of the general auxiliary wires (GASL).

The first auxiliary connection holes ASCH1 may be arranged in the second diagonal direction DD2.

The third bypass wire (DETL3) adjacent to the second data wire (DL2) has a third main extension part (MEX3) extending in the second direction (DR2), protrudes from the third main extension part (MEX3), and extends in the first direction (DR2). A fourth sub-protrusion (SPR4) facing the first sub-protrusion (SPR1) of the data wire (DL1), and an auxiliary connection hole (ASCH) facing the first main extension (MEX1) of the first data wire (DL1) It may include a fifth sub protrusion (SPR5) overlapping with one of the second bypass connection holes (DECH2).

The fifth sub protrusion SPR5 may protrude toward one pixel driver adjacent to the intersection between one end of the second bypass line DETL2 and one third bypass line DETL3.

The second extension auxiliary wire EASL2 adjacent to the second data wire DL2 protrudes from the fourth main extension part MEX4 extending in the second direction DR2 and the fourth main extension part MEX4. 2 It may include a sixth sub-protrusion SPR6 facing the first sub-protrusion SPR1 of the data line DL2.

In the general area GA, the second extension auxiliary line EASL2 may further include a seventh sub protrusion that protrudes from the sixth main extension part MEX6 and overlaps the second auxiliary connection hole ASCH2.

The second auxiliary connection holes ASCH2 may be arranged in the second diagonal direction DD2 in the first general side area GSA1. The arrangement direction of the first auxiliary connection holes (ASCH1) and the arrangement direction of the second auxiliary connection holes (ASCH2) may be parallel.

Meanwhile, the second display side area DSDA2 and the second general side area GSA2 are formed by the third data line DL3 and the fourth data line DL4 instead of the first data line DL1 and the second data line DL2. ), and is substantially similar to the first display side area (DSDA1) and the first general side area (GSA1), except that it includes a first bypass line (DETL1) instead of a third bypass line (DETL3), The third data line DL3 and the fourth data line DL4 are similar to the first data line DL1 and the second data line DL2, and the first bypass line DETL1 is similar to the third bypass line DETL3. Since it is similar to , duplicate description is omitted.

As described above, according to the third embodiment, each of the data lines DL and the second dummy lines DML2 includes only sub protrusions that overlap the via holes VIAH. Accordingly, compared to the case where each of the data lines DL and the second dummy lines DML2 includes a pair of sub-projections that protrude toward each of the adjacent pixel drivers PXD and are mutually symmetrical, the number of sub-projections increases. can be reduced. Accordingly, as the number of sub-protrusions is reduced, the resistance of each of the data lines DL and the second dummy lines DML2 can be lowered, and thus the RC delay can be reduced.

FIG. 20 is a plan view showing data wires, first dummy wires, second dummy wires, and via holes arranged in portion D of FIG. 4 in the display device according to the fourth embodiment. FIG. 21 is a plan view showing data wires, first dummy wires, second dummy wires, and via holes arranged in portion E of FIG. 4 of the display device according to the fourth embodiment.

20 and 21, in the display device 10 according to the fourth embodiment, the auxiliary connection holes (ASCH) do not include the second auxiliary connection hole (ASCH2) and the third auxiliary connection hole (ASCH3). 15 and 16, except that the first extension auxiliary wire (EASL1) and the second extension auxiliary wire (EASL2) are connected to the second power supply wire (VSSPL) in the non-display area (NDA). Since it is substantially the same as the first embodiment shown in FIG. 17 or the second embodiment shown in FIG. 17, redundant description will be omitted below.

According to the fourth embodiment, the auxiliary connection holes (ASCH) may include only the first auxiliary connection holes (ASCH1) that overlap the general auxiliary wiring (GASL).

The first extension auxiliary wiring (EASL1) and the second extension auxiliary wiring (EASL2) are not electrically connected to the first auxiliary wiring (ASL1), but are instead connected to the second power supply wiring (VSSPL) in the non-display area (NDA). Can be directly electrically connected.

In this way, the resistance of the second power source (ELVSS) can be lowered due to the mesh structure between the general auxiliary wiring (GASL) and the first auxiliary wiring (ASL1), and heat generation is reduced due to the reduction of auxiliary connection holes (ASCH). It can be lowered.

FIG. 22 is a plan view showing data wires, first dummy wires, second dummy wires, and via holes arranged in portion E of FIG. 4 of the display device according to the fifth embodiment.

Referring to FIG. 22, the display device according to the fifth embodiment has a pair of data lines DL and second dummy lines DML2 each protruding toward each of the adjacent pixel drivers PXD and symmetrical to each other. It is substantially the same as the fourth embodiment shown in FIGS. 20 and 21, except that it does not include sub-projections, but only sub-projections that overlap the via holes (VIAH), so overlapping descriptions are provided below. Omit it.

Also, like the fourth embodiment, according to the fifth embodiment, the auxiliary connection holes (ASCH) include only the first auxiliary connection holes (ASCH1) that overlap the general auxiliary wiring (GASL). Accordingly, each of the first extension auxiliary wiring (EASL1) or the second extension auxiliary wiring (EASL2) has a seventh sub-protrusion (SPR7) overlapping with the second auxiliary connection hole (ASCH2) or the third auxiliary connection hole (ASCH3). It may not include the first sub-protrusion SPR1 and may only include the sixth sub-protrusion SPR6 facing the first sub-protrusion SPR1.

The fourth main extension part (MEX4) of each of the first extension auxiliary wire (EASL1) and the second extension auxiliary wire (EASL2) extends to the non-display area (NDA) and may be connected to the second power supply wire (VSSPL). .

According to the fifth embodiment, the data wires DL and the second dummy wires DML2 each have a sub protrusion SPR1 overlapping the data connection hole DTCH and a sub protrusion facing the data connection hole DTCH. (SPR3, SPR4, SPR6), the sub protrusion (SPR2) overlapping with the auxiliary connection hole (ASCH), and the sub protrusion (SPR5) overlapping with the first bypass connection hole (DECH1) or the second bypass connection hole (DECH2). Except for the inclusion point, it is substantially the same as the first embodiment shown in FIGS. 15 and 16 or the second embodiment shown in FIG. 17, so duplicate descriptions will be omitted below.

Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention can be implemented in other specific forms without changing its technical idea or essential features. You will be able to understand it. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive.

10: display device 100: display panel
MA: Main area SBA: Sub area
DA: Display area NDA: Non-display area
200: display driving circuit 300: circuit board
EA: luminous area
EA1, EA2, EA3: first, second and third light emitting areas
PX: Pixel 110: Substrate
120: circuit layer 130: light emitting device layer
140: sealing layer 150: sensor electrode layer
DXA: Demux area XMA: Demux middle area
XSA1, XSA2: 1st and 2nd demux side areas
DAA: Demux adjacent area GA: Normal area
DMDA: Display middle area GMA: General middle area
DSDA1, DSDA2: 1st and 2nd display side areas
GSA1, GSA2: 1st and 2nd general side areas
DMC: Demux circuit DL: Data wiring
DMC1, DMC2, DMC3: 1st, 2nd, 3rd demux circuit units
DL1, DL2, DL3, DL4: 1st, 2nd, 3rd, 4th data wires
DL5, DL6: 5th, 6th data wiring
DIP: input terminal
AOP: 1st output terminal BOP: 2nd output terminal
DSPL1, DSPL2, DSPL3: 1st, 2nd, 3rd data supply wiring
ICNL: Input connection wiring IDEL: Input bypass wiring
DETL1, DETL2, DETL3: 1st, 2nd, 3rd bypass wiring
VDSPL, VSSPL: 1st, 2nd power supply wiring
DML1, DML2: 1st, 2nd dummy wiring
ASL1, ASL2: 1st, 2nd auxiliary wiring
GASL: General Auxiliary Wiring
EASL1, EASL2: 1st, 2nd extension auxiliary wiring
VIAH: Via hole ASCH: Auxiliary connection hole
DECH1, DECH2: 1st, 2nd bypass connection holes
ASCH1, ASCH2, ASCH3: 1st, 2nd, 3rd auxiliary connection holes
DTCH: data connection hole
MEX1, MEX2, MEX3, MEX4: 1st, 2nd, 3rd, 4th main extensions
SPR1-7: 1-7 sub protrusion
VDAL: Primary power auxiliary wiring
TDM1, TDM2: 1st and 2nd demux transistors
DXCL1, DXCL2: 1st, 2nd demux control wiring
AT, BT: Senior, junior output period
DDRS: Data Drive Signal

Claims (20)

A substrate including a main area including a display area in which light emitting areas are arranged, a non-display area arranged around the display area, and a sub-area protruding from one side of the main area;
a circuit layer disposed on the substrate; and
A light-emitting device layer disposed on the circuit layer and including light-emitting devices corresponding to each of the light-emitting regions,
The circuit layer is
pixel drivers corresponding to the light-emitting areas and electrically connected to the light-emitting elements;
data lines transmitting data signals to the pixel drivers;
first dummy wires disposed in the display area and extending in a first direction crossing the data wires; and
Second dummy wires extending in a second direction parallel to the data wires and adjacent to the data wires on one side of the first direction,
Some of the via holes for electrical connection between the first dummy wires and the second dummy wires overlap one of the light emitting areas, and some of the remaining via holes overlap the light emitting areas. A display device disposed in a non-emission area, which is the spaced area between the display devices. According to claim 1,
further comprising a display driving circuit disposed in the sub-region of the substrate and supplying data driving signals corresponding to data signals of data lines of the circuit layer,
The circuit layer further includes demux circuit units disposed in a demux area adjacent to the sub-area among the non-display areas and electrically connected between the display driving circuit and the data wires,
One of the demux circuit units is
A display device including an input terminal electrically connected to the display driving circuit, and a first output terminal and a second output terminal respectively electrically connected to two of the data wires. According to clause 2,
The demux region includes a central demux middle region, a first demux side region adjacent to a bent portion of an edge of the substrate, and a second demux disposed between the demux middle region and the first demux side region. Includes a side area,
The demux circuit units include a first demux circuit unit disposed in the first demux side area, and a second demux circuit unit disposed in the second demux side area,
The circuit layer further includes data supply wires electrically connected to output terminals of the display driving circuit, respectively,
Among the data supply wires, a first data supply wire extends from the sub-area to the second demux side area and is electrically connected to the input terminal of the first demux circuit unit through an input bypass wire disposed in the display area. And
A second data supply line among the data supply lines extends from the sub-region to the second demux side region and is connected to an input terminal of the second demux circuit unit. According to clause 3,
Among the display areas, the demultiplex adjacent area adjacent to the demultiplex area includes a display middle area adjacent to the demultiplex area, a first display side area adjacent to the first demultiplex side area, and a second demultiplex side area. comprising an adjacent second display side region;
The input bypass wiring is
a first bypass wire disposed in the second display side area, extending in the second direction, and electrically connected to the first data supply wire;
a second bypass wire extending from the second display side area and the first display side area in the first direction and electrically connected to the first bypass wire; and
a third bypass wire disposed in the first display side area, extending in the second direction toward the first demux side area, and electrically connected to the second bypass wire;
The first dummy wires include the second bypass wire,
The second dummy wires include the first bypass wire and the third bypass wire. According to clause 4,
The circuit layer is
a first power supply wire and a second power supply wire disposed in the sub-area and the non-display area and respectively delivering first power and second power for driving the light-emitting elements; and
further comprising first power auxiliary wires disposed in the display area, extending in the first direction, and electrically connected to the first power supply wire;
The first dummy wires further include first auxiliary wires electrically connected to the second power supply wire,
The second dummy wires further include second auxiliary wires electrically connected to the second power supply wire. According to clause 5,
The display area further includes a general area disposed between the demultiplexed adjacent area and the non-display area in the second direction,
The general area includes a general middle area adjacent to the display middle area, a first general side area adjacent to the first display side area, and a second general side area adjacent to the second display side area,
the first bypass wiring extends in the second direction between the first data supply wiring and the second bypass wiring,
The second bypass wiring extends in the first direction between the first bypass wiring and the third bypass wiring,
The third bypass wiring extends in the second direction between the first demux side area and the second bypass wiring,
The second auxiliary wires are
general auxiliary wires extending between both ends of the display area in the second direction;
a first extension auxiliary wire spaced apart from one end of the first bypass wire in the second direction and extending to the second general side area;
A display device comprising a second extension auxiliary wire that is spaced apart from one end of the third bypass wire in the second direction and extends to the first general side area. According to clause 6,
The data wires are
a first data line and a second data line electrically connected to the first output terminal and the second output terminal of the first demux circuit unit, respectively, and disposed in the first display side area and the first general side area;
a third data line and a fourth data line electrically connected to the first output terminal and the second output terminal of the second demux circuit unit, respectively, and disposed in the second display side area and the second general side area; ,
Each of the first data wire and the third data wire is adjacent to one of the general auxiliary wires on one side in the first direction,
The second data wire is adjacent to the third bypass wire and the second extension auxiliary wire on one side in the first direction,
The fourth data wire is adjacent to the first bypass wire and the first extension auxiliary wire on one side in the first direction. According to clause 7,
The via holes are
a first bypass connection hole for electrical connection between the first bypass wiring and the second bypass wiring;
a second bypass connection hole for electrical connection between the second bypass wiring and the third bypass wiring; and
A display device including auxiliary connection holes for electrical connection between the first auxiliary wires and the second auxiliary wires. According to clause 8,
The auxiliary connection holes include first auxiliary connection holes that overlap the general auxiliary wiring,
The first bypass connection hole and the second bypass connection hole are disposed in the non-emission area,
A display device wherein each of the first auxiliary connection holes overlaps one of the light-emitting areas. According to clause 9,
The auxiliary connection holes include a second auxiliary connection hole disposed in the first general side area and overlapping the second extension auxiliary wire, and a third auxiliary connection hole disposed in the second general side area and overlapping the first extension auxiliary wire. It further includes an auxiliary connection hole,
The second auxiliary connection hole and the third auxiliary connection hole are disposed in the non-emission area. According to clause 9,
The first extension auxiliary wire and the second extension auxiliary wire are connected to the second power supply wire in the non-display area. According to clause 8,
The auxiliary connection holes include first auxiliary connection holes that overlap the general auxiliary wiring,
Each of the first bypass connection hole and the second bypass connection hole overlaps a light emitting area of one of the light emitting areas,
The first auxiliary connection holes are disposed in the non-emission area. According to clause 8,
First bypass connection holes each overlapping with adjacent first bypass wires in the second direction are arranged in a first diagonal direction crossing the first direction and the second direction,
The second bypass connection holes, each overlapping with adjacent first bypass wires in the second direction, are arranged in a second diagonal direction symmetrical to the first diagonal direction. According to clause 8,
Each of the pixel drivers is electrically connected to one of the data wires through a data connection hole,
Each of the first data wire and the second data wire includes a first main extension extending in the second direction and a first sub-projection that protrudes from the first main extension and overlaps the data connection hole; ,
A general auxiliary wire adjacent to the first data wire includes a second main extension extending in the second direction, and a second sub-protrusion that protrudes from the second main extension and faces the first sub-projection of the first data wire. It includes a sub protrusion and a third sub protrusion that faces the first main extension of the first data wire and overlaps a first auxiliary connection hole of one of the auxiliary connection holes,
A third bypass wire adjacent to the second data wire has a third main extension extending in the second direction, and a third bypass wire that protrudes from the third main extension and faces the first sub-projection of the second data wire. A display device comprising four sub-protrusions and a fifth sub-protrusion that protrudes from the third main extension, faces the first main extension of the second data line, and overlaps the second bypass connection hole. According to claim 14,
A second extension auxiliary wire adjacent to the second data wire has a fourth main extension extending in the second direction, protrudes from the fourth main extension and faces a first sub-projection of the second data wire. Comprising a sixth sub protrusion,
The fourth main extension part is connected to the second power supply wire in the non-display area. According to claim 15,
A second extension auxiliary wire adjacent to the second data wire protrudes from the fourth main extension, faces the first main extension of the second data wire, and connects with another one of the auxiliary connection holes. A display device further comprising an overlapping seventh sub protrusion. A substrate including a main area including a display area in which light emitting areas are arranged, a non-display area arranged around the display area, and a sub-area protruding from one side of the main area;
a circuit layer disposed on the substrate;
a light-emitting device layer disposed on the circuit layer and including light-emitting devices corresponding to each of the light-emitting regions; and
a display driving circuit disposed in the sub-region of the substrate and supplying data driving signals corresponding to data signals of data lines of the circuit layer;
The circuit layer is
pixel drivers corresponding to the light-emitting areas and electrically connected to the light-emitting elements;
data lines transmitting data signals to the pixel drivers;
first dummy wires disposed in the display area and extending in a first direction crossing the data wires;
second dummy wires extending in a second direction parallel to the data wires and adjacent to the data wires on one side of the first direction;
Demux circuit units disposed in a demux area adjacent to the sub-area among the non-display areas;
data supply wires electrically connected to output terminals of the display driving circuit, respectively;
a first power supply wire and a second power supply wire disposed in the sub-area and the non-display area and respectively delivering first power and second power for driving the light-emitting elements; and
First power auxiliary wires disposed in the display area, extending in the first direction, and electrically connected to the first power supply wire,
The demux region includes a central demux middle region, a first demux side region adjacent to a bent portion of an edge of the substrate, and a second demux disposed between the demux middle region and the first demux side region. Includes a side area,
Among the display areas, the demultiplex adjacent area adjacent to the demultiplex area includes a display middle area adjacent to the demultiplex area, a first display side area adjacent to the first demultiplex side area, and a second demultiplex side area. comprising an adjacent second display side area,
The demux circuit units include a first demux circuit unit disposed in the first demux side area, and a second demux circuit unit disposed in the second demux side area,
Among the data supply wires, a first data supply wire extends from the sub-area to the second demux side area and is electrically connected to the input terminal of the first demux circuit unit through an input bypass wire disposed in the display area. And
Among the data supply wires, a second data supply wire extends from the sub-region to the second demux side area and is connected to an input terminal of the second demux circuit unit,
The input bypass wiring is
a first bypass wire disposed in the second display side area, extending in the second direction, and electrically connected to the first data supply wire;
a second bypass wire extending from the second display side area and the first display side area in the first direction and electrically connected to the first bypass wire; and
a third bypass wire disposed in the first display side area, extending in the second direction toward the first demux side area, and electrically connected to the second bypass wire;
The first dummy wires include the second bypass wire and first auxiliary wires,
The second dummy wires include the first bypass wire, the third bypass wire, and second auxiliary wires,
The first auxiliary wires and the second auxiliary wires are electrically connected to the second power supply wire,
A first bypass connection hole for electrical connection between the first bypass wiring and the second bypass wiring overlaps one of the light emitting regions,
A second bypass connection hole for electrical connection between the third bypass wiring and the second bypass wiring overlaps with another light emitting region among the light emitting regions,
Auxiliary connection holes for electrical connection between the first auxiliary wires and the second auxiliary wires are disposed in a non-emission area, which is a spaced area between the light emitting areas. According to claim 17,
The display area further includes a general area disposed between the demultiplexed adjacent area and the non-display area in the second direction,
The general area includes a general middle area adjacent to the display middle area, a first general side area adjacent to the first display side area, and a second general side area adjacent to the second display side area,
the first bypass wiring extends in the second direction between the first data supply wiring and the second bypass wiring,
The second bypass wiring extends in the first direction between the first bypass wiring and the third bypass wiring,
The third bypass wiring extends in the second direction between the first demux side area and the second bypass wiring,
The second auxiliary wires are
general auxiliary wires extending between both ends of the display area in the second direction;
a first extension auxiliary wire spaced apart from one end of the first bypass wire in the second direction and extending to the second general side area;
a second extension auxiliary wire spaced apart from one end of the third bypass wire in the second direction and extending to the first general side area;
The data wires are
a first data line and a second data line electrically connected to the first demux circuit unit and disposed in the first display side area and the first general side area;
a third data line and a fourth data line electrically connected to the second demux circuit unit and disposed in the second display side area and the second general side area;
Each of the first data wire and the third data wire is adjacent to one of the general auxiliary wires on one side in the first direction,
The second data wire is adjacent to the third bypass wire and the second extension auxiliary wire on one side in the first direction,
The fourth data wire is adjacent to the first bypass wire and the first extension auxiliary wire on one side in the first direction. According to clause 18,
The first extension auxiliary wire and the second extension auxiliary wire are connected to the second power supply wire in the non-display area. According to clause 19,
Each of the pixel drivers is electrically connected to one of the data wires through a data connection hole,
Each of the first data wire and the second data wire includes a first main extension extending in the second direction and a first sub-projection that protrudes from the first main extension and overlaps the data connection hole; ,
A general auxiliary wire adjacent to the first data wire includes a second main extension extending in the second direction, and a second sub-protrusion that protrudes from the second main extension and faces the first sub-projection of the first data wire. It includes a sub protrusion and a third sub protrusion that faces the first main extension of the first data wire and overlaps an auxiliary connection hole of one of the auxiliary connection holes,
A third bypass wire adjacent to the second data wire has a third main extension extending in the second direction, and a third bypass wire that protrudes from the third main extension and faces the first sub-projection of the second data wire. It includes four sub protrusions and a fifth sub protrusion that protrudes from the third main extension, faces the first main extension of the second data wire, and overlaps the second bypass connection hole,
A second extension auxiliary wire adjacent to the second data wire has a fourth main extension extending in the second direction, protrudes from the fourth main extension and faces a first sub-projection of the second data wire. Comprising a sixth sub protrusion,
The fourth main extension part is connected to the second power supply wire in the non-display area.

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