KR20240017302A - Display apparatus - Google Patents

Abstract

A display device is provided. The display device includes a substrate, a plurality of pixel drivers, data wires, a circuit array layer including demultiplex circuit units disposed in a demultiplex area adjacent to the sub-area of the non-display area, and corresponding to the data wires. and a display driving circuit that supplies data driving signals. A second data input wire connected to the second demux circuit unit disposed in the second demux area, which is an area on one side of the first direction of the demux area, is a main input wire, and a digital signal disposed in the display area and connected to the main input wire. It includes a mux bypass wiring, and a bypass additional wiring connecting the demux bypass wiring and the input terminal of the second demux circuit unit.

Description

DISPLAY APPARATUS}

The present invention relates to a display device.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. For example, display devices are applied to various electronic devices such as smartphones, digital cameras, laptop computers, navigation systems, and smart televisions.

A display device may include a display panel that emits light for displaying an image, and a driver that supplies a signal or power to drive the display panel.

At least one surface of the display device may be referred to as a display surface on which an image is displayed. The display surface may include a display area in which a plurality of light-emitting areas that emit respective lights for image display are arranged, and a non-display area surrounding the display area.

The display device may include data lines disposed in the display area and transmitting respective data signals to a plurality of light emitting areas, and a display driving circuit supplying respective data signals to the data lines.

Meanwhile, as signal transmission wires between data wires and the display driving circuit are arranged in the non-display area, as the number of data wires increases to improve resolution, the width of the non-display area may increase.

On the other hand, when the width of the non-display area is reduced to increase the ratio of the display area to the display surface, it becomes difficult to arrange the signal transmission wires at intervals greater than a critical distance in consideration of short circuit prevention. That is, since the number of signal transmission wires that can be arranged in the non-display area is limited to a predetermined number, it is difficult to improve the resolution of the display device.

Accordingly, the problem to be solved by the present invention is to provide a display device that can reduce the width of the non-display area without affecting resolution.

The problems of the present invention are not limited to the problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the description below.

A display device according to an embodiment for solving the above problem includes a display area in which a plurality of light-emitting areas are arranged in a first direction and a second direction, a main area including a non-display area disposed around the display area, and the main area. A substrate including a sub-region protruding from one side of the region, a plurality of pixel drivers disposed on the substrate, each corresponding to the plurality of light-emitting regions, and data transmitting a data signal to the plurality of pixel drivers. A circuit array layer including wires and demux circuit units disposed in a demux area adjacent to the sub-region of the non-display area, and data driving signals disposed in the sub-region of the substrate and corresponding to the data wires. Includes a display driving circuit that supplies One of the demux circuit units outputs two or more data signals based on one data driving signal. The demux circuit units include a first demux circuit unit disposed in a first demux area adjacent to the sub-area among the demux areas, and a first demux circuit unit in contact with one side of the first demux area in the first direction among the demux areas. It includes a second demux circuit unit disposed in the second demux area. The circuit array layer includes a first data input line extending from the sub-area to the first demultiplex area and connected to the input terminal of the first demultiplex circuit section, and a second data input line connected to the input terminal of the second demultiplex circuit section. It further includes input wiring. The second data input wire includes a main input wire extending from the sub area to the first demultiplex area, a demultiplex bypass wire disposed in the display area and connected to the main input wire, and a main input wire extending from the sub area to the first demultiplex area. It is disposed and includes a bypass additional wiring connecting the demux bypass wiring and the input terminal of the second demux circuit unit.

The display area may include a demux adjacent area adjacent to the demux area. The demux bypass wire is disposed in a center adjacent area adjacent to the first demux area among the demux adjacent areas, is connected to the main input wire, and extends in the second direction, the first bypass wire. a second bypass line connected to and extending in the first direction, and an area between the center adjacent area and the non-display area among the demultiplexed adjacent areas, and disposed in an edge adjacent area adjacent to the second demultiplexed area, It may include a third bypass wiring that extends in the second direction toward the second demux area and connects the second bypass wiring and the bypass additional wiring.

The additional bypass wiring may extend in the second direction.

Alternatively, the bypass additional wiring may include a first extension connected to the third bypass wiring and extending in the second direction, and connected between the first extension and the input terminal of the second demux circuit and extending in the first direction. It may include a second extension extending to.

The sub-region may include a bending region that is transformed into a bent shape, a first sub-region disposed between the main region and one side of the bending region, and a second sub-region disposed between the other side of the bending region. there is. The circuit array layer is disposed in the second sub-region and has a first data supply line and a second data supply line respectively connected to output terminals of the display driving circuit, and between the first data supply line and the first data input line. It may further include a first data bending wire connected to and disposed in the bending area, and a second data bending wire connected between the second data supply wire and the main input wire and disposed in the bending area.

The display device may further include a light emitting array layer disposed on the third planarization layer and including a plurality of light emitting elements respectively corresponding to the plurality of light emitting regions. The data wires may extend in the second direction. The circuit array layer is disposed in the display area and includes first and second power supply wires that are disposed in the non-display area and transmit first and second power supplies for driving the light-emitting elements, respectively, and the display area. It may further include a second power auxiliary wire extending in a second direction and electrically connected to the second power supply wire. A portion of each of the first power supply wiring and the second power supply wiring may overlap the demux circuit units.

One of two or more data wires disposed in an area adjacent to the center and connected to the first demux circuit unit may be disposed adjacent to the first bypass wire. Among the two or more data wires disposed in the area adjacent to the center and connected to the first demultiplexer circuit, all but one adjacent to the first bypass wire may be disposed adjacent to the second power auxiliary wire.

Any one of two or more data wires disposed in an area adjacent to the edge and connected to the second demux circuit unit may be disposed adjacent to the third bypass wire. Among the two or more data wires disposed in the area adjacent to the edge and connected to the second demux circuit unit, all but one adjacent to the third bypass wire may be arranged adjacent to the second power auxiliary wire.

The center adjacent area may include a central middle area and a side area between the middle area and the edge adjacent area. The first demux circuit unit may be disposed in a portion of the first demux area adjacent to the side area. The demux circuit units may further include a third demux circuit unit disposed in another portion of the first demux area adjacent to the middle area. Two or more data wires arranged in the middle area and connected to the third demux circuit unit may be arranged adjacent to the second power auxiliary wire.

The circuit array layer includes a first power auxiliary wire disposed in the display area, extending in the first direction and electrically connected to the first power supply wire, and a general area remaining in the display area excluding the area adjacent to the demux. It may further include a second power sub-wire disposed in the area, extending in the first direction, and electrically connected to the second power supply wire. The first power auxiliary wire may be arranged adjacent to the second bypass wire in the demux adjacent area, and may be arranged adjacent to the second power sub wire in the general area.

The circuit array layer includes first dummy wires spaced side by side on one side of the first bypass wire in the second direction and one side of the third bypass wire in the second direction and extending in the second direction, and It may further include second dummy wires that are spaced apart from each other in parallel on both sides of the second bypass wire in the first direction and extend in the first direction.

The first dummy wires or the second dummy wires may be electrically connected to the second power supply wire.

The circuit array layer includes a semiconductor layer on the substrate, a first conductive layer on a first gate insulating layer covering the semiconductor layer, a second conductive layer on a second gate insulating layer covering the first conductive layer, and the second conductive layer. a third conductive layer on the interlayer insulating layer covering the third conductive layer, a fourth conductive layer on the first planarization layer covering the third conductive layer, a fifth conductive layer on the second planarization layer covering the fourth conductive layer, and the fifth conductive layer. It may be provided with a structure including a third planarization layer covering the layer. The data wires, the first bypass wire, the third bypass wire, the second power auxiliary wire, and the first dummy wire may be formed of the fifth conductive layer. The second bypass wiring, the first power auxiliary wiring, the second dummy wiring, and the second power sub wiring may be formed of the fourth conductive layer.

Each of the demux circuit units may include two or more demux transistors. Gate electrodes of the two or more demux transistors may each be connected to two or more demux control wires. The two or more demux control wires may supply demux control signals of different phases.

The light emitting array layer is disposed on the third planarization layer and includes a plurality of anode electrodes, each corresponding to the plurality of light emitting regions and electrically connected to the plurality of pixel drivers, respectively, disposed on the third planarization layer. a pixel definition layer corresponding to a non-emission area, which is a spaced area between the plurality of light emitting areas, and covering an edge of each of the plurality of anode electrodes, and a pixel definition layer corresponding to each of the plurality of light emitting areas and covering the edges of each of the plurality of anode electrodes. It may include a plurality of light-emitting layers respectively disposed in, and a cathode electrode corresponding to the plurality of light-emitting regions, disposed on the pixel definition layer and the plurality of light-emitting layers, and connected to the second power supply wire. Each of the plurality of light emitting devices may include an anode electrode and a cathode electrode facing each other, and a light emitting layer disposed between the anode electrode and the cathode electrode.

A display device according to an embodiment includes a display area in which a plurality of light-emitting areas are arranged in a first direction and a second direction, a main area including a non-display area disposed around the display area, and a main area that protrudes from one side of the main area. a substrate including a sub-region, a plurality of pixel drivers disposed on the substrate and corresponding to each of the plurality of light-emitting regions, data lines that transmit data signals to the plurality of pixel drivers, and a circuit array layer including demux circuit units disposed in a demux area adjacent to the sub-area among non-display areas, a display driving circuit disposed in the sub-area of the substrate and supplying data driving signals corresponding to the data lines; and a light emitting array layer disposed on the circuit array layer and including a plurality of light emitting elements each corresponding to the plurality of light emitting regions. One of the demux circuit units outputs two or more data signals based on one data driving signal. The circuit array layer further includes a first power supply wire and a second power supply wire that are disposed in the non-display area and transmit first power and second power for driving the light emitting elements, respectively. A portion of each of the first power supply wiring and the second power supply wiring overlaps the demux circuit portions.

The demux circuit units include a first demux circuit unit disposed in a first demux area adjacent to the sub-region, and a second demux circuit unit disposed in a second demux area adjacent to one side of the first demux area in the first direction. It may include a demux circuit. The circuit array layer includes a first data input line extending from the sub-area to the first demultiplex area and connected to the input terminal of the first demultiplex circuit section, and a second data input line connected to the input terminal of the second demultiplex circuit section. It may further include input wiring. The second data input wire includes a main input wire extending from the sub area to the first demultiplex area, a demultiplex bypass wire disposed in the display area and connected to the main input wire, and a main input wire extending from the sub area to the first demultiplex area. It may include an additional bypass wire that is disposed and connects the demux bypass wire and the input terminal of the second demux circuit unit.

The display area may include a demux adjacent area adjacent to the demux area. The demultiplex bypass wire is disposed in a center adjacent area adjacent to the first demultiplex area among the demultiplex adjacent areas, is connected to the main input wire, and extends in the second direction. a second bypass line connected to and extending in the first direction, and an area between the center adjacent area and the non-display area among the demultiplexed adjacent areas, and disposed in an edge adjacent area adjacent to the second demultiplexed area, It may include a third bypass wiring that extends in the second direction toward the second demux area and connects the second bypass wiring and the additional bypass wiring.

The additional bypass wiring may extend in the second direction.

Alternatively, the bypass additional wiring may include a first extension connected to the third bypass wiring and extending in the second direction, and connected between the first extension and the input terminal of the second demux circuit and extending in the first direction. It may include a second extension extending to.

The circuit array layer may further include a second power auxiliary wire disposed in the display area, extending in the second direction, and electrically connected to the second power supply wire. One of the two or more data wires disposed in the area adjacent to the center and connected to the first demux circuit unit is disposed adjacent to the first bypass wire, and the remaining data wires are arranged adjacent to the second power auxiliary wire. You can.

The circuit array layer may further include a second power auxiliary wire disposed in the display area, extending in the second direction, and electrically connected to the second power supply wire. One of the two or more data wires disposed in the area adjacent to the edge and connected to the second demux circuit unit is disposed adjacent to the third bypass wire, and the remaining data wires are arranged adjacent to the second power auxiliary wire. You can.

The circuit array layer includes a second power auxiliary wire disposed in the display area, extending in the second direction, and electrically connected to the second power supply wire, and a second power auxiliary wire, disposed in the display area, extending in the first direction, and electrically connected to the second power supply wire. 1 A first power auxiliary wire electrically connected to the power supply wire, and disposed in a general area other than the area adjacent to the demux of the display area, extending in the first direction and electrically connected to the second power supply wire. It may further include a connected second power sub-wiring. The first power auxiliary wire may be arranged adjacent to the second bypass wire in the demux adjacent area, and may be arranged adjacent to the second power sub wire in the general area.

The circuit array layer includes first dummy wires spaced side by side on one side of the first bypass wire in the second direction and one side of the third bypass wire in the second direction and extending in the second direction, and It may further include second dummy wires that are spaced apart from each other in parallel on both sides of the second bypass wire in the first direction and extend in the first direction.

The first dummy wires or the second dummy wires may be electrically connected to the second power supply wire.

The circuit array layer includes a semiconductor layer on the substrate, a first conductive layer on a first gate insulating layer covering the semiconductor layer, a second conductive layer on a second gate insulating layer covering the first conductive layer, and the second conductive layer. a third conductive layer on the interlayer insulating layer covering the third conductive layer, a fourth conductive layer on the first planarization layer covering the third conductive layer, a fifth conductive layer on the second planarization layer covering the fourth conductive layer, and the fifth conductive layer. It may be provided with a structure including a third planarization layer covering the layer. The data wires, the first bypass wire, the third bypass wire, the second power auxiliary wire, and the first dummy wire may be formed of the fifth conductive layer. The second bypass wiring, the first power auxiliary wiring, the second dummy wiring, and the second power sub wiring may be formed of the fourth conductive layer.

The light emitting array layer is disposed on the third planarization layer and includes a plurality of anode electrodes, each corresponding to the plurality of light emitting regions and electrically connected to the plurality of pixel drivers, respectively, disposed on the third planarization layer. a pixel definition layer corresponding to a non-emission area, which is a spaced area between the plurality of light emitting areas, and covering an edge of each of the plurality of anode electrodes; a pixel definition layer corresponding to each of the plurality of light emitting areas and covering the edges of each of the plurality of anode electrodes; It may include a plurality of light-emitting layers respectively disposed in, and a cathode electrode corresponding to the plurality of light-emitting regions, disposed on the pixel definition layer and the plurality of light-emitting layers, and connected to the second power supply wiring. Each of the plurality of light emitting devices may include an anode electrode and a cathode electrode facing each other, and a light emitting layer between the anode electrode and the cathode electrode.

The sub-region may include a bending region that is transformed into a bent shape, a first sub-region disposed between the main region and one side of the bending region, and a second sub-region disposed between the other side of the bending region. there is. The circuit array layer is disposed in the second sub-region and has a first data supply line and a second data supply line respectively connected to output terminals of the display driving circuit, and between the first data supply line and the first data input line. It may further include a first data bending wire connected to and disposed in the bending area, and a second data bending wire connected between the second data supply wire and the main input wire and disposed in the bending area.

Specific details of other embodiments are included in the detailed description and drawings.

A display device according to an embodiment includes data wires that transmit data signals to a plurality of pixel drivers corresponding to a plurality of light-emitting areas, and a demultiplex circuit disposed in a demultiplex area adjacent to a sub-region among the non-display areas. It includes a circuit array layer including a display driving circuit that supplies data driving signals corresponding to the data lines. Here, each of the demux circuit units outputs two or more data signals based on one data driving signal.

As such, the display device of one embodiment includes demux circuit units connected between the display driving circuit and the data wires, so the output terminal of the display driving circuit is not directly connected to the data wires, but has fewer output terminals than the data wires. It is connected to the demux circuits of Therefore, since the number of data supply wires connected to the output terminal of the display driving circuit and the number of data bending wires connected to the data supply wires can be smaller than the number of data wires, the width of the non-display area can be reduced. Alternatively, the spacing between data bending wires placed in the bending area may be widened, or the width of the data bending wires placed in the bending area may be widened.

Accordingly, since the width of the non-display area can be reduced without reducing the number of data wires, limitations in resolution due to a decrease in the width of the non-display area can be eliminated.

Additionally, according to one embodiment, a portion of each of the first power supply wiring and the second power supply wiring may overlap with the demux circuit portions of the demux area. Accordingly, since the width of the non-display area does not increase by the width of the demux area, the width of the non-display area can be prevented from being greatly increased while including the demux area.

In addition, according to one embodiment, the demux circuit units include a first demux circuit unit disposed in a first demux area adjacent to the sub-region, and a second demux area adjacent to one side of the first demux area in the first direction. It includes a second demux circuit unit disposed. The first data input line connected to the input terminal of the first demux circuit unit may extend from the first sub-area to the first demux area. And, the second data input wire connected to the input terminal of the second demux circuit unit includes a main input wire extending from the first sub area to the first demux area, a demux bypass wire disposed in the display area, and a second demux circuit. Includes bypass additional wiring disposed in the mux area.

That is, the second data input line does not extend from the first sub-area to the second demux area, but instead detours from the first sub-area to the first demux area and the display area to reach the second demux area.

In this way, since the second data input wire does not extend from the first sub-region to the second demux areas, the second data input wire is not arranged in the second demux area, so the portion bent along the edge of the substrate The width of the second demux area including may be reduced. Therefore, the width of the non-display area can be further reduced.

Effects according to the embodiments are not limited to the contents exemplified above, and further various effects are included in the present specification.

1 is a perspective view showing a display device according to an embodiment.
FIG. 2 is a plan view showing the display device of FIG. 1 .
Figure 3 is a cross-sectional view showing an example of a surface cut along line A-A' of Figure 2.
FIG. 4 is a plan view showing the main area and sub area of the display device of FIG. 1 .
FIG. 5 is a layout diagram showing part B of FIG. 4 according to the first embodiment.
FIG. 6 is an equivalent circuit diagram showing an example of the pixel driver of FIG. 5.
FIG. 7 is an equivalent circuit diagram showing another example of the pixel driver of FIG. 5.
FIG. 8 is a plan view showing an example of a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer among two neighboring pixel drivers of FIG. 5 .
Figure 9 is a plan view showing an example of two adjacent pixel drivers.
FIG. 10 is a cross-sectional view showing an example of a surface cut along line G-G' of FIGS. 8 and 9.
FIG. 11 is an equivalent circuit diagram showing the demux circuit unit of FIG. 5 according to the first embodiment.
FIG. 12 is a plan view showing an example of portion E of FIG. 5.
Figure 13 is a cross-sectional view showing an example of a surface cut along line H-H' of Figure 12.
Figure 14 is a cross-sectional view showing an example of a surface cut along line F-F' of Figure 5.
FIG. 15 is a layout diagram showing an example of the fourth and fifth conductive layers in part C of FIG. 4 according to the first embodiment.
FIG. 16 is a layout diagram showing another example of the fourth and fifth conductive layers in part C of FIG. 4 according to the first embodiment.
FIG. 17 is a layout diagram showing an example of the fourth and fifth conductive layers in portion D of FIG. 4 according to the first embodiment.
FIG. 18 is an equivalent circuit diagram showing the demux circuit of FIG. 5 according to the second embodiment.
Figure 19 is a layout diagram showing part of the display area and part of the demux area according to the second embodiment.
FIG. 20 is a layout diagram showing part B of FIG. 4 according to the third embodiment.
FIG. 21 is a plan view showing an example of portion I of FIG. 20.

The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and will be implemented in various different forms. The present embodiments only serve to ensure that the disclosure of the present invention is complete and that common knowledge in the technical field to which the present invention pertains is not limited. It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims.

When an element or layer is referred to as “on” another element or layer, it includes instances where the element or layer is directly on top of or intervening with the other element. Like reference numerals refer to like elements throughout the specification. The shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining the embodiments are illustrative and the present invention is not limited to the details shown.

Although first, second, etc. are used to describe various components, these components are of course not limited by these terms. These terms are merely used to distinguish one component from another. Therefore, it goes without saying that the first component mentioned below may also be a second component within the technical spirit of the present invention.

Each feature of the various embodiments of the present invention can be combined or combined with each other, partially or entirely, and various technological interconnections and operations are possible, and each embodiment can be implemented independently of each other or together in a related relationship. It may be possible.

Hereinafter, specific embodiments will be described with reference to the attached drawings.

1 is a perspective view showing a display device according to an embodiment. FIG. 2 is a plan view showing the display device of FIG. 1 . Figure 3 is a cross-sectional view showing an example of a surface cut along line A-A' of Figure 2. FIG. 4 is a plan view showing a main area and a sub area of the display device of FIG. 1 .

Referring to FIG. 1, the display device 10 is a device that displays moving images or still images, and is used in mobile phones, smart phones, tablet personal computers, and smart watches. ), watch phones, mobile communication terminals, electronic notebooks, e-books, PMP (portable multimedia players), navigation, UMPC (Ultra Mobile PC), as well as portable electronic devices such as televisions, laptops, monitors, billboards, etc. It can be used as a display screen for various products such as the Internet of Things (IOT).

The display device 10 may include an organic light emitting display device using an organic light emitting diode, a quantum dot light emitting display device including a quantum dot light emitting layer, an inorganic light emitting display device including an inorganic semiconductor, and a micro or nano light emitting diode (micro LED). It may be a light-emitting display device such as a miniature light-emitting display device using (or nano LED)). Hereinafter, the description will focus on the fact that the display device 10 is an organic light emitting display device. However, the present invention is not limited to this and can be applied to display devices including organic insulating materials, organic light-emitting materials, and metal materials.

The display device 10 may be formed flat, but is not limited thereto. For example, the display device 10 is formed at the left and right ends and may include a curved portion having a constant curvature or a changing curvature. In addition, the display device 10 may be flexibly formed to be bent, curved, bent, folded, or rolled.

The display device 10 may include a substrate 110, a display driving circuit 200, and a circuit board 300.

The substrate 110 includes a display area DA in which a plurality of light-emitting areas (EA in FIG. 5 ) for displaying an image are arranged.

That is, the substrate 110 includes a main area (MA) including a display area (DA) and a non-display area (NDA) that is a peripheral area of the display area (DA), and a second direction DR2 of the main area (MA). It may include a sub-area (SBA) protruding from one side.

1 and 4 show the sub-area (SBA) spread out parallel to the main area (MA). On the other hand, Figure 2 illustrates a state in which a portion of the sub-area SBA is bent.

Referring to FIG. 2 , the display area DA may be formed as a rectangular plane having a short side in the first direction DR1 and a long side in the second direction DR2 that intersects the first direction DR1. A corner where the short side in the first direction DR1 and the long side in the second direction DR2 meet may be rounded to have a predetermined curvature or may be formed at a right angle. The planar shape of the display area DA is not limited to a square, and may be formed in other polygonal, circular, or oval shapes.

The display area DA may occupy most of the main area MA. The display area DA may be placed in the center of the main area MA.

The display area DA may include a plurality of light emitting areas EA arranged in parallel with each other. Additionally, the display area DA may further include a non-emission area (NEA in FIG. 10 ) that is a spaced area between the plurality of emission areas EA.

The plurality of light emitting areas EA may be arranged parallel to each other in the first direction DR1 and the second direction DR2.

Each of the plurality of light emitting areas EA may have a diamond-shaped planar shape or a rectangular planar shape. However, this is only an example, and the planar shape of the plurality of light emitting areas EA according to one embodiment is not limited to that shown in FIG. 9. That is, the plurality of light emitting areas EA may have a polygonal, circular, or oval planar shape other than a square.

The plurality of light-emitting areas EA include a first light-emitting area EA1 that emits light of a first color in a predetermined wavelength band, and a first light-emitting area EA1 that emits light of a second color in a wavelength band lower than the first color. It may include two light-emitting areas EA2 and third light-emitting areas EA3 that emit light of a third color in a wavelength band lower than that of the second color.

As an example, the first color may be red in a wavelength range of approximately 600 nm to 750 nm. The second color may be green in a wavelength range of approximately 480 nm to 560 nm. The third color may be blue in a wavelength band of approximately 370 nm to 460 nm.

As shown in FIG. 2 , the first emission areas EA1 and the third emission areas EA3 may be alternately arranged in the first direction DR1 or the second direction DR2. Additionally, the second light emitting areas EA2 may be arranged side by side in the first direction DR1 or the second direction DR2.

A plurality of pixels (PX) that display respective luminance and color may be provided by these plurality of light emitting areas (EA). Each of the plurality of pixels (PX) may be a basic unit that displays various colors, including white, at a predetermined luminance.

Each of the plurality of pixels (PX) may include at least one first emission area (EA1), at least one second emission area (EA2), and at least one third emission area (EA3) adjacent to each other.

Each of the plurality of pixels (PX) is composed of a mixture of light emitted from each of at least one first emission area (EA1), at least one second emission area (EA2), and at least one third emission area (EA3) adjacent to each other. Color and luminance can be displayed.

Meanwhile, FIG. 2 illustrates a case where a plurality of light emitting areas EA have the same area, but this is only an example. As another example, the third light-emitting area EA3 may have the largest area, and the second light-emitting area EA2 may have the smallest area.

Also, although FIG. 2 illustrates a case where a plurality of light emitting areas EA are arranged side by side in the first direction DR1 and the second direction DR2, this is only an example. As another example, the second light-emitting areas EA2 may be adjacent to the first light-emitting area EA1 and the third light-emitting area EA3 in a diagonal direction that intersects the first direction DR1 and the second direction DR2. there is.

Referring to FIG. 3, the display panel 100 of the display device 10 includes a substrate 110 including a main area (MA) and a sub-area (SBA), and a circuit array layer ( 120). The circuit array layer 120 transmits data signals to a plurality of pixel drivers (PXDs in FIGS. 12 and 13) corresponding to each of the plurality of light emitting areas EA and a plurality of pixel drivers PXDs. Includes wiring (DL in FIGS. 5, 12, and 13).

Additionally, the display panel 100 of the display device 10 may further include a light emitting array layer 130 disposed on the circuit array layer 120 . The light emitting array layer 130 includes a plurality of light emitting elements (LELs in FIGS. 6, 7, and 10) respectively corresponding to a plurality of light emitting areas EA.

In addition, the display panel 100 of the display device 10 may further include a sealing structure 140 covering the light emitting array layer 130 and a sensor electrode layer 150 disposed on the sealing structure 140.

The substrate 110 may be made of an insulating material such as polymer resin. For example, the substrate 110 may be made of polyimide. The substrate 110 may be a flexible substrate capable of bending, folding, rolling, etc.

Alternatively, the substrate 100 may be made of an insulating material such as glass.

The sealing structure 140 is disposed on the circuit array layer 120, corresponds to the main area MA, and covers the light emitting array layer 130. The sealing structure 140 may include a structure in which the light emitting array layer 130 is alternately stacked with at least one inorganic layer and at least one organic layer.

The sensor electrode layer 150 may be disposed on the sealing structure 140 and correspond to the main area (MA). The sensor electrode layer 150 may include touch electrodes for detecting the touch of a person or object.

The display device 10 may further include a cover window (not shown) disposed on the sensor electrode layer 150. The cover window may be attached to the sensor electrode layer 150 by a transparent adhesive member such as an optically clear adhesive (OCA) film or an optically clear resin (OCR). The cover window may be inorganic, such as glass, or organic, such as plastic or polymer materials. By this cover window, the sensor electrode layer 150, the sealing structure 140, the light emitting array layer 130, and the circuit array layer 120 can be protected from electrical and physical shock on the display surface.

Additionally, the display device 10 may further include an anti-reflection member (not shown) disposed between the sensor electrode layer 150 and the cover window. The anti-reflection member may be a polarizing film or a color filter. External light reflected from the sensor electrode layer 150, the sealing structure 140, the light emitting array layer 130, and the circuit array layer 120 and their interfaces is blocked by this anti-reflection member, thereby displaying the display device 10. Deterioration of image visibility due to this can be prevented.

The display device 10 may further include a touch driving circuit 400 for driving the sensor electrode layer 150.

The touch driving circuit 400 may be prepared as an integrated circuit (IC). The touch driving circuit 400 may be electrically connected to the sensor electrode layer 150 by being mounted on the circuit board 300 bonded to signal pads (SPDs).

Alternatively, the touch driving circuit 400 may be mounted in the second sub-region SB2 of the substrate 110, like the display driving circuit 200.

The touch driving circuit 400 applies a touch driving signal to a plurality of driving electrodes provided in the sensor electrode layer 150, receives a touch detection signal from each of a plurality of touch nodes through a plurality of sensing electrodes, and responds to the touch detection signal. Based on this, the change in charge of mutual capacitance can be detected.

That is, the touch driving circuit 400 can determine whether the user has touched the device and whether the user is in proximity, etc., according to the touch detection signal of each of the plurality of touch nodes. The user's touch refers to direct contact of an object, such as the user's finger or a pen, to the front of the display device 10. The user's proximity refers to the positioning of an object, such as the user's finger or pen, away from the front of the display device 10, such as hovering.

Referring to FIG. 4, the sub-area SBA includes a bending area BA that is deformed into a bent shape, and a first sub-area SB1 and a second sub-area SB2 adjoining both sides of the bending area BA. It can be included.

The first sub-area SB1 is an area disposed between the main area MA and the bending area BA. One side of the first sub-area SB1 may be in contact with the non-display area NDA of the main area MA, and the other side of the first sub-area SB1 may be in contact with the bending area BA.

The second sub-area SB2 is spaced apart from the main area MA with the bending area BA in between, and is an area disposed on the lower surface of the substrate 110 by the bending area BA deformed into a bent shape. That is, the second sub-area SB2 may overlap the main area MA in the thickness direction DR3 of the substrate SUB due to the bending area BA transformed into a bent shape.

One side of the second sub-area SB2 may be in contact with the bending area BA. The other side of the second sub-region SB2 may contact a portion of the edge of the substrate 110 .

Signal pads SPD and the display driving circuit 200 may be disposed in the second sub-area SB2.

The display driving circuit 200 may generate signals and voltages for driving the pixel drivers PD in the display area DPA.

The display driving circuit 200 is provided as an integrated circuit (IC) and is formed using a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method in the second sub region (SB2) of the substrate 110. ), but is not limited to this. For example, the display driving circuit 200 may be attached to the circuit board 300 using a chip on film (COF) method.

The circuit board 300 may be attached and electrically connected to the signal pads SPD of the second sub-region SB2 using a low-resistance, high-reliability material such as an anisotropic conductive film or SAP.

The pixel drivers PD in the display area DPA and the display driving circuit 200 may receive digital video data, timing signals, and driving voltages from the circuit board 300 .

The circuit board 300 may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

The non-display area (NDA) includes a demux area (DMXA) disposed between the display area (DA) and the sub-area (SBA).

Additionally, the non-display area NDA may further include a scan driving circuit area SCDA disposed adjacent to at least one side of the display area DA in the first direction DR1.

The circuit array layer 120 may include a scan driving circuit (not shown) corresponding to the scan driving circuit area (SCDA). The scan driving circuit may supply each scan signal to scan lines disposed in the display area DA and extending in the first direction DR1.

As an example, the display driving circuit 200 or the circuit board 300 may supply a scan control signal to the scan driving circuit based on digital video data and timing signals.

Additionally, the circuit board 300 may supply a predetermined constant voltage for generating a scan signal to the scan driving circuit.

FIG. 4 illustrates a case where the scan driving circuit area SCDA is a partial area adjacent to both sides of the display area DA in the first direction DR1 among the non-display area NDA, but this is only an example. That is, although not separately shown, the scan driving circuit area SCDA may be a portion of the non-display area NDA adjacent to one side of the display area DA in the first direction DR1, and the display area DA It may also be provided as partition areas that overlap parts of .

The demux area (DMXA) is a part of the non-display area (NDA) adjacent to the sub area (SBA). In the demux area DMXA, demux circuit units (DMC in FIG. 5) connected between the data lines DL of the display area DA and the display driving circuit 200 are disposed.

Each of the demux circuit units (DMCs) outputs two or more data signals based on one data driving signal.

That is, one of the demux circuit units (DMCs) receives one data driving signal from the display driving circuit 200 as an input terminal and time divides (TIME DEMULTIPLEXING) one data driving signal into two. More than one data signal can be generated, and two or more data signals can be output for different periods through two or more output terminals each connected to two or more data lines DL.

The demux area DMXA includes a central first demux area DMXA1 adjacent to the sub-area SBA and a second demux area adjoining both sides of the first demux area DMXA1 in the first direction DR1. (DMXA2) may be included.

The display area (GA) may include a demultiplexed area (DAA) adjacent to the demultiplexed area (DMXA) and a general area (GA) excluding the demultiplexed adjacent area (DAA). Here, a demux bypass line (DETL in FIG. 5) is disposed in the demux adjacent area (DAA).

The demux adjacent area (DAA) is divided into a center adjacent area (CDAA) adjacent to the first demux area (DMXA1) and the second direction (DR2), and a center adjacent area (CDAA) adjacent to the first demux area (DMXA1) and the second demux area (DMXA2) in the second direction (DR2). It may include an adjacent edge-adjacent area (EDAA).

The center adjacent area (CDAA) is the central portion of the demux adjacent area (DAA).

The edge adjacent area (EDAA) is the part of the demux adjacent area (DAA) between the center adjacent area (CDAA) and the non-display area (NDA).

That is, the center adjacent area CDAA may contact the edge adjacent area EDAA on both sides of the first direction DR1.

The center adjacent area (CDAA) may include a central middle area (MDA) in the first direction DR1, and a side area (SDA) between the middle area (MDA) and the edge adjacent area (EDAA).

That is, the middle area MDA may contact the side area SDA on both sides of the first direction DR1.

FIG. 5 is a layout diagram showing part B of FIG. 4 according to the first embodiment.

Referring to FIG. 5, the display device 10 according to an embodiment includes a main area (MA) including a display area (DA) and a non-display area (NDA), and a sub area protruding from one side of the main area (MA). A substrate 110 including an area SBA, a plurality of pixel drivers PXD disposed on the substrate 110 and each corresponding to a plurality of light emitting areas EA, and a plurality of pixel drivers PXD A circuit array layer 120 including data lines (DL) transmitting data signals, demux circuit units (DMCs) disposed in the demux area (DMXA) of the non-display area (NDA), and the substrate 110. It includes a display driving circuit 200 disposed in the sub-area SBA and supplying data driving signals corresponding to the data lines DL.

The demux circuit units (DMCs) are electrically connected between the display driving circuit 200 and the data lines DL, and are connected to each of the data lines DL based on data driving signals received from the display driving circuit 200. Outputs data signals.

That is, one of the demux circuit units (DMC) is connected to two or more data lines (DL) and outputs two or more data signals based on one data driving signal.

The demux circuit units (DMCs) include a first demux circuit unit (DMC1) disposed in the first demux area (DMXA1) and a second demux circuit unit (DMC2) disposed in the second demux areas (DMXA2). do.

The circuit array layer 120 includes a first data input line (DIPL1) connected to the input terminal of the first demux circuit portion (DMC1), and a second data input line (DIPL2) connected to the input terminal of the second demux circuit portion (DMC2). ) further includes.

The first data input line DIPL1 extends from the sub-area SBA to the first demux area DMXA1.

The second data input wire (DIPL2) is a main input wire (MIPL) extending from the sub area (SBA) to the first demux area (DMXA1), disposed in the display area (DA) and connected to the main input wire (MIPL). A demux bypass line (DETL) and a bypass additional line (DEAL) disposed in the second demux areas (DMXA2) and connected between the demux bypass line (DETL) and the input terminal of the second demux circuit unit (DMC2). Includes.

That is, the second data input line DIPL2 is bypassed to the first demux area DMXA1 and the display area DA by the main input line MIPL and the demux bypass line DETL, thereby bypassing the sub area SBA. ) does not extend to the second demux area (DMXA2). Accordingly, since the second data input line DIPL2 is not arranged in the second demux area DMXA2, the width of the second demux area DMXA2, which is bent along the edge of the substrate, may be reduced.

The circuit array layer 120 is disposed in the second sub-region SB2 and includes a first data supply line DSPL1 and a second data supply line DSPL2, respectively connected to the output terminals of the display driving circuit 200. A first data bending line (DBDL1) connected to the data supply line (DSPL1) and disposed in the bending area (BA), a second data bending line connected to the second data supply line (DSPL2) and disposed in the bending area (BA) (DBDL2) may be further included. The first data input line DIPL1 may connect between the first data bending line DBDL1 and the input terminal of the first demux circuit unit DMC1. The second data input line DIPL2 may connect between the second data input line DBDL2 and the input terminal of the second demux circuit unit DMC2.

The demux bypass line DETL of the second data input line DIPL2 may be disposed in the demux adjacent area DAA of the display area DA.

That is, the demux bypass line (DETL) is disposed in the center adjacent area (CDAA), is connected to the main input line (MIPL), and extends in the second direction (DR2), including a first bypass line (DETL1) and a first bypass line ( a second bypass line (DETL2) connected to DETL1) and extending in the first direction (DR1), and disposed in the edge adjacent area (EDAA) and extending in the second direction (DR2) toward the second demux areas (DMXA2) and may include a third bypass wiring (DETL3) connecting the second bypass wiring (DETL2) and the additional bypass wiring (DEAL).

In this way, the second data input line DIPL2 between the second demux circuit unit DMC2 and the second data bending line DBDL2 is directly connected from the first sub-area SB1 to the second demux area DMXA2. Rather than extending, it bypasses the first sub-area SB1 to the first demux area DMXA1 and the display area DA and extends to the second demux areas DMXA2.

On the other hand, the first data input line DIPL1 between the first demux circuit unit DMC1 and the first data bending line DBDL1 extends from the first sub-area SB1 to the first demux area DMXA1.

The data lines DL may extend in the second direction DR2.

The data lines DL include a first data line DL1 and a second data line DL2 connected to the first demux circuit portion DMC1 and disposed in the center adjacent area CDAA, and a second demux circuit portion DMC2. ) and may include a third data line (DL3) and a fourth data line (DL4) connected to the edge adjacent area (EDAA).

Among the demultiplexed adjacent areas (DAA) of the display area (DA), the center adjacent area (CDAA) is located between the center middle area (MDA) and the middle area (MDA) and the edge adjacent area (EDAA) in the first direction (DR1). It may include a side area (SDA). That is, both sides of the middle area MDA in the first direction DR1 may contact the side area SDA.

The first bypass line (DETL1) is not disposed in the middle area (MDA).

That is, the main input line (MIPL) of the second data input line (DIPL2) is disposed in a part of the first demux area (DMXA) adjacent to the side area (SDA), and the main input line (MIPL) of the second data input line (DIPL2) is disposed in the other part adjacent to the middle area (MDA). 2 The main input wire (MIPL) of the data input wire (DIPL2) is not placed.

In other words, the first demux circuit unit (DMC1) is disposed only in a portion of the first demux area (DMXA1) adjacent to the side area (SDA), and the demux circuit units (DMCs) are located in the first demux area (DMXA1). It may further include a third demux circuit unit (DMC3) disposed in another part adjacent to the middle area (MDA).

The data lines DL may further include a fifth data line DL5 disposed in the middle area MDA and connected to the third demux circuit unit DMC3.

Unlike the side area (SDA), the first bypass line (DETL1) is not disposed in the middle area (MDA), so two or more fifth data disposed in the middle area (MDA) and connected to the third demux circuit unit (DMC3) The wires D5 may be disposed adjacent to the second power auxiliary wire VSAL.

The circuit array layer 120 is disposed in the non-display area (NDA) and has a first power supply line (VDSPL) that transmits the first power and the second power for driving the light emitting elements (LEL) of the light emitting array layer 130, respectively. ) and a second power supply wiring (VSSPL).

In addition, the circuit array layer 120 further includes a second power auxiliary line (VSAL) disposed in the display area (DA), extending in the second direction (DR2), and electrically connected to the second power supply line (VSSPL). can do.

The first power supply line VDSPL extends from the first sub-area SB1 to the non-display area NDA and may be arranged to surround the display area DA.

The second power supply line (VSSPL) extends from the first sub-area (SB1) to the non-display area (NDA) and may be arranged to surround the first power supply line (VDSPL).

The circuit array layer 120 may further include data output lines (DMOL) disposed in the demultiplex area (DMXA) and respectively connecting output terminals of the demultiplexer circuits (DMCs) and the data lines (DL).

The output terminals of the first demux circuit unit (DMC1) disposed in the first demux area (DMXA1) are disposed in the center adjacent area (CDAA) and are connected to the first and second data lines (DL1) and DL2 that are adjacent to each other. You can.

The first bypass line (DETL1) of the second data input line (DIPL2) is disposed in the center adjacent area (CDAA) and extends in the second direction (DR2), so that the first data line (DL1) and the second data line (DL2) ) may be placed adjacent to any one of the following.

In other words, one of the first data line DL1 and the second data line DL2 connected to the first demux circuit unit DMC1 (for example, the first data line DL1) is the first bypass line. It can be placed adjacent to (DETL1).

And, of the first data line DL1 and the second data line DL2 connected to the first demux circuit unit DMC1, except for one adjacent to the first bypass line DETL1 (i.e., the second data line ( DL2)) may be disposed adjacent to the second power auxiliary line (VSAL).

The output terminals of the second demux circuit unit DMC2 disposed in the second demux areas DMXA2 are disposed in the edge adjacent area EDAA and are connected to the third data line DL3 and the fourth data line DL4 adjacent to each other. can be connected

The third bypass line (DETL3) of the second data input line (DIPL2) is disposed in the edge adjacent area (EDAA) and extends in the second direction (DR2), so that the third data line (DL3) and the fourth data line (DL4) ) can be placed adjacent to any one of the following.

In other words, one of the third data line DL3 and the fourth data line DL4 connected to the second demux circuit unit DMC2 (for example, the third data line DL3) is a third bypass line. It can be placed adjacent to (DETL3).

And, among the third data line DL3 and the fourth data line DL4 connected to the second demux circuit unit DMC2, all but one adjacent to the third bypass line DETL3 (i.e., the fourth data line ( DL4)) may be disposed adjacent to the second power auxiliary line (VSAL).

According to the first embodiment, the circuit array layer 120 is disposed in the display area DA, extends in the first direction DR1, and is electrically connected to the first power supply line VDSPL. VDAL) may further be included.

In addition, the circuit array layer 120 is disposed in the general area GA of the display area DA, extends in the first direction DR1, and is electrically connected to the second power supply line VSSPL. (VSSBL) may be further included.

The second bypass line DETL2 is disposed in the demultiplex adjacent area DAA and extends in the first direction DR1.

Accordingly, the first power auxiliary wiring (VDAL) is disposed adjacent to the second bypass wiring (DETL2) in the demultiplex adjacent area (DAA) and adjacent to the second power sub-wiring (VSSBL) in the general area (GA). can be placed.

That is, in the demux adjacent area DAA, the first power auxiliary line VDAL and the second bypass line DETL2 may be arranged to alternate with each other in the second direction DR2.

Also, in the general area GA, the first power auxiliary line VDAL and the second power sub line VSSBL may be arranged to alternate with each other in the second direction DR2.

The circuit array layer 120 is spaced side by side on one side of the second direction DR2 of the first bypass wiring DETL1 and one side of the second direction DR2 of the third bypass wiring DETL3, and is spaced in the second direction ( first dummy wires DML1 extending in DR2), and second dummy wires spaced apart from each other in parallel on both sides of the second bypass wire DETL2 in the first direction DR1 and extending in the first direction DR1 (DML2) may further be included.

In addition to these first dummy wires (DML1) and second dummy wires (DML2), the second power auxiliary wire (VSAL), the first power auxiliary wire (VDAL), and the second power sub-wire (VSSBL), The demux bypass wiring (DETL: DETL1, DETL2, DETL3) disposed only in a portion of the display area (DA) can be prevented from being clearly visible.

A portion of each of the first power supply line (VDSPL) and the second power supply line (VSSPL) may overlap with the demux circuit units (DMC).

That is, not only the demux circuit units (DMCs) are disposed in the demux area (DMXA), but also a portion of each of the first power supply line (VDSPL) and the second power supply line (VSSPL) are further disposed.

In this way, the width of the non-display area (NDA) can be prevented from increasing by the width of the demux area (DMXA). As a result, the extent to which the width of the non-display area (NDA) increases due to the arrangement of the demultiplexing area (DMXA) can be relatively small, which can be advantageous in reducing the width of the non-display area (NDA).

According to the first embodiment, the circuit array layer 120 includes a first power bending line (VDBDL) and a second power supply line (VSSPL) connected to the first power supply line (VDSPL) and disposed in the bending area (BA). A second power bending line (VSBDL) connected to and disposed in the bending area (BA), a first power pad line (VDPDL) connected to the first power bending line (VDBDL) and disposed in the second sub-area (SB2), and a second power pad wire (VSPDL) connected to the second power bending wire (VSBDL) and disposed in the second sub-region (SB2).

Although not shown in detail, the first power pad wire (VDPDL) and the second power pad wire (VSPDL) may be connected to different signal pads (SPD).

As described above, the display device 10 according to the first embodiment includes demux circuit units (DMCs) connected between the display driving circuit 200 and the data lines DL. Accordingly, the output terminals of the display driving circuit 200 are not directly connected to the data lines DL, but are connected to fewer demux circuit units (DMCs) than the data lines DL.

That is, the number of first and second data supply wires (DSPL1, DSPL2) connected to the display driving circuit 200, and the first and second data connected to the first and second data supply wires (DSPL1, DSPL2) The number of bending wires (DBDL1, DBDL2), the number of first and second data input wires (DIPL1, DIPL2) connected to the first and second data bending wires (DBDL1, DBDL2), and the demux circuit unit (DMC) The number may be smaller than the number of data lines DL in inverse proportion to the number of demux transistors included in each demux circuit unit (DMC).

Therefore, as the number of first and second data supply lines (DSPL1, DSPL2) disposed in the second sub-area (SB2) is reduced, the gap between the first and second data supply lines (DSPL1, DSPL2) is widened. Alternatively, the width of the second sub-area SB2 may be reduced.

As the number of first and second data bending lines DBDL1 and DBDL2 disposed in the bending area BA is reduced, the gap between the first and second data bending lines DBDL1 and DBDL2 may be widened, or Alternatively, the width of the bending area BA may be reduced.

That is, the spacing between wires arranged in the sub-area SBA can be widened without reducing the number of data wires DL, which affects resolution.

In addition, the second data input lines DIPL2 connected to the second demux circuit units DMC2 disposed in the second demux areas DMXA2 are connected to the second demux area DMXA2 in the first sub-area SB1. ), but instead extends from the first sub-area SB1 to the first demux area DMXA1 and the display area DA and extends to the second demux area DMXA2.

Accordingly, the area allocated to the arrangement of the second data input lines DIPL2 among the second demux areas DMXA2 where the second demux circuit units DMC2 are disposed may be reduced. That is, since the width of the second demux areas DMXA2 corresponding to the corners of the main area MA can be reduced, it can be advantageous to reduce the width of the non-display area NDA.

FIG. 6 is an equivalent circuit diagram showing an example of the pixel driver of FIG. 5. FIG. 7 is an equivalent circuit diagram showing another example of the pixel driver of FIG. 5.

The circuit array layer 120 includes a plurality of pixel drivers PDX, each corresponding to a plurality of light emitting areas EA. The plurality of pixel drivers PDX each supply driving current to the plurality of light emitting elements LEL provided in the light emitting array layer 130.

Each of the plurality of pixel drivers PDX may include a driving transistor DT, at least one switch element, and at least one capacitor.

Referring to FIG. 6, one of the plurality of pixel drivers (PDX) provided in the circuit array layer 120 includes a driving transistor (DT), a first transistor (ST1: Switch Transistor), and a second transistor (ST2). , switch elements of the third transistor (ST3), fourth transistor (ST4), fifth transistor (ST5), and sixth transistor (ST6), and a capacitor (C1).

In addition, the scan wires of the circuit array layer 120 connected to the scan drive circuit of the scan drive circuit area SCDA are write scan wires connected to the gate electrodes of each of the first transistor ST1 and the second transistor ST2. GWL), an initialization scan line (GIL) connected to the gate electrode of the third transistor (ST3), a control scan line (GCL) connected to the gate electrode of the fourth transistor (ST4), and the fifth transistor (ST5) and the It may include an emission control line (ECL) connected to the gate electrode of each of the six transistors (ST6).

The driving transistor DT is connected in series with the light emitting element LEL between the first power line VDL and the second power line VSL.

The first electrode of the driving transistor DT may be connected to the first power line VDL through the fifth transistor ST5.

Additionally, the first electrode of the driving transistor DT may be connected to the data line DL through the second transistor ST2.

The second electrode of the driving transistor DT may be connected to the light emitting element LEL through the sixth transistor ST6.

The capacitor C1 is connected between the first power line VDL and the gate electrode of the driving transistor DT. That is, the gate electrode of the driving transistor DT may be connected to the first power line VDL through the capacitor C1.

Accordingly, when the data signal of the data line DL is applied to the first electrode of the driving transistor DT, the driving transistor DT generates a drain-source current corresponding to the data signal. The current between the drain and source of the driving transistor (DT) is supplied as the driving current of the light emitting element (LEL).

The light emitting element (LEL) emits light with a brightness corresponding to the driving current by the driving transistor (DT).

The light emitting element (LEL) includes an anode electrode (AND in Figure 10) and a cathode electrode (CTD in Figure 10) facing each other, and a light emitting layer (EML in Figure 10) between the anode electrode (AND) and the cathode electrode (CTD). can do.

As an example, the light emitting element (LEL) may be an organic light emitting diode having a light emitting layer made of an organic light emitting material. Alternatively, the light emitting device (LEL) may be an inorganic light emitting device having a light emitting layer made of an inorganic semiconductor. Alternatively, the light emitting device (LEL) may be a quantum dot light emitting device having a quantum dot light emitting layer. Alternatively, the light emitting element (LEL) may be a micro light emitting diode.

The capacitor (Cel) connected in parallel with the light emitting element (LEL) is a parasitic capacitance between the anode and cathode electrodes.

The first transistor ST1 is connected between the gate electrode of the driving transistor DT and the second electrode of the driving transistor DT.

The second transistor ST2 is connected between the first electrode of the driving transistor DT and the data line DL.

The gate electrodes of each of the first transistor (ST1) and the second transistor (ST2) are connected to the write scan line (GWL).

When a write scan signal is supplied through the write scan line (GWL), the first transistor (ST1) and the second transistor (ST2) are turned on, and the gate electrode of the driving transistor (DT) is turned on through the turned-on first transistor (ST1). and the second electrode are at the same potential. Then, the data signal of the data line DL is supplied to the first electrode of the driving transistor DT through the turned-on second transistor ST2.

At this time, when the voltage difference between the first electrode and the gate electrode of the driving transistor (DT) becomes greater than the threshold voltage, the driving transistor (DT) turns on to generate a drain-source current between the first and second electrodes of the driving transistor (DT). may occur.

The third transistor ST3 is connected between the gate electrode of the driving transistor DT and the gate initialization voltage line VGIL. The gate electrode of the third transistor ST3 is connected to the initialization scan line GIL.

When an initialization scan signal is supplied through the initialization scan line (GIL), the third transistor (ST3) is turned on. At this time, the gate electrode of the driving transistor DT is connected to the gate initialization voltage line VGIL through the turned-on third transistor ST3, so that the potential of the gate electrode of the driving transistor DT is equal to the gate initialization voltage line VGIL. It is initialized to the first initialization voltage of .

The fourth transistor ST4 is connected between the anode electrode of the light emitting element LEL and the anode initialization voltage line VAIL. The gate electrode of the fourth transistor ST4 is connected to the control scan line GCL.

When the control scan signal is supplied through the control scan line (GCL), the fourth transistor (ST4) is turned on. At this time, the anode electrode of the light emitting device (LEL) is connected to the anode initialization voltage line (VAIL) through the turned-on fourth transistor (ST4), so that the potential of the anode electrode of the light emitting device (LEL) is equal to the anode initialization voltage line (VAIL). It is initialized with the second initialization voltage of .

The fifth transistor ST5 is connected between the first electrode of the driving transistor DT and the first power line VDL.

The sixth transistor ST6 is connected between the second electrode of the driving transistor DT and the anode electrode of the light emitting element LEL.

The gate electrodes of each of the fifth transistor (ST5) and sixth transistor (ST6) are connected to the emission control line (ECL).

When a light emission control signal is supplied through the light emission control line (ECL), the driving transistor (DT) and the light emitting element (LEL) are connected in series between the first power line (VDL) and the second power line (VSL), thereby emitting light. The element LEL emits light based on the driving current by the driving transistor DT.

As shown in FIG. 6, the driving transistor DT and at least one switch element ST1 to 6 provided in the pixel driver PXD may all be provided as P-type MOSFETs.

In this case, all scan wires (GWL, GIL, GCL, ECL) can supply a low-level turn-on signal.

Alternatively, unlike the illustration in FIG. 6, some of the driving transistor DT and at least one switch element ST1 to 6 provided in the pixel driver PXD are P-type MOSFETs, and the remaining portions are N-type MOSFETs. It can be prepared with MOSFET. In this way, the switching elements provided as P-type MOSFETs and the switching elements provided as N-type MOSFETs may include active layers of different semiconductor materials. Therefore, the width of the pixel driver (PXD) can be reduced through the stacked structure, which can be advantageous in improving resolution.

For example, as shown in FIG. 7, the pixel driver PXD of another example includes a driving transistor DT and at least one switch element ST1 to 6, of which the driving transistor DT, The second transistor (ST2), the fourth transistor (ST4), the fifth transistor (ST5), and the sixth transistor (ST6) are provided as P-type MOSFETs with an active layer of polysilicon semiconductor material, and the first transistor (ST1) and the third transistor ST3 may be prepared as an N-type MOSFET with an active layer of an oxide semiconductor material.

In this case, unlike the second transistor ST2, the first transistor ST1 is turned on by a high-level turn-on signal, so the gate electrode of the first transistor ST1 is not the write scan line GWL, but a separate It may be connected to an additional write scan line (GWL').

Alternatively, although not separately shown, according to another example, not only the first transistor (ST1) and the third transistor (ST3) among the switch elements (ST1 to 6), but also the fourth transistor (ST4) is provided as an N-type MOSFET. It can be. In this case, the control scan line (GCL) can transmit a high-level turn-on signal.

FIG. 8 is a plan view showing an example of a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer among two neighboring pixel drivers of FIG. 5 . Figure 9 is a plan view showing an example of two adjacent pixel drivers. FIG. 10 is a cross-sectional view showing an example of a surface cut along line G-G' of FIGS. 8 and 9.

First, referring to FIG. 10, the circuit array layer 120 of the display device 10 according to one embodiment includes a semiconductor layer (SEL in FIG. 8) on the substrate 110 and a first gate covering the semiconductor layer (SEL). A first conductive layer (CDL1 in FIG. 8) on the insulating layer (122 in FIG. 10), and a second conductive layer (CDL2 in FIG. 8) on the second gate insulating layer (123 in FIG. 10) covering the first conductive layer (CDL1). ), a third conductive layer (CDL3 in FIG. 8) on the interlayer insulating layer (124 in FIG. 10) covering the second conductive layer (CDL2), and a first planarization layer (125 in FIG. 10) covering the third conductive layer (CDL3). ) on the fourth conductive layer (CDL4 in FIG. 9), the fifth conductive layer (CDL5) on the second planarization layer (126 in FIG. 10) covering the fourth conductive layer (CDL4), and the fifth conductive layer (CDL5) It may be provided with a structure including a third planarization layer (127 in FIG. 10) covering it.

And, the light emitting array layer 130 may be disposed on the third planarization layer 127.

FIG. 8 shows a semiconductor layer (SEL), a first conductive layer (CDL1), a second conductive layer (CDL2), and a third conductive layer (CDL3) of the pixel driver (PXD) according to the equivalent circuit diagram of FIG. 6. 9 shows the fourth conductive layer CDL4 and the fifth conductive layer CDL5 of the pixel driver PXD according to the equivalent circuit diagram of FIG. 6, along with FIG. 8.

Referring to FIG. 8, the semiconductor layer (SEL) is a driving transistor (DT) and the channel portions (CHDT, CH1-1, CH1-2, CH2, CH3-1, CH3-2, CH4, CH5, CH6), source electrodes (SDT, S1-1, S1-2, S2, S3-1, S3-2, S4, S5, S6) and drain electrodes (DDT, D1-1, D1-2, D2, D3-1, D3-2, D4, D5, D6).

The first conductive layer (CDL1) is a gate electrode (GDT, G1-1, G1-2, G2, G3-1, G3-2, G4, G5, G6) may be included.

And, the first conductive layer (CDL1) is the gate electrode (GDT, G1-1, G1-2, G2, G3-1, G3-2, G4, G5, G6) of the first to sixth transistors (ST1 to 6). ), that is, a write scan line (GWL), an initialization scan line (GIL), an emission control line (ECL), and a control scan line (GCL) connected to the line. The write scan line (GWL), the initialization scan line (GIL), the emission control line (ECL), and the control scan line (GCL) extend in the first direction DR1.

The second conductive layer (CDL2) is connected to the drain electrode (D3-2) of the third transistor (ST3), the gate initialization voltage line (VGIL) that transmits the first initialization voltage, and the drain electrode of the fourth transistor (ST4). It may include an anode initialization voltage line (VAIL) connected to (D4) and transmitting a second initialization voltage. The gate initialization voltage line VGIL and the anode initialization voltage line VAIL may extend in the first direction DR1.

The first power line (VDL) may include a first power horizontal auxiliary line (VDSBL1) extending in the first direction (DR1) and a second power vertical auxiliary line (VDSBL2) extending in the second direction (DR2). there is.

The second conductive layer (CDL2) may further include a first power horizontal auxiliary line (VDSBL1).

The third conductive layer (CDL3) may include a second power vertical auxiliary line (VDSBL2).

The third conductive layer (CDL3) may further include a gate initialization voltage auxiliary line (VGIAL) and an anode initialization voltage auxiliary line (VAIAL).

The gate initialization voltage auxiliary line (VGIAL) is electrically connected to the gate initialization voltage line (VGIL) and may extend in the second direction (DR2).

The anode initialization voltage auxiliary wiring (VAIAL) may be electrically connected to the anode initialization voltage wiring (VAIL) and extend in the second direction (DR2).

The first power vertical auxiliary wiring (VDSBL2) may be electrically connected to the first power horizontal auxiliary wiring (VDSBL1).

Specifically, the driving transistor (DT) includes a channel part (CHDT), a source electrode (SDT) and a drain electrode (DDT) connected to both sides of the channel part (CHDT), and a gate electrode (DTG) overlapping the channel part (CHDT). may include.

The source electrode (SDT) of the driving transistor (DT) may be connected to the drain electrode (D2) of the second transistor (ST2) and the drain electrode (D5) of the fifth transistor (ST5).

The drain electrode (DDT) of the driving transistor (DT) may be connected to the source electrode (S1-1) of the 1-1 transistor (ST1-1) and the source electrode (S6) of the sixth transistor (ST6).

The channel portion (CHDT), source electrode (SDT), and drain electrode (DDT) of the driving transistor (DT) may be made of a semiconductor layer (SEL). The source electrode (SDT) and drain electrode (DDT) may be formed of a portion of the semiconductor layer (SEL) made conductive by doping ions or impurities into a semiconductor material.

The gate electrode (GDT) of the driving transistor (DT) may be provided with the first conductive layer (CDL1).

The first transistor ST1 may include a 1-1 transistor ST1-1 and a 1-2 transistor ST1-2 that are connected in series.

The 1-1 transistor (ST1-1) includes a channel portion (CH1-1), a source electrode (S1-1) and a drain electrode (D1-1) connected to both sides of the channel portion (CH1-1), and a channel portion ( It may include a gate electrode (G1-1) that overlaps CH1-1) and is formed as part of the write scan line (GWL).

The source electrode (S1-1) of the 1-1 transistor (ST1-1) may be connected to the drain electrode (DDT) of the driving transistor (DT).

The drain electrode D1-1 of the 1-1 transistor ST1-1 may be connected to the source electrode S1-2 of the 1-2 transistor ST1-2.

The 1-2 transistor (ST1-2) includes a channel unit (CH1-2), a source electrode (S1-2) and a drain electrode (D1-2) connected to both sides of the channel unit (CH1-2), and a channel unit. It may include a gate electrode (G1-2) that overlaps (CH1-2) and consists of a protrusion of the write scan line (GWL).

The source electrode (S1-2) of the 1-2 transistor (ST1-2) may be connected to the drain electrode (D1-1) of the 1-1 transistor (ST1-1).

The drain electrode (D1-2) of the 1-2 transistor (ST1-2) may be connected to the source electrode (S3-1) of the 3-1 transistor (ST3-1).

The channel portion (CH1-1), the source electrode (S1-1), and the drain electrode (D1-1) of the 1-1 transistor (ST1-1), and the channel portion ( CH1-2), the source electrode (S1-2), and the drain electrode (D1-2) may be provided as a semiconductor layer (SEL). The source electrodes (S1-1, S1-2) and drain electrodes (D1-1, D1-2) of each of the 1-1 transistor (ST1-1) and the 1-2 transistor (ST1-2) are formed by a semiconductor layer ( Among SELs, it may be made up of a part that is made conductive by doping ions or impurities into a semiconductor material.

The gate electrodes (G1-1, G1-2) of each of the 1-1 transistor (ST1-1) and the 1-2 transistor (ST1-2) are connected to the write scan line (GWL) provided with the first conductive layer (CDL1). Each may be made up of different parts of .

The gate electrode (DTG) of the driving transistor (DT) is connected to the first connection electrode (CE1) through the first contact hole (CT1), and the first connection electrode (CE1) is connected to the first connection electrode (CE1) through the second contact hole (CT2). 1-2 It can be connected to the drain electrode (D1-2) of the transistor (ST1-2).

The first connection electrode (CE1) may be made of a third conductive layer (CDL3).

The second transistor (ST2) overlaps the channel portion (CH2), the source electrode (S2) and drain electrode (D2) connected to both sides of the channel portion (CH2), and the channel portion (CH2) and writes scan wiring (GWL). It may include a gate electrode (G2) made of another part of.

The source electrode S2 of the second transistor ST2 may be connected to the second connection electrode CE2 through the fourth contact hole CT4.

The drain electrode D2 of the second transistor ST2 may be connected to the source electrode SDT of the driving transistor DT and the drain electrode D5 of the fifth transistor ST5.

The channel portion (CH2), source electrode (S2), and drain electrode (D2) of the second transistor (ST2) may be made of a semiconductor layer (SEL). The source electrode S2 and the drain electrode D2 may be formed of a portion of the semiconductor layer SEL made conductive by doping ions or impurities into a semiconductor material.

The gate electrode G2 of the second transistor ST2 may be formed as a part of the write scan line GWL provided with the first conductive layer CDL1.

The second connection electrode (CE2) may be formed of the third conductive layer (CDL3).

The third transistor ST3 may include a 3-1 transistor (ST3-1) and a 3-2 transistor (ST3-2) connected in series with each other.

The 3-1 transistor (ST3) includes a channel portion (CH3-1), a source electrode (S3-1) and a drain electrode (D3-1) connected to both sides of the channel portion (CH3-1), and a channel portion (CH3-1). It may include a gate electrode (G3-1) overlapping with 1).

The source electrode (S3-1) of the 3-1 transistor (ST3-1) may be connected to the drain electrode (D1-2) of the 1-2 transistor (ST1-2).

The drain electrode (D3-1) of the 3-1 transistor (ST3-1) may be connected to the source electrode (S3-2) of the 3-2 transistor (ST3-2).

The 3-2 transistor (ST3-2) includes a channel unit (CH3-2), a source electrode (S3-2) and a drain electrode (D3-2) connected to both sides of the channel unit (CH3-2), and a channel unit. It may include a gate electrode (G3-2) overlapping with (CH3-2).

The drain electrode (D3-2) of the 3-2 transistor (ST3-2) may be connected to the gate initialization auxiliary wiring (VGIAL) through the second initialization contact hole (VICH2).

The channel portion (CH3-1), the source electrode (S3-1), and the drain electrode (D3-1) of the 3-1 transistor (ST3-1), and the channel portion ( CH3-2), the source electrode (S3-2), and the drain electrode (D3-2) may be made of a semiconductor layer (SEL). The source electrodes (S3-1, S3-2) and drain electrodes (D3-1, D3-2) of each of the 3-1 transistor (ST3-1) and the 3-2 transistor (ST3-2) are formed by a semiconductor layer ( Among SELs, it may be made up of a part that is made conductive by doping ions or impurities into a semiconductor material.

The gate electrodes (G3-1, G3-2) of each of the 3-1 transistor (ST3-1) and the 3-2 transistor (ST3-2) are connected to an initialization scan line (GIL) formed of the first conductive layer (CDL1). Each may be made up of different parts of .

The circuit array layer 120 may further include a shielding electrode (SHE) overlapping at least a portion of the source electrode (S3-1) of the 3-2 transistor (ST3-2).

The shielding electrode (SHE) may be provided as a second conductive layer (CDL2).

The shielding electrode (SHE) may be connected to the first power vertical auxiliary wiring (VDSBL2) through the third contact hole (CT3).

The shielding electrode (SHE) may further overlap a portion of the drain electrode (D1-1) of the 1-1 transistor (ST1-1).

The first power vertical auxiliary wiring (VDSBL2) may be connected to the first power horizontal auxiliary wiring (VDSBL1) through the fifth contact hole (CT5).

The fourth transistor (ST4) overlaps the channel portion (CH4), the source electrode (S4) and drain electrode (D4) connected to both sides of the channel portion (CH4), and the channel portion (CH4) and the control scan line (GCL). It may include a gate electrode (G4) made up of a portion of.

The source electrode S4 of the fourth transistor ST4 may be connected to the drain electrode D6 of the sixth transistor ST6.

The drain electrode D4 of the fourth transistor ST4 may be connected to the anode initialization auxiliary wiring VAIAL through the fourth initialization contact hole VACH2.

The channel portion (CH4), source electrode (S4), and drain electrode (D4) of the fourth transistor (ST4) may be made of a semiconductor layer (SEL). The source electrode S4 and the drain electrode D4 may be formed of a portion of the semiconductor layer SEL made conductive by doping ions or impurities into a semiconductor material.

The gate electrode (G4) of the fourth transistor (ST4) may be formed as a part of the control scan line (GCL) provided with the first conductive layer (CDL1).

The fifth transistor (ST5) overlaps the channel portion (CH5), the source electrode (S5) and drain electrode (D5) connected to both sides of the channel portion (CH5), and the channel portion (CH5) and has an emission control line (ECL). It may include a gate electrode (G5) made up of a portion of.

The source electrode S5 of the fifth transistor ST5 may be connected to the first power vertical auxiliary line VDSBL2 through the sixth contact hole CT6.

The drain electrode D5 of the fifth transistor ST5 may be connected to the source electrode SDT of the driving transistor DT.

The sixth transistor (ST6) overlaps the channel portion (CH6), the source electrode (S6) and drain electrode (D6) connected to both sides of the channel portion (CH6), and the channel portion (CH6) and has an emission control line (ECL). It may include a gate electrode (G6) made up of another part of.

The source electrode S6 of the sixth transistor ST6 may be connected to the drain electrode DDT of the driving transistor DT.

The drain electrode D6 of the sixth transistor ST6 is connected to the source electrode S4 of the fourth transistor ST4 and can be connected to the third connection electrode CE3 through the seventh contact hole CT7.

The third connection electrode (CE3) may be made of a third conductive layer (CDL3).

The channel portion (CH5), source electrode (S5), and drain electrode (D5) of the fifth transistor (ST4) may be made of a semiconductor layer (SEL). The source electrode S5 and the drain electrode D5 may be formed of a portion of the semiconductor layer SEL made conductive by doping ions or impurities into a semiconductor material.

The channel portion (CH6), source electrode (S6), and drain electrode (D6) of the sixth transistor (ST6) may be made of a semiconductor layer (SEL). The source electrode S6 and the drain electrode D6 may be formed of a portion of the semiconductor layer SEL made conductive by doping ions or impurities into a semiconductor material.

The gate electrodes G5 and G6 of each of the fifth transistor ST5 and ST6 may be formed as different parts of the emission control line ECL formed of the first conductive layer CDL1.

The capacitor C1 may be provided by overlapping the first capacitor electrode CAE1 and the second capacitor electrode CAE2.

Here, the first capacitor electrode CAE1 may be formed as a part of the gate electrode GDT of the driving transistor DT provided with the first conductive layer CDL1.

The second capacitor electrode CAE2 may be formed as a part of the first power horizontal auxiliary line VDSBL1 provided with the second conductive layer CDL2.

The second connection electrode CE2 is connected to the source electrode S2 of the second transistor ST2 through the fourth contact hole CT4.

Referring to FIG. 9, the second bypass line (DETL2), the second dummy line (DML2), the first power auxiliary line (VDAL), and the second power sub line (VSSBL) each extend in the first direction (DR1) It may be provided as a fourth conductive layer (CDL4).

And, each of the data wire (DL), the first bypass wire (DETL1), the third bypass wire (DELT3), the first dummy wire (DML1), and the second power auxiliary wire (VSAL) extends in the second direction (DR2). and can be provided as a fifth conductive layer (CDL5).

The fourth connection electrode (CE4) is made of the fourth conductive layer (CDL4) and may be connected to the second connection electrode (CE2) through the tenth contact hole (CT10).

The data line DL formed of the fifth conductive layer CDL5 may be connected to the fourth connection electrode CE4 through the eleventh contact hole CT11.

Accordingly, the source electrode S2 of the second transistor ST2 may be connected to the data line DL through the second connection electrode CE2 and the fourth connection electrode CE4.

The first power auxiliary line VDAL may be electrically connected to the first power vertical auxiliary line VDSBL2 of the third conductive layer CDL3 through the twelfth contact hole CT12.

As shown in FIG. 8, the third connection electrode (CE3) made of the third conductive layer (CDL3) is connected to the source electrode (ST4) of the fourth transistor (ST4) made of the semiconductor layer (SEL) through the seventh contact hole (CT7). S4) and the drain electrode (D6) of the sixth transistor (ST6).

As shown in FIG. 9 , the fifth connection electrode CE5 formed of the fourth conductive layer CDL4 may be connected to the third connection electrode CE3 through the eighth contact hole CT8.

The sixth connection electrode CE6 made of the fifth conductive layer CDL5 may be connected to the fifth connection electrode CE5 through the ninth contact hole CT9.

Accordingly, the sixth connection electrode (CE6) is connected to the source electrode (S4) of the fourth transistor (ST4) and the drain electrode (S4) of the sixth transistor (ST6) through the third connection electrode (CE5) and the fifth connection electrode (CE5). D6) can be connected.

This sixth connection electrode (CE6) may be connected to the anode electrode of the light emitting element (LEL) through an anode contact hole (ANCT in FIG. 10) penetrating the third planarization layer 127.

The first bypass wiring DETL1 in the second direction DR2 provided by the fifth conductive layer CDL5 is the second bypass wiring DETL2 and the first bypass wiring DETL1 in the first direction DR1 provided by the fourth conductive layer CDL4. It can be connected through the bypass connection hole (DETH1).

As shown in FIG. 10, the circuit array layer 120 includes a semiconductor layer (SEL) on the substrate 110, a first conductive layer (CDL1) on the first gate insulating layer 122 covering the semiconductor layer (SEL), and a first conductive layer (CDL1) on the semiconductor layer (SEL). 1 A second conductive layer (CDL2) on the second gate insulating layer 123 covering the conductive layer (CDL1), a third conductive layer (CDL3) on the interlayer insulating layer 124 covering the second conductive layer (CDL2), The fourth conductive layer (CDL4) on the first planarization layer (125) covering the third conductive layer (CDL3), the fifth conductive layer (CDL5) on the second planarization layer (126) covering the fourth conductive layer (CDL4), and the 5 It may include a third planarization layer 127 covering the conductive layer (CDL5).

The circuit array layer 120 may further include a buffer layer 121 disposed between the substrate 110 and the semiconductor layer (SEL).

The buffer layer 121 is intended to protect the circuit array layer 120 and the light emitting array layer 130 from moisture penetrating through the substrate 110, and may be made of at least one inorganic film.

As an example, the buffer layer 121 may be made of a multilayer in which one or more inorganic layers of silicon nitride, silicon oxy nitride, silicon oxide, titanium oxide, and aluminum oxide are alternately stacked.

The semiconductor layer (SEL) is disposed on the buffer layer 121 and may be made of a silicon semiconductor such as polycrystalline silicon, single crystalline silicon, low-temperature polycrystalline silicon, and amorphous silicon.

The semiconductor layer (SEL) is a channel unit (CHDT, CH1-1, CH1-2, CH2, CH3- in FIG. 8) of the driving transistor (DT) and switch elements (ST1 to ST6) provided in the pixel driver (PXD). 1, CH3-2, CH4, CH5, CH6).

In addition, the semiconductor layer (SEL) is the source electrode (SDT, S1-1, S1-2, S2, S3-1, S3-2 in FIG. 8) of the driving transistor (DT) and the switch elements (ST1 to ST6). S4, S5, S6) and drain electrodes (DDT, D1-1, D1-2, D2, D3-1, D3-2, D4, D5, and D6 in FIG. 8).

In the semiconductor layer (SEL), the source electrodes of each of the driving transistor (DT) and switch elements (ST1 to ST6) (SDT, S1-1, S1-2, S2, S3-1, S3-2, S4 in FIG. 8, S5, S6) and some others corresponding to the drain electrodes (DDT, D1-1, D1-2, D2, D3-1, D3-2, D4, D5, D6 in Figure 8) are doped with ions or impurities and are conductive. You can have

On the other hand, the channel portions of each of the driving transistor (DT) and switch elements (ST1 to ST6) in the semiconductor layer (SEL) (CHDT, CH1-1, CH1-2, CH2, CH3-1, CH3-2 in FIG. 8, Some of them corresponding to CH4, CH5, CH6) are not doped by the gate electrode (GDT, G1-1, G1-2, G2, G3-1, G3-2, G4, G5, G6) and are carriers depending on the potential difference. It is possible to maintain the semiconductor properties that create a channel for the movement of .

The first gate insulating layer 122 may be formed of an inorganic film disposed on the buffer layer 121 and covering the semiconductor layer (SEL).

For example, the first gate insulating layer 122 may be made of an inorganic layer of a silicon nitride layer, a silicon oxy nitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

The first conductive layer CDL1 is disposed on the first gate insulating layer 122 .

The first conductive layer (CDL1) is formed on the gate electrodes (GDT, G1-1, G1-2, G2, G3-1) of each of the driving transistor (DT) and switch elements (ST1 to ST6) provided in the pixel driver (PXD). , G3-2, G4, G5, G6).

And, the first conductive layer (CDL1) is the gate electrode (G1-1, G1-2, G2, G3-1, G3-) of each of the first to sixth transistors (ST1 to ST6) provided in the pixel driver (PXD). 2, G4, G5, G6) and further comprising a write scan line (GWL), an initialization scan line (GIL), a control scan line (GCL), and an emission control line (ECL) extending in the first direction (DR1). can do.

The first conductive layer (CDL1) is made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Alternatively, it may be formed as a single layer or multiple layers made of alloys thereof.

The second gate insulating layer 123 may be formed of an inorganic film disposed on the first gate insulating layer 122 and covering the first conductive layer (CDL1).

For example, the second gate insulating layer 123 may be made of an inorganic layer of a silicon nitride layer, a silicon oxy nitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

The second conductive layer CDL2 is disposed on the second gate insulating layer 123.

The second conductive layer (CDL2) may include a shielding electrode (SHE), a first power horizontal auxiliary line (VDSBL1), a gate initialization voltage line (VGIL), and an anode initialization voltage line (VAIL).

The second conductive layer (CDL2) is made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Alternatively, it may be formed as a single layer or multiple layers made of alloys thereof.

The interlayer insulating layer 124 may be formed of an inorganic film disposed on the second gate insulating layer 123 and covering the second conductive layer (CDL2).

For example, the interlayer insulating layer 124 may be made of an inorganic layer of a silicon nitride layer, a silicon oxy nitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

The third conductive layer (CDL3) is disposed on the interlayer insulating layer 124.

The third conductive layer (CDL3) includes a first connection electrode (CE1), a second connection electrode (CE2), a third connection electrode (CE3), a first power vertical auxiliary line (VDSBL2), and a gate initialization voltage auxiliary line (VGIAL). and an anode initialization voltage auxiliary wiring (VAIAL).

Referring to FIGS. 8 and 10, the pixel driver PXD includes a first contact hole (CT1), a second contact hole (CT2), a third contact hole (CT3), a fourth contact hole (CT4), and a third contact hole (CT4). It may include a fifth contact hole (CT5), a sixth contact hole (CT6), and a seventh contact hole (CT7).

The first contact hole (CT1) is for connecting the first connection electrode (CE1) and the gate electrode (GDT) of the driving transistor (DT).

The first contact hole (CT1) corresponds to a portion of the gate electrode (GDT) of the driving transistor (DT) and may penetrate the second gate insulating layer 123 and the interlayer insulating layer 124. Accordingly, the first connection electrode (CE1) made of the third conductive layer (CDL3) is connected to the gate electrode (GDT) of the driving transistor (DT) made of the first conductive layer (CDL1) through the first contact hole (CT1). Can be electrically connected.

The second contact hole (CT2) is connected to any one of the drain electrode (D1-2) of the 1-2 transistor (ST1-2) and the source electrode (S3-1) of the 3-1 transistor (ST3-1). 1 This is to connect between the connection electrodes (CE1). The drain electrode (D1-2) of the 1-2 transistor (ST1-2) and the source electrode (S3-1) of the 3-1 transistor (ST3-1) are connected to each other.

The second contact hole (CT2) is a portion of any one of the drain electrode (D1-2) of the 1-2 transistor (ST1-2) and the source electrode (S3-1) of the 3-1 transistor (ST3-1). Corresponds to and may penetrate the first gate insulating layer 122, the second gate insulating layer 123, and the interlayer insulating layer 124. Accordingly, the first connection electrode CE1 made of the third conductive layer CDL3 is connected to the drain electrode of the 1-2 transistor ST1-2 made of the semiconductor layer SEL through the second contact hole CT2. D1-2) and the source electrode (S3-1) of the 3-1 transistor (ST3-1).

And, the gate electrode (GDT) of the driving transistor (DT) is connected to the 1-2 transistor (ST1-2) through the first contact hole (CT1), the second contact hole (CT2), and the first connection electrode (CE1). It may be electrically connected to the drain electrode (D1-2) of and the source electrode (S3-1) of the 3-1 transistor (ST3-1).

The third contact hole (CT3) is for connecting the shielding electrode (SHE) and the first power vertical auxiliary wiring (VDSBL2).

The third contact hole (CT3) corresponds to a portion of the first power vertical auxiliary wiring (VDSBL2) and may penetrate the interlayer insulating layer 124. As a result, the shielding electrode (SHE) made of the second conductive layer (CDL2) can be electrically connected to the first power vertical auxiliary wiring (VDSBL2) made of the third conductive layer (CDL3) through the third contact hole (CT3). there is.

The fourth contact hole CT4 is for connecting the second connection electrode CE2 and the source electrode S2 of the second transistor ST2.

The fourth contact hole (CT4) corresponds to a part of the source electrode (S2) of the second transistor (ST2), and the first gate insulating layer 122, the second gate insulating layer 123, and the interlayer insulating layer 124 can penetrate. Accordingly, the second connection electrode CE2 made of the third conductive layer CDL3 is electrically connected to the source electrode S2 of the second transistor ST2 made of the semiconductor layer SEL through the fourth contact hole CT4. It can be connected to .

The fifth contact hole (CT5) is for connecting the first power horizontal auxiliary wire (VDSBL1) and the first power vertical auxiliary wire (VDSBL2).

The fifth contact hole CT5 corresponds to a portion of the first power horizontal auxiliary wiring VDSBL1 and may penetrate the interlayer insulating layer 124. Accordingly, the first power vertical auxiliary wiring (VDSBL2) made of the third conductive layer (CDL3) is connected to the first power horizontal auxiliary wiring (VDSBL1) made of the second conductive layer (CDL2) through the fifth contact hole (CT5). Can be electrically connected.

The sixth contact hole (CT6) is for connecting the first power vertical auxiliary wiring (VDSBL2) and the source electrode (S5) of the fifth transistor (ST5).

The sixth contact hole CT6 corresponds to a portion of the source electrode S5 of the fifth transistor ST5 and includes the first gate insulating layer 122, the second gate insulating layer 123, and the interlayer insulating layer 124. It can penetrate. Accordingly, the first power vertical auxiliary wiring (VDSBL2) made of the third conductive layer (CDL3) is connected to the source electrode (S5) of the fifth transistor (ST5) made of the semiconductor layer (SEL) through the sixth contact hole (CT6). can be electrically connected to.

The seventh contact hole (CT7) is for connecting the third connection electrode (CE3) and the drain electrode (D5) of the fifth transistor (ST5).

The seventh contact hole (CT7) corresponds to a portion of the drain electrode (D5) of the fifth transistor (ST5) and connects the first gate insulating layer 122, the second gate insulating layer 123, and the interlayer insulating layer 124. It can penetrate. Accordingly, the third connection electrode CE3 made of the third conductive layer CDL3 is electrically connected to the drain electrode D5 of the fifth transistor ST5 made of the semiconductor layer SEL through the seventh contact hole CT7. It can be connected to .

The third conductive layer (CDL3) may have a multi-layer structure including a metal layer with low resistance characteristics and a metal layer with ion diffusion prevention characteristics disposed on the top and bottom surfaces, respectively.

As an example, the third conductive layer (CDL3) may be composed of a stacked structure of metal layers, and each of the metal layers of the third conductive layer (CDL3) is molybdenum (Mo), aluminum (Al), chromium (Cr), and gold (Au). ), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

Specifically, the metal layer with low resistance characteristics may be made of any one of aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), and copper (Cu).

The metal layer with ion diffusion prevention properties may be made of titanium (Ti).

That is, the third conductive layer (CDL3) may be prepared in a stacked structure (Ti/Al/Ti) of titanium (Ti)/aluminum (Al)/titanium (Ti).

The first planarization layer 125 covering the third conductive layer (CDL3) is made of acryl resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin ( It may be made of an organic film such as polyimide resin.

The fourth conductive layer CDL4 is disposed on the first planarization layer 125 .

As shown in FIG. 9, the fourth conductive layer (CDL4) includes the second power sub-wiring (VSSBL), the second bypass wiring (DETL2), the second dummy wiring (DML2), the first power auxiliary wiring (VDAL), and the second power sub-wiring (VSSBL). It may include four connection electrodes (CE4) and a fifth connection electrode (CE5).

The fourth conductive layer (CDL4) is made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Alternatively, it may be made of a single layer or multiple layers of alloys thereof.

Like the third conductive layer (CDL3), the fourth conductive layer (CDL4) may be made of a stacked structure of metal layers, and each of the metal layers of the third conductive layer (CDL3) is molybdenum (Mo), aluminum (Al), and chromium. It may be made of any one of (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

That is, the fourth conductive layer (CDL4) may be prepared in a stacked structure (Ti/Al/Ti) of titanium (Ti)/aluminum (Al)/titanium (Ti).

The second planarization layer 126 covering the fourth conductive layer (CDL4) is made of acryl resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin ( It may be made of an organic film such as polyimide resin.

The fifth conductive layer CDL5 is disposed on the second planarization layer 126 .

As shown in FIG. 9, the fifth conductive layer (CDL5) includes a data line (DL), a first bypass line (DETL1), a third bypass line (DETL3), a first dummy line (DML1), and a second power auxiliary line. (VSAL) and a sixth connection electrode (CE6).

The fifth conductive layer (CDL5) is made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Alternatively, it may be made of a single layer or multiple layers of alloys thereof.

As shown in FIG. 10, the third planarization layer 127 covering the fifth conductive layer (CDL5) is made of acryl resin, epoxy resin, phenolic resin, and polyamide resin. It may be made of an organic film such as resin or polyimide resin.

Referring to FIGS. 9 and 10, the pixel driver PXD further includes an eighth contact hole (CT8), a ninth contact hole (CT9), a tenth contact hole (CT10), and an eleventh contact hole (CT11). It can be included.

The eighth contact hole CT8 is for connecting the fifth connection electrode CE5 and the third connection electrode CE3.

The eighth contact hole CT8 corresponds to a portion of the third connection electrode CE3 and may penetrate the first planarization layer 125. As a result, the fifth connection electrode (CE5) made of the fourth conductive layer (CDL4) can be electrically connected to the third connection electrode (CE3) made of the third conductive layer (CDL3) through the eighth contact hole (CT8). there is.

The ninth contact hole CT9 is for connecting the fifth connection electrode CE5 and the sixth connection electrode CE6.

The ninth contact hole CT9 corresponds to another part of the fifth connection electrode CE5 and may penetrate the second planarization layer 126. As a result, the sixth connection electrode (CE6) made of the fifth conductive layer (CDL5) can be electrically connected to the fifth connection electrode (CE5) made of the fourth conductive layer (CDL4) through the ninth contact hole (CT9). there is.

The tenth contact hole CT10 is for connecting the fourth connection electrode CE4 and the second connection electrode CE2.

The tenth contact hole CT10 corresponds to a portion of the second connection electrode CE2 and may penetrate the first planarization layer 125 . Accordingly, the fourth connection electrode (CE4) made of the fourth conductive layer (CDL4) can be electrically connected to the second connection electrode (CE2) made of the third conductive layer (CDL3) through the tenth contact hole (CT10). .

The eleventh contact hole CT11 is for connecting the fourth connection electrode CE4 and the data line DL.

The eleventh contact hole CT11 corresponds to another part of the fourth connection electrode CE4 and may penetrate the second planarization layer 126. Accordingly, the data line DL made of the fifth conductive layer CDL5 can be electrically connected to the fourth connection electrode CE4 made of the fourth conductive layer CDL4 through the 11th contact hole CT11.

As shown in FIG. 10, the light emitting array layer 130 may be disposed on the third planarization layer 127 of the circuit array layer 120.

As an example, the light emitting array layer 130 is disposed on the third planarization layer 127 and includes a plurality of anodes, each corresponding to a plurality of light emitting areas EA and electrically connected to a plurality of pixel drivers PXD. Electrodes (AND), disposed on the third planarization layer 127, correspond to the non-emissive area (NEA), which is a spaced area between the plurality of light-emitting areas (EA), and have edges of each of the plurality of anode electrodes (AND) A pixel definition layer (PDL) covering a plurality of light emitting layers (EML), each corresponding to a plurality of light emitting areas (EA) and disposed on a plurality of anode electrodes (AND), and a plurality of light emitting areas (EA) ) and may include a cathode electrode (CTD) disposed on the pixel definition layer (PDL) and a plurality of light emitting layers (EML) and connected to the second power supply line (VSSPL).

The anode electrode (AND) may be connected to the sixth connection electrode (CE6) through the anode contact hole (ANCT) penetrating the third planarization layer (127).

Accordingly, the anode electrode (AND) is connected to the seventh contact hole (CT7), the third connection electrode (CE3), the eighth contact hole (CT8), the fifth connection electrode (CE5), the ninth contact hole (CT9), and the sixth contact hole (CT9). It can be electrically connected to the drain electrode (DDT) of the driving transistor (DT) through the connection electrode (CE6) and the anode contact hole (ANCT).

The pixel defining layer (PDL) may be made of an organic layer.

The light emitting layer (EML) may include an organic light emitting material.

Although not separately shown, a first common layer (not shown) containing at least a hole transport material may be disposed between the anode electrode AND and the light emitting layer EML.

Additionally, a second common layer (not shown) containing at least an electron transport material may be disposed between the emission layer (EML) and the cathode electrode (CTD).

The cathode electrode CTD may correspond to the front surface of the display area DA.

Although not separately shown, the cathode electrode (CTD) may be connected to the second power supply line (VSSPL) in the non-display area (NDA).

Accordingly, the light emitting array layer 130 has a structure that corresponds to a plurality of light emitting areas (EA) and includes an anode electrode (AND) and a cathode electrode (CTD) facing each other, and an light emitting layer (EML) sandwiched between them. Each may include a plurality of light emitting elements (LEL).

The light emitting array layer 130 may be covered with a sealing structure layer 140 to block penetration of oxygen or moisture.

The sealing structure layer 140 covers the light emitting array layer 130 and may have a structure in which at least one inorganic layer and at least one organic layer are cross-stacked.

As an example, the sealing structure layer 140 covers the cathode electrode (CTD), is in contact with the interlayer insulating layer 124 in the non-display area (NDA), and includes a first sealing layer 141 made of an inorganic insulating material, a first sealing layer ( 141), a second sealing layer 142 corresponding to the display area DA and made of an organic insulating material, and a first sealing layer 141 covering the second sealing layer 142 and in the non-display area NDA. ) and may include a third sealing layer 143 made of an inorganic insulating material.

Next, the first embodiment will be described in more detail.

FIG. 11 is an equivalent circuit diagram showing the demux circuit unit of FIG. 5 according to the first embodiment.

FIG. 11 illustrates a case where the demux circuit unit (DMC) of the first embodiment is connected to two data lines (DL).

As shown in FIG. 11, one of the demux circuit units (DMC) according to the first embodiment includes two demux transistors (TDM1 and TDM2) corresponding to two output terminals, respectively. do.

The first electrode (eg, source electrode) of the two demux transistors TDM1 and TDM2 may be connected to the data input line DIPL.

The second electrode (eg, drain electrode) of the two demux transistors TDM1 and TDM2 may be connected to the first data output line DOPL1 and the second data output line DOPL2, respectively.

That is, in the case of the first demux circuit unit DMC1, the second electrode of the first demux transistor TDM1 is connected to the first data line DL1 through the first data output line DOPL1, and the second electrode is connected to the first data line DL1 through the first data output line DOPL1. The second electrode of the mux transistor TDM2 may be connected to the second data line DL2 through the second data output line DOPL2.

Alternatively, in the case of the second demux circuit unit DMC2, the second electrode of the first demux transistor TDM1 is connected to the third data line DL3 through the first data output line DOPL1, and the second electrode is connected to the third data line DL3 through the first data output line DOPL1. The second electrode of the mux transistor TDM2 may be connected to the fourth data line DL4 through the second data output line DOPL2.

The gate electrode of the first demux transistor (TDM1) may be connected to the first demux control line (SCSL1), and the gate electrode of the second demux transistor (TDM2) may be connected to the second demux control line (SCSL2). .

The first demux control line (SCSL1) and the second demux control line (SCSL2) transmit a first demux control signal (SCS1) and a second demux control signal (SCS2) of different phases, respectively.

By these different phases of the first demux control signal (SCS1) and the second demux control signal (SCS2), the first demux transistor (TDM1) and the second demux transistor (TDM2) are turned on for different periods. It can be.

Therefore, the data driving signal of the display driving circuit 200 transmitted through the data input line DIPL is time-divided ( It can be demultiplexed using the Time Division method. Accordingly, each data signal may be transmitted to the first data line DL1 and the second data line DL2 connected to the output terminals of the demux circuit unit DMC for different periods of time.

FIG. 12 is a plan view showing an example of portion E of FIG. 5. Figure 13 is a cross-sectional view showing an example of a surface cut along line H-H' of Figure 12.

Referring to FIG. 12, each of the demux circuit units (DMCs) connects two adjacent data lines (DL1, DL2) (DL3, DL4) among the data lines (DL) through two data output lines (DMOL). Each can be connected.

As shown in FIG. 5, the first data input line DIPL1 connected to the input terminal of the first demux circuit unit DMC1 of the first demux area DMXA1 is the first demux line in the first sub-area SB1. It extends to the area (DMXA1).

And, the second data input line DIPL2 connected to the input terminal of the second demux circuit part DMC2 of the second demux area DMXA2 is connected from the first sub-area SB1 to the first demux area DMXA1. The extended main input line (MIPL), the demultiplex bypass line (DETL) disposed in the demultiplex adjacent area (DAA) of the display area (DA), and the additional bypass line ( DEAL).

As shown in FIG. 12 , in the first demux area DMXA1, the main input line MIPL may be arranged in parallel with the first data input line DIPL1.

The demultiplex bypass line (DETL) includes a first bypass line (DETL1) in the second direction (DR2) disposed in the center adjacent area (CDAA), and a first bypass line (DETL1) in the first direction (DR1) disposed in the demultiplex adjacent area (DAA). It may include two bypass lines (DETL2) and a third bypass line (DETL3) in the second direction (DR2) disposed in the edge adjacent area (EDAA).

The data lines DL include a first data line DL1 and a second data line DL2 connected to the first demux circuit portion DMC1 and disposed in the center adjacent area CDAA, and a second demux circuit portion DMC2. ) and may include a third data line (DL3) and a fourth data line (DL4) connected to the edge adjacent area (EDAA).

Among the first data line DL1 and the second data line DL2 connected to the first demux circuit unit DMC1, the first data line DL1 is adjacent to the first bypass line DETL1 and the second data line (DL2) may be adjacent to the second power auxiliary line (VSAL).

Among the third and fourth data lines DL3 and DL4 connected to the second demux circuit unit DMC2, the third data line DL3 is adjacent to the third bypass line DETL3, and is the fourth data line. (DL4) may be adjacent to the second power auxiliary line (VSAL).

As shown in FIG. 13, each of the data lines DL, the first bypass line DETL1, the third bypass line DETL3, and the second power auxiliary line VSAL extends in the second direction DR2. , It may be made of a fifth conductive layer (CDL5).

In addition, first dummy wires DML1 are arranged in parallel on one side of the first bypass wire DETL1 in the second direction DR2 and on one side of the third bypass wire DETL3 in the second direction DR2. It extends in the second direction DR2 and may be made of a fifth conductive layer CDL5.

Each of the second bypass line DETL2 and the first power auxiliary line VDAL extends in the first direction DR1 and may be formed of the fourth conductive layer CDL4. The second bypass wiring DETL2 and the first power auxiliary wiring VDAL may be alternately arranged in the second direction DR2.

In addition, the second dummy wires DML2 arranged side by side on both sides of the second bypass wire DETL2 in the first direction DR1 also extend in the first direction DR1, and the fourth conductive layer CDL4 It can be done.

Each of the data output lines (DOPL), the first data input line (DIPL1), and the main input line (MIPL) is connected to the first conductive layer (CDL1) or the second gate insulating layer 123 on the first gate insulating layer 122. It may be provided as a second conductive layer (CDL2).

The data lines (DL) may be respectively connected to the data output lines (DMOL) through the data connection hole (DCH).

As shown in FIG. 12, the first bypass wiring (DETL1) may be electrically connected to the second bypass wiring (DETL2) through the first bypass connection hole (DETH1) corresponding to one end of the second bypass wiring (DETL2). .

The third bypass wiring DETL3 may be electrically connected to the second bypass wiring DETL2 through the second bypass connection hole DETH2 corresponding to the other end of the second bypass wiring DETL2.

The third bypass wiring DETL3 may be electrically connected to the additional bypass wiring DEAL through the third bypass connection hole DETH3 corresponding to one end of the additional bypass wiring DEAL.

According to the first embodiment, the bypass additional wiring DEAL extends in the second direction DR2. Accordingly, the input terminal of the first demux circuit unit DMC1 connected to the bypass additional wiring DEAL extends in the first direction DR1 toward the bypass additional wiring DEAL, and the second demux circuit unit DMC2 It may be of a different form from the input terminal of .

Each demux circuit unit (DMC) may include a first demux transistor (TDM1) and a second demux transistor (TDM2).

As shown in FIG. 13, the first demux transistor (TDM1) and the second demux transistor (TDM2) each overlap a channel portion, a first electrode, and a second electrode provided with the semiconductor layer (SEL), and the channel portion. It may include a gate electrode.

The gate electrode of the first demux transistor (TDM1) may be formed as a part of the first demux control line (SCSL1) overlapping the channel portion of the first demux transistor (TDM1).

The gate electrode of the second demux transistor (TDM2) may be formed as a part of the second demux control line (SCSL2) overlapping the channel portion of the second demux transistor (TDM2).

At least a portion of each of the first power supply line (VDSPL) and the second power supply line (VSSPL) disposed in the non-display area (NDA) and the first sub-area (SB1) is disposed in the demux area (DMXA). That is, the demux circuit units (DMC) disposed in the demux area (DMXA) may overlap each of the first power supply line (VDSPL) and the second power supply line (VSSPL).

Each of the first power supply wiring (VDSPL) and the second power supply wiring (VSSPL) is provided in a jumping structure consisting of a combination of the third conductive layer (CDL3), the fourth conductive layer (CDL4), and the fifth conductive layer (CDL5). It can be.

The second power auxiliary wiring (VSAL) may be branched from the second power supply wiring (VSSPL) of the fifth conductive layer (CDL5). In this case, a portion of the first power supply line (VDSPL) crossing the second power auxiliary line (VSAL) may be formed of the third conductive layer (CDL3) or the fourth conductive layer (CDL4).

The first demux control line (SCSL1) and the second demux control line (SCSL2) may be formed of a third conductive layer (CDL3).

However, this is only an example, and the arrangement structures of the first power supply line (VDSPL) and the second power supply line (VSSPL), and the first demux control line (SCSL1) and the second demux control line (SCSL2) are mutually It is insulated and can be freely modified within the range of being insulated from the data output lines (DMOL) and data input lines (DIPL).

Additionally, each of the first demux control line (SCSL1) and the second demux control line (SCSL2) may be arranged in a jumping shape consisting of a combination of the third conductive layer (CDL3) and the fourth conductive layer (CDL4).

In addition, the constant voltage supply line (CVL) disposed in the non-display area (NDA) and extending from the first sub-area (SB1) to the scan driving circuit area (SDCA) is connected to the third conductive layer (CDL3) and the fourth conductive layer (CDL4). ) can also be arranged in a jumping form consisting of a combination of

In this way, the first power supply wiring (VDSPL), the second power supply wiring (VSSPL), the first demux control wiring (SCSL1), the second demux control wiring (SCSL2), and the constant voltage supply wiring (CVL) are Since they can be integrated while being mutually insulated in the display area (NDA), it can be advantageous to reduce the width of the non-display area (NDA).

Meanwhile, the display device 10 may further include a dam structure (DAMS) disposed in the non-display area (NDA) and configured to surround the display area (DA).

The second sealing layer 142 of the sealing structure layer 140 may be disposed in an area surrounded by the dam structure (DAMS).

Figure 14 is a cross-sectional view showing an example of a surface cut along line F-F' of Figure 5.

Among the sub-areas (SBA), the bending area (BA) is an area that is transformed into a bending shape. When deformed into this bending form, the inorganic film is vulnerable to cracking due to bending stress, so the buffer layer 121, the first gate insulating layer 122, the second gate insulating layer 123, and the interlayer insulating layer 124 are made of an inorganic film. ) Among each, a part corresponding to the bending area BA may be removed.

Therefore, wires in the bending area BA may be separately provided to connect the wires in the first sub-area BA1 with the wires in the second sub-area BA2.

Referring to FIG. 14 , at least a portion of the second power supply line (VSSPL) in the non-display area (NDA) and the first sub-area (SBA1) and the second power pad line (VSPDL) in the second sub-area (SBA2) At least some of them may be provided as the fifth conductive layer (CDL5) on the second planarization layer 126.

In addition, the second power bending line (VSBDL) of the bending area (BA) connecting the second power supply line (VSSPL) and the second power pad line (VSPDL) is the fourth conductive layer on the first planarization layer (125). It can be prepared as (CDL4). However, this is only an example, and the wires in the bending area BA are each formed of a conductive layer disposed on at least one of the first planarization layer 125, the second planarization layer 126, and the third planarization layer 127. It can be.

In addition, although not separately shown, the first power supply line (VDSPL) of the non-display area (NDA) and the first sub-area (SBA1) and the first power pad line (VDPDL) of the second sub-area (SBA2) are each It may be provided as a fifth conductive layer (CDL5) on the second planarization layer 126, and the first power bending line (VDBDL) may be provided as a fourth conductive layer (CDL4) on the first planarization layer 125.

The organic layer and wires of the sensor electrode layer 150 may extend to the bending area BA and the second sub-area SB2.

FIG. 15 is a layout diagram showing an example of the fourth and fifth conductive layers in part C of FIG. 4 according to the first embodiment. FIG. 16 is a layout diagram showing another example of the fourth and fifth conductive layers in part C of FIG. 4 according to the first embodiment.

15 and 16 each show a portion of the center adjacent area (CDAA) and a portion of the edge adjacent area (EDAA) adjacent to the boundary between the center adjacent area (CDAA) and the edge adjacent area (EDAA) in the display area (DA). .

Referring to FIGS. 15 and 16 , the first data line DL1 and the second data line DL2 connected to the first demux circuit unit DMC1 are disposed in the center adjacent area CDAA.

In the center adjacent area CDAA, the first data line DL1 may be adjacent to the first bypass line DETL1, and the second data line DL2 may be adjacent to the second power auxiliary line VSAL. That is, in the center adjacent area (CDAA), the first bypass line (DETL1), the first data line (DL1), the second power auxiliary line (VSAL), and the second data line (DL2) are connected in the first direction (DR1). It may be arranged repeatedly along one side.

The third data line DL3 and the fourth data line DL4 connected to the second demux circuit unit DMC2 are disposed in the edge adjacent area EDAA.

In the edge adjacent area EDAA, the third data line DL3 may be adjacent to the third bypass line DETL3, and the fourth data line DL4 may be adjacent to the second power auxiliary line VSAL. That is, in the edge adjacent area EDAA, the third bypass line DETL3, the third data line DL3, the second power auxiliary line VSAL, and the fourth data line DL4 are connected in the first direction DR1. It may be arranged repeatedly along one side.

One side of the second bypass wiring (DETL2) is connected to the first bypass wiring (DETL1) through the first bypass connection hole (DETH1) in the center adjacent area (CDAA), and the other side of the second bypass wiring (DETL2) is connected to the edge. It is connected to the third bypass wiring (DETL3) through the second bypass connection hole (DETH2) in the adjacent area (EDAA).

The first power auxiliary wiring (VDAL) extends in the first direction (DR1) and is alternately arranged in the second direction (DR2) with the second bypass wiring (DETL2).

The first dummy wires DML1 are spaced apart in parallel on one side of the first bypass wire DETL1 in the second direction DR2 and one side of the third bypass wire DETL3 in the second direction DR2, and It extends in the direction (DR2).

The second dummy wires DML2 are spaced apart from each other in parallel on both sides of the second bypass wire DETL2 in the first direction DR1 and extend in the first direction DR1.

As shown in FIG. 15 , the first bypass connection holes DETH1 of the second bypass wires DETL2 adjacent to each other in the second direction DR2 may be arranged side by side in the first diagonal direction DD1.

The second bypass connection holes DETH2 of the second bypass wires DETL2 adjacent in the second direction DR2 may be arranged side by side in the second diagonal direction DD2.

In this case, the second bypass wires DETL2 adjacent in the second direction DR2 may have a longer length as they are further away from the demultiplex area DMXA.

Alternatively, as shown in FIG. 16 , the first bypass connection holes DETH1 of the second bypass wiring DETL2 adjacent to each other in the second direction DR2 may be arranged side by side in the second diagonal direction DD2.

The second bypass connection holes DETH2 of the second bypass wires DETL2 adjacent in the second direction DR2 may be arranged side by side in the first diagonal direction DD1.

In this case, the second bypass wires DETL2 adjacent in the second direction DR2 may have shorter lengths as they are further away from the demultiplex area DMXA.

In this way, whether the first bypass connection holes (DETH1) and the second bypass connection holes (DETH2) are normally arranged can be determined by the arrangement of the first bypass connection holes (DETH1) and the arrangement of the second bypass connection holes (DETH2). It can be relatively easily inferred from the shape.

As shown in FIGS. 15 and 16, the further away the second demux circuit units DMC2 arranged in the second demux areas DMXA2 are from the first demux area DMXA1, the longer the second bypass wiring. It may be connected to a second data input line (DIPL2) including (DETL2).

FIG. 17 is a layout diagram showing an example of the fourth and fifth conductive layers in portion D of FIG. 4 according to the first embodiment.

FIG. 17 shows a portion of the general area (GA) remaining in the display area (DA) excluding the demultiplexed adjacent area (DAA).

FIG. 17 illustrates a layout of some areas of FIGS. 15 and 16 and a portion of the general area GA parallel to the second direction DR2.

Referring to FIG. 17, the first data line DL1, the second data line DL2, the third data line DL3, the fourth data line DL4, and the first data line DL1, the second data line DL2, the third data line DL3, and the first data line DL4 are disposed in the demultiplex adjacent area (DAA). Each of the dummy wire DML1 and the second power auxiliary wire VSAL extends in the second direction DR2 and is also disposed in the general area GA.

According to the first embodiment, the circuit array layer 120 is disposed in the general area GA, is connected to the second power auxiliary line VSAL, and extends in the first direction DR1. It may further include.

In the general area GA, the first power auxiliary line VDAL is adjacent to the second power sub line VSSBL. That is, in the general area GA, the first power auxiliary line VDAL and the second power sub line VSSBL may be alternately arranged in the second direction DR2.

The second power sub-wiring (VSSBL) may be provided as the fourth conductive layer (CDL4) on the first planarization layer 125 along with the first power auxiliary wiring (VDAL).

The second power sub-wiring (VSSBL) may be electrically connected to the second power auxiliary wiring (VSAL) through the first power connection hole (PCH1).

Additionally, the second power sub-wire (VSSBL) may be electrically connected to the first dummy wire (DML1) through the second power connection hole (PCH2).

Accordingly, the first dummy wiring (DML1) is electrically connected to the second power auxiliary wiring (VSAL) through the second power sub-wiring (VSSBL), the first power connection hole (PCH1), and the second power connection hole (PCH2). can be connected

Although not separately shown, the second dummy wire DML2 in the demultiplex adjacent area DAA may be electrically connected to the first dummy wire DML1 through a predetermined connection hole.

Accordingly, the first dummy wire (DML1) and the second dummy wire (DML2) are used to reduce the visibility of the first demultiplex bypass wire (DETL1), the second demultiplex bypass wire (DETL2), and the third demultiplex bypass wire (DETL3). ) is not maintained in a floating state, but is connected to the second power auxiliary wiring (VSAL) through the second power sub-wiring (VSSBL), so that the RC delay of the second power transmission path can be reduced.

The first power connection holes (PCH1) and the second power connection holes (PCH2) may be arranged side by side, alternating with each other in a predetermined diagonal direction.

In this way, it can be determined whether the first power connection hole (PCH1) and the second power connection hole (PCH2) are properly arranged through the arrangement of the first power connection hole (PCH1) and the second power connection hole (PCH2). It can be detected relatively easily.

As described above, according to the first embodiment, the demux circuit unit (DMC) connected between the display driving circuit 200 and the data lines DL is connected to the display area DA and the sub-area of the non-display area NDA. It is placed in the demux area (DMXA), which is a part between (SBA).

Accordingly, since the signal transmission path between the demux circuits (DMCs) and the data lines (DL) is relatively short, the RC delay of the signal transmitted from the demux circuits (DMCs) to the data lines (DL) can be reduced. You can.

Since the data supply lines (DSPL), data bending lines (DBDL), and data input lines (DIPL) are provided as many as the demux circuit units (DMCs), the spacing between the lines arranged in the sub area (SBA) is wide. Alternatively, the width of the wires arranged in the sub-area SBA may be increased, or the width of the sub-area SBA may be reduced.

According to the first embodiment, as the demux circuit units (DMCs) are disposed in the non-display area (NDA), the width of the non-display area (NDA) may become somewhat larger. However, since the demux circuit units (DMCs) can be arranged side by side, the second demux area (DMXA2) can be arranged along the edge of the main area (MA). Additionally, the demux area (DMXA) may overlap with a portion of each of the first power supply line (VDSPL) and the second power supply line (VSSPL). As a result, the increase in width of the non-display area (NDA) according to the arrangement of the demux circuit units (DMCs) can be relatively small.

In addition, according to the first embodiment, the second data input lines DIPL2 connected to the second demux circuit units DMC2 disposed along the edges of the main area MA are connected to the first sub area SB1. Instead of extending to the second demux areas DMXA2, it detours from the first sub-area SB1 to the first demux area DMXA1 and the display area DA to form the second demux areas DMXA2. is extended to

Accordingly, since the second data input lines DIPL2 are not arranged side by side along the edges of the main area MA, the width of the non-display area NDA may be reduced.

Accordingly, the width of the non-display area (NDA) may be reduced, and as a result, the ratio to which the display area (DA) is allocated among the display surface of the display device 10 may increase, thereby improving the aesthetics and performance of the display device 10. It can be advantageous for improvement.

FIG. 18 is an equivalent circuit diagram showing the demux circuit of FIG. 5 according to the second embodiment. Figure 19 is a layout diagram showing a portion of each display area and demux area according to the second embodiment.

As shown in FIGS. 18 and 19, the display device of the second embodiment is substantially similar to the display device of the first embodiment, except that each of the demux circuit units (DMCs) includes three output terminals instead of two output terminals. Since they are the same, redundant descriptions will be omitted below.

Referring to FIG. 18, the demux circuit unit (DMC) according to the second embodiment includes a first demux transistor (TDM1) connected between the data input line (DIPL) and the first data output line (DMOL1), and a data input line. A second demux transistor (TDM2) connected between (DIPL) and the second data output line (DMOL2), and a third demux transistor connected between the data input line (DIPL) and the third data output line (DMOL3) (TDM3).

As an example, the first electrode (eg, source electrode) of each of the first demux transistor (TDM1), the second demux transistor (TDM2), and the third demux transistor (TDM3) is connected to the data input line (DIPL) and can be connected And, the second electrode (for example, drain electrode) of each of the first demux transistor (TDM1), the second demux transistor (TDM2), and the third demux transistor (TDM3) is connected to the data output lines (DMOL). can be connected

The gate electrode of the first demux transistor TDM1 may be connected to the first demux control line SCSL1 that transmits a predetermined first demux control signal SCS1.

The gate electrode of the second demux transistor (TDM2) may be connected to the second demux control line (SCSL2) that transmits the second demux control signal (SCS2) having a different phase from the first demux control signal (SCS1). there is.

The gate electrode of the third demux transistor (TDM3) transmits a third demux control signal (SCS3) having a different phase from the first demux control signal (SCS1) and the second demux control signal (SCS3). It can be connected to the demux control wire (SCSL3).

Referring to FIG. 19, the data lines DL according to the second embodiment include a first data line DL1 and a second data line connected to the first demux circuit unit DMC1 and disposed in the center adjacent area CDAA. (DL2) and the third data line (DL3), and the fourth data line (DL4), the fifth data line (DL5) and the It may include 6 data lines (DL6).

Any one of the first data line DL1, the second data line DL2, and the third data line DL3 (for example, the first data line DL1) connected to the first demux circuit unit DMC1 It is adjacent to the first bypass line (DETL1), and each of the others (for example, the second data line (DL2) and the third data line (DL3)) may be adjacent to the second power auxiliary line (VSAL). .

And, one of the fourth data line DL4, the fifth data line DL5, and the sixth data line DL6 (for example, the fourth data line DL4) connected to the second demux circuit unit DMC2. ) is adjacent to the third bypass line (DETL3), and the others (for example, the fifth data line (DL5) and the sixth data line (DL6)) are each adjacent to the second power auxiliary line (VSAL). You can.

However, the first and second embodiments are only examples, and it is natural that each of the demux circuit units (DMCs) may be connected to four or more data wires within the range in which data driving signals can be generated.

FIG. 20 is a layout diagram showing part B of FIG. 4 according to the third embodiment. FIG. 21 is a plan view showing an example of portion I of FIG. 20.

Referring to FIGS. 19 and 20 , the display device 10 according to the third embodiment has a bypass additional wiring DEAL′ having a first extension portion DETP1 extending in the second direction DR2 and a first direction ( Except for including the second extension part DETP2 extending to DR1), it is substantially the same as the display device of the first embodiment, and thus redundant description will be omitted below.

As shown in FIG. 20, the bypass additional wiring DEAL' according to the third embodiment includes a first extension portion DETP1 connected to the third bypass wiring DETL3 and extending in the second direction DR2, and a first extension portion DETP1 connected to the third bypass wiring DETL3 and extending in the second direction DR2. It includes a second extension part (DETP2) connected to the first extension part (DETP1) and extending in the first direction (DR1) toward the input terminal of the second demux circuit part (DMC2).

That is, the additional bypass wiring DEAL' of the third embodiment may have a bent shape.

In this way, the input terminal of the second demux circuit unit DMC2 does not extend in the first direction DR1 toward the bypass additional wiring DEAL', but is provided in a similar form to the input terminal of the first demux circuit unit DMC1. It can be.

As a result, the patterning process for preparing demux circuit parts (DMCs) can become easier and it can be advantageous to improve the volume ratio.

Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention can be implemented in other specific forms without changing its technical idea or essential features. You will be able to understand it. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive.

10: display device 100: display panel
MA: Main area SBA: Sub area
DA: Display area NDA: Non-display area
200: display driving circuit 300: circuit board
EA: luminescent area 110: substrate
120: circuit array layer 130: light emitting array layer
140: Sealing structure layer 150: Sensor electrode layer
DMXA: Demux area DAA: Demux adjacent area
DMXA1, DMXA2: 1st, 2nd demux area
CDAA: Center Adjacent Area EDAA: Edge Adjacent Area
DMC: Demux circuitry
DMC1, DMC2: 1st and 2nd demux circuit units
DSPL1, DSPL2: 1st and 2nd data supply wiring
DBDL1, DBDL2: 1st, 2nd data bending wiring
DIPL1, DIPL2: 1st, 2nd data input wiring
MIPL: Main input wiring DETL: Demux bypass wiring
DETL1, DETL2, DETL3: 1st, 2nd, 3rd bypass wiring
DEAL, DEAL': Additional bypass wiring
DMOL: Demux output wiring CVL: Constant voltage supply wiring
DL: Data wiring PXD: Pixel driver
DL1, DL2, DL3, DL4: 1st, 2nd, 3rd, 4th data wires
DML1, DML2: 1st, 2nd dummy wiring
VDAL: 1st power auxiliary wiring VSAL: 2nd power auxiliary wiring
VDSPL: primary power supply wiring VSSPL: secondary power supply wiring
VDBDL: primary power bending wiring VSBDL: secondary power bending wiring
VDPDL: first power pad wiring VSPDL: second power pad wiring
SEL: semiconductor layer
CDL1, CDL2, CDL3: first, second, third conductive layers
CDL4, CDL5: 4th, 5th conductive layer VSSBL: 2nd power sub-wiring
DETH1, DETH2, DETH3: 1st, 2nd, 3rd bypass connection holes
PCH1, PCH2: 1st and 2nd power connection holes
TDM1, TDM2, TDM3: first, second, third demux transistors
SCSL1, SCSL2, SCSL3: 1st, 2nd, 3rd demux control wiring
DMOL1, DMOL2, DMOL3: 1st, 2nd, 3rd demux output wiring

Claims (28)

A substrate including a display area in which a plurality of light-emitting areas are arranged in a first direction and a second direction, a main area including a non-display area disposed around the display area, and a sub-area protruding from one side of the main area;
A plurality of pixel drivers disposed on the substrate, each corresponding to the plurality of light-emitting areas, data lines for transmitting data signals to the plurality of pixel drivers, and in the sub-area of the non-display area. a circuit array layer including demux circuit units disposed in adjacent demux areas; and
a display driving circuit disposed in the sub-region of the substrate and supplying data driving signals corresponding to the data lines;
One of the demux circuit units outputs two or more data signals based on one data driving signal,
The demux circuit units include a first demux circuit unit disposed in a first demux area adjacent to the sub-area among the demux areas, and a first demux circuit unit in contact with one side of the first demux area in the first direction among the demux areas. It includes a second demux circuit unit disposed in the second demux area,
The circuit array layer is
a first data input line extending from the sub-region to the first demux region and connected to an input terminal of the first demux circuit unit; and
It further includes a second data input wire connected to the input terminal of the second demux circuit unit,
The second data input wiring is
a main input line extending from the sub-area to the first demux area;
a demux bypass wire disposed in the display area and connected to the main input wire; and
A display device including a bypass additional wiring disposed in the second demultiplex area and connecting the demultiplex bypass wiring and an input terminal of the second demultiplex circuit unit. According to claim 1,
The display area includes a demultiplexed adjacent area adjacent to the demultiplexed area,
The demux bypass wiring is
a first bypass wire disposed in a center adjacent area adjacent to the first demultiplex area among the demultiplex adjacent areas, connected to the main input wire, and extending in the second direction;
a second bypass wiring connected to the first bypass wiring and extending in the first direction; and
It is an area between the center adjacent area and the non-display area among the demultiplexed adjacent areas, is disposed in an edge adjacent area adjacent to the second demultiplexed area, extends in the second direction toward the second demultiplexed area, and is an area between the center adjacent area and the non-display area. 2. A display device including a third bypass wiring connecting the bypass wiring and the bypass additional wiring. According to clause 2,
The display device wherein the bypass additional wiring extends in the second direction. According to clause 2,
The bypass additional wiring is
a first extension connected to the third bypass wiring and extending in the second direction; and
A display device comprising a second extension part connected between the first extension part and an input terminal of the second demux circuit unit and extending in the first direction. According to clause 2,
The sub-region includes a bending region that is transformed into a bent shape, a first sub-region disposed between the main region and one side of the bending region, and a second sub-region disposed between the other side of the bending region,
The circuit array layer is
a first data supply line and a second data supply line disposed in the second sub-region and respectively connected to output terminals of the display driving circuit;
a first data bending wire connected between the first data supply wire and the first data input wire and disposed in the bending area; and
The display device further includes a second data bending wire connected between the second data supply wire and the main input wire and disposed in the bending area. According to clause 2,
It further includes a light emitting array layer disposed on the third planarization layer and including a plurality of light emitting elements respectively corresponding to the plurality of light emitting regions,
The data wires extend in the second direction,
The circuit array layer is
a first power supply line and a second power supply line disposed in the non-display area and transmitting first power and second power for driving the light emitting elements, respectively; and
It further includes a second power auxiliary wire disposed in the display area, extending in the second direction, and electrically connected to the second power supply wire,
A display device wherein a portion of each of the first power supply wiring and the second power supply wiring overlaps the demux circuit units. According to clause 6,
One of two or more data wires disposed in an area adjacent to the center and connected to the first demultiplexer circuit is disposed adjacent to the first bypass wire,
A display device in which, of the two or more data wires disposed in an area adjacent to the center and connected to the first demultiplexer circuit, all but one adjacent to the first bypass wire are disposed adjacent to the second power auxiliary wire. According to clause 6,
One of the two or more data wires disposed in the area adjacent to the edge and connected to the second demux circuit unit is disposed adjacent to the third bypass wire,
Of the two or more data wires disposed in the area adjacent to the edge and connected to the second demux circuit unit, except for one adjacent to the third bypass wire, the remaining data wires are arranged adjacent to the second power auxiliary wire. According to clause 6,
The center adjacent area includes a central middle area and a side area between the middle area and the edge adjacent area,
The first demux circuit unit is disposed in a portion of the first demux area adjacent to the side area,
The demux circuit units further include a third demux circuit unit disposed in another portion of the first demux area adjacent to the middle area,
Two or more data wires disposed in the middle area and connected to the third demux circuit unit are disposed adjacent to the second power auxiliary wire. According to clause 6,
The circuit array layer is
a first power auxiliary wire disposed in the display area, extending in the first direction, and electrically connected to the first power supply wire; and
further comprising a second power sub-wire disposed in a general area other than the demultiplexed area of the display area, extending in the first direction, and electrically connected to the second power supply wire;
The first power auxiliary wiring is disposed adjacent to the second bypass wiring in the demux adjacent area, and is disposed adjacent to the second power sub-wiring in the general area. According to clause 9,
The circuit array layer is
first dummy wires spaced apart in parallel on one side of the first bypass wire in the second direction and one side of the third bypass wire in the second direction and extending in the second direction; and
The display device further includes second dummy wires spaced apart from each other in parallel on both sides of the second bypass wire in the first direction and extending in the first direction. According to claim 10,
The first dummy wires or the second dummy wires are electrically connected to the second power supply wire. According to claim 10,
The circuit array layer is
a semiconductor layer on the substrate;
a first conductive layer on the first gate insulating layer covering the semiconductor layer;
a second conductive layer on the second gate insulating layer covering the first conductive layer;
a third conductive layer on the interlayer insulating layer covering the second conductive layer;
a fourth conductive layer on the first planarization layer covering the third conductive layer;
a fifth conductive layer on the second planarization layer covering the fourth conductive layer; and
It is provided with a structure including a third planarization layer covering the fifth conductive layer,
The data wires, the first bypass wire, the third bypass wire, the second power auxiliary wire, and the first dummy wire are made of the fifth conductive layer,
The second bypass wiring, the first power auxiliary wiring, the second dummy wiring, and the second power sub wiring are formed of the fourth conductive layer. According to clause 6,
Each of the demux circuit units includes two or more demux transistors,
Gate electrodes of the two or more demux transistors are respectively connected to two or more demux control wires,
The two or more demux control wires supply demux control signals of different phases. According to clause 6,
The light emitting array layer is
a plurality of anode electrodes disposed on the third planarization layer, each corresponding to the plurality of light emitting regions, and each electrically connected to the plurality of pixel drivers;
a pixel definition layer disposed on the third planarization layer, corresponding to a non-emission area that is a spaced area between the plurality of light emitting areas, and covering edges of each of the plurality of anode electrodes;
a plurality of light-emitting layers respectively corresponding to the plurality of light-emitting regions and respectively disposed on the plurality of anode electrodes; and
A cathode electrode corresponding to the plurality of light-emitting regions, disposed on the pixel definition layer and the plurality of light-emitting layers, and connected to the second power supply line,
Each of the plurality of light emitting elements includes an anode electrode and a cathode electrode facing each other, and a light emitting layer disposed between the anode electrode and the cathode electrode. A substrate including a display area in which a plurality of light-emitting areas are arranged in a first direction and a second direction, a main area including a non-display area disposed around the display area, and a sub-area protruding from one side of the main area;
A plurality of pixel drivers disposed on the substrate, each corresponding to the plurality of light-emitting areas, data lines for transmitting data signals to the plurality of pixel drivers, and in the sub-area of the non-display area. a circuit array layer including demux circuit units disposed in adjacent demux areas;
a display driving circuit disposed in the sub-region of the substrate and supplying data driving signals corresponding to the data lines; and
a light emitting array layer disposed on the circuit array layer and including a plurality of light emitting elements respectively corresponding to the plurality of light emitting regions,
One of the demux circuit units outputs two or more data signals based on one data driving signal,
The circuit array layer further includes a first power supply line and a second power supply line disposed in the non-display area and transmitting first power and second power for driving the light emitting elements, respectively,
A display device wherein a portion of each of the first power supply wiring and the second power supply wiring overlaps the demux circuit units. According to claim 16,
The demux circuit units include a first demux circuit unit disposed in a first demux area adjacent to the sub-region, and a second demux circuit unit disposed in a second demux area adjacent to one side of the first demux area in the first direction. Includes a demux circuit,
The circuit array layer is
a first data input line extending from the sub-region to the first demux region and connected to an input terminal of the first demux circuit unit; and
It further includes a second data input wire connected to the input terminal of the second demux circuit unit,
The second data input wiring is
a main input line extending from the sub-area to the first demux area;
a demux bypass wire disposed in the display area and connected to the main input wire; and
A display device including a bypass additional wiring disposed in the second demultiplex area and connecting the demultiplex bypass wiring and an input terminal of the second demultiplex circuit unit. According to claim 17,
The display area includes a demultiplexed adjacent area adjacent to the demultiplexed area,
The demux bypass wiring is
a first bypass wire disposed in a center adjacent area adjacent to the first demultiplex area among the demultiplex adjacent areas, connected to the main input wire, and extending in the second direction;
a second bypass wiring connected to the first bypass wiring and extending in the first direction; and
It is an area between the center adjacent area and the non-display area among the demultiplexed adjacent areas, is disposed in an edge adjacent area adjacent to the second demultiplexed area, extends in the second direction toward the second demultiplexed area, and is an area between the center adjacent area and the non-display area. 2. A display device including a third bypass wiring connecting the bypass wiring and the bypass additional wiring. According to clause 18,
The display device wherein the bypass additional wiring extends in the second direction. According to clause 18,
The bypass additional wiring is
a first extension connected to the third bypass wiring and extending in the second direction; and
A display device comprising a second extension part connected between the first extension part and an input terminal of the second demux circuit unit and extending in the first direction. According to clause 18,
The circuit array layer further includes a second power auxiliary wire disposed in the display area, extending in the second direction, and electrically connected to the second power supply wire,
One of two or more data wires disposed in an area adjacent to the center and connected to the first demultiplexer circuit is disposed adjacent to the first bypass wire,
A display device in which, of the two or more data wires disposed in an area adjacent to the center and connected to the first demultiplexer circuit, all but one adjacent to the first bypass wire are disposed adjacent to the second power auxiliary wire. According to clause 18,
The circuit array layer further includes a second power auxiliary wire disposed in the display area, extending in the second direction, and electrically connected to the second power supply wire,
One of the two or more data wires disposed in the area adjacent to the edge and connected to the second demux circuit unit is disposed adjacent to the third bypass wire,
Of the two or more data wires disposed in the area adjacent to the edge and connected to the second demux circuit unit, except for one adjacent to the third bypass wire, the remaining data wires are arranged adjacent to the second power auxiliary wire. According to clause 18,
The circuit array layer is
a second power auxiliary wire disposed in the display area, extending in the second direction, and electrically connected to the second power supply wire;
a first power auxiliary wire disposed in the display area, extending in the first direction, and electrically connected to the first power supply wire; and
further comprising a second power sub-wire disposed in a general area other than the demultiplexed area of the display area, extending in the first direction, and electrically connected to the second power supply wire;
The first power auxiliary wire is disposed adjacent to the second bypass wire in the demux adjacent area, and is arranged adjacent to the second power sub wire in the general area. According to clause 23,
The circuit array layer is
first dummy wires spaced apart in parallel on one side of the first bypass wire in the second direction and one side of the third bypass wire in the second direction and extending in the second direction; and
The display device further includes second dummy wires spaced apart from each other in parallel on both sides of the second bypass wire in the first direction and extending in the first direction. According to clause 24,
The first dummy wires or the second dummy wires are electrically connected to the second power supply wire. According to clause 25,
The circuit array layer is
a semiconductor layer on the substrate;
a first conductive layer on the first gate insulating layer covering the semiconductor layer;
a second conductive layer on the second gate insulating layer covering the first conductive layer;
a third conductive layer on the interlayer insulating layer covering the second conductive layer;
a fourth conductive layer on the first planarization layer covering the third conductive layer;
a fifth conductive layer on the second planarization layer covering the fourth conductive layer; and
It is provided with a structure including a third planarization layer covering the fifth conductive layer,
The data wires, the first bypass wire, the third bypass wire, the second power auxiliary wire, and the first dummy wire are made of the fifth conductive layer,
The second bypass wiring, the first power auxiliary wiring, the second dummy wiring, and the second power sub wiring are formed of the fourth conductive layer. According to clause 26,
The light emitting array layer is
a plurality of anode electrodes disposed on the third planarization layer, each corresponding to the plurality of light-emitting areas, and each electrically connected to the plurality of pixel drivers;
a pixel definition layer disposed on the third planarization layer, corresponding to a non-emission area that is a spaced area between the plurality of light emitting areas, and covering edges of each of the plurality of anode electrodes;
a plurality of light-emitting layers respectively corresponding to the plurality of light-emitting regions and respectively disposed on the plurality of anode electrodes; and
A cathode electrode corresponding to the plurality of light-emitting regions, disposed on the pixel definition layer and the plurality of light-emitting layers, and connected to the second power supply wire,
Each of the plurality of light emitting elements includes an anode electrode and a cathode electrode facing each other, and a light emitting layer between the anode electrode and the cathode electrode. According to claim 17,
The sub-region includes a bending region that is transformed into a bent shape, a first sub-region disposed between the main region and one side of the bending region, and a second sub-region disposed between the other side of the bending region,
The circuit array layer is
a first data supply line and a second data supply line disposed in the second sub-region and respectively connected to output terminals of the display driving circuit;
a first data bending wire connected between the first data supply wire and the first data input wire and disposed in the bending area; and
The display device further includes a second data bending wire connected between the second data supply wire and the main input wire and disposed in the bending area.

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