CN117858557A

CN117858557A - Display device

Info

Publication number: CN117858557A
Application number: CN202311222089.1A
Authority: CN
Inventors: 崔允瑄; 崔原硕
Original assignee: Samsung Display Co Ltd
Current assignee: Samsung Display Co Ltd
Priority date: 2022-10-07
Filing date: 2023-09-21
Publication date: 2024-04-09

Abstract

A display device includes a substrate and a circuit layer. The circuit layer includes: a plurality of pixel drivers; a plurality of data lines; a first transmission detour line electrically connected to a first data line among the plurality of data lines and extending in a first direction; and a second transmission detour line adjacent to a second data line among the data lines, extending in the second direction, and electrically connected to the first transmission detour line. The first transmission detour line includes: a first main stream extending in a first direction between a first data line and a second transmission detour line; a first sub-branch extending from the first main stream in the second direction and overlapping a portion of the first data line; and a second sub-branch extending from the first main stream in the second direction and overlapping a portion of the second transmission detour.

Description

Display device

Cross Reference to Related Applications

The present application claims priority and ownership of korean patent application No. 10-2022-012387 filed on 7 of 10 th month 2022 and korean patent application No. 10-2023-0028924 filed on 6 of 3 rd month 2023, the contents of which are incorporated herein by reference in their entirety.

Technical Field

The present disclosure relates to a display device.

Background

With the advancement of information-oriented society, there is an increasing demand for display devices that display images in various ways. For example, the display device is applied to various electronic devices such as a smart phone, a digital camera, a notebook computer, a navigation device, and a smart television.

The display device may include a display panel emitting light for image display and a driver supplying a signal or power for driving the display panel.

The display device may display an image on at least one surface. The display surface of the display device may include a display region in which a plurality of emission regions emitting light for image display are arranged, and a non-display region disposed around the display region.

The display device may include a data line for transmitting data signals to the plurality of emission regions, and a display driving circuit for supplying the data signals to the data line.

Disclosure of Invention

A data supply line for connecting the data line to the display driving circuit is provided in the non-display region. Accordingly, as the number of data lines increases to improve resolution, the width of the arrangement of the increased data supply lines increases, and thus, the width of the non-display region may increase.

In this case, the ratio of the display area on the display surface is reduced, so that the display quality of the display device may be deteriorated. That is, the ratio of the display area on the display surface may have a trade-off relationship with the resolution.

Features of the present disclosure provide a display device capable of reducing the width of a non-display area without affecting resolution.

In an embodiment of the present disclosure, there is provided a display device including: a substrate including a main region including a display region in which an emission region is arranged and a non-display region disposed around the display region; the circuit layer is arranged on the substrate; and a light emitting element layer disposed on the circuit layer and including light emitting elements respectively corresponding to the emission regions. The detour area on the display area side includes: a detour middle region, the detour middle region being centrally located; a first detour side region parallel to the detour middle region in the first direction and in contact with the non-display region; and a second detour side region disposed between the detour intermediate region and the first detour side region. The circuit layer includes: pixel drivers corresponding to the light emitting regions, respectively, and electrically connected to the light emitting elements of the light emitting element layer; a data line extending in a second direction crossing the first direction and transmitting a data signal to the pixel driver; a first transmission detour line electrically connected to a first data line disposed in the first detour side region and extending in the first direction among the data lines; and a second transmission detour line adjacent to a second data line, which is disposed in the second detour side region, extends in the second direction, and is electrically connected to the first transmission detour line, among the data lines. The first transmission detour line includes: a first main stream extending in a first direction between the first data line and the second transmission detour line; a first sub-branch provided in the first detour side region, extending from the first main flow in the second direction, and overlapping a portion of the first data line; and a second sub-branch provided in the second detour side region and extending from the first main flow in the second direction and overlapping with a part of the second transmission detour line.

In an embodiment, each of the pixel drivers includes a data connection electrode electrically connected to one of the data lines through the data connection hole. The pixel driver includes a first pixel driver adjacent to a first sub-branch of the first transmission detour. The first data line includes: a first main extension extending in a second direction; a first sub-protrusion adjacent to the first pixel driver and protruding from the first main extension and overlapping the first sub-branch; and a second sub-protrusion adjacent to the first pixel driver and protruding from the first main extension and overlapping the data connection hole of the first pixel driver. The first transmission detour line is electrically connected to the first data line through a first detour connection hole overlapping the first sub-branch and the first sub-protrusion. The first detour connection hole is spaced apart from an intersection between the first main stream of the first transmission detour line and the first main extension of the first data line.

In an embodiment, the pixel driver further includes a second pixel driver disposed in the first detour side region, electrically connected to the first data line, and spaced apart from the first pixel driver. The first data line further includes a third sub-protrusion and a fourth sub-protrusion adjacent to the second pixel driver and protruding from the first main extension. The third sub-protrusion overlaps the first dummy hole. The fourth sub-protrusion overlaps the data connection electrode of the second pixel driver.

In an embodiment, the data line and the second transmission detour line are disposed on a via layer covering the first transmission detour line and the data connection electrode. The first bypass connection hole, the second bypass connection hole and the first dummy hole penetrate through the via layer.

In an embodiment, the first dummy hole overlaps the dummy electrode covered with the via layer.

In an embodiment, the pixel driver further includes a third pixel driver disposed in the second detour side region adjacent to the second sub-branch of the first transfer detour line, electrically connected to the second data line, and disposed in parallel with the first pixel driver in the first direction. The second data line includes: a second main extension extending in a second direction; a fifth sub-protrusion adjacent to the third pixel driver and protruding from the second main extension and disposed in parallel with the first sub-protrusion of the first data line in the first direction; and a sixth sub-protrusion adjacent to the third pixel driver, protruding from the second main extension, disposed in parallel with the second sub-protrusion of the first data line in the first direction and overlapping the data connection electrode of the third pixel driver. The fifth sub-protrusion overlaps the second dummy hole penetrating the via layer.

In an embodiment, the second transmission detour comprises: a third main extension extending in a second direction; a seventh sub-protrusion adjacent to the third pixel driver, protruding from the third main extension, facing the fifth sub-protrusion of the second data line, and overlapping the second sub-branch; and an eighth sub-protrusion adjacent to the third pixel driver, protruding from the third main extension and facing the sixth sub-protrusion of the second data line. The first transmission detour is electrically connected to the second transmission detour through a second detour connection hole overlapping the second sub-branch and the seventh sub-protrusion. The eighth sub-protrusion overlaps the third dummy hole penetrating through the hole layer.

In an embodiment, the circuit layer further comprises: a first power supply line and a second power supply line that are disposed in the non-display region and transmit first power and second power for driving the light emitting element, respectively; a first power auxiliary line disposed in the display region, extending in the first direction, and electrically connected to the first power line; first dummy lines adjacent to the first power auxiliary lines and extending in a first direction, respectively; and second dummy lines respectively adjacent to the data lines and extending in the second direction. The first dummy line includes a first auxiliary line electrically connected to the second power supply line and a first transmission detour line. The second dummy line includes a second auxiliary line electrically connected to the second power supply line and a second transmission detour line. One of the first auxiliary lines includes: a second main flow extending in the first direction; and a third sub-branch extending from the second main flow in the second direction. Each second auxiliary line includes: a fourth main extension extending in the second direction; and a ninth sub-protrusion and a tenth sub-protrusion protruding from the fourth main extension to each pixel driver. Some of the ninth sub-protrusions of the second auxiliary line overlap the third sub-branch. The other of the ninth sub-protrusion of the second auxiliary line and the tenth sub-protrusion of the second auxiliary line overlaps with the fourth dummy hole penetrating the via layer. The first auxiliary line is electrically connected to the second auxiliary line through an auxiliary connection hole overlapping the third sub-branch and the ninth sub-protrusion.

In an embodiment, the first dummy hole, the second dummy hole, the third dummy hole, and the fourth dummy hole overlap the dummy electrode covered with the via layer, respectively.

In an embodiment, the circuit layer has a structure including: a semiconductor layer on the substrate; a first conductive layer on the first gate insulating layer covering the semiconductor layer; a second conductive layer on the second gate insulating layer covering the first conductive layer; a third conductive layer on the interlayer insulating layer covering the second conductive layer; a fourth conductive layer on the first planarization layer covering the third conductive layer; a fifth conductive layer on the second planarization layer covering the fourth conductive layer; and a third planarization layer covering the fifth conductive layer. The fourth conductive layer includes a first power auxiliary line, a first dummy line, and a dummy electrode. The fifth conductive layer includes a data line and a second dummy line. The via layer includes a second planarizing layer.

In an embodiment, the substrate further comprises an aperture area surrounded by the display area. The data line further includes a hole intersecting data line intersecting the hole region. The hole intersecting data line includes: a first hole adjacent portion disposed adjacent to one side of the hole region in the second direction; and a second hole adjacent portion provided adjacent to an opposite side of the hole region in the second direction. The first dummy line further includes: a first hole detour electrically connected to a first hole adjacent portion of the hole-intersecting data line; and a second hole detour electrically connected to a second hole adjacent portion of the hole-intersecting data line. The second dummy line further includes a third hole detour electrically connecting the first hole detour and the second hole detour. The first hole detour line includes: a third main flow extending in the first direction between the first hole adjacent portion and the third hole detour; a fourth sub-branch extending from the third main flow in the second direction and overlapping a portion of the first hole adjacent portion; and a fifth sub-branch extending from the third main flow in the second direction and overlapping with a part of the third hole detour.

In an embodiment, the second aperture detour comprises: a fourth main flow extending in the first direction between the second hole adjacent portion and the third hole detour; a sixth sub-branch extending from the fourth main flow in the second direction and overlapping with a part of the third hole detour; and a seventh sub-branch extending from the fourth main flow in the second direction and overlapping with a portion of the second hole adjacent portion.

In an embodiment, the display device further includes: and a display driving circuit disposed in a sub-region protruding from one side of the main region of the substrate in the second direction and outputting a data signal of each data line. The circuit layer further comprises: and data supply lines disposed in the non-display region and the sub-region, respectively electrically connected to output terminals of the display driving circuit and transmitting a data signal of each data line to the display region. Among the data supply lines, a first data supply line for transmitting a data signal of the first data line is connected to a second transmission detour line. Among the data supply lines, a second data supply line for transmitting a data signal of the second data line is connected to the second data line.

In an embodiment, the first main stream of the first transmission detour is arranged closer to the first sub-protrusion in the second direction between the first sub-protrusion and the second sub-protrusion of the first data line.

In an embodiment, the first main stream of the first transmission detour is arranged in the second direction between the first sub-protrusion and the second sub-protrusion of the first data line.

In an embodiment of the present disclosure, there is provided a display device including: a substrate including a main region including a display region in which an emission region is arranged and a non-display region disposed around the display region; a circuit layer disposed on the substrate and including pixel drivers corresponding to the emission regions, respectively; and a light emitting element layer disposed on the circuit layer and including light emitting elements respectively corresponding to the emission regions. The circuit layer includes: pixel drivers corresponding to the light emitting regions, respectively, and electrically connected to the light emitting elements of the light emitting element layer; a data line for transmitting a data signal to the pixel driver; a first dummy line extending in a first direction crossing the data line; and second dummy lines extending in a second direction parallel to the data lines and respectively adjacent to the data lines. The data line and the second dummy line are disposed on the via layer covering the first dummy line. One of the pixel drivers is adjacent to one of the data lines and one of the second dummy lines. Each of one of the data lines and one of the second dummy lines includes: a main extension extending in a second direction; and a pair of sub-protrusions protruding from the main extension, adjacent to one of the pixel drivers and overlapping the via penetrating the via layer.

In an embodiment, in the display area, the detour area adjacent to the sub-area includes: a detour intermediate region disposed at the center in the first direction; a first detour side region parallel to the detour middle region in the first direction and in contact with the non-display region; and a second detour side region disposed between the detour intermediate region and the first detour side region. The data line includes: a first data line disposed in the first detour side region; and a second data line disposed in the second detour side region. The first dummy line includes a first transmission detour line electrically connected to the first data line. The second dummy line includes a second transmission detour line adjacent to the second data line and electrically connected to the first transmission detour line. The first transmission detour line includes: a first main stream extending in a first direction between the first data line and the second transmission detour line; a first sub-branch provided in the first detour side region, extending from the first main flow in the second direction and overlapping a portion of the first data line; and a second sub-branch provided in the second detour side region, extending from the first main flow in the second direction and overlapping with a part of the second transmission detour line.

In an embodiment, the circuit layer further comprises: a first power supply line and a second power supply line that are disposed in the non-display region and transmit first power and second power for driving the light emitting element, respectively; and first power auxiliary lines disposed in the display region, extending in the first direction, adjacent to the first dummy lines, respectively, and electrically connected to the first power supply lines. The first dummy line includes a first auxiliary line electrically connected to the second power supply line and a first transmission detour line. The second dummy line includes a second auxiliary line electrically connected to the second power supply line and a second transmission detour line. One of the first auxiliary lines includes: a second main flow extending in the first direction; and a third sub-branch extending from the second main flow in the second direction and overlapping a portion of one of the second auxiliary lines.

In an embodiment, each of the pixel drivers includes a data connection electrode electrically connected to one of the data lines through the data connection hole. Among the vias, the remaining vias except some of the vias overlapping the data connection electrode, the first sub-branch, the second sub-branch, and the third sub-branch overlap the dummy electrode covered with the via layer, respectively.

In an embodiment, the substrate further comprises an aperture region surrounded by the display region. The data line further includes a hole intersecting data line intersecting the hole region. The hole intersecting data line includes: a first hole adjacent portion disposed adjacent to one side of the hole region in the second direction; and a second hole adjacent portion provided adjacent to an opposite side of the hole region in the second direction. The first dummy line further includes: a first hole detour electrically connected to a first hole adjacent portion of the hole-intersecting data line; and a second hole detour electrically connected to a second hole adjacent portion of the hole-intersecting data line. The second dummy line further includes a third hole detour electrically connecting the first hole detour and the second transmission detour. The first hole detour line includes: a third main flow extending in the first direction between the first hole adjacent portion and the third hole detour; a fourth sub-branch extending from the third main flow in the second direction and overlapping a portion of the first hole adjacent portion; and a fifth sub-branch extending from the third main flow in the second direction and overlapping with a part of the third hole detour.

In an embodiment, the pair of sub-protrusions includes a first sub-protrusion and a second sub-protrusion, and the first main stream of the first transmission detour line is disposed closer to the first sub-protrusion in the second direction between the first sub-protrusion and the second sub-protrusion of the first data line.

In an embodiment, the pair of sub-protrusions includes a first sub-protrusion and a second sub-protrusion, and the first main stream of the first transmission detour line is disposed between the first sub-protrusion and the second sub-protrusion of the first data line in the second direction.

In an embodiment, a display device in an embodiment includes: a substrate having a main region including a display region and a non-display region disposed around the display region; the circuit layer is arranged on the substrate; and a light emitting element layer provided on the circuit layer.

In an embodiment, a detour region on a display region side of a substrate includes: a detour middle region located at the center; a first detour side region parallel to the detour middle region in the first direction and in contact with the non-display region; and a second detour side region disposed between the detour intermediate region and the first detour side region.

In an embodiment, a circuit layer includes: pixel drivers corresponding to the light emitting regions, respectively; a data line for transmitting a data signal to the pixel driver; a first transmission detour line electrically connected to a first data line disposed in the first detour side region and extending in the first direction among the data lines; and a second transmission detour line adjacent to the second data line, which is provided in the second detour side region, extends in the second direction, and is electrically connected to the first transmission detour line, among the data lines.

In an embodiment, the data signal of each data line may be supplied by a display driving circuit disposed in a sub-region protruding from one side of the main region of the substrate. For this, the circuit layer may include data supply lines connected to output terminals of the display driving circuits, respectively, disposed in the non-display region and extending to the display region.

In addition, a portion of the non-display region in contact with the first detour side region may include a shape curved along a point at which both sides of the substrate edge meet.

In an embodiment, the first data line of the first detour side region adjacent to the non-display region may be electrically connected to the second transmission detour line of the second detour side region adjacent to the detour middle region by an extended first transmission detour line in the first direction.

In addition, among the data supply lines, a first data supply line for transmitting a data signal of the first data line may be electrically connected to a second transmission detour line of the second detour side region. Accordingly, the first data line may be electrically connected to the first data supply line through the first transmission detour line and the second transmission detour line.

In other words, even when the first data supply line extends to the second detour side region instead of the first detour side region, it can be electrically connected to the first data line of the first detour side region through the first transmission detour line and the second transmission detour line.

Accordingly, a portion adjacent to the first detour side region and including the non-display region of the curved shape may have a smaller width because the first data supply line is not disposed therein.

Accordingly, the width of the non-display area can be reduced without reducing the number of data lines.

In an embodiment, the first transmission detour comprises: a first main stream extending in a first direction between the first data line and the second transmission detour line; a first sub-branch provided in the first detour side region, extending from the first main flow in the second direction and overlapping a portion of the first data line; and a second sub-branch provided in the second detour side region, extending from the first main flow in the second direction and overlapping with a part of the second transmission detour line.

In other words, in the first transmission detour line, the first main stream extending in the first direction between the first data line and the second transmission detour line does not overlap with the first data line and the second transmission detour line.

In addition, the first transmission detour line may be electrically connected to the first data line and the second transmission detour line by the first sub-branch and the second sub-branch extending in the second direction. Thus, an overlap region between the first transmission detour and each of the first data line and the second transmission detour may be spaced apart from an end of the first main stream.

Accordingly, the increase in visibility of the end portion of the first main stream can be prevented by the first detour connection hole and the second detour connection hole defined in the overlapping region between the first transmission detour line and each of the first data line and the second transmission detour line.

Accordingly, since the visibility of the first transmission detour line and the second transmission detour line for reducing the width of the non-display region can be prevented from increasing, deterioration in the display quality of the display device due to the presence of the first transmission detour line and the second transmission detour line can be reduced.

Effects of the present disclosure are not limited to the above-described effects, and various other effects are included in the specification.

Drawings

The above and other features of the present disclosure will become more apparent by describing in detail embodiments thereof with reference to the accompanying drawings in which:

fig. 1 is a perspective view showing an embodiment of a display device;

fig. 2 is a plan view illustrating the display device of fig. 1;

FIG. 3 is a cross-sectional view showing a plane taken along line A-A' of FIG. 2;

fig. 4 is a plan view showing main regions and sub-regions of the display device of fig. 1;

fig. 5 is a layout diagram showing a portion B of fig. 4;

Fig. 6 is a layout diagram illustrating the data line, the first dummy line, the second dummy line, and the first power auxiliary line in part C of fig. 4;

FIG. 7 is a cross-sectional view in the plane taken along line I-I' of FIG. 6;

FIG. 8 is a cross-sectional view taken in the plane of line J-J' of FIG. 6;

fig. 9 is a layout view of the data line, the first dummy line, the second dummy line, and the first power auxiliary line in part D of fig. 4;

fig. 10 is a layout diagram illustrating the data line, the first dummy line, the second dummy line, and the first power auxiliary line in part E of fig. 4;

FIG. 11 is an equivalent circuit diagram illustrating one embodiment of one pixel driver of the circuit layer of FIG. 3;

fig. 12 is a plan view showing a portion G of fig. 5 according to the first embodiment;

fig. 13 is a plan view showing the semiconductor layer, the first conductive layer, the second conductive layer, and the third conductive layer in the plan view of fig. 12;

fig. 14 is a plan view showing the fourth conductive layer and the fifth conductive layer in the plan view of fig. 12;

FIG. 15 is a cross-sectional view taken along line K-K' of FIG. 12;

fig. 16 is a plan view showing the fourth conductive layer and the fifth conductive layer in part H of fig. 5 according to the first embodiment;

fig. 17 is a plan view showing the fourth conductive layer and the fifth conductive layer in part G of fig. 5 according to the second embodiment;

Fig. 18 is a plan view showing the fourth conductive layer and the fifth conductive layer in part G of fig. 5 according to the third embodiment;

fig. 19 is a layout diagram showing a portion F of fig. 4 according to a fourth embodiment;

fig. 20 is a layout diagram showing data lines, first dummy lines, and second dummy lines in a portion of each of the first hole vicinity side region and the second hole vicinity side region of fig. 19; and

fig. 21 is a sectional view showing a plane taken along a line L-L' of fig. 20.

Detailed Description

Embodiments will now be described more fully hereinafter with reference to the accompanying drawings. However, the embodiments may be provided in different forms and should not be construed as limiting. Like reference numerals refer to like components throughout the disclosure. In the attached drawings, the thickness of layers and regions may be exaggerated for clarity.

For the purpose of describing embodiments of the present disclosure, some components not relevant to the present description may not be provided.

It will also be understood that when a layer or substrate is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. In contrast, when an element is referred to as being "directly on" another element, there may be no intervening elements present.

Further, the phrase "in a plan view" means when the object portion is viewed from above, and the phrase "in a schematic cross-sectional view" means when a schematic cross-section taken by vertically cutting the object portion is viewed from the side. The term "overlapping" or "overlapping" means that a first object may be above or below or to one side of a second object, and vice versa. In addition, the term "overlapping" may include "stacked," "facing or facing," "extending over," "covering" or "partially covering," or any other suitable term as would be appreciated and understood by one of ordinary skill in the art. The term "non-overlapping" may include meanings such as "separate" or "spaced" or "offset," as well as any other suitable terms that will be appreciated and understood by those of ordinary skill in the art. The terms "facing" and "facing" may mean that a first object may be directly or indirectly opposite a second object. In the case where the third object is interposed between the first object and the second object, the first object and the second object may be understood to be indirectly opposite to each other while still facing each other.

For ease of description, spatially relative terms "below … …," "below … …," "lower," "above … …," or "upper" and the like may be used herein to describe an element or component's relationship to another element or component as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, where the apparatus shown in the figures is turned over, elements located "below" or "beneath" another apparatus could be oriented "above" the other apparatus. Thus, the illustrative term "below … …" may include both a lower position and an upper position. The device may also be oriented in other directions and the spatially relative terms may thus be interpreted differently depending on the orientation.

When an element is referred to as being "connected" or "coupled" to another element, it can be "directly connected" or "directly coupled" to the other element or be "electrically connected" or "electrically coupled" to the other element through one or more intervening elements between the element and the other element. It will be further understood that the terms "comprises," "comprising," "has," "including," "having," "contains," "containing," and/or "including" when used, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of other features, integers, steps, operations, elements, components, and/or groups thereof.

It will be understood that, although the terms "first," "second," or "third," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another or to facilitate description and explanation thereof. For example, when "a first element" is discussed in the specification, it can be described as a "second element" or a "third element", and "second element" and "third element" can be described in a similar manner without departing from the teachings herein.

The term "about" or "approximately" as used herein includes the values in view of the measurement in question and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system), and refers to within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art. For example, "about" may mean within one or more standard deviations or within ±30%, ±20%, ±10% or ±5% of the value.

In the description and claims, for the purposes of their meaning and explanation, the term "and/or" is intended to include any combination of the terms "and" or ". For example, "a and/or B" may be understood to mean "a", "B" or "a and B". The terms "and" or "may be used in a combined or separate sense and are to be understood as being equivalent to" and/or ". In the description and claims, for the purposes of their meaning and explanation, the phrase "at least one" is intended to include the meaning of "at least one selected from the group of … …". For example, "at least one of a and B" may be understood to mean "a", "B" or "a and B".

Unless otherwise defined or implied, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

Fig. 1 is a perspective view showing an embodiment of a display device. Fig. 2 is a plan view illustrating the display device of fig. 1. Fig. 3 is a cross-sectional view showing a plane taken along line A-A' of fig. 2.

Referring to fig. 1, a display device 10 is a device for displaying a moving image or a still image. The display device 10 may be used as a display screen for various devices such as televisions, notebook computers, monitors, billboards, and internet of things ("IoT") devices, as well as portable electronic devices such as mobile phones, smart phones, tablet personal computers ("PCs"), smartwatches, wristwatch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players ("PMPs"), navigation devices, and ultra mobile PCs ("UMPCs").

The display device 10 may be a light emitting display device such as an organic light emitting display using organic light emitting diodes, a quantum dot light emitting display including a quantum dot light emitting layer, an inorganic light emitting display including an inorganic semiconductor, or a micro light emitting display using micro light emitting diodes ("LEDs") or nano light emitting diodes ("LEDs"). In the following description, it is assumed that the display device 10 is an organic light emitting display device. However, the present disclosure is not limited thereto, and may be applied to a display device including an organic insulating material, an organic light emitting material, and a metal material.

The display device 10 may be formed in a plane, but is not limited thereto. In an embodiment, for example, the display device 10 may include a curved portion formed at left and right ends and having a constant curvature or a varying curvature. In addition, the display device 10 may be flexibly formed such that it may be bent, folded, or curled.

As shown in fig. 1, the display device 10 may include a display panel 100, a display driving circuit 200, and a circuit board 300.

The display panel 100 has a main area MA including a display area DA for displaying emitted light of an image and a non-display area NDA as a peripheral area surrounding the display area DA.

Referring to fig. 2, the display panel 100 of the display device 10 may include a main area MA and a sub-area SBA protruding from one side of the main area MA.

The main area MA may include a display area DA at the center and a non-display area NDA surrounding the display area DA.

Further, in some embodiments, the main area MA may further include a hole area HLA surrounded by the display area DA. A display device including a hole region HLA according to a fourth embodiment will be described later with reference to fig. 19 to 21.

The sub-area SBA may be an area protruding from the non-display area NDA of the main area MA to one side in the second direction DR 2.

Because a portion of the sub-area SBA is deformed to be bent, another portion of the sub-area SBA may be disposed on the rear surface of the display panel 100.

Fig. 2 shows a situation in which a part of the sub-area SBA is bent.

A plurality of emission areas EA for emitting light having a corresponding brightness are arranged in the display area DA.

In a plan view, the display area DA may be formed in a quadrangular shape (e.g., a rectangular shape having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR 1). The angle at which the short side in the first direction DR1 and the long side in the second direction DR2 intersect may be rounded to have a predetermined curvature, or may be a right angle. The planar shape of the display area DA is not limited to a quadrangular shape (e.g., a rectangular shape), and may be formed in another polygonal shape, a circular shape, or an elliptical shape.

The display area DA may occupy a large portion of the main area MA. The display area DA may be disposed at the center of the main area MA.

The display area DA may include a plurality of emission areas EA arranged side by side. In addition, the display area DA may further include a non-emission area as a separation area between the plurality of emission areas EA.

The plurality of emission areas EA may be arranged side by side in the first direction DR1 and the second direction DR 2.

Each of the plurality of emission areas EA may have a diamond-shaped planar shape or a quadrangular (e.g., rectangular) planar shape. However, this is merely an illustrative embodiment, and the planar shape of the plurality of emission areas EA in the embodiment is not limited to the shape shown in fig. 2. That is, in a plan view, the plurality of emission areas EA may have a polygonal shape such as a diamond shape or a hexagonal shape, a circular shape, or an elliptical shape, in addition to a quadrangular shape (e.g., a rectangular shape).

The plurality of emission areas EA may include a first emission area EA1 that emits light of a first color in a predetermined wavelength band, a second emission area EA2 that emits light of a second color in a wavelength band lower than the wavelength band of the first color, and a third emission area EA3 that emits light of a third color in a wavelength band lower than the wavelength band of the second color.

In an embodiment, for example, the first color may be red having a wavelength band of about 600 nanometers (nm) to about 750 nm. For example, the second color may be green having a wavelength band of about 480nm to about 560 nm. The third color may be blue having a wavelength band of about 370nm to about 460 nm.

As shown in fig. 2, the first and third emission areas EA1 and EA3 may be alternately arranged in at least one of the first and second directions DR1 and DR 2. Further, the second emission areas EA2 may be arranged side by side in at least one of the first direction DR1 and the second direction DR 2.

The plurality of pixels PX displaying the corresponding luminance and color may include a plurality of emission areas EA.

Each of the plurality of pixels PX may be a basic unit for displaying various colors including white with a predetermined brightness.

Each of the plurality of pixels PX may include at least one first emission area EA1, at least one second emission area EA2, and at least one third emission area EA3 adjacent to each other. Accordingly, each of the plurality of pixels PX may display brightness and color obtained by mixing light emitted from at least one first, at least one second, and at least one third emission area EA1, EA2, and EA3 adjacent to each other.

Although fig. 2 shows a case where the plurality of emission areas EA have the same area, this is merely an exemplary embodiment. That is, in another embodiment, the third emission area EA3 may have a maximum area and the second emission area EA2 may have a minimum area.

Further, although fig. 2 shows a case where a plurality of emission areas EA are arranged side by side in the first direction DR1 and the second direction DR2, this is only an exemplary embodiment. In another embodiment, the second emission area EA2 may be adjacent to the first and third emission areas EA1 and EA3 in a diagonal direction intersecting the first and second directions DR1 and DR 2.

Referring to fig. 3, and also referring to fig. 2, the display panel 100 of the display device 10 includes: a substrate 110, the substrate 110 having a main area MA including a display area DA in which an emission area EA is arranged and a non-display area NDA disposed around the display area DA; a circuit layer 120, the circuit layer 120 being disposed on the substrate 110; and a light emitting element layer 130, the light emitting element layer 130 being disposed on the circuit layer 120.

The substrate 110 may further include a sub-region SBA protruding from one side of the main region MA.

The light emitting element layer 130 includes light emitting elements LEL (refer to fig. 11 and 15) corresponding to the emission regions EA, respectively.

The circuit layer 120 includes: a pixel driver PXD (refer to fig. 5, 6 and 11) corresponding to the emission area EA and electrically connected to the light emitting elements LEL of the light emitting element layer 130, respectively; and a data line DL (refer to fig. 5, 6 and 11) extending in the second direction DR2, and transmitting a data signal Vdata (refer to fig. 11) to the pixel driver PXD.

The display device 10 may further include a display driving circuit 200 disposed in the sub-region SBA of the substrate 110. The display driving circuit 200 may output the data signal Vdata of the data line DL.

The circuit layer 120 may further include data supply lines DSPL (refer to fig. 5) disposed in the non-display area NDA and the sub-area SBA, the data supply lines DSPL being electrically connected to output terminals of the display driving circuit 200, respectively, and for transmitting the data signal Vdata of each data line DL to the display area DA.

The display driving circuit 200 may be provided as an integrated circuit ("IC") and disposed (e.g., mounted) on the second sub-region SB2 of the substrate 110 by a chip on glass ("COG") method, a chip on plastic ("COP") method, or an ultrasonic bonding method. However, this is merely an illustrative embodiment, and the arrangement of the display driving circuit 200 is not limited to that shown in fig. 3.

In an embodiment, the display driving circuit 200 may be attached to the circuit board 300, for example, by a chip on film ("COF") method.

The circuit board 300 may be bonded to the signal pads SPD (refer to fig. 4) provided in the sub-region SBA of the substrate 110.

In an embodiment, for example, using a low-resistance high-reliability material such as SAP or an anisotropic conductive film, the circuit board 300 may be attached to and electrically connected to the signal pads SPD of the sub-area SBA (refer to fig. 4).

The pixel driver PXD and the display driving circuit 200 of the display area DA may receive digital video data, timing signals, and driving voltages from the circuit board 300.

The circuit board 300 may be a printed circuit board such as a flexible printed circuit board or a flexible film such as a COF.

In addition, the display panel 100 of the display device 10 may further include: an encapsulation layer 140 covering the light emitting element layer 130; and a sensor electrode layer 150 disposed on the encapsulation layer 140.

The substrate 110 may include or consist of an insulating material such as a polymer resin. In an embodiment, for example, the substrate 110 may include or consist of polyimide. The substrate 110 may be a flexible substrate that may be bent, folded, or rolled.

In alternative embodiments, the substrate 110 may include or consist of an insulating material such as glass or the like.

As will be described later with reference to fig. 15, the circuit layer 120 may have a structure including: the semiconductor layer SEL (see fig. 13) on the substrate 110, the first conductive layer CDL1 (see fig. 13) on the first gate insulating layer 122 covering the semiconductor layer SEL, the second conductive layer CDL2 (see fig. 13) on the second gate insulating layer 123 covering the first conductive layer CDL1, the third conductive layer CDL3 (see fig. 13) on the interlayer insulating layer 124 covering the second conductive layer CDL2, the fourth conductive layer CDL4 (see fig. 14) on the first planarization layer 125 covering the third conductive layer CDL3, the fifth conductive layer CDL5 (see fig. 14) on the second planarization layer 126 covering the fourth conductive layer CDL4, and the third planarization layer 127 covering the fifth conductive layer CDL 5.

The encapsulation layer 140 is disposed on the circuit layer 120, corresponds to the main region MA, and covers the light emitting element layer 130.

The encapsulation layer 140 may include a structure in which two or more inorganic layers and at least one organic layer are alternately stacked on the light emitting element layer 130.

The sensor electrode layer 150 may be disposed on the encapsulation layer 140 and may correspond to the main area MA. The sensor electrode layer 150 may include a touch electrode for sensing a touch of a person or an object.

In addition, the display device 10 may further include a cover window (not shown) disposed on the sensor electrode layer 150. The cover window may be attached to the sensor electrode layer 150 by a transparent adhesive member such as an optically clear adhesive ("OCA") film or an optically clear resin ("OCR") film. The cover window may comprise or consist of an inorganic material such as glass or an organic material such as a plastic or polymer material. Due to the cover window, the sensor electrode layer 150, the encapsulation layer 140, the light emitting element layer 130, and the circuit layer 120 can be protected from electrical and physical effects on the display surface.

In addition, the display device 10 may further include an anti-reflection member (not shown) disposed between the sensor electrode layer 150 and the cover window. The anti-reflection member may be a polarizing film or a color filter. The anti-reflection member blocks external light reflected from the sensor electrode layer 150, the encapsulation layer 140, the light emitting element layer 130, the circuit layer 120, and interfaces thereof, so that the visibility of an image in the display device 10 can be prevented from being lowered.

The display device 10 may further include a touch driving circuit 400 for driving the sensor electrode layer 150.

The touch driving circuit 400 may be provided as an IC. The touch driving circuit 400 may be electrically connected to the sensor electrode layer 150 while being disposed (e.g., mounted) on the circuit board 300.

In an alternative embodiment, similar to the display driving circuit 200, the touch driving circuit 400 may be disposed (e.g., mounted) on the sub-region SBA of the substrate 110.

The touch driving circuit 400 may apply a touch driving signal to a plurality of driving electrodes provided on the sensor electrode layer 150, receive a touch sensing signal of each of a plurality of touch nodes through the plurality of sensing electrodes, and sense a charge variation amount of a mutual capacitance based on the touch sensing signal.

That is, the touch driving circuit 400 may determine whether a touch of a user has been made, whether the user is near, or the like, according to a touch sensing signal of each of the plurality of touch nodes. The user's touch refers to direct contact of an object, such as a pen or a user's finger, with the front surface of the display device 10. The proximity of the user means that an object such as a pen or a finger of the user is disposed away from the front surface of the display device 10 (such as hovering).

Fig. 4 is a plan view showing main regions and sub-regions of the display device of fig. 1.

Referring to fig. 4, a display panel 100 of a display device 10 (refer to fig. 1) in an embodiment includes: a main area MA including a display area DA and a non-display area NDA; and a sub-area SBA protruding from one side of the main area MA.

The display area DA includes an emission area EA (refer to fig. 15) arranged in the first direction DR1 and the second direction DR 2. In addition, the display area DA may further include a non-emission area NEA (refer to fig. 15) as a separation area between the emission areas EA.

The display area DA may include: a detour area DEA, which is a portion oppositely adjacent to the sub-area SBA on one side of the second direction DR 2; a regular region GA, which is the rest except for the detour region DEA.

The detour area DEA includes: a detouring middle area MDDA centrally arranged in the first direction DR 1; a first detour side area SDA1 parallel to the detour middle area MDDA in the first direction DR1 and in contact with the non-display area NDA; and a second detour side area SDA2 disposed between the detour middle area MDDA and the first detour side area SDA 1.

The first bypass side area SDA1 and the second bypass side area SDA2 may be disposed between the bypass middle area MDDA and the non-display area NDA on opposite sides of the bypass middle area MDDA in the first direction DR 1.

The portion of the non-display area NDA contacting the first bypass-side area SDA1 may include a shape bent along a point where both sides of the edge of the substrate 110 meet.

The general region GA may include: a normal middle area GMA, a detour middle area MDDA connected to the detour area DEA in the second direction DR 2; a first regular side area GSA1 connected to a first detour side area SDA1 of the detour area DEA in the second direction DR 2; and a second regular side area GSA2 connected to the second detour side area SDA2 of the detour area DEA in the second direction DR 2.

In the embodiment of fig. 4, the hole area HLA may be disposed in the conventional intermediate area GMA. However, this is only an exemplary embodiment, and the hole area HLA may be disposed at any position in the display area DA. In alternative embodiments, the hole area HLA may be disposed in the non-display area NDA and the display area DA.

In the non-display area NDA, the circuit layer 120 may further include a scan driving circuit SCDA disposed adjacent to at least one side of the display area DA in the first direction DR 1. The scan driving circuit SCDA may supply a corresponding gate signal to the gate line disposed in the display area DA and extending in the first direction DR 1.

In an embodiment, for example, the display driving circuit 200 or the circuit board 300 (refer to fig. 3) may supply a scan control signal to the scan driving circuit SCDA based on digital video data and a timing signal.

The sub-region SBA may include a folded region BA deformed to be folded and first and second sub-regions SB1 and SB2 respectively contacting opposite sides of the folded region BA.

The first sub-region SB1 is disposed between the main region MA and the folded region BA. One side of the first sub-area SB1 may contact the non-display area NDA of the main area MA, and the opposite side of the first sub-area SB1 may contact the folded area BA.

The second sub-region SB2 is spaced apart from the main region MA, the folded region BA is interposed between the second sub-region SB2 and the main region MA, and the second sub-region SB2 faces the bottom surface of the substrate 110 by being deformed into the folded region BA. That is, the second sub-region SB2 may overlap the main region MA in the third direction (also referred to as thickness direction) DR3 of the substrate 110 due to the bending region BA deformed to be bent.

One side of the second sub-region SB2 may contact the bending region BA. The opposite side of the second sub-region SB2 may contact a portion of the edge of the substrate 110.

The display driving circuit 200 may be disposed in the second sub-region SB2.

In addition, the signal pads SPD bonded to the circuit board 300 may also be provided in the second sub-region SB 2.

Fig. 5 is a layout diagram showing a portion B of fig. 4.

As described above with reference to fig. 4, the detour area DEA on one side of the display area DA includes: a detour middle area MDDA located in the center; a first detour side area SDA1 parallel to the detour middle area MDDA in the first direction DR1 and in contact with the non-display area NDA; and a second detour side area SDA2 disposed between the detour middle area MDDA and the first detour side area SDA 1.

Referring to fig. 5, and also to fig. 3, 4 and 15, the circuit layer 120 of the display panel 100 of the display device 10 in the embodiment includes pixel drivers PXD (refer to fig. 6) respectively corresponding to the emission areas EA (refer to fig. 2), data lines DL extending in the second direction DR2 and transmitting data signals Vdata (refer to fig. 11) to the pixel drivers PXD, first dummy lines DML1 extending in a first direction DR1 crossing the data lines DL, and second dummy lines DML2 extending in a second direction DR2 parallel to and adjacent to the data lines DL.

Although not shown in detail in fig. 5, the circuit layer 120 may further include: the first and second power supply lines VDSPL and VSSPL extending from the second sub-region SB2, provided in the non-display region NDA and for transmitting first and second power ELVDD (refer to fig. 11) and ELVSS (refer to fig. 11) for driving the light emitting elements LEL of the light emitting element layer 130, respectively; and a first power auxiliary line VDAL (refer to fig. 6) disposed in the display area DA, extending in the first direction DR1, and electrically connected to the first power supply line VDSPL.

The first and second power supply lines VDSPL and VSSPL may be electrically connected to the signal pads SPD disposed in the second sub-region SB2 of the sub-region SBA and may extend to the non-display region NDA.

The first and second power lines VDSPL and VSSPL may be disposed to surround at least a portion of the display area DA.

The first dummy lines DML1 may be adjacent to the first power auxiliary lines VDAL, respectively.

The first dummy line DML1 may include: a first transmission detour line TDEL1 electrically connected to the first data line DL1 provided in the first detour side area SDA1 among the data lines DL; and a first auxiliary line ASL1 electrically connected to the second power line VSSPL.

Thus, in the detour area DEA, each of the first power auxiliary lines VDAL may include a portion adjacent to the first transmission detour line TDEL1 and another portion adjacent to the first auxiliary line ASL 1.

In the conventional region GA, each of the first power auxiliary lines VDAL (refer to fig. 15) may be adjacent to the first auxiliary line ASL 1.

The second dummy line DML2 may include: a second transmission detour line TDEL2, the second transmission detour line TDEL2 being adjacent to a second data line DL2, which is disposed in the second detour side area SDA2 and electrically connected to the first transmission detour line TDEL1, among the data lines DL; and a second auxiliary line ASL2, the second auxiliary line ASL2 being electrically connected to the second power line VSSPL.

The data line DL may include: the first data line DL1 disposed in the first detour side area SDA1 of the detour area DEA and the first regular side area GSA1 of the regular area GA; the second data line DL2 is disposed in the second detour side area SDA2 of the detour area DEA and the second normal side area GSM2 of the normal area GA 2; and a third data line DL3 disposed in the detour middle area MDDA of the detour area DEA and the regular middle area GMA of the regular area GA.

Among the data lines DL, each of the second data lines DL2 disposed in the second detour side area SDA2 of the detour area DEA and the second regular side area GSA2 of the regular area GA may include a portion adjacent to the second transmission detour line TDEL2 and another portion adjacent to the second auxiliary line ASL 2.

Among the data lines DL, each of the first data lines DL1 disposed in the first detour side area SDA1 of the detour area DEA and the first regular side area GSA1 of the regular area GA and each of the third data lines DL3 disposed in the detour middle area MDDA of the detour area DEA and the regular middle area GMA of the regular area GA may be adjacent to the second auxiliary line ASL 2.

In other words, the circuit layer 120 of the display panel 100 of the display device 10 in the embodiment includes: pixel drivers PXD corresponding to the emission areas EA, respectively; a data line DL extending in the second direction DR2 and transmitting a data signal Vdata to the pixel driver PXD; a first transmission detour line TDEL1, the first transmission detour line TDEL1 being electrically connected to a first data line DL1 provided in the first detour side area SDA1 among the data lines DL and extending in the first direction DR 1; and a second transmission detour line TDEL2, the second transmission detour line TDEL2 being adjacent to a second data line DL2, which is provided in the second detour side area SDA2 and extends in the second direction DR2 and is electrically connected to the first transmission detour line TDEL1, among the data lines DL.

The display device 10 in the embodiment may include a display driving circuit 200, the display driving circuit 200 being disposed in the second sub-region SB2 of the sub-region SBA of the substrate 110, and the display driving circuit 200 being configured to output the data signal Vdata of each data line DL.

The circuit layer 120 may include data supply lines DSPL disposed in the non-display area NDA and the sub-area SBA, the data supply lines DSPL being electrically connected to output terminals of the display driving circuit 200, respectively, and the data supply lines DSPL for transmitting the data signal Vdata of each data line DL to the display area DA.

The data supply line DSPL may include: a first data supply line DSPL1 for transmitting a data signal Vdata of the first data line DL1 of the first detour side area SDA 1; a second data supply line DSPL2 for transmitting a data signal Vdata of the second data line DL2 of the second detour side area SDA 2; and a third data supply line DSPL3 for transmitting a data signal Vdata of the third data line DL3 bypassing the middle area MDDA.

The second data supply line DSPL2 may be connected to the second data line DL2.

The third data supply line DSPL3 may be connected to the third data line DL3.

The first data supply line DSPL1 for transmitting the data signal Vdata of the first data line DL1 may be connected to the second transmission detour line TDEL2 of the second detour side area SDA 2.

Therefore, the first data supply line DSPL1 does not extend to the first detour side area SDA1. Accordingly, a portion of the non-display area NDA adjacent to the first detour side area SDA1 may have a reduced width because the first data supply line DSPL1 is not disposed therein.

The portion of the non-display area NDA adjacent to the first bypass side area SDA1 includes a shape bent along a point where both sides of the edge of the substrate 110 meet. Accordingly, when the width of the portion of the non-display area NDA adjacent to the first detour side area SDA1 is reduced, the ratio of the display area DA in the main area MA may be increased, so that the aesthetic sense of the display device 10 may be improved.

Fig. 6 is a layout diagram illustrating the data line, the first dummy line, the second dummy line, and the first power auxiliary line in part C of fig. 4. Fig. 7 is a cross-sectional view in a plane taken along line I-I' of fig. 6. Fig. 8 is a cross-sectional view of a plane taken along line J-J' in fig. 6.

Referring to fig. 6, and also referring to fig. 3, the first transmission detour line TDEL1 of the display device 10 in the embodiment includes: a first main stream MST1, the first main stream MST1 extending in a first direction DR1 between the first data line DL1 and the second transmission detour line TDEL 2; a first sub-branch SBR1 provided in the first detour side area SDA1, extending from the first main flow MST1 in the second direction DR2, and overlapping a portion of the first data line DL 1; and a second sub-branch SBR2, the second sub-branch SBR2 being provided in the second detour side area SDA2, extending from the first main flow MST1 in the second direction DR2 and overlapping with a part of the second transmission detour line TDEL 2.

Each of the pixel drivers PXD of the circuit layer 120 may include a data connection electrode DCE electrically connected to one of the data lines DL (refer to fig. 5) through a data connection hole DTCH.

Referring to fig. 6 and 7, the data line DL and the second transmission detour TDEL2 may be disposed on the VIA layer VIA1 covering the first transmission detour TDEL1 and the data connection electrode DCE.

The data line DL and the second transmission detour line TDEL2 may be covered with a planarization passivation layer VIA2.

In each pixel driver PXD, the data connection hole DTCH may overlap the data connection electrode DCE and the data line DL and penetrate the hole layer VIA1.

As shown in fig. 6, the pixel driver PXD may include a first pixel driver PXD1 adjacent to the first sub-branch SBR1 of the first transmission detour line TDEL 1.

The first data line DL1 may include: the first main extension MEX1 extending in the second direction DR 2; a first sub-protrusion SPR1, the first sub-protrusion SPR1 being adjacent to the first pixel driver PXD1, protruding from the first main extension MEX1, and overlapping the first sub-branch SBR 1; and a second sub-protrusion SPR2, the second sub-protrusion SPR2 being adjacent to the first pixel driver PXD1, protruding from the first main extension MEX1, and overlapping the data connection hole DTCH of the first pixel driver PXD1.

The first transmission detour TDEL1 may be electrically connected to the first data line DL1 through a first detour connection hole DECH1 overlapped with the first sub-branch SBR1 of the first transmission detour TDEL1 and the first sub-protrusion SPR1 of the first data line DL1.

As shown in fig. 7, a first detour connection hole DECH1 for electrical connection between the first transmission detour line TDEL1 and the first data line DL1 may penetrate the VIA layer VIA1.

As described above, in the embodiment, the first detour connection hole DECH1 for the electrical connection between the first transmission detour line TDEL1 and the first data line DL1 does not overlap the first main flow MST1 extending in the first direction DR1 in the first transmission detour line TDEL1, but overlaps the first sub-branch SBR1 extending in the second direction DR2 from the first main flow MST 1. Accordingly, the first detour connection hole DECH1 may be spaced apart from an intersection between the first main stream MST1 of the first transmission detour line TDEL1 and the first main extension MEX1 of the first data line DL1. Therefore, it is possible to prevent the visibility of the end portion of the first main stream MST1 from being increased due to the first detour connection hole DECH 1.

As shown in fig. 6, the first sub-branches SBR1 of the first transmission detour line TDEL1 provided in the first detour side area SDA1 may be arranged side by side in a predetermined second oblique line direction DD2 intersecting the first direction DR1 and the second direction DR 2.

In this way, it can be easily deduced from the arrangement of the first sub-branch SBR1 whether the electrical connection between the first data line DL1 and the first transmission detour line TDEL1 is normal.

In an embodiment, the pixel driver PXD of the circuit layer 120 may further include a second pixel driver PXD2, the second pixel driver PXD2 being disposed in the first detour side area SDA1, electrically connected to the first data line DL1, and spaced apart from the first pixel driver PXD 1.

The first data line DL1 may further include a third sub-protrusion SPR3 and a fourth sub-protrusion SPR4 adjacent to the second pixel driver PXD2 and protruding from the first main extension MEX 1.

The third sub-protrusion SPR3 may overlap the first dummy hole DMH 1.

The first dummy holes DMH1 may overlap the dummy electrodes DME covered with the VIA layer VIA 1.

That is, since the first dummy hole DMH1 penetrates through the hole layer VIA1, the circuit layer 120 of the display device 10 in the embodiment may further include the dummy electrode DME overlapped with the first dummy hole DMH1 to prevent other conductive layers under the VIA layer VIA1 from being damaged by the first dummy hole DMH 1.

The fourth sub-protrusion SPR4 may overlap the data connection electrode DCE of the second pixel driver PXD 2.

Among the first, second, third, and fourth sub-protrusions SPR1, SPR2, SPR3, and SPR4 of the first data line DL1, the third sub-protrusion SPR3 does not overlap the data connection hole DTCH and the first detour connection hole DECH 1.

In an embodiment, the third sub-protrusion SPR3 of the first data line DL1 may overlap the first dummy hole DMH 1.

Referring to fig. 8, and also to fig. 6, similar to the first detour connection hole DECH1 (refer to fig. 7) and the data connection hole DTCH, the first dummy hole DMH1 may penetrate the VIA layer VIA1.

The first dummy holes DMH1 may overlap the dummy electrodes DME covered with the VIA layer VIA1. That is, a portion of the dummy electrode DME overlapped with the first dummy hole DMH1 may be exposed through the first dummy hole DMH 1. In other words, the dummy electrode DME may serve as an etching prevention layer protecting components under the VIA layer VIA1 from the first dummy hole DMH 1. Accordingly, defects due to the first dummy holes DMH1 can be prevented.

Because the dummy electrode DME has an island pattern, the first dummy holes DMH1 and the dummy electrode DME may be independent of electrical connection.

As described above, in the embodiment, since all of the first, second, third, and fourth sub-protrusions SPR1, SPR2, SPR3, and SPR4 of the first data line DL1 overlap the VIA hole VIA penetrating through the VIA layer VIA1, the visibility of the VIA hole VIA may be reduced according to the layout of the VIA hole VIA.

Each of the second auxiliary lines ASL2 may include a fourth main extension MEX4 extending in the second direction DR2 and a ninth sub-protrusion SPR9 and a tenth sub-protrusion SPR10 protruding from the fourth main extension MEX4 to each of the pixel drivers PXD.

In an embodiment, for example, the ninth sub-protrusion SPR9 of one of the second auxiliary lines ASL2 adjacent to the first pixel driver PXD1 may face the first sub-protrusion SPR1 of one of the first data lines DL1 adjacent to the first pixel driver PXD 1. In addition, the tenth sub-protrusion SPR10 of one second auxiliary line ASL2 adjacent to the first pixel driver PXD1 may face the second sub-protrusion SPR2 of one first data line DL1 adjacent to the first pixel driver PXD 1.

In addition, some of the ninth sub-protrusions SPR9 of the second auxiliary line ASL2 may overlap the auxiliary connection hole ASCH (refer to fig. 9 and 10) penetrating the VIA layer VIA1 (refer to fig. 7 and 8).

Accordingly, the first auxiliary line ASL1 may be electrically connected to the second auxiliary line ASL2 through the auxiliary connection hole ASCH.

In addition, the other of the ninth sub-protrusion SPR9 of the second auxiliary line ASL2 and the tenth sub-protrusion SPR10 of the second auxiliary line ASL2 may overlap the fourth dummy hole DMH 4.

As shown in fig. 8, fourth dummy holes DMH4 may penetrate through the VIA layer VIA1 (refer to fig. 7 and 8).

Further, the fourth dummy holes DMH4 may overlap the dummy electrodes DME covered with the VIA layers VIA1 (refer to fig. 7 and 8). That is, the portion of the dummy electrode DME overlapping the fourth dummy hole DMH4 may be exposed through the fourth dummy hole DMH 4.

Because the dummy electrode DME has an island pattern, the fourth dummy hole DMH4 may be independent of the electrical connection.

In this way, both the ninth sub-protrusion SPR9 and the tenth sub-protrusion SPR10 of the second auxiliary line ASL2 may overlap the auxiliary connection hole ASCH or the fourth dummy hole DMH 4. Because the auxiliary connection hole ASCH and the fourth dummy hole DMH4 are contained in the VIA through the VIA layer VIA1, the visibility of the VIA may be reduced according to the layout of the VIA.

In an embodiment, as shown in fig. 6, the pixel driver PXD of the circuit layer 120 (refer to fig. 3) may further include a third pixel driver PXD3, the third pixel driver PXD3 being adjacent to the second sub-branch SBR2 of the first transmission detour line TDEL1 and electrically connected to the second data line DL2.

The second data line DL2 disposed in the second detour side area SDA2 may include: a second main extension MEX2 extending in a second direction DR 2; a fifth sub-protrusion SPR5, the fifth sub-protrusion SPR5 being adjacent to the third pixel driver PXD3, protruding from the second main extension MEX2, and disposed parallel to the first sub-protrusion SPR1 of the first data line DL1 in the first direction DR 1; and a sixth sub-protrusion SPR6, the sixth sub-protrusion SPR6 being adjacent to the third pixel driver PXD3, protruding from the second main extension MEX2, and disposed parallel to the second sub-protrusion SPR2 of the first data line DL1 in the first direction DR 1.

Similar to the second and fourth sub-protrusions SPR2 and SPR4 of the first data line DL1, the sixth sub-protrusion SPR6 of the second data line DL2 may overlap the data connection electrode DCE of the third pixel driver PXD 3.

Further, similar to the third sub-protrusion SPR3 of the first data line DL1, the fifth sub-protrusion SPR5 of the second data line DL2 may overlap the second dummy hole DMH 2.

Similar to the first dummy holes DMH1, the second dummy holes DMH2 may penetrate the VIA layer VIA1 (refer to fig. 7 and 8). Since the second dummy holes DMH2 overlap the island-shaped dummy electrodes DME covered with the VIA layers VIA1 (refer to fig. 7 and 8), they can be independent of electrical connection.

The second transmission detour line TDEL2 may include: a third main extension MEX3, the third main extension MEX3 extending in the second direction DR 2; a seventh sub-protrusion SPR7, the seventh sub-protrusion SPR7 being adjacent to the third pixel driver PXD3, protruding from the third main extension MEX3, facing the fifth sub-protrusion SPR5 of the second data line DL2, and overlapping the second sub-branch SBR2 of the first transfer detour TDEL 1; and an eighth sub-protrusion SPR8, the eighth sub-protrusion SPR8 being adjacent to the third pixel driver PXD3, protruding from the third main extension MEX3, and facing the sixth sub-protrusion SPR6 of the second data line DL 2.

The second transmission detour TDEL2 may be electrically connected to the first transmission detour TDEL1 through a second detour connection hole DECH2 overlapping the second sub-branch SBR2 of the first transmission detour TDEL1 and the seventh sub-protrusion SPR7 of the second transmission detour TDEL 2.

As shown in fig. 7, similar to the first detour connection hole DECH1, a second detour connection hole DECH2 for electrical connection between the first transmission detour line TDEL1 and the second transmission detour line TDEL2 may penetrate the VIA layer VIA1 (refer to fig. 7 and 8).

The eighth sub-projection SPR8 of the second transmission detour TDEL2 may overlap the third dummy hole DMH 3.

Similar to the first dummy holes DMH1 and the second dummy holes DMH2, the third dummy holes DMH3 may penetrate the VIA layer VIA1 (refer to fig. 7 and 8). In addition, since the third dummy holes DMH3 overlap the island-shaped dummy electrodes DME covered with the VIA layers VIA1 (refer to fig. 7 and 8), they can be independent of electrical connection.

As described above, in the embodiment, the second detour connection hole DECH2 for the electrical connection between the first transmission detour line TDEL1 and the second transmission detour line TDEL2 does not overlap the first main flow MST1 extending in the first direction DR1 in the first transmission detour line TDEL1, but overlaps the second sub-branch SBR2 extending from the first main flow MST1 in the second direction DR 2. Thus, the second detour connection hole DECH2 may be spaced apart from the intersection between the first main flow MST1 of the first transmission detour line TDEL1 and the third main extension MEX3 of the second transmission detour line TDEL 2. Therefore, it is possible to prevent the visibility of the end portion of the first main stream MST1 from being increased due to the second detour connection hole DECH 2.

Further, as shown in fig. 6, the second sub-branches SBR2 of the first transmission detour line TDEL1 provided in the second detour side area SDA2 may be arranged side by side in a predetermined first oblique line direction DD1 intersecting the first direction DR1 and the second direction DR 2.

In this way, it can be easily deduced from the arrangement of the second sub-branch SBR2 whether the electrical connection between the second transmission detour TDEL2 and the first transmission detour TDEL1 is normal.

Fig. 9 is a layout diagram of the data line, the first dummy line, the second dummy line, and the first power auxiliary line in part D of fig. 4.

Referring to fig. 9, and also referring to fig. 4, in the first regular side region GSA1 contacting the first detour side region SDA1 in the second direction DR2, the second auxiliary line ASL2 and the first data line DL1 of the first detour side region SDA1 may continuously extend in the second direction DR 2.

In the second normal-side region GSA2 contacting the second detour-side region SDA2 in the second direction DR2, the second auxiliary line ASL2 and the second data line DL2 of the second detour-side region SDA2 may continuously extend in the second direction DR 2.

The first auxiliary line ASL1 and the first power auxiliary line VDAL extending in the first direction DR1 may be alternately disposed in the first and second regular side regions GSA1 and GSA 2.

Fig. 10 is a layout diagram illustrating the data line, the first dummy line, the second dummy line, and the first power auxiliary line in part E of fig. 4.

Referring to fig. 10, and also to fig. 4, 6 and 9, the data line DL (refer to fig. 5, 6 and 11) of the circuit layer 120 (refer to fig. 3) may further include a third data line DL3 disposed in the detour middle area MDDA and the normal middle area GMA.

In an embodiment, as shown in fig. 6, 9 and 10, one of the first auxiliary lines ASL1 may include a second main stream MST2 extending in the first direction DR1 and a third sub-branch SBR3 extending from the second main stream MST2 in the second direction DR2 and overlapping a portion of one of the second auxiliary lines ASL2.

The pixel driver PXD of the circuit layer 120 may further include a fourth pixel driver PXD4 adjacent to the third sub-branch SBR3.

Among the second auxiliary lines ASL2, one second auxiliary line ASL2 overlapping the third sub-branch SBR3 may include a fifth main extension MEX5 extending in the second direction DR2, and eleventh and twelfth sub-protrusions SPR11 and SPR12 adjacent to the fourth pixel driver PXD4 and protruding from the fifth main extension MEX 5.

A first auxiliary line ASL1 may be electrically connected to a second auxiliary line ASL2 through an auxiliary connection hole ASCH defined in an overlapping region between the third sub-branch SBR3 and the eleventh sub-protrusion SPR 11.

As shown in fig. 7, the auxiliary connection hole ASCH may penetrate the VIA layer VIA1.

As described above, the auxiliary connection hole ASCH may be non-overlapping with the second main flow MST2 extending in the first direction DR1 in one first auxiliary line ASL1, and may be spaced apart from an intersection between the second main flow MST2 and the fifth main extension MEX 5.

As shown in fig. 6 and 9, the third sub-branches SBR3 of the first auxiliary line ASL1 adjacent to each other in the second direction DR2 may be arranged side by side in the first diagonal direction DD1 or the second diagonal direction.

Further, in the detour intermediate area MDDA and the regular intermediate area GMA, the third subsidiary branch SBR3 of the first auxiliary line ASL1 may be arranged side by side in one of the first diagonal direction DD1 and the second diagonal direction DD 2.

In the embodiment, as shown in fig. 10, in the detour middle area MDDA and the regular middle area GMA, for example, the third sub-branch SBR3 of the first auxiliary line ASL1 may be arranged side by side in the first diagonal direction DD 1.

In this way, it can be easily deduced from the arrangement of the third sub-branch SBR3 whether the electrical connection between the first auxiliary line ASL1 and the second auxiliary line ASL2 is normal.

Each of the second auxiliary lines ASL2 may be electrically connected to two or more of the first auxiliary lines ASL1.

The twelfth sub-protrusion SPR12 of one second auxiliary line ASL2 may overlap the fifth dummy hole DMH 5.

Similar to the first dummy holes DMH1 and the second dummy holes DMH2, the fifth dummy holes DMH5 may penetrate the VIA layer VIA1 (refer to fig. 7 and 8). The fifth dummy holes DMH5 may overlap the island-shaped dummy electrodes DME covered with the VIA layers VIA1 (refer to fig. 7 and 8), and thus may be independent of electrical connection.

In an embodiment, as shown in fig. 6, 9 and 10, the pixel driver PXD of the circuit layer 120 may further include a fifth pixel driver PXD5 spaced apart from the first and second sub-branches SBR1 and SBR2 of the first transmission detour line TDEL1 and the third sub-branch SBR3 of the first auxiliary line ASL 1.

Among the second auxiliary lines ASL2, one second auxiliary line ASL2 adjacent to the fifth pixel driver PXD5 may include a fourth main extension MEX4 extending in the second direction DR2, and a fifteenth sub-protrusion SPR15 and a sixteenth sub-protrusion SPR16 adjacent to the fifth pixel driver PXD5 and protruding from the fourth main extension MEX 4.

Each of the fifteenth sub-tab SPR15 and the sixteenth sub-tab SPR16 may overlap the sixth dummy hole DMH 6.

Similar to the first dummy holes DMH1 and the second dummy holes DMH2, the sixth dummy holes DMH6 may penetrate the VIA layer VIA1 (refer to fig. 7 and 8). The sixth dummy holes DMH6 may overlap the island-shaped dummy electrodes DME covered with the VIA layers VIA1 (refer to fig. 7 and 8), and thus may be independent of electrical connection.

As described above, in the embodiment, the first data line DL1 of the first detour side area SDA1 may be electrically connected to the second transmission detour line TDEL2 of the second detour side area SDA2 through the first transmission detour line TDEL 1. The first transmission detour TDEL1 includes a first main stream MST1 extending in the first direction DR1, a first sub-branch SBR1 extending from the first main stream MST1 in the second direction DR2 and overlapping the first sub-protrusion SPR1 of the first data line DL1, and a second sub-branch SBR2 extending from the first main stream MST1 in the second direction DR2 and overlapping the seventh sub-protrusion SPR7 of the second transmission detour TDEL2.

The first detour connection hole DECH1 for the electrical connection between the first data line DL1 and the first transmission detour line TDEL1 may overlap the first sub-protrusion SPR1 and the first sub-branch SBR 1. Accordingly, the first detour connection hole DECH1 may be spaced apart from an intersection between the first main stream MST1 of the first transmission detour line TDEL1 and the first main extension MEX1 of the first data line DL 1.

Furthermore, the second detour connection hole DECH2 for the electrical connection between the second transmission detour line TDEL2 and the first transmission detour line TDEL1 may overlap with the seventh sub-protrusion SPR7 and the second sub-branch SBR2. Thus, the second detour connection hole DECH2 may be spaced apart from the intersection between the first main flow MST1 of the first transmission detour line TDEL1 and the third main extension MEX3 of the second transmission detour line TDEL2.

That is, opposite ends of the first main stream MST1 of the first transmission detour line TDEL1 may be spaced apart from the first detour connection hole DECH1 and the second detour connection hole DECH 2.

Therefore, it is possible to prevent the visibility of the opposite ends of the first main stream MST1 of the first transmission detour line TDEL1 from being increased due to the first detour connection hole DECH1 and the second detour connection hole DECH 2.

Therefore, in the embodiment, the visibility of the first transmission detour line TDEL1, the second transmission detour line TDEL2, the first detour connection hole DECH1, and the second detour connection hole DECH2 provided to reduce the width of the non-display area NDA can be prevented from increasing, so that degradation in the display quality of the display device 10 due to the first transmission detour line TDEL1 can be reduced.

Further, in an embodiment, the data line DL and the second dummy line DML2 extending in the second direction DR2 include a pair of sub-protrusions protruding toward each of the adjacent pixel drivers. Further, all the sub-protrusions included in the data line DL and the second dummy line DML2 overlap the VIA hole VIA penetrating through the VIA layer VIA 1.

The VIA holes VIA are collectively referred to herein as holes penetrating through the VIA layer VIA 1. That is, the via hole via may include not only the first bypass connection hole DECH1, the second bypass connection hole DECH2, the data connection hole DTCH, and the auxiliary connection hole ASCH provided for the electrical connection, but also the fourth dummy hole DMH4 unrelated to the electrical connection.

Among the VIA holes VIA, the first dummy hole DMH1, the second dummy hole DMH2, the third dummy hole DMH3, and the fourth dummy hole DMH4 (which are holes other than the first bypass connection hole DECH1, the second bypass connection hole DECH2, the data connection hole DTCH, and the auxiliary connection hole ASCH overlapped with the data connection electrode DCE, the first sub-branch SBR1, the second sub-branch SBR2, and the third sub-branch SBR 3) may overlap with the dummy electrode DME covered with the VIA layer VIA1, respectively.

The first planarization layer 125 may be protected from the first, second, third, and fourth dummy holes DMH1, DMH2, DMH3, and DMH4 due to the dummy electrode DME.

As described above, in the embodiment, the VIA penetrating the VIA layer VIA1 further includes the first to fourth dummy holes DMH1 to DMH4 irrelevant to the electrical connection, so that the visibility of the first bypass connection hole DECH1, the second bypass connection hole DECH2, the data connection hole DTCH, and the auxiliary connection hole ASCH provided for the electrical connection can be reduced.

Accordingly, degradation of the display quality of the display device 10 due to the visibility of the via can be reduced.

Fig. 11 is an equivalent circuit diagram illustrating one embodiment of one pixel driver of the circuit layer of fig. 3.

Referring to fig. 11, one of the pixel drivers PXD of the circuit layer 120 (refer to fig. 3) may include a driving transistor DT, at least one of the switching elements ST1 to ST6, and a capacitor C1. The switching elements ST1 to ST6 may include a first transistor (also referred to as a switching transistor) ST1, a second transistor ST2, a third transistor ST3, a fourth transistor ST4, a fifth transistor ST5, and a sixth transistor ST6. In other words, the switching elements ST1 to ST6 may be referred to as a first transistor ST1, a second transistor ST2, a third transistor ST3, a fourth transistor ST4, a fifth transistor ST5, and a sixth transistor ST6.

The circuit layer 120 may further include a scan write line GWL for transmitting the scan write signal GW to the pixel driver PXD, a gate control line GCL for transmitting the gate control signal GC to the pixel driver PXD, a scan initialization line GIL for transmitting the scan initialization signal GI to the pixel driver PXD, an emission control line ECL for transmitting the emission control signal EC to the pixel driver PXD, a gate initialization voltage line VGIL for transmitting the first initialization voltage Vgint to the pixel driver PXD, an anode initialization voltage line fail for transmitting the second initialization voltage vant to the pixel driver PXD, and a first power line VDL for transmitting the first power ELVDD to the pixel driver PXD.

The scan writing line GWL may be electrically connected to a gate electrode of each of the first transistor ST1 and the second transistor ST 2. The scan initialization line GIL may be electrically connected to a gate electrode of the third transistor ST 3. The gate control line GCL may be electrically connected to a gate electrode of the fourth transistor ST 4. The emission control line ECL may be electrically connected to a gate electrode of each of the fifth transistor ST5 and the sixth transistor ST 6.

The driving transistor DT may be connected in series with the light emitting element LEL between the first power line VDL and the second power line VSL.

The first electrode of the driving transistor DT may be connected to a first power line VDL through a fifth transistor ST 5.

Further, the first electrode of the driving transistor DT may be connected to the data line DL through the second transistor ST 2.

The second electrode of the driving transistor DT may be connected to the light emitting element LEL through a sixth transistor ST 6.

The capacitor C1 may be connected between the first power line VDL and the gate electrode of the driving transistor DT. That is, the gate electrode of the driving transistor DT may be connected to the first power line VDL through the capacitor C1.

Accordingly, when the data signal Vdata of the data line DL is applied to the first electrode of the driving transistor DT, the driving transistor DT may generate a drain-source current corresponding to the data signal Vdata. The drain-source current of the driving transistor DT may be supplied as a driving current of the light emitting element LEL.

The light emitting element LEL may emit light having a luminance corresponding to a driving current of the driving transistor DT.

The light emitting element LEL may include an anode electrode AND (refer to fig. 15) AND a cathode electrode CTD (refer to fig. 15) disposed to face each other, AND a light emitting layer EML (refer to fig. 15) between the anode electrode AND the cathode electrode CTD.

In an embodiment, the light emitting element LEL may be an organic light emitting diode having a light emitting layer including an organic light emitting material. In an alternative embodiment, the light emitting element LEL may be an inorganic light emitting element including a light emitting layer including an inorganic semiconductor. In an alternative embodiment, the light emitting element LEL may be a quantum dot light emitting element having a quantum dot light emitting layer. In alternative embodiments, the light emitting elements LEL may be micro light emitting diodes.

The capacitor Cel connected in parallel to the light emitting element LEL is a parasitic capacitance between the anode electrode and the cathode electrode.

The first transistor ST1 is connected between the gate electrode of the driving transistor DT and the second electrode of the driving transistor DT.

The first transistor ST1 may include a plurality of sub-transistors connected in series. In an embodiment, for example, the first transistor ST1 may include a first sub-transistor ST11 and a second sub-transistor ST12.

The first electrode of the first sub-transistor ST11 may be connected to the second electrode of the driving transistor DT, the second electrode of the first sub-transistor ST11 may be connected to the first electrode of the second sub-transistor ST12, and the second electrode of the second sub-transistor ST12 may be connected to the gate electrode of the driving transistor DT.

In this way, the potential of the gate electrode of the driving transistor DT can be prevented from being changed due to the leakage current caused by the turned-off first transistor ST 1.

The second transistor ST2 is connected between the first electrode of the driving transistor DT and the data line DL.

The gate electrode of each of the first transistors ST1 and the gate electrode of the second transistor ST2 are connected to the scan write line GWL.

When the scan write signal GW is transmitted through the scan write line GWL, the first transistor ST1 and the second transistor ST2 are turned on, and the gate electrode and the second electrode of the driving transistor DT become to have the same potential through the turned-on first transistor ST 1. Further, the data signal Vdata of the data line DL is supplied to the first electrode of the driving transistor DT through the turned-on second transistor ST 2.

At this time, when a voltage difference between the first electrode and the gate electrode of the driving transistor DT becomes greater than a threshold voltage, the driving transistor DT is turned on to generate a drain-source current between the first electrode and the second electrode of the driving transistor DT.

The third transistor ST3 is connected between the gate electrode of the driving transistor DT and the gate initialization voltage line VGIL. A gate electrode of the third transistor ST3 is connected to the scan initialization line GIL.

The third transistor ST3 may include a plurality of sub-transistors connected in series. In an embodiment, for example, the third transistor ST3 may include a third sub-transistor ST31 and a fourth sub-transistor ST32.

The first electrode of the third sub-transistor ST31 may be connected to the gate electrode of the driving transistor DT, the second electrode of the third sub-transistor ST31 may be connected to the first electrode of the fourth sub-transistor ST32, and the second electrode of the fourth sub-transistor ST32 may be connected to the gate initialization voltage line VGIL.

In this way, the potential of the gate electrode of the driving transistor DT can be prevented from being changed due to the leakage current caused by the off third transistor ST 3.

The third transistor ST3 may be turned on when the scan initialization signal GI is supplied through the scan initialization line GIL. At this time, the gate electrode of the driving transistor DT is connected to the gate initialization voltage line VGIL through the turned-on third transistor ST3 so that the potential of the gate electrode of the driving transistor DT may be initialized to the first initialization voltage Vgint of the gate initialization voltage line VGIL.

The fourth transistor ST4 may be connected between the anode electrode of the light emitting element LEL and the anode initialization voltage line tail. The gate electrode of the fourth transistor ST4 may be connected to the gate control line GCL.

The fourth transistor ST4 may be turned on when the control scan signal GC is supplied through the gate control line GCL. At this time, the anode electrode of the light emitting element LEL is connected to the anode initialization voltage line vat through the fourth transistor ST4 that is turned on, so that the potential of the anode electrode of the light emitting element LEL can be initialized to the second initialization voltage vant of the anode initialization voltage line vat.

The fifth transistor ST5 may be connected between the first electrode of the driving transistor DT and the first power line VDL.

The sixth transistor ST6 may be connected between the second electrode of the driving transistor DT and the anode electrode of the light emitting element LEL.

A gate electrode of each of the fifth transistor ST5 and the sixth transistor ST6 may be connected to the emission control line ECL.

When the emission control signal EC is supplied through the emission control line ECL, the driving transistor DT and the light emitting element LEL may be connected in series between the first power line VDL and the second power line VSL. Accordingly, the driving current of the driving transistor DT may be supplied to the light emitting element LEL, and thus, the light emitting element LEL may emit light based on the driving current.

As shown in fig. 11, the driving transistor DT and one or more switching elements ST1 to ST6 provided in the pixel driver PXD may be all implemented as P-type Metal Oxide Semiconductor Field Effect Transistors (MOSFETs).

In alternative embodiments, some of the one or more switching elements ST1 to ST6 and the driving transistor DT provided in the pixel driver PXD may be implemented as a P-type MOSFET, and others may be implemented as N-type MOSFETs. In this case, the switching element implemented as a P-type MOSFET and the switching element implemented as an N-type MOSFET may include active layers of different semiconductor materials. Accordingly, the width of the pixel driver PXD can be reduced by the stacked structure, which can be advantageous to improve resolution.

Fig. 12 is a plan view showing a portion G of fig. 5 according to the first embodiment. Fig. 13 is a plan view showing the semiconductor layer, the first conductive layer, the second conductive layer, and the third conductive layer in the plan view of fig. 12. Fig. 14 is a plan view showing the fourth conductive layer and the fifth conductive layer in the plan view of fig. 12. Fig. 15 is a sectional view taken along line K-K' of fig. 12.

Fig. 12 is a plan view showing two pixel drivers PXD disposed in the first detour side area SDA1 and adjacent to each other in the first direction DR 1.

First, as shown in fig. 15, in an embodiment, the circuit layer 120 may have a structure including a semiconductor layer SEL (refer to fig. 13) on the substrate 110, a first conductive layer CDL1 (refer to fig. 13) on a first gate insulating layer 122 covering the semiconductor layer SEL, a second conductive layer CDL2 (refer to fig. 13) on a second gate insulating layer 123 covering the first conductive layer CDL1, a third conductive layer CDL3 (refer to fig. 13) on an interlayer insulating layer 124 covering the second conductive layer CDL2, a fourth conductive layer CDL4 (refer to fig. 12) on a first planarizing layer 125 covering the third conductive layer CDL3, a fifth conductive layer CDL5 (refer to fig. 12) on a second planarizing layer 126 covering the fourth conductive layer CDL4, and a third planarizing layer 127 covering the fifth conductive layer CDL 5.

Further, the light emitting element layer 130 may be disposed on the third planarization layer 127.

Referring to fig. 13, the semiconductor layer SEL may include channel portions CHDT, CH11, CH12, CH2, CH31, CH32, CH4, CH5, and CH6, source electrodes SDT, S11, S12, S2, S31, S32, S4, S5, and S6, and drain electrodes DDT, D11, D12, D2, D31, D32, D4, D5, and D6 of the driving transistor DT and the first to sixth transistors ST1 to ST 6.

In the semiconductor layer SEL, the source electrodes SDT, S11, S12, S2, S31, S32, S4, S5, and S6 and the drain electrodes DDT, D11, D12, D2, D31, D32, D4, D5, and D6 may include or consist of a portion having conductivity by doping the semiconductor material with ions or impurities.

The first conductive layer CDL1 may include gate electrodes GDT, G11, G12, G2, G31, G32, G4, G5, and G6 of the driving transistor DT and the first to sixth transistors ST1 to ST 6.

In addition, the first conductive layer CDL1 may further include a scan write line GWL, a scan initialization line GIL, an emission control line ECL, and a gate control line GCL connected to the gate electrodes GDT, G11, G12, G2, G31, G32, G4, G5, and G6 of the first to sixth transistors ST1 to ST 6. The scan writing line GWL, the scan initializing line GIL, the emission control line ECL, and the gate control line GCL may extend in the first direction DR 1.

In an embodiment, for example, for integration of the circuit layer 120, the gate control line GCL of the current column may be provided as the scan initialization line GIL of the previous column.

The second conductive layer CDL2 may include a gate initialization voltage line VGIL for transmitting the first initialization voltage Vgint and an anode initialization voltage line valid for transmitting the second initialization voltage vant. The gate initialization voltage line VGIL and the anode initialization voltage line VAIL may extend in the first direction DR 1.

The first power line VDL may include a first power level auxiliary line VDSBL1 extending in the first direction DR1 and a first power vertical auxiliary line VDSBL2 extending in the second direction DR 2.

The second conductive layer CDL2 may further include a first power level auxiliary line VDSBL1.

The third conductive layer CDL3 may include a first power vertical auxiliary line VDSBL2.

The third conductive layer CDL3 may further include a gate initialization voltage auxiliary line VGIAL and an anode initialization voltage auxiliary line vanal.

The gate initialization voltage auxiliary line VGIAL and the anode initialization voltage auxiliary line vanal may be electrically connected to the initialization voltage line vat and may extend in the second direction DR 2.

The gate initialization voltage auxiliary line VGIAL may be electrically connected to the gate initialization voltage line VGIL through the first initialization connection hole VICH1, and may be electrically connected to the drain electrode D32 of the third transistor ST3 through the second initialization connection hole VICH 2.

The anode initialization voltage auxiliary line VAIALs may be electrically connected to the anode initialization voltage line VAIL through the third initialization connection hole VICH3, and may be electrically connected to the drain electrode D4 of the fourth transistor ST4 through the fourth initialization connection hole VICH 4.

The first power vertical auxiliary line VDSBL2 may be electrically connected to the first power horizontal auxiliary line VDSBL1 through the fifth contact hole CT 5.

The driving transistor DT may include a channel portion CHDT, source and drain electrodes SDT and DDT connected to opposite sides of the channel portion CHDT, and a gate electrode GDT overlapping the channel portion CHDT.

The source electrode SDT of the driving transistor DT may be connected to the drain electrode D2 of the second transistor ST2 and the drain electrode D5 of the fifth transistor ST 5.

The drain electrode DDT of the driving transistor DT may be connected to the source electrode S11 of the first sub-transistor ST11 and the source electrode S6 of the sixth transistor ST 6.

The gate electrode GDT of the driving transistor DT may be provided as the first conductive layer CDL1.

The first transistor ST1 may include a first sub-transistor ST11 and a second sub-transistor ST12 connected in series.

The first sub-transistor ST11 may include a channel portion CH11, source and drain electrodes S11 and D11 connected to opposite sides of the channel portion CH11, and a gate electrode G11 overlapping the channel portion CH11 and including or consisting of a portion of the scan writing line GWL.

The source electrode S11 of the first sub-transistor ST11 may be connected to the drain electrode DDT of the driving transistor DT.

The drain electrode D11 of the first sub-transistor ST11 may be connected to the source electrode S12 of the second sub-transistor ST12.

The second sub-transistor ST12 may include a channel portion CH12, source and drain electrodes S12 and D12 connected to opposite sides of the channel portion CH12, and a gate electrode G12 overlapping the channel portion CH12 and including or consisting of a protruding portion of the scan writing line GWL.

The source electrode S12 of the second sub-transistor ST12 may be connected to the drain electrode D11 of the first sub-transistor ST 11.

The drain electrode D12 of the second sub-transistor ST12 may be connected to the source electrode S31 of the third sub-transistor ST 31.

The gate electrode G11 of the first sub-transistor ST11 and the gate electrode G12 of the second sub-transistor ST12 may include or consist of different portions of the scan writing line GWL.

The gate electrode GDT of the driving transistor DT may be electrically connected to the first connection electrode CE1 through the first contact hole CT1, and the first connection electrode CE1 may be electrically connected to the drain electrode D12 of the second sub-transistor ST12 through the second contact hole CT 2.

The first connection electrode CE1 may include or consist of the third conductive layer CDL 3.

The second transistor ST2 may include a channel portion CH2, source and drain electrodes S2 and D2 connected to opposite sides of the channel portion CH2, and a gate electrode G2 overlapping the channel portion CH2 and including or consisting of a portion of the scan writing line GWL.

The source electrode S2 of the second transistor ST2 may be electrically connected to the second connection electrode CE2 through the fourth contact hole CT 4.

The second connection electrode CE2 may be provided as the third conductive layer CDL3.

The drain electrode D2 of the second transistor ST2 may be connected to the source electrode SDT of the driving transistor DT and the drain electrode D5 of the fifth transistor ST 5.

The third transistor ST3 may include a third sub-transistor ST31 and a fourth sub-transistor ST32 connected in series.

The third sub-transistor ST31 may include a channel portion CH31, source and drain electrodes S31 and D31 connected to opposite sides of the channel portion CH31, and a gate electrode G31 overlapping the channel portion CH 31.

The source electrode S31 of the third sub-transistor ST31 may be connected to the drain electrode D12 of the second sub-transistor ST 12.

The drain electrode D31 of the third sub-transistor ST31 may be connected to the source electrode S32 of the fourth sub-transistor ST32.

The fourth sub-transistor ST32 includes a channel portion CH32, source and drain electrodes S32 and D32 connected to opposite sides of the channel portion CH32, and a gate electrode G32 overlapping the channel portion CH 32.

The drain electrode D32 of the fourth sub-transistor ST32 may be electrically connected to the initialization auxiliary line via through the second initialization connection hole VICH 2.

The gate electrode G31 of the third sub-transistor ST31 and the gate electrode G32 of the fourth sub-transistor ST32 may include or consist of different portions of the scan initialization line GIL.

The pixel driver PXD (refer to fig. 5) may further include a shielding electrode SHE overlapping at least a portion of the source electrode S31 of the third sub-transistor ST 31. The shielding electrode SHE may further overlap a portion of the drain electrode D11 of the first sub-transistor ST 11.

The shielding electrode SHE may be provided as the second conductive layer CDL2.

The shielding electrode SHE may be electrically connected to the first power vertical auxiliary line VDSBL2 through the third contact hole CT 3.

The fourth transistor ST4 may include a channel portion CH4, source and drain electrodes S4 and D4 connected to opposite sides of the channel portion CH, and a gate electrode G4 overlapping the channel portion CH4 and including or consisting of a portion of the gate control line GCL.

The source electrode S4 of the fourth transistor ST4 may be connected to the drain electrode D6 of the sixth transistor ST 6.

The drain electrode D4 of the fourth transistor ST4 may be electrically connected to the initialization auxiliary line via through the third initialization connection hole VICH 3.

The fifth transistor ST5 may include a channel portion CH5, source and drain electrodes S5 and D5 connected to opposite sides of the channel portion CH5, and a gate electrode G5 overlapping the channel portion CH5 and including or consisting of a portion of the emission control line ECL.

The source electrode S5 of the fifth transistor ST5 may be electrically connected to the first power vertical auxiliary line VDSBL2 through the sixth contact hole CT 6.

The drain electrode D5 of the fifth transistor ST5 may be connected to the source electrode SDT of the driving transistor DT.

The sixth transistor ST6 may include a channel portion CH6, source and drain electrodes S6 and D6 connected to opposite sides of the channel portion CH6, and a gate electrode G6 overlapping the channel portion CH6 and including or consisting of another portion of the emission control line ECL.

The source electrode S6 of the sixth transistor ST6 may be connected to the drain electrode DDT of the driving transistor DT.

The drain electrode D6 of the sixth transistor ST6 may be connected to the source electrode S4 of the fourth transistor ST4 and may be connected to the third connection electrode CE3 through the seventh contact hole CT 7.

The third connection electrode CE3 may include or consist of a third conductive layer CDL 3.

The capacitor C1 may be provided as an overlapping region between the first capacitor electrode CAE1 and the second capacitor electrode CAE 2.

The first capacitor electrode CAE1 may include or consist of a portion of the gate electrode GDT of the driving transistor DT, and the first capacitor electrode CAE1 is provided as the first conductive layer CDL1.

The second capacitor electrode CAE2 may include or consist of a portion of the first power level auxiliary line VDSBL1, and the second capacitor electrode CAE2 is provided as the second conductive layer CDL2.

The second connection electrode CE2 may be electrically connected to the source electrode S2 of the second transistor ST2 through the fourth contact hole CT 4.

Referring to fig. 14, and also referring to fig. 6 and 13, the fourth conductive layer CDL4 may include a first transmission detour line TDEL1 and a first power auxiliary line VDAL. Since the first transmission detour line TDEL1 is included in the first dummy line DML1, the fourth conductive layer CDL4 may include the first dummy line DML1 and the first power auxiliary line VDAL. Further, the first dummy line DML1 may include a first transmission detour line TDEL1 and a first auxiliary line ASL1.

The first power auxiliary line VDAL may be electrically connected to the first power vertical auxiliary line VDSBL2 of the third conductive layer CDL3 through the twelfth contact hole CT 12.

The fourth conductive layer CDL4 may further include a fourth connection electrode CE4, a data connection electrode DCE, and a dummy electrode DME.

The data connection electrode DCE may be electrically connected to the second connection electrode CE2 through the tenth contact hole CT 10. The second connection electrode CE2 may be electrically connected to the source electrode S2 of the second transistor ST2 through the fourth contact hole CT 4.

The fifth conductive layer CDL5 may include: the data line DL including the first data line DL1 and the second dummy line DML2 respectively adjacent to the data line DL. The second dummy line DML2 may include a second transmission detour line TDEL2 and a second auxiliary line ASL2.

The fifth conductive layer CDL5 may further include a fifth connection electrode CE5.

The first data line DL1 may be electrically connected to the data connection electrode DCE through the data connection hole DTCH.

Accordingly, the first data line DL1 may be electrically connected to the source electrode S2 of the second transistor ST2 through the second connection electrode CE2, the data connection electrode DCE, and the data connection hole DTCH.

The fourth connection electrode CE4 may be electrically connected to the third connection electrode CE3 through the eighth contact hole CT 8. The third connection electrode CE3 may be electrically connected to the source electrode S4 of the fourth transistor ST4 and the drain electrode D6 of the sixth transistor ST6 provided as the semiconductor layer SEL through the seventh contact hole CT 7.

The fifth connection electrode CE5 may be electrically connected to the fourth connection electrode CE4 through the ninth contact hole CT 9.

Further, as shown in fig. 14 AND 15, the fifth connection electrode CE5 may be electrically connected to the anode electrode AND of the light emitting element LEL through the anode contact hole ANCT penetrating the third planarization layer 127.

Accordingly, the anode electrode AND of the light emitting element LEL may be electrically connected to the fourth transistor ST4 AND the sixth transistor ST6 through the third connection electrode CE3, the fourth connection electrode CE4, the fifth connection electrode CE5, AND the anode contact hole ANCT.

According to the first embodiment, among the first dummy lines DML1, the first transmission detour line TDEL1 includes: a first main flow MST1 extending in a first direction DR 1; and a first sub-branch SBR1 extending from the first main stream MST in the second direction DR2 and overlapping with the first sub-protrusion SPR1 of the first data line DL 1.

The first main stream MST1 of the first transfer detour line TDEL1 may be spaced apart from the scan initialization line GIL in the second direction DR2 or the third direction DR3 with the gate initialization voltage line VGIL interposed therebetween.

In an embodiment, for example, in the second direction DR2, the gate initialization voltage line VGIL may be disposed between the first main stream MST1 of the first transfer detour line TDEL1 and the scan initialization line GIL.

In an alternative embodiment, the gate initialization voltage line VGIL may overlap the first main stream MST1 of the first transfer detour line TDEL1 in the third direction DR3 and may be spaced apart from the scan initialization line GIL in the second direction DR 2.

In this way, it is possible to prevent a defect in which the scan initialization signal GI of the scan initialization line GIL is coupled with the data signal Vdata of the first data line DL1 transmitted through the first transmission detour line TDEL 1.

The first data line DL1 may include a first main extension MEX1 extending in the second direction DR2, and first and second sub-protrusions SPR1 and SPR2 protruding from the first main extension MEX 1.

The first sub-protrusion SPR1 may overlap the first sub-branch SBR1, and the second sub-protrusion SPR2 may overlap the data connection hole DTCH for electrical connection between the source electrode S2 of the second transistor ST2 and the first data line DL 1.

The first detour connection hole DECH1 for the electrical connection between the first transmission detour line TDEL1 and the first data line DL1 may overlap the first sub-branch SBR1 and the first sub-protrusion SPR1.

Here, the first main stream MST1 of the first transmission detour line TDEL1 may be spaced apart from each of the first and second sub-protrusions SPR1 and SPR2 of the first data line DL 1. Further, the first main stream MST1 of the first transmission detour TDEL1 may be disposed closer to the first sub-protrusion SPR1 between the first sub-protrusion SPR1 and the second sub-protrusion SPR2 of the first data line DL1 in the second direction DR 2. In this way, the first sub-branch SBR1 may have a relatively small length and may be spaced apart from the data connection electrode DCE for electrical connection between the first data line DL1 and the second transistor ST 2.

As shown in fig. 6, the first data line DL1 may further include third and fourth sub-protrusions SPR3 and SPR4, the third and fourth sub-protrusions SPR3 and SPR4 being spaced apart from the first sub-branch SBR1 of the first transmission detour line TDEL1, adjacent to the normal region GA, and protruding from the first main extension MEX 1.

The third sub-protrusion SPR3 may overlap the first dummy hole DMH1 (which is independent of the electrical connection).

The fourth sub-protrusion SPR4 may overlap the data connection hole DTCH.

The second auxiliary line ASL2 may include a fourth main extension MEX4 extending in the second direction DR2, and a ninth sub-protrusion SPR9 and a tenth sub-protrusion SPR10 protruding from the fourth main extension MEX4 toward each pixel driver PXD.

Some of the ninth sub-protrusions SPR9 of the second auxiliary line ASL2 may overlap with auxiliary connection holes ASCH (refer to fig. 9 and 10) for electrical connection between the first auxiliary line ASL1 and the second auxiliary line ASL2.

That is, among the first dummy lines DML1, one first auxiliary line ASL1 may include a second main stream MST2 extending in the first direction DR1 and a third sub-branch SBR3 extending from the second main stream MST2 in the second direction DR2 and overlapping with the one second auxiliary line ASL2.

Some of the ninth sub-protrusions SPR9 of the second auxiliary line ASL2 may overlap the auxiliary connection hole ASCH penetrating the VIA layer VIA1 and the third sub-branch SBR3 of the first auxiliary line ASL 1. Accordingly, the first auxiliary line ASL1 may be electrically connected to the second auxiliary line ASL2 through the auxiliary connection hole ASCH overlapped with the third sub-branch SBR3 of the first auxiliary line ASL1 and the ninth sub-protrusion SPR9 of the second auxiliary line ASL2.

Further, the other of the ninth sub-protrusion SPR9 of the second auxiliary line ASL2 and the tenth sub-protrusion SPR10 of the second auxiliary line ASL2 may overlap the fourth dummy hole DMH4 and the dummy electrode DME.

In an embodiment, for example, the ninth sub-protrusion SPR9 and the tenth sub-protrusion SPR10 of one second auxiliary line ASL2 adjacent to the first data line DL1 among the second auxiliary lines ASL2 may face the first sub-protrusion SPR1 and the second sub-protrusion SPR2 of the first data line DL1, respectively. Further, each of the ninth and tenth sub-protrusions SPR9 and SPR10 of one second auxiliary line ASL2 adjacent to the first data line DL1 may overlap the fourth dummy hole DMH4 and the dummy electrode DME.

Referring to fig. 15, and also referring to fig. 13 and 14, the circuit layer 120 may include a semiconductor layer SEL on the substrate 110, a first conductive layer CDL1 on a first gate insulating layer 122 covering the semiconductor layer SEL, a second conductive layer CDL2 on a second gate insulating layer 123 covering the first conductive layer CDL1, a third conductive layer CDL3 on an interlayer insulating layer 124 covering the second conductive layer CDL2, a fourth conductive layer CDL4 on a first planarization layer 125 covering the third conductive layer CDL3, a fifth conductive layer CDL5 on a second planarization layer 126 covering the fourth conductive layer CDL4, and a third planarization layer 127 covering the fifth conductive layer CDL 5.

The circuit layer 120 may further include a buffer layer 121 disposed between the substrate 110 and the semiconductor layer SEL.

The buffer layer 121 may serve to protect the circuit layer 120 and the light emitting element layer 130 from moisture penetrating the substrate 110, and may include or consist of at least one inorganic layer.

In an embodiment, for example, the buffer layer 121 may be formed as a multilayer in which one or more inorganic layers such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked.

The semiconductor layer SEL is disposed on the buffer layer 121, and may include or consist of a silicon semiconductor such as polycrystalline silicon, single crystal silicon, low temperature polycrystalline silicon, and amorphous silicon.

The semiconductor layer SEL may include channel portions CHDT, CH11, CH12, CH2, CH31, CH32, CH4, CH5, and CH6 of fig. 13 of the driving transistor DT and the first to sixth transistors ST1 to ST6 provided in the pixel driver PXD.

In addition, the semiconductor layer SEL may further include the source electrodes SDT, S11, S12, S2, S31, S32, S4, S5, and S6 of fig. 13 and the drain electrodes DDT, D11, D12, D2, D31, D32, D4, D5, and D6 of fig. 13, which drive each of the transistors DT and the switching elements ST1 to ST 6.

Another portion corresponding to the source electrodes SDT, S11, S12, S2, S31, S32, S4, S5, and S6 of fig. 13 and the drain electrodes DDT, D11, D12, D2, D31, D32, D4, D5, and D6 of fig. 13 of each of the driving transistor DT and the switching elements ST1 to ST6 of the semiconductor layer SEL may be doped with ions or impurities to have conductivity.

The portions corresponding to the channel portions CHDT, CH11, CH12, CH2, CH31, CH32, CH4, CH5, and CH6 of fig. 13 of each of the driving transistor DT and the switching elements ST1 to ST6 of the semiconductor layer SEL may not be doped due to the gate electrodes GDT, G11, G12, G2, G31, G32, G4, G5, and G6, and characteristics of the semiconductor that generate channels serving as carrier movement paths according to potential differences may be maintained.

The first gate insulating layer 122 may include an inorganic layer disposed on the buffer layer 121 and covering the semiconductor layer SEL, or consist of an inorganic layer disposed on the buffer layer 121 and covering the semiconductor layer SEL.

In an embodiment, for example, the first gate insulating layer 122 may include or consist of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

The first conductive layer CDL1 is disposed on the first gate insulating layer 122.

As shown in fig. 13, the first conductive layer CDL1 may include gate electrodes GDT, G11, G12, G2, G31, G32, G4, G5, and G6 of the driving transistor DT and the switching elements ST1 to ST6 provided in the pixel driver PXD, and scan write lines GWL, scan initialization lines GIL, gate control lines GCL, and emission control lines ECL connected to the gate electrodes G11, G12, G2, G31, G32, G4, G5, and G6 of the first to sixth transistors ST1 to ST6 and extending in the first direction DR 1.

The first conductive layer CDL1 may be formed to include a single layer or multiple layers of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or any alloy thereof.

As shown in fig. 15, the second gate insulating layer 123 may include an inorganic layer disposed on the first gate insulating layer 122 and covering the first conductive layer CDL1, or consist of an inorganic layer disposed on the first gate insulating layer 122 and covering the first conductive layer CDL 1.

In an embodiment, for example, the second gate insulating layer 123 may include or consist of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

The second conductive layer CDL2 is disposed on the second gate insulating layer 123.

As shown in fig. 13, the second conductive layer CDL2 may include a shielding electrode SHE, a first power level auxiliary line VDSBL1, a gate initialization voltage line VGIL, and an anode initialization voltage line VAIL.

The second conductive layer CDL2 may be formed to include a single layer or multiple layers of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or any alloy thereof.

As shown in fig. 15, the interlayer insulating layer 124 may include an inorganic layer disposed on the second gate insulating layer 123 and covering the second conductive layer CDL2, or consist of an inorganic layer disposed on the second gate insulating layer 123 and covering the second conductive layer CDL 2.

In an embodiment, for example, the interlayer insulating layer 124 may include or consist of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

The third conductive layer CDL3 is disposed on the interlayer insulating layer 124.

As shown in fig. 13, the third conductive layer CDL3 may include a first connection electrode CE1, a second connection electrode CE2, a third connection electrode CE3, a first power vertical auxiliary line VDSBL2, a gate initialization voltage auxiliary line VGIAL, and an anode initialization voltage auxiliary line vanal.

Referring to fig. 13 and 15, the pixel driver PXD (refer to fig. 5, 6 and 11) may include a first contact hole CT1, a second contact hole CT2, a third contact hole CT3, a fourth contact hole CT4, a fifth contact hole CT5, a sixth contact hole CT6 and a seventh contact hole CT7.

The first contact hole CT1 is used to connect between the first connection electrode CE1 and the gate electrode GDT of the driving transistor DT.

The first contact hole CT1 may correspond to a portion of the gate electrode GDT of the driving transistor DT and may penetrate the second gate insulating layer 123 and the interlayer insulating layer 124. Thus, the first connection electrode CE1 including or consisting of the third conductive layer CDL3 may be electrically connected to the gate electrode GDT of the driving transistor DT including or consisting of the first conductive layer CDL1 through the first contact hole CT 1.

The second contact hole CT2 is used to connect between any one of the drain electrode D12 of the second sub-transistor ST12 and the source electrode S31 of the third sub-transistor ST31 and the first connection electrode CE 1. The drain electrode D12 of the second sub-transistor ST12 is connected to the source electrode S31 of the third sub-transistor ST 31.

The second contact hole CT2 may correspond to a portion of any one of the drain electrode D12 of the second sub-transistor ST12 and the source electrode S31 of the third sub-transistor ST31, and may penetrate the first gate insulating layer 122, the second gate insulating layer 123, and the interlayer insulating layer 124. Accordingly, the first connection electrode CE1 including or consisting of the third conductive layer CDL3 may be electrically connected to the drain electrode D12 of the second sub-transistor ST12 and the source electrode S31 including or consisting of the semiconductor layer SEL and the third sub-transistor ST31 through the second contact hole CT 2.

In addition, the gate electrode GDT of the driving transistor DT may be electrically connected to the drain electrode D12 of the second sub-transistor ST12 and the source electrode S31 of the third sub-transistor ST31 through the first contact hole CT1, the second contact hole CT2, and the first connection electrode CE 1.

The third contact hole CT3 is used to connect between the shielding electrode SHE and the first power vertical auxiliary line VDSBL2.

The third contact hole CT3 may correspond to a portion of the first power vertical auxiliary line VDSBL2 and pass through the interlayer insulating layer 124. Thus, the shielding electrode SHE including or consisting of the second conductive layer CDL2 may be electrically connected to the first power vertical auxiliary line VDSBL2 including or consisting of the third conductive layer CDL3 through the third contact hole CT 3.

The fourth contact hole CT4 is used to connect between the second connection electrode CE2 and the source electrode S2 of the second transistor ST 2.

The fourth contact hole CT4 may correspond to a portion of the source electrode S2 of the second transistor ST2 and may pass through the first gate insulating layer 122, the second gate insulating layer 123, and the interlayer insulating layer 124. Accordingly, the second connection electrode CE2 including or consisting of the third conductive layer CDL3 may be electrically connected to the source electrode S2 including or consisting of the semiconductor layer SEL or the second transistor ST2 through the fourth contact hole CT 4.

The fifth contact hole CT5 is used to connect between the first power horizontal auxiliary line VDSBL1 and the first power vertical auxiliary line VDSBL 2.

The fifth contact hole CT5 may correspond to a portion of the first power level auxiliary line VDSBL1 and may pass through the interlayer insulating layer 124. Thus, the first power vertical auxiliary line VDSBL2 including or consisting of the third conductive layer CDL3 may be connected to the first power horizontal auxiliary line VDSBL1 including or consisting of the second conductive layer CDL2 through the fifth contact hole CT 5.

The sixth contact hole CT6 is used to connect between the first power vertical auxiliary line VDSBL2 and the source electrode S5 of the fifth transistor ST 5.

The sixth contact hole CT6 may correspond to a portion of the source electrode S5 of the fifth transistor ST5 and may pass through the first gate insulating layer 122, the second gate insulating layer 123, and the interlayer insulating layer 124. Accordingly, the first power vertical auxiliary line VDSBL2 including or consisting of the third conductive layer CDL3 may be electrically connected to the source electrode S5 of the fifth transistor ST5 including or consisting of the semiconductor layer SEL through the sixth contact hole CT 6.

The seventh contact hole CT7 is used to connect between the third connection electrode CE3 and the drain electrode D5 of the fifth transistor ST 5.

The seventh contact hole CT7 may correspond to a portion of the drain electrode D5 of the fifth transistor ST5 and may pass through the first gate insulating layer 122, the second gate insulating layer 123, and the interlayer insulating layer 124. Accordingly, the third connection electrode CE3 including or consisting of the third conductive layer CDL3 may be electrically connected to the drain electrode D5 of the fifth transistor ST5 including or consisting of the semiconductor layer SEL through the seventh contact hole CT 7.

The third conductive layer CDL3 may have a multilayer structure including a metal layer having a relatively low resistance characteristic and metals disposed on top and bottom surfaces of the metal layer, respectively, and having ion diffusion preventing characteristics.

In an embodiment, for example, the third conductive layer CDL3 may have a stacked structure of metal layers, and each metal layer of the third conductive layer CDL3 may include or consist of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

Specifically, the metal layer having relatively low resistance characteristics may include or consist of any one of aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), and copper (Cu).

The metal layer having ion diffusion preventing properties may include or consist of titanium (Ti).

That is, the third conductive layer CDL3 may have a stacked structure of titanium (Ti)/aluminum (Al)/titanium (Ti) (Ti/Al/Ti).

The first planarization layer 125 covering the third conductive layer CDL3 may include or consist of an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

The fourth conductive layer CDL4 is disposed on the first planarization layer 125.

As shown in fig. 14, the fourth conductive layer CDL4 may include a first power auxiliary line VDAL, a first dummy line DML1, a fourth connection electrode CE4, and a data connection electrode DCE.

The first dummy line DML1 may include a first transmission detour line TDEL1 and a first auxiliary line ASL1.

The fourth conductive layer CDL4 may be formed to include a single layer or multiple layers of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or any alloy thereof.

Like the third conductive layer CDL3, the fourth conductive layer CDL4 may have a stacked structure of metal layers, and each metal layer of the third conductive layer CDL3 may include or consist of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

That is, the fourth conductive layer CDL4 may have a stacked structure of titanium (Ti)/aluminum (Al)/titanium (Ti) (Ti/Al/Ti).

As shown in fig. 15, the second planarization layer 126 covering the fourth conductive layer CDL4 may include or consist of an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

Since the fourth conductive layer CDL4 includes the first dummy line DML1 and the second planarization layer 126 covers the fourth conductive film CDL4, the VIA layer VIA1 (refer to fig. 8 and 9) may include the second planarization layer 126.

A fifth conductive layer CDL5 is disposed on the second planarization layer 126.

As shown in fig. 14, the fifth conductive layer CDL5 may include a data line DL, a second dummy line DML2, and a fifth connection electrode CE5.

The second dummy line DML2 may include a second transmission detour line TDEL2 and a second auxiliary line ASL2.

The fifth conductive layer CDL5 may be formed to include a single layer or multiple layers of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or any alloy thereof.

As shown in fig. 15, the third planarization layer 127 covering the fifth conductive layer CDL5 may include or consist of an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

The eighth contact hole CT8 is used to connect between the fourth connection electrode CE4 and the third connection electrode CE3.

The eighth contact hole CT8 may correspond to a portion of the third connection electrode CE3 and may penetrate the first planarization layer 125. Accordingly, the fourth connection electrode CE4 including or consisting of the fourth conductive layer CDL4 may be electrically connected to the third connection electrode CE3 including or consisting of the third conductive layer CDL3 through the eighth contact hole CT 8.

The ninth contact hole CT9 is used for connection between the fourth connection electrode CE4 and the fifth connection electrode CE 5.

The ninth contact hole CT9 may correspond to another portion of the fourth connection electrode CE4 and penetrate the second planarization layer 126. Thus, the fifth connection electrode CE5 including or consisting of the fifth conductive layer CDL5 may be electrically connected to the fourth connection electrode CE4 including or consisting of the fourth conductive layer CDL4 through the ninth contact hole CT 9.

The tenth contact hole CT10 is for connection between the data connection electrode DCE and the second connection electrode CE2.

The tenth contact hole CT10 may correspond to a portion of the second connection electrode CE2 and may penetrate the first planarization layer 125. Thus, the data connection electrode DCE including or consisting of the fourth conductive layer CDL4 may be electrically connected to the second connection electrode CE2 including or consisting of the third conductive layer CDL3 through the tenth contact hole CT 10.

The data connection hole DTCH is used to connect between the data connection electrode DCE and the data line DL.

The data connection hole DTCH may correspond to another portion of the data connection electrode DCE, and may penetrate the second planarization layer 126. Accordingly, the data line DL may be electrically connected to the data connection electrode DCE through the data connection hole DTCH.

As shown in fig. 15, the light emitting element layer 130 may be disposed on the third planarization layer 127 of the circuit layer 120.

In an embodiment, for example, the light emitting element layer 130 may include: anode electrodes AND disposed on the third planarization layer 127, respectively corresponding to the emission areas EA, AND respectively electrically connected to the pixel drivers PXD; a pixel defining layer PDL which is provided on the third planarization layer 127, corresponds to the non-emission region NEA as a separation region between the emission regions EA, AND covers an edge of the anode electrode AND; light emitting layers EML corresponding to the emission areas EA, respectively, AND disposed on the anode electrodes AND, respectively; and a cathode electrode CTD which is disposed on the pixel defining layer PDL and the light emitting layer EML corresponding to the emission area EA, and is electrically connected to the second power line VSSPL.

The anode electrode AND may be connected to the fifth connection electrode CE5 through an anode contact hole ANCT penetrating the third planarization layer 127.

Accordingly, the anode electrode AND may be electrically connected to the fourth transistor ST4 AND the sixth transistor ST6 through the seventh contact hole CT7, the third connection electrode CE3, the eighth contact hole CT8, the fourth connection electrode CE4, the ninth contact hole CT9, the fifth connection electrode CE5, AND the anode contact hole ANCT.

The pixel defining layer PDL may include or consist of an organic layer.

The light emitting layer EML may include an organic light emitting material.

Although not shown separately, at least a first common layer (not shown) including a hole transport material may be disposed between the anode electrode AND the light emitting layer EML.

A second common layer (not shown) including at least an electron transport material may be disposed between the emission layer EML and the cathode electrode CTD.

The cathode electrode CTD may correspond to the display area DA.

Although not shown separately, the cathode electrode CTD may be electrically connected to the second power line VSSPL in the non-display area NDA.

Accordingly, the light emitting element layer 130 may include light emitting elements LEL respectively corresponding to the emission regions EA, AND each of the light emitting elements LEL has a structure including anode AND cathode electrodes AND CTD facing each other AND a light emitting layer EML interposed therebetween.

The light emitting element layer 130 may be covered with an encapsulation layer 140 to block permeation of oxygen or moisture.

The encapsulation layer 140 may cover the light emitting element layer 130 and may have a structure in which at least one inorganic layer and at least one organic layer are cross-stacked.

In an embodiment, for example, the encapsulation layer 140 may include: a first inorganic layer 141 including or consisting of an inorganic insulating material, covering the cathode electrode CTD, and contacting the interlayer insulating layer 124 in the non-display area NDA; an organic layer 142, the organic layer 142 including or consisting of an organic insulating material, disposed on the first inorganic layer 141, and corresponding to the display area DA; and a second inorganic layer 143, the second inorganic layer 143 including or consisting of an inorganic insulating material, covering the organic layer 142, and contacting the first inorganic layer 141 in the non-display area NDA.

Fig. 16 is a plan view showing the fourth conductive layer and the fifth conductive layer in part H of fig. 5 according to the first embodiment.

Fig. 16 is a plan view showing two pixel drivers PXD disposed in the second detour side area SDA2 and adjacent to each other in the first direction DR 1.

Referring to fig. 16, the second data line DL2 may include a second main extension MEX2 extending in the second direction DR2, and fifth and sixth sub-protrusions SPR5 and SPR6 protruding from the second main extension MEX 2.

The fifth sub-protrusion SPR5 may overlap the second dummy hole DMH2 and the dummy electrode DME (which is independent of the electrical connection).

The sixth sub-protrusion SPR6 may overlap the data connection electrode DCE and the data connection hole DTCH of the pixel driver PXD (refer to fig. 5, 6 and 11).

The second transmission detour line TDEL2 adjacent to the second data line DL2 may include a third main extension MEX3 and seventh and eighth sub-protrusions SPR7 and SPR8 protruding from the third main extension MEX3 and facing the fifth and sixth sub-protrusions SPR5 and SPR6, respectively, of the second data line DL 2.

The seventh sub-protrusion SPR7 may overlap the second sub-branch SBR2 of the first transmission detour TDEL 1.

The second detour connection hole DECH2 for the electrical connection between the first transmission detour line TDEL1 and the second transmission detour line TDEL2 may overlap the second sub-branch SBR2 and the seventh sub-protrusion SPR 7.

The eighth sub-tab SPR8 may overlap the third dummy hole DMH3 and the dummy electrode DME (which is independent of the electrical connection).

As shown in fig. 16, the pixel driver PXD of the second detour side area SDA2 is substantially the same as the pixel driver of the first detour side area SDA1 shown in fig. 14 except that the components provided as the fifth conductive layer CDL5 are not the first data line DL1 and the second auxiliary line ASL2 but the second data line DL2, the second transmission detour line TDEL2, and the second auxiliary line ASL2, so that a redundant description thereof will be omitted.

Fig. 17 is a plan view showing the fourth conductive layer and the fifth conductive layer in part G of fig. 5 according to the second embodiment.

Referring to fig. 17, the display device 10 according to the second embodiment is substantially the same as the display device according to the first embodiment of fig. 14 except that the first data line DL1 of the circuit layer 120 (refer to fig. 3) includes an inclined portion OBL for connecting the first main extension MEX1 and the second sub-protrusion SPR2 and extending in a predetermined oblique line direction intersecting the first direction DR1 and the second direction DR2, so that a redundant description thereof will be omitted hereinafter.

The inclined portion OBL may connect the opposite side of the second sub-protrusion SPR2 in the second direction DR2 to the first main extension MEX1.

As described above, according to the second embodiment, the first data line DL1 includes the inclined portion OBL, so that the width of the overlapping region between each of the second connection electrode CE2 and the data connection electrode DCE and the first data line DL1 can be reduced. Accordingly, unnecessary parasitic capacitance can be prevented, and malfunction of the pixel driver PXD can be prevented.

Since the second and third data lines DL2 and DL3 according to the second embodiment are substantially the same as the first data line DL1 of fig. 17, redundant description thereof will be omitted hereinafter.

Fig. 18 is a plan view showing the fourth conductive layer and the fifth conductive layer in part G of fig. 5 according to the third embodiment.

Referring to fig. 18, the display device 10 according to the third embodiment is substantially the same as the display device according to the second embodiment of fig. 17 except that the first main stream MST1 of the first transmission detour line TDEL1 of the circuit layer 120 (refer to fig. 3) is spaced apart from each of the first and second sub-protrusions SPR1 and SPR2 of the first data line DL1 and is disposed between the first and second sub-protrusions SPR1 and SPR2 of the first data line DL1 in the second direction DR2, so that redundant description thereof will be omitted hereinafter.

Fig. 19 is a layout diagram showing a portion F of fig. 4 according to the fourth embodiment. Fig. 20 is a layout diagram showing the data lines, the first dummy lines, and the second dummy lines in a portion of each of the first hole vicinity side region and the second hole vicinity side region of fig. 19. Fig. 21 is a sectional view showing a plane taken along a line L-L' of fig. 20.

The main area MA of the display device 10 according to the fourth embodiment may include a hole area HLA surrounded by the display area DA.

Referring to fig. 19, and also to fig. 3, the substrate 110 of the display panel 100 of the display device 10 according to the fourth embodiment may further include a penetration portion THM disposed in the hole region HLA and penetrating the display panel 100.

The display panel 100 of the display device 10 may further include a penetration portion vicinity seal portion (not shown) provided between the penetration portion THM in the hole region HLA and the display region DA.

The penetrating portion THM may overlap at least a portion of a functional module (not shown) disposed outside the display panel 100, and may be provided as a path for inputting sensing information of the functional module or a path for outputting sound of the functional module.

In the embodiment, for example, the functional module may be disposed to overlap with the penetration portion THM on the rear surface of the display panel 100 and the vicinity thereof, or may be disposed in the penetration portion THM.

In an embodiment, for example, the functional modules may include a camera module for imaging or recognizing an image corresponding to the front surface of the display device 10, a face recognition sensor module for detecting a face of a user, a pupil recognition sensor module for detecting a pupil of the user, an acceleration sensor module and a geomagnetic sensor module for determining movement of the display device, a proximity sensor module and an infrared sensor module for detecting whether the front surface of the display device 10 is close, and an illuminance sensor module for measuring external brightness or the like.

Since the display device 10 includes the hole region HLA, the display region DA may include a hole vicinity region NHA in which a detour line for electrically connecting lines separated by the hole region HLA is provided.

The data lines DL of the circuit layer 120 may include a hole intersecting data line HINDL intersecting the hole region HLA, an adjacent data line ADDL disposed in the hole vicinity region NHA, and other data lines DL'.

The other data lines DL' may include a first data line DL1, a second data line DL2, and a third data line DL3 shown in fig. 6.

The hole intersecting data line HINDL is separated by a hole region HLA, and thus may include a first hole adjacent portion ADHP1 and a second hole adjacent portion ACHP2 spaced apart from each other in the second direction DR 2.

The first hole adjacent portion ADHP1 may be disposed adjacent to one side (lower side of fig. 20) of the hole region HLA in the second direction DR 2.

The second hole adjacent portion ADHP2 may be disposed adjacent to an opposite side (upper side of fig. 20) of the hole region HLA in the second direction DR 2.

Since the first hole adjacent portion ADHP1 and the second hole adjacent portion ACHP2 are spaced apart from each other, the circuit layer 120 of the display device 10 according to the fourth embodiment may further include a first hole detour line HDEL1, a second hole detour line HDEL2, and a third hole detour line HDEL3 provided for electrical connection between the first hole adjacent portion ADHP1 and the second hole adjacent portion ADHP 2.

The first, second, and third via detour lines HDEL1, HDEL2, and HDEL3 may be disposed in a via vicinity area NHA (which is disposed around the via area HLA in the display area DA).

According to the fourth embodiment, the first dummy line DML1 of the circuit layer 120 may further include a first hole detour line HDEL1 electrically connected to the first hole adjacent portion ADHP1 of the hole intersecting data line HINDL and a second hole detour line HDEL2 electrically connected to the second hole adjacent portion ADHP2 of the hole intersecting data line HINDL.

Further, the second dummy line DML2 of the circuit layer 120 may further include a third via detour line HDEL3 for electrically connecting the first via detour line HDEL1 to the second via detour line HDEL2.

The hole vicinity area NHA may be separated by an imaginary line in the first direction DR1 and an imaginary line in the second direction DR2 with respect to a midpoint THC of the hole area HLA. Thus, the hole vicinity NHA can be divided into: the first hole adjacent region HADA11 and the second hole adjacent region HADA12, the first hole adjacent region HADA11 and the second hole adjacent region HADA12 contacting one side of the hole region HLA in the first direction DR1 (left side of fig. 19) and being adjacent to each other in the second direction DR 2; and third and fourth hole adjacent regions HADA21 and HADA22, the third and fourth hole adjacent regions HADA21 and HADA22 being in contact with opposite sides of the hole region HLA (right side of fig. 19) in the first direction DR1 and being adjacent to the first and second hole adjacent regions HADA11 and HADA12 in the first direction DR 1.

The first hole adjacent portion ADHP1 and the second hole adjacent portion ADHP2 provided in the first hole adjacent region HADA11 and the second hole adjacent region HADA12, respectively, may be electrically connected to each other through the first hole detour line HDEL1, the second hole detour line HDEL2, and the third hole detour line HDEL3 provided in the first hole adjacent region HADA11 and the second hole adjacent region HADA 12.

Similarly, the first hole adjacent portion ADHP1 and the second hole adjacent portion ADHP2 provided in the third hole adjacent region HADA21 and the fourth hole adjacent region HADA22, respectively, may be electrically connected to each other through the first hole detour line HDEL1, the second hole detour line HDEL2, and the third hole detour line HDEL3 provided in the third hole adjacent region HADA21 and the fourth hole adjacent region HADA 22.

A portion of the hole vicinity area NHA may be included in the display area DA, and another portion of the hole vicinity area NHA may be included in the non-display area NDA.

The hole intersecting data line HINDL may be adjacent to the second auxiliary line ASL 2.

The first hole detour HDEL1 may extend in the first direction DR1 between the first hole adjacent portion ADHP1 and the third hole detour HDEL 3.

The second hole detour HDEL2 may extend between the second hole adjacent portion ADHP2 and the third hole detour HDEL3 in the first direction DR 1.

The third via detour line HDEL3 may be adjacent to the adjacent data line ADDL, and may extend between the first via detour line HDEL1 and the second via detour line HDEL2 in the second direction DR 2.

Referring to fig. 20, the first hole detour HDEL1 may include a third main stream MST3 extending in the first direction DR1 between the first hole adjacent portion ADHP1 and the third hole detour HDEL3, a fourth sub-branch SBR4 extending from the third main stream MST3 in the second direction DR2 and overlapping a portion of the first hole adjacent portion ADHP1, and a fifth sub-branch SBR5 extending from the third main stream MST3 in the second direction DR2 and overlapping a portion of the third hole detour HDEL 3.

The second hole detour HDEL2 may include a fourth main stream MST4 extending in the first direction DR1 between the second hole adjacent portion ADHP2 and the third hole detour HDEL3, a sixth sub-branch SBR6 extending from the fourth main stream MST4 in the second direction DR2 and overlapping a portion of the third hole detour HDEL3, and a seventh sub-branch SBR7 extending from the third main stream MST3 in the second direction DR2 and overlapping a portion of the second hole adjacent portion ADHP 2.

The first hole detour HDEL1 may be electrically connected to the first hole adjacent portion ADHP1 through a first hole detour connection hole HDCH1 defined in an overlapping region between the fourth sub-branch SBR4 and one of the sub-protrusions of the first hole adjacent portion ADHP1.

The first hole detour HDEL1 may be electrically connected to the third hole detour HDEL3 through the second hole detour connection hole HDCH2 defined in the overlapping region between the fifth sub-branch SBR5 and one sub-protrusion of the third hole detour HDEL3.

Therefore, the first hole adjacent portion ADHP1 may be electrically connected to the third hole detour HDEL3 through the first hole detour HDEL 1.

The second hole detour HDEL2 may be electrically connected to the third hole detour HDEL3 through a third hole detour connection hole HDCH3 defined in an overlapping region between the sixth sub-branch SBR6 and the other sub-protrusion of the third hole detour HDEL3.

The second hole detour HDEL2 may be electrically connected to the second hole adjacent portion ADHP2 through a fourth hole detour connection hole HDCH4 defined in an overlapping region between the seventh sub-branch SBR7 and one of the sub-protrusions of the second hole adjacent portion ADHP2.

Therefore, the second hole adjacent portion ADHP2 may be electrically connected to the third hole detour HDEL3 through the second hole detour HDEL 2.

Accordingly, the first hole adjacent portion ADHP1 and the second hole adjacent portion ADHP2 of the hole intersecting data line HINDL may be electrically connected to each other through the first hole detour line HDEL1, the second hole detour line HDEL2, and the third hole detour line HDEL3.

Referring to fig. 21, each of the first, second, third, and fourth VIA-detour connection holes HDCH1, HDCH2, HDCH3, and HDCH4 may penetrate the VIA layer VIA1.

However, the effects of the present disclosure are not limited to those described herein. The above and other effects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referencing the claims.

Claims

1. A display device, wherein the display device comprises:

a substrate, the substrate comprising:

a main region including a display region in which an emission region is arranged and a non-display region disposed around the display region;

a sub-region protruding from one side of the main region;

a circuit layer disposed on the substrate and including a plurality of pixel drivers corresponding to the emission regions, respectively; and

a light emitting element layer provided on the circuit layer and including a plurality of light emitting elements respectively corresponding to the emission regions,

wherein the circuit layer comprises:

the plurality of pixel drivers electrically connected to the plurality of light emitting elements of the light emitting element layer, respectively;

A plurality of data lines transmitting data signals to the plurality of pixel drivers;

a plurality of first dummy lines extending in a first direction crossing the plurality of data lines; and

a plurality of second dummy lines extending in a second direction parallel to the plurality of data lines and respectively adjacent to the plurality of data lines,

the plurality of data lines and the plurality of second dummy lines are disposed on a via layer covering the plurality of first dummy lines,

one of the plurality of pixel drivers is adjacent to one of the plurality of data lines and one of the plurality of second dummy lines,

each of the one of the plurality of data lines and the one of the plurality of second dummy lines includes:

a main extension extending in the second direction; and

a pair of sub-protrusions protruding from the main extension, the pair of sub-protrusions being adjacent to the one of the plurality of pixel drivers, and the pair of sub-protrusions overlapping with vias penetrating the via layer.

2. The display device according to claim 1, wherein, in the display region, a detour region adjacent to the sub-region includes: a detour intermediate region disposed centrally in the first direction, a first detour side region parallel to the detour intermediate region in the first direction and in contact with the non-display region, and a second detour side region disposed between the detour intermediate region and the first detour side region,

The plurality of data lines includes a first data line disposed in the first detour side region and a second data line disposed in the second detour side region,

the plurality of first dummy lines includes a first transmission detour electrically connected to the first data line,

the plurality of second dummy lines includes a second transmission detour line adjacent to the second data line and electrically connected to the first transmission detour line, an

The first transmission detour line includes:

a first main stream extending in the first direction between the first data line and the second transmission detour line;

a first sub-branch provided in the first detour side region, the first sub-branch extending from the first main flow in the second direction, and overlapping a portion of the first data line; and

a second sub-branch provided in the second detour side region, the second sub-branch extending from the first main flow in the second direction, and the second sub-branch overlapping a portion of the second transmission detour line.

3. The display device of claim 2, wherein the circuit layer further comprises:

a plurality of first power lines and a plurality of second power lines disposed in the non-display region and transmitting first power and second power for driving the plurality of light emitting elements, respectively; and

a first power auxiliary line provided in the display region, extending in the first direction, adjacent to the plurality of first dummy lines, respectively, and electrically connected to the plurality of first power lines,

the plurality of first dummy lines includes a plurality of first auxiliary lines electrically connected to the plurality of second power lines and the first transmission detour line,

the plurality of second dummy lines include a plurality of second auxiliary lines electrically connected to the plurality of second power supply lines and the second transmission detour line, and

one of the plurality of first auxiliary lines includes:

a second main flow extending in the first direction; and

a third sub-branch extending from the second main flow in the second direction and overlapping a portion of one of the plurality of second auxiliary lines.

4. A display device according to claim 3, wherein each of the plurality of pixel drivers includes a data connection electrode electrically connected to one of the plurality of data lines through a data connection hole, and

among the vias, the remaining vias except some of the vias overlapping the data connection electrode, the first sub-branch, the second sub-branch, and the third sub-branch overlap the dummy electrode covered with the via layer, respectively.

5. The display device of claim 4, wherein the substrate further comprises an aperture region surrounded by the display region,

the plurality of data lines further includes an aperture intersection data line intersecting the aperture region,

the hole intersecting data line includes:

a first hole adjacent portion provided adjacent to one side of the hole region in the second direction; and

a second hole adjacent portion provided adjacent to an opposite side of the hole region in the second direction,

the plurality of first dummy lines further includes:

a first via detour electrically connected to the first via adjacent portion of the via-intersecting data line; and

A second hole detour electrically connected to the second hole adjacent portion of the hole intersecting data line,

the plurality of second dummy lines further includes a third hole detour electrically connecting the first hole detour and the second hole detour, and

the first hole detour line includes:

a third main flow extending in the first direction between the first hole adjacent portion and the third hole detour;

a fourth sub-branch extending from the third main flow in the second direction and overlapping a portion of the first hole adjacent portion; and

a fifth sub-branch extending from the third main flow in the second direction and overlapping with a portion of the third hole detour.

6. The display device according to claim 5, wherein the second aperture detour line comprises:

a fourth main flow extending in the first direction between the second hole adjacent portion and the third hole detour;

a sixth sub-branch extending from the fourth main flow in the second direction and overlapping with a portion of the third hole detour; and

A seventh sub-branch extending from the fourth main flow in the second direction and overlapping a portion of the second hole adjacent portion.

7. The display device according to claim 4, wherein the pair of sub-protrusions includes a first sub-protrusion and a second sub-protrusion, and

the first main stream of the first transmission detour line is disposed closer to the first sub-protrusion of the first data line and the first sub-protrusion of the second sub-protrusion in the second direction.

8. The display device according to claim 4, wherein the pair of sub-protrusions includes a first sub-protrusion and a second sub-protrusion, and

the first main stream of the first transmission detour line is disposed between the first sub-protrusion and the second sub-protrusion of the first data line in the second direction.