CN117855252A - Groove type super-junction MOSFET device and preparation method - Google Patents

Abstract

The invention discloses a groove type super-junction MOSFET device, which is formed by arranging a P-type epitaxial filling layer and an N-type epitaxial layer region repeating unit which are connected with a source electrode in an active region, and adopting the repeating unit of a shallow groove as a device on and off control region, wherein the width of the P-type epitaxial filling layer is wider than the width of the shallow groove, the depth of the P-type epitaxial filling layer is at least 5 times deeper than the depth of the shallow groove, and the device active region formed by matching the repeating units can reduce the on internal resistance and the grid charge Qg of the device, so that the FOM figure of merit of the device is further reduced. Meanwhile, the invention also provides a preparation method of the device, which can be well compatible with the existing MOSFET device manufacturing process, so that the technical bottleneck of the unrealizable process is avoided, and the preparation method has high conversion value.

Description

Groove type super-junction MOSFET device and preparation method

Technical Field

The invention relates to the technical field of semiconductor manufacturing, in particular to a groove type super-junction MOSFET device and a preparation method thereof.

Background

Among power devices, power MOSFETs have found very wide application due to their superior performance. And because the downstream application has different performance requirements on the voltage resistance, the switching frequency, the on-resistance and the like of the MOSFET device, the MOSFET device develops MOSFET types with different structures such as plane, trench, super Junction and Shield Gate.

For a power MOSFET, its main losses come from two aspects: firstly, the on-loss is determined by the on-resistance in the power MOSFET device, if the on-resistance is required to be smaller, the channel length of the device is continuously reduced, and when the unit cell density of the device is increased, the channel resistance and the epitaxial layer resistance of the whole device are reduced by reducing the thickness of the device and changing the unit cell structure of the device from a plane type to a groove type, so that the whole on-resistance of the device is reduced; second, switching losses, i.e., power losses introduced by parasitic capacitance charge-discharge processes or parasitic diode reverse recovery time delays during switching of the power MOSFET. The on-resistance (Rdson) and the gate charge (Qg) are generally selected as indexes for evaluating the switching loss, but because the requirements of different application fields on the switching loss and the on-loss of the device are different, the optimal value (FOM) of the product of the on-resistance (Rdson) and the gate charge (Qg) is generally used as a standard for evaluating the cost performance of the device, and the on-resistance (Ron, sp) in unit area is used as an important key index for measuring the on-loss in unit area of the device, and the lower the on-resistance is, the better the on-resistance is.

At present, the development direction of the power MOSFET is how to effectively reduce the on-resistance. However, the breakdown voltage and on-resistance in power MOSFETs are contradictory, because the high withstand voltage has a low concentration and a thicker drift region; and as the thickness of the drift region increases and the concentration decreases, the resistance of the drift region, which is the main part of the on-resistance of the device, increases, resulting in a large increase in the on-resistance. In general, the on-resistance of a power MOSFET increases to about 2.5 times with the change of breakdown voltage, and for a high voltage power device (voltage exceeding 200V), a planar MOSFET usually needs at least 25um epitaxial layer thickness to meet the voltage withstanding requirement of the device, and an increase in epitaxial layer thickness leads to a steep increase in on-resistance. Therefore, it is difficult for the conventional power MOSFET to meet the use requirements of smaller on-resistance and gate charge Qg.

Disclosure of Invention

The first aspect of the present invention provides a trench-type superjunction MOSFET device, where a superjunction structure is formed by disposing a P-type epitaxial filling layer and an N-type epitaxial layer region repeating unit in an active region, which are connected to a source, and using a repeating unit of a shallow trench as a device on and off control region, where the P-type epitaxial filling layer is wider than the shallow trench and has a depth at least 5 times deeper than the shallow trench. The groove type super-junction MOSFET device is suitable for a high-voltage range with breakdown voltage of more than 200V, and the on-resistance of the device can be further reduced. The device active region formed by the repeated unit collocation can reduce the device conduction internal resistance and the grid charge Qg so as to further reduce the device FOM figure of merit.

The second aspect of the present invention provides a method for manufacturing the trench super-junction MOSFET device, which is well compatible with the existing MOSFET device manufacturing process, so that the method does not bring about a technical bottleneck of an unrealizable process, and has a high conversion value.

The technical scheme provided by the invention is as follows:

a trench superjunction MOSFET device adapted for use in a voltage range of 200V or more, the trench superjunction MOSFET device comprising an n+ substrate;

the N-epitaxial layer is arranged on the N+ substrate, and the surface of the N-epitaxial layer is sequentially divided into a terminal voltage-resistant area and an active area along a first direction;

the first type grooves are independent block grooves, the first type grooves are etched and formed in the terminal voltage-resistant area and the active area, the first type grooves are filled with P-type epitaxial filling layers, the first type grooves are arranged in a staggered mode, and the distance between any two adjacent first type grooves is equal;

the second type grooves are etched and formed in the active area, groove metal layers are filled in the second type grooves, the second type grooves are strip-shaped grooves or closed type grooves, the strip-shaped grooves are formed between the adjacent first type grooves, the strip-shaped grooves extend from one side of the N-epitaxial layer to the other side along a second direction, and the adjacent strip-shaped grooves are isolated from each other; the closed type grooves are formed on the periphery of each first type groove in the active area;

The width of the first type of groove exceeds the width of the second type of groove, and the depth of the first type of groove exceeds more than five times of the depth of the second type of groove;

the P-type body region is implanted and formed on the surface of the N-epitaxial layer;

the N+ source region is implanted and formed on the surface of the P-type body region;

the isolation layer is deposited on the upper surface of the N-epitaxial layer, and a source electrode metal layer is arranged on the surface of the isolation layer;

the contact holes comprise a first type contact hole and a second type contact hole which are formed in the active area in a deposited mode, one end of the first type contact hole is in contact with the P-type epitaxial filling layer, and the other end of the first type contact hole penetrates through the isolation layer to be in contact with the source metal layer; the second type contact hole is used for connecting the P-type body region and the source electrode metal layer;

if the second type of grooves are strip-shaped grooves, the contact holes comprise first type of contact holes and second type of contact holes which are connected in a whole, the contact holes are parallel to the second type of grooves, the contact holes extend from one side of the N-epitaxial layer to the other side of the N-epitaxial layer along the second direction, the contact holes are connected with all the first type of grooves distributed along the second direction, the first type of contact holes are connected with a P-type epitaxial filling layer and a source electrode metal layer in the first type of grooves, and the second type of contact holes are connected with a P-type body region and the source electrode metal layer; the depth of the first type grooves is larger than 3um, and the interval between any two adjacent first type grooves is larger than 3um;

If the second type of groove is a closed type groove, the contact holes are a first type of blocky contact hole and an annular second type of contact hole, the first type of contact hole is respectively used for connecting the P-type epitaxial filling layer and the source electrode metal layer which are distributed in the active area, the second type of contact hole is respectively formed between the first type of contact hole and the second type of groove corresponding to the first type of contact hole, different second type of contact holes are isolated from each other, and each second type of contact hole is of a closed structure.

Further, the semiconductor device further comprises a drain metal layer, wherein the drain metal layer is formed on the back surface of the N+ substrate.

Further, the second type of grooves sequentially penetrate through the N+ source region and the P type body region and extend into the N-epitaxial layer.

Further, contact hole injection layers are formed at the contact positions of the second type contact holes and the P-type body region, and are formed by ion injection of P-type heavily doped elements and activation of the injection elements at high temperature.

Further, a gate oxide layer is formed on the side wall of the second type groove.

Further, a contact hole metal layer is deposited in the contact hole, and the contact hole metal layer is made of Ti/TiN material;

The isolating layer is silicon dioxide containing boron and phosphorus elements.

Further, if the second type of grooves are strip-shaped grooves, the second type of grooves are formed in the middle positions of the adjacent first type of contact holes, and the adjacent two rows of the first type of grooves are arranged in a staggered manner along the first direction and/or the second direction;

if the second type grooves are closed grooves, each second type groove is communicated with the other adjacent second type grooves.

Meanwhile, the invention also provides a preparation method of the groove type super junction MOSFET device, which is used for preparing the groove type super junction MOSFET device and comprises the following steps:

s100, providing an N+ substrate, and stacking an N-epitaxial layer on the N+ substrate;

s200, depositing a first hard mask oxide layer on the surface of the N-epitaxial layer, determining the position of a first type of groove through photoresist and a hard mask plate, etching the exposed hard mask plate, removing the photoresist, and forming the first type of groove by taking the hard mask plate as a blocking etch;

s300, depositing and forming a P-type epitaxial filling layer in all the first type trenches, removing the P-type doped epitaxial layer on the surface of the wafer by a CMP (chemical mechanical polishing) mode, stopping on the surface of the first hard mask oxide layer, removing the first hard mask oxide layer by a wet method mode, and determining a terminal voltage-resistant area and an active area;

S400, defining a P-type body region to be injected through a photoetching process, injecting P-type doping elements through ions, removing photoresist, and pushing the P-type body region to a first target junction depth through a hot push well mode; defining an N+ source region to be injected through a photoetching process, injecting an N-type heavy doping element through ions, removing photoresist, and pushing the N+ source region to a second target junction depth through a hot push well mode;

s500, depositing a second hard mask oxide layer on the surface of the N-epitaxial layer, defining a second type groove region to be etched in the active region through a photoetching process, removing surface silicon dioxide in a dry etching mode, removing silicon through a dry etching process after photoresist is removed to form the second type groove, growing a high-quality gate oxide layer through a gate oxide process, and depositing a groove metal layer in the second type groove;

s600, removing the second hard mask oxide layer by a wet method, depositing a layer of silicon dioxide containing boron and phosphorus elements on the surface of the N-epitaxial layer to serve as an isolation layer of the device, defining a contact hole area to be etched in an active area by a photoetching process, forming a contact hole by a dry etching process, forming a contact hole injection layer by ion injection, depositing to form a contact hole metal layer, and depositing a layer of metal layer on the surface of the isolation layer to form a source electrode metal layer; and adopting a back thinning process, evaporating a metal layer on the back of the N+ substrate to form a drain electrode metal layer.

Further, in step S500, if the second type of trench formed by etching is a stripe trench, the stripe trench extends from one side of the N-epi layer to the other side along the second direction, adjacent stripe trenches are isolated from each other, the depth of the first type of trench formed is greater than 3um, and the interval between any two adjacent first type of trenches is greater than 3um;

in step S600, the contact holes formed by etching are a first type contact hole and a second type contact hole, the contact holes are parallel to the second type trenches, and extend from one side of the N-epitaxial layer to the other side along the second direction, the contact holes are connected with all the first type trenches distributed along the second direction in the active region, and the second type trenches are disposed between the adjacent contact holes.

Further, in step S500, if the second type of trench formed by etching is a closed trench;

in step S600, the contact holes formed by etching are a first type contact hole and a second type contact hole, wherein the first type contact hole and the second type contact hole are block-shaped, the second type contact hole penetrates through the n+ source region and extends into the P-type body region, and a contact hole injection layer is formed at the contact positions of the second type contact hole and the P-type body region.

Compared with the prior art, the invention has the beneficial effects that:

1. the invention sets up the P-type epitaxy filling layer and N-type epitaxy layer district repeating unit that links with source electrode in the active area of the device to form the "P-N" super junction structure and adopt the repeating unit of the shallow trench as the device opens and shuts the control area, wherein the width of the P-type epitaxy filling layer is wider than the width of the shallow trench, its depth is deeper than the depth of the shallow trench by more than 5 times; the device active region formed by the matching of the repeated units can reduce the on internal resistance and the grid charge Qg of the device so as to further reduce the figure of merit (FOM) of the device;

2. the super-junction structure repeating unit formed by the P-type epitaxial filling layer and the N-type epitaxial layer region repeating unit connected with the source electrode is arranged in the active region of the device, is used for supporting the breakdown voltage of the active region of the device, is mainly suitable for a high-voltage range with the breakdown voltage of more than 200V, and can further reduce the on-resistance of the device;

3. the invention adopts the repeated unit of the shallow groove as the device opening and closing control area in the device active area, which can further reduce the grid charge Qg of the device;

4. in the invention, the peripheral terminal part (namely the terminal voltage-resistant area) also adopts the P-type epitaxial filling layer repeating units which are arranged in a suspending way to form a super-junction structure, so that the peripheral terminal of the device generates an electric field shielding effect and the electric field distribution is smoother to improve the terminal voltage resistance of the device, and the device has high stability;

4. The preparation method of the trench super-junction MOSFET device provided by the invention can be well compatible with the existing MOSFET device manufacturing process, so that the technical bottleneck of the unrealizable process is avoided, and the conversion value is very high.

Drawings

FIG. 1 is a layout I of a termination cross-over region of a trench superjunction MOSFET device in an embodiment of the present invention;

fig. 2 is a cross-sectional view of a trench superjunction MOSFET device along the AY direction of a termination cross-over region layout one in an embodiment of the present invention;

FIG. 3 is a layout II of a termination junction region of a trench superjunction MOSFET device in an embodiment of the present invention;

fig. 4 is a cross-sectional view of a trench superjunction MOSFET device along the BY direction of the termination cross-over region layout two in an embodiment of the present invention;

fig. 5 is a schematic diagram of one step in the fabrication of a trench superjunction MOSFET device according to an embodiment of the present invention;

fig. 6 is a schematic diagram of a second step in the fabrication of a trench superjunction MOSFET device according to an embodiment of the present invention;

fig. 7 is a schematic diagram of a third step in the fabrication of a trench superjunction MOSFET device according to an embodiment of the present invention;

fig. 8 is a schematic diagram of one of the steps in the fabrication of a trench superjunction MOSFET device according to an embodiment of the present invention;

fig. 9 is a schematic diagram of a fifth step in the fabrication of a trench superjunction MOSFET device according to an embodiment of the present invention;

Fig. 10 is a schematic diagram of a sixth step in the fabrication of a trench superjunction MOSFET device according to an embodiment of the present invention;

fig. 11 is a schematic diagram of a seventh step in the fabrication of a trench superjunction MOSFET device according to an embodiment of the present invention;

fig. 12 is a schematic diagram of one step eight of fabricating a trench superjunction MOSFET device in accordance with an embodiment of the present invention;

fig. 13 is a schematic diagram of one step nine of preparing a trench superjunction MOSFET device according to an embodiment of the present invention;

fig. 14 is a schematic diagram showing one of the steps in the fabrication of a trench superjunction MOSFET device according to an embodiment of the present invention;

fig. 15 is a schematic diagram of one step eleven of the fabrication of a trench superjunction MOSFET device according to an embodiment of the present invention;

fig. 16 is a schematic diagram showing twelve steps in preparing a trench superjunction MOSFET device according to an embodiment of the present invention;

fig. 17 is a schematic diagram of thirteen steps in preparing a trench superjunction MOSFET device according to an embodiment of the present invention;

fig. 18 is a schematic diagram showing fourteen steps in preparing a trench superjunction MOSFET device according to an embodiment of the present invention.

The reference numerals are as follows:

1-N+ substrate, 2-N-epitaxial layer, 3-first type trench, 4-P type epitaxial filling layer, 5-P type body region, 6-N+ source region, 7-first hard mask oxide layer, 8-second type trench, 9-gate oxide layer, 10-trench metal layer, 11-isolation layer, 12-contact hole, 13-contact hole injection layer, 14-contact hole metal layer, 15-source metal layer, 16-drain metal layer, 17-second hard mask oxide layer, 100-terminal voltage-withstanding region and 200-active region.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It will be apparent that the embodiments described below are some, but not all, of the embodiments of the present application. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations.

Accordingly, the following detailed description of the embodiments of the present application, taken in conjunction with the accompanying drawings, is intended to represent only selected embodiments of the present application, and not to limit the scope of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

It should be understood that in the description of embodiments of the invention, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, features defining "first," "second," etc. may explicitly or implicitly include one or more of the described features.

In describing embodiments of the present invention, it should be noted that, unless explicitly stated and limited otherwise, the terms "disposed," "mounted," "connected," and "connected" should be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically connected, electrically connected or can be communicated with each other; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the embodiments of the present invention can be understood by those of ordinary skill in the art according to specific circumstances.

Referring to fig. 1-4, the present invention provides a trench superjunction MOSFET device suitable for a voltage range above 200V, the trench superjunction MOSFET device comprising an n+ substrate 1, an N-epitaxial layer 2, a first type trench 3, a second type trench 8, a P-type body region 5, an n+ source region 6, an isolation layer 11, a contact hole 12, and a source metal layer 15.

The N-epitaxial layer 2 is disposed on the n+ substrate 1, and the surface of the N-epitaxial layer 2 is sequentially divided into a termination voltage-resistant region 100 and an active region 200 along a first direction, i.e., an AY or BY direction in fig. 1 or 3.

The first type trenches 3 are independent block-shaped trenches, the first type trenches 3 are etched and formed in the terminal voltage-resistant area 100 and the active area 200, the first type trenches 3 are filled with the P-type epitaxial filling layers 4, the first type trenches 3 are arranged in a staggered mode, the distances between any two adjacent first type trenches 3 are equal, and the setting of the distances needs to ensure that the distance positions between the first type trenches 3 in all directions are completely exhausted when the device is reversely biased.

The second type of groove 8 is etched and formed in the active area 200, a groove metal layer 10 is filled in the second type of groove 8, the second type of groove 8 is a strip-shaped groove or a closed-type groove, the strip-shaped groove is formed between the adjacent first type of grooves 3, the strip-shaped groove extends from one side of the N-epitaxial layer 2 to the other side along a second direction (perpendicular to the first direction), and the adjacent strip-shaped grooves are isolated from each other; a closed trench is formed around each first type trench 3 in the active region 200.

The width of the first type trenches 3 and the P-type epitaxial filling layer 4 exceeds the width of the second type trenches 8, and the depth of the first type trenches 3 exceeds the depth of the second type trenches 8 by more than five times. The P-type epitaxial filling layer 4 in the first type groove 3 and the N-epitaxial layer 2 between the first type groove 3 form a P-N super junction structure, the depth of the first type groove 3 exceeds more than five times of the depth of the second type groove 8, higher breakdown voltage can be obtained when the device is reversely biased, meanwhile, the protection of a gate oxide layer in the second type groove 8 can be formed, and the stability of the device is improved.

The P-type body region 5 is implanted and formed on the surface of the N-epitaxial layer 2.

The n+ source region 6 is implanted and formed on the surface of the P-type body region 5.

The isolation layer 11 is deposited on the upper surface of the N-epitaxial layer 2, and the surface of the isolation layer 11 is provided with the source metal layer 15.

The contact hole 12 comprises a first type contact hole and a second type contact hole which are deposited and formed in the active region 200, wherein one end of the first type contact hole is contacted with the P-type epitaxial filling layer 4, and the other end of the first type contact hole penetrates through the isolation layer 11 to be contacted with the source metal layer 15; the second type of contact holes are used to connect the P-type body region 5 and the source metal layer 15.

As shown in fig. 1, if the second type trench 8 is a stripe trench, the contact hole 12 includes a first type contact hole and a second type contact hole that are smoothly connected, the contact hole 12 is parallel to the second type trench 8, the contact hole 12 extends from one side of the N-epitaxial layer 2 to the other side along the second direction, the contact hole 12 connects all the first type trenches 3 distributed along the second direction, the first type contact hole connects the P-type epitaxial filling layer 4 and the source metal layer 15 in the first type trench 3, and the second type contact hole connects the P-type body region 5 and the source metal layer 15. The depth of the first type grooves 3 is larger than 3um, and the interval between any two adjacent first type grooves 3 is larger than 3um. The P-type epitaxial filling layer 4 in the first type groove 3 and the N-epitaxial layer 2 between the first type groove 3 form a P-N super junction structure, the deeper the first type groove 3 is, the higher breakdown voltage can be obtained when the device is reversely biased, the distance between the first type grooves 3 is used as a current channel of the device in an open state to mainly determine the on-resistance of the device, and on the premise that charge balance is met, the larger the distance is, the smaller the on-resistance of the device is.

It should be noted that, the first type grooves 3 are arranged in a staggered manner, as shown in fig. 1, the first type grooves 3 of the first row are horizontally arranged along the second direction, the distance between the first type grooves 3 is equal, the first type grooves 3 of the second row are translated to the left side by a certain distance, and the distance between the first type grooves 3 of the second row is half of the distance between the two adjacent first type grooves 3. Then, the first type grooves 3 of the third row are arranged, the first type grooves 3 of the third row are parallel and aligned with the first type grooves 3 of the first row, the first type grooves 3 of the second row are positioned between the first type grooves 3 of the first row and the third row, the first type grooves 3 of the fourth row are parallel and aligned with the first type grooves 3 of the second row, and the arrangement is repeated in sequence. Within the active region 200, the first contact holes 13 pass through all of the first type trenches 3 of the row from left to right, and the second contact holes 12 also pass through all of the first type trenches 3 of the row from left to right. The number of the contact holes 12 is equal to the number of the rows of the first type trenches 3 in the active area 200, all the contact holes 12 penetrate through the first type trenches 3 in the row, the first type contact holes in the contact holes 12 are connected with the P-type epitaxial filling layer 4 and the source metal layer 15 in the first type trenches 3, and the second type contact holes are connected with the P-type body region 5 and the source metal layer 15 outside the first type trenches 3. If a cross section is taken along the AY direction in fig. 1, a structure as shown in fig. 2 is formed, and a plurality of repeating units are formed in the active region 200 on the cross section, where each repeating unit includes two first type trenches 3, and two first type contact holes connect the P-type epitaxial filling layer 4 and the source metal layer 15 in the first type trenches 3 respectively. Two second type trenches 8 are arranged between the two first type trenches 3, and as the first type trenches 3 are arranged in a staggered manner, a second type contact Kong Cunzai is arranged between the two first type trenches 3 in fig. 2, and a second type contact hole is formed between the two second type trenches 8.

As shown in fig. 3, if the second type trench 8 is a closed type trench, the contact holes 12 are a first type of block contact hole and a second type of annular contact hole, the first type of contact hole is used for connecting the P-type epitaxial filling layer 4 and the source metal layer 15 distributed in the active region 200, the second type of contact hole is formed between the first type of contact hole and the second type trench 8 corresponding to the first type of contact hole, the different second type of contact holes are isolated from each other, and each second type of contact hole is in a closed structure.

The first type of trench 3 in fig. 3 is arranged in the same manner as in fig. 1, except that the first type of contact hole, the second type of contact hole, and the second type of trench 8 are designed differently. In the scheme, as shown in fig. 3, a closed structure design is adopted, all first type trenches 3 in an active area 200 are provided with first type contact holes for connecting a P-type epitaxial filling layer 4 in the first type trenches 3 with a source metal layer 15, the periphery of each first type trench 3 is also provided with a second type contact hole in an annular closed state, the periphery of each second type contact hole is also provided with a second type trench 8 in an annular closed state, and all second type trenches 8 are connected together to form a closed loop integrally. The second type trenches 8 function as electrical conductors and the first type trenches 3 function to shield the electric field to protect the second type trenches 8. If a cross section is taken along the BY direction in fig. 3, a structure as shown in fig. 4 is formed, and a plurality of repeating units are formed in the active region 200 on the cross section, where each repeating unit includes two first type trenches 3, and two first type contact holes connect the P-type epitaxial filling layer 4 and the source metal layer 15 in the first type trenches 3 respectively. A second type groove 8 is arranged between the two first type grooves 3, a second type contact hole is arranged between the second type groove 8 and the two first type grooves 3, the left side and the right side of the two first type grooves 3 are respectively distributed with the second type groove 8, and a second type contact hole is distributed between the second type groove 8 and the first type grooves 3.

The trench type super-junction MOSFET device provided by the invention is characterized in that a P-type epitaxial filling layer 4 connected with a source metal layer 15 and a plurality of repeated units of a second type trench 8 and a contact hole 12 which are in strip shape or closed shape are arranged in a device active region 200 to form a PN super-junction structure, and the repeated units of a shallow trench (namely the second type trench 8) are used as a device on-off control region, wherein the region can reduce the grid charge Qg of the device, and the PN super-junction structure plays a role of shielding an electric field to improve the breakdown voltage of the device, so that the device is mainly suitable for a high voltage range of which the breakdown voltage exceeds 200V. By adopting a repeated P-N super junction structure, higher breakdown voltage (applicable to the voltage range of 200V) than that of SGT shielded gate MOS can be obtained, and meanwhile, compared with planar MOS, a thicker and thinner epitaxial layer can obtain higher breakdown voltage, which means lower on-resistance. If the voltage is 200V, the thickness of the epitaxial layer within 20um is only needed to meet the requirement of the P-N super junction structure; at the same voltage, conventional planar MOSFETs require an epitaxial layer thickness of at least 25um to be satisfactory. The device active region formed by the repeated unit collocation can reduce the device conduction internal resistance and the grid charge Qg so as to reduce the device FOM figure of merit. In addition, the peripheral terminal part also adopts the P-type epitaxial filling layer 4 repeated units which are arranged in a suspending way to form a super junction structure, so that the peripheral terminal of the device generates an electric field shielding effect and the electric field distribution is smoother at the same time to improve the withstand voltage of the terminal of the device, and the device has high stability.

Optionally, a drain metal layer 16 is further included, and the drain metal layer 16 is formed on the back surface of the n+ substrate 1.

Optionally, the second type trench 8 sequentially penetrates through the n+ source region 6 and the P-type body region 5 and extends into the N-epitaxial layer 2.

Optionally, contact hole injection layers 13 are formed at contact positions of the second type contact holes and the P-type body region 5, and the contact hole injection layers 13 are formed by ion injection of P-type heavily doped elements and activation of the injected elements at high temperature.

Optionally, a gate oxide layer 9 is formed on the sidewalls of the second type trenches 8.

Optionally, a contact hole metal layer 14 is deposited in the contact hole 12, and the contact hole metal layer 14 is made of Ti/TiN.

The isolation layer 11 is made of silicon dioxide containing boron and phosphorus elements.

Optionally, if the second type trenches 8 are stripe-shaped trenches, the second type trenches 8 are formed at the middle positions of the adjacent first type contact holes, and the adjacent two rows of the first type trenches 3 are arranged in a staggered manner along the first direction and/or the second direction.

If the second type grooves 8 are closed type grooves, each second type groove 8 is communicated with the adjacent other second type grooves 8.

The invention also provides a preparation method of the groove type super junction MOSFET device, which comprises the following steps:

s100, providing an N+ substrate 1, and stacking an N-epitaxial layer 2 on the N+ substrate 1.

S200, depositing a first hard mask oxide layer 7 on the surface of the N-epitaxial layer 2, determining the position of the first type groove 3 through photoresist and a hard mask plate, etching the exposed hard mask plate, removing the photoresist, and forming the first type groove 3 by taking the hard mask plate as a blocking etch.

S300, depositing and forming a P-type epitaxial filling layer 4 in all the first type trenches 3, removing the P-type doped epitaxial layer on the surface of the wafer by a CMP mode, stopping on the surface of the first hard mask oxide layer 7, removing the first hard mask oxide layer 7 by a wet mode, and determining the terminal voltage-resistant area 100 and the active area 200.

S400, defining a region of the P-type body region 5 to be injected through a photoetching process, injecting P-type doping elements through ions, removing photoresist, and pushing the P-type body region 5 to a first target junction depth through a hot push well mode; the region of the N+ source region 6 to be implanted is defined through a photoetching process, an N-type heavily doped element is implanted through ions, photoresist is removed, and then the N+ source region 6 is pushed to a second target junction depth through a hot push well mode.

S500, depositing a second hard mask oxide layer 17 on the surface of the N-epitaxial layer 2, defining a second type groove region to be etched in the active region 200 through a photoetching process, removing surface silicon dioxide through a dry etching mode, removing silicon through a dry etching process after photoresist removal to form a second type groove 8, growing a high-quality gate oxide layer 9 through a gate oxide process, and depositing a groove metal layer 10 in the second type groove 8.

S600, removing the second hard mask oxide layer by a wet method, depositing a layer of silicon dioxide containing boron and phosphorus elements on the surface of the N-epitaxial layer 2 as an isolation layer 11 of the device, defining a contact hole 12 area to be etched in the active area 200 by a photoetching process, forming a contact hole 12 by a dry etching process, forming a contact hole injection layer 13 by ion injection, depositing a contact hole metal layer 14, depositing a metal layer on the surface of the isolation layer 11, and forming a source metal layer 15; and a metal layer is evaporated on the back of the N+ substrate 1 by adopting a back thinning process, so as to form a drain metal layer 16.

Optionally, in step S500, if the second type trenches 8 formed by etching are stripe-shaped trenches, the stripe-shaped trenches extend from one side of the N-epi layer 2 to the other side along the second direction, and adjacent stripe-shaped trenches are isolated from each other. If the second type trenches 8 formed by etching are stripe-shaped trenches, the depth of the first type trenches 3 formed in step S200 is greater than 3um, and the space between any two adjacent first type trenches 3 is greater than 3um.

In step S600, the etched contact holes 12 are the first type contact holes and the second type contact holes, the contact holes 12 are parallel to the second type trenches 8, and extend from one side of the N-epi layer 2 to the other side along the second direction, the contact holes 12 are connected to all the first type trenches 3 distributed along the second direction in the active area 200, and the second type trenches 8 are disposed between the adjacent contact holes 12.

Optionally, in step S500, if the second type trench 8 formed by etching is a closed trench; in step S600, the contact holes 12 formed by etching are a first type contact hole and a second type contact hole, the second type contact hole penetrates through the n+ source region 6 and extends into the P-type body region 5, and contact hole injection layers 13 are formed at contact positions of the second type contact hole and the P-type body region 5.

Example 1

The embodiment provides a method for manufacturing the trench super-junction MOSFET device, which is used for manufacturing a device with a strip-shaped trench 8 of a second type, and comprises the following steps:

step 101, providing an n+ substrate 1, and growing an N-epitaxial layer 2 on the surface of the n+ substrate 1, as shown in fig. 5.

Step 102, a first hard mask oxide layer 7 is deposited on the surface of the N-epitaxial layer 2 to serve as a groove etching barrier layer, the position of the first type groove 3 is determined through photoresist and a silicon dioxide hard mask plate, the exposed silicon dioxide hard mask plate is etched, then the photoresist is removed, and the silicon dioxide hard mask plate serves as a barrier etching to form the first type groove 3, as shown in fig. 6.

Step 103, removing the P-type doped epitaxial layer on the wafer surface by CMP (chemical polishing) to stop on the surface of the first hard mask oxide layer 7 by depositing a P-type doped epitaxial layer as the P-type epitaxial filling layer 4 of the device, and removing the first hard mask oxide layer 7 by wet method, as shown in fig. 7.

104, determining a terminal voltage-resistant area 100 and an active area 200, defining an area of a P-type body area 5 to be injected through a photoetching process, injecting P-type doping elements through ions, removing photoresist, and pushing the P-type body area 5 to a required junction depth through a hot pushing well mode; the region of the n+ source region 6 to be implanted is defined by a photolithography process, the n+ source region 6 is pushed to a desired junction depth by ion implantation of an N-type heavily doped element, photoresist removal, and a thermal push well, as shown in fig. 8.

Step 105, a second hard mask oxide layer 17 is deposited, a second type trench 8 region to be etched is defined in the active region 200 by a photolithography process, surface silicon dioxide is removed by a dry etching method, the second type trench 8 is formed by a dry etching process after photoresist removal, the depth of the second type trench 8 must penetrate through the n+ source region 6 and the P-type body region 5, and then a high-quality gate oxide layer 9 is grown by a gate oxide process, as shown in fig. 9.

Step 106, a layer of metal tungsten is deposited, the metal tungsten on the surface of the hard mask oxide layer is removed through CMP, and then a groove metal layer 10 is formed inside the second type groove 8 through a back etching process, as shown in FIG. 10.

Step 107, removing the second hard mask oxide layer 17 by a wet process, depositing a layer of silicon dioxide (BPSG) insulating dielectric oxide layer containing boron and phosphorus elements to form the isolation layer 11 of the device, defining a contact hole 12 region to be etched in the active region 200 by a photolithography process, removing the surface insulating dielectric oxide layer by a dry etching method, removing photoresist, and forming the contact hole 12 by a dry etching process, wherein the depth of the contact hole must penetrate through the n+ source region 6, as shown in fig. 11.

Step 108, ion implanting P-type heavily doped element, and activating the implanted element at high temperature to form a contact hole implantation layer 13, as shown in fig. 12.

Step 109, a Ti/TiN layer is deposited, then a good ohmic contact is formed on the surface of the contact hole 12 by a suitable high temperature process, a tungsten layer is deposited, and the BPSG surface layer metal tungsten is removed by a back etching process, so as to form a contact hole metal layer 14, as shown in fig. 13.

Step 110, a metal layer is deposited on the front side of the device, and then a source metal layer 15 is defined by an etching process, as shown in fig. 14.

Step 111, then, a device backside thinning process is performed, and a metal-defined drain metal layer 16 is deposited on the device backside, as shown in fig. 15.

It should be noted that, the second type of trench 8 formed by the preparation method is a stripe trench, the stripe trench extends from one side of the N-epi layer 2 to the other side along the second direction, and adjacent stripe trenches are isolated from each other. The etched contact holes 12 are a first type contact hole and a second type contact hole, the contact holes 12 are parallel to the second type trenches 8, and extend from one side of the N-epitaxial layer 2 to the other side along the second direction, the contact holes 12 are connected with all the first type trenches 3 distributed along the second direction in the active area 200, and the second type trenches 8 are arranged between the adjacent contact holes 12.

Example 2

The difference between the method provided in the embodiment and the method provided in the embodiment 1 is that in step 105, the etched second type trench 8 is a closed trench, in step 107, the etched contact hole 12 is a block-shaped first type contact hole and a ring-shaped second type contact hole, the second type contact hole penetrates the n+ source region 6 to extend into the P-type body region 5, and a contact hole injection layer 13 is formed at the contact position between the second type contact hole and the P-type body region 5. The contact hole metal layer 14 prepared by this method is shown in fig. 16. The process adopted by the rest steps is unchanged. The trench super junction MOSFET device prepared by the method is shown in fig. 17 and 18.

It will be appreciated that the embodiments of the present invention describe a trench superjunction MOSFET device in which the substrate and epitaxial layers are both N-doped (e.g., arsenic or phosphorus doped), the doping of the source region is N-heavily doped (e.g., AS implant), the body region is P-doped (e.g., B implant), the shallow trenches (i.e., trenches 8 of the second type) are filled with tungsten metal, and the deep trenches (i.e., trenches 3 of the first type) are filled with P-type epitaxy to form P-type epitaxial fill layer 4.

The invention comprises a super junction structure formed by a P-type epitaxial filling layer 4 connected with a source electrode and an N-type epitaxial layer region repeating unit in an active region of a device, and adopts the repeating unit of a shallow groove as a device on and off control region, wherein the width of the P-type epitaxial filling layer 4 is wider than the width of the shallow groove, and the depth of the P-type epitaxial filling layer is at least 5 times deeper than the depth of the shallow groove. The device active region formed by the repeated unit collocation can reduce the device conduction internal resistance and the grid charge Qg so as to further reduce the device FOM figure of merit.

In embodiment 1, the active region repeating unit combination is a stripe type shallow trench and a stripe type deep trench. In addition, the stripe-type shallow trench is provided with a thinner gate oxide layer 9, and the stripe-type deep trench is filled with a P-type epitaxial layer to form a P-type epitaxial filling layer 4.

In embodiment 2, the active region repeating unit combination adopts a closed shallow trench and a block-shaped deep trench. In addition, the closed shallow trench has a thin gate oxide layer 9. The super junction structure repeating unit formed by the P-type epitaxial filling layer 4 and the N-type epitaxial layer region repeating unit connected with the source electrode is arranged in the active region of the device, is used for supporting the breakdown voltage of the active region of the device, is mainly suitable for a high-voltage range with the breakdown voltage of more than 200V, and can further reduce the on-resistance of the device.

The invention adopts the repeated unit of the shallow groove as the device on and off control area in the device active area 200, which further reduces the grid charge Qg of the device.

In the invention, the P-type epitaxial filling layer 4 repeated units which are arranged in a suspending way are also adopted to form a P-N super junction structure at the peripheral terminal part (namely the terminal voltage-resistant area 100), so that the peripheral terminal of the device generates an electric field shielding effect and the electric field distribution is smoother to improve the terminal voltage resistance of the device, and the device has high stability.

Compared with the traditional power MOSFET device, the relation between the on-resistance and the breakdown voltage of the groove type super-junction MOSFET device is greatly improved, and the traditional 2.5 power relation is changed into a linear relation. Therefore, on-resistance can be reduced by more than 80% on the same chip area, the traditional silicon limit is broken at one time, and the on-resistance control method has the advantage of high switching speed.

Finally, the preparation method of the groove type super-junction MOSFET device provided by the invention can be well compatible with the existing MOSFET device manufacturing process, so that the technical bottleneck of the unrealizable process is avoided, and the conversion value is very high.

The foregoing is merely a preferred embodiment of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions within the technical scope of the present disclosure should be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. A trench superjunction MOSFET device adapted for use in a voltage range of 200V or greater, comprising an n+ substrate;

the N-epitaxial layer is arranged on the N+ substrate, and the surface of the N-epitaxial layer is sequentially divided into a terminal voltage-resistant area and an active area along a first direction;

the first type grooves are independent block grooves, the first type grooves are etched and formed in the terminal voltage-resistant area and the active area, the first type grooves are filled with P-type epitaxial filling layers, the first type grooves are arranged in a staggered mode, and the distance between any two adjacent first type grooves is equal;

the second type grooves are etched and formed in the active area, groove metal layers are filled in the second type grooves, the second type grooves are strip-shaped grooves or closed type grooves, the strip-shaped grooves are formed between the adjacent first type grooves, the strip-shaped grooves extend from one side of the N-epitaxial layer to the other side along a second direction, and the adjacent strip-shaped grooves are isolated from each other; the closed type grooves are formed on the periphery of each first type groove in the active area;

The width of the first type of groove exceeds the width of the second type of groove, and the depth of the first type of groove exceeds more than five times of the depth of the second type of groove;

the P-type body region is implanted and formed on the surface of the N-epitaxial layer;

the N+ source region is implanted and formed on the surface of the P-type body region;

the isolation layer is deposited on the upper surface of the N-epitaxial layer, and a source electrode metal layer is arranged on the surface of the isolation layer;

the contact holes comprise a first type contact hole and a second type contact hole which are formed in the active area in a deposited mode, one end of the first type contact hole is in contact with the P-type epitaxial filling layer, and the other end of the first type contact hole penetrates through the isolation layer to be in contact with the source metal layer; the second type contact hole is used for connecting the P-type body region and the source electrode metal layer;

if the second type of grooves are strip-shaped grooves, the contact holes comprise first type of contact holes and second type of contact holes which are connected in a whole, the contact holes are parallel to the second type of grooves, the contact holes extend from one side of the N-epitaxial layer to the other side of the N-epitaxial layer along the second direction, the contact holes are connected with all the first type of grooves distributed along the second direction, the first type of contact holes are connected with a P-type epitaxial filling layer and a source electrode metal layer in the first type of grooves, and the second type of contact holes are connected with a P-type body region and the source electrode metal layer; the depth of the first type grooves is larger than 3um, and the interval between any two adjacent first type grooves is larger than 3um;

If the second type of groove is a closed type groove, the contact holes are a first type of blocky contact hole and an annular second type of contact hole, the first type of contact hole is respectively used for connecting the P-type epitaxial filling layer and the source electrode metal layer which are distributed in the active area, the second type of contact hole is respectively formed between the first type of contact hole and the second type of groove corresponding to the first type of contact hole, different second type of contact holes are isolated from each other, and each second type of contact hole is of a closed structure.

2. The trench superjunction MOSFET device of claim 1, wherein:

the semiconductor device further comprises a drain metal layer, wherein the drain metal layer is formed on the back surface of the N+ substrate.

3. The trench superjunction MOSFET device of claim 1, wherein:

the second type groove sequentially penetrates through the N+ source region and the P type body region to extend into the N-epitaxial layer.

4. The trench superjunction MOSFET device of claim 1, wherein:

and contact hole injection layers are formed at the contact positions of the second type of contact holes and the P-type body region, and are formed by ion injection of P-type heavily doped elements and activation of the injection elements at high temperature.

5. The trench superjunction MOSFET device of any of claims 1-4, wherein:

and a gate oxide layer is formed on the side wall of the second type groove.

6. The trench superjunction MOSFET device of claim 5, wherein:

depositing a contact hole metal layer in the contact hole, wherein the contact hole metal layer is made of Ti/TiN material;

the isolating layer is silicon dioxide containing boron and phosphorus elements.

7. The trench superjunction MOSFET device of claim 1, wherein:

if the second type of grooves are strip-shaped grooves, the second type of grooves are formed in the middle positions of the adjacent first type of contact holes, and the adjacent two rows of the first type of grooves are arranged in a staggered manner along the first direction and/or the second direction;

if the second type grooves are closed grooves, each second type groove is communicated with the other adjacent second type grooves.

8. A method for fabricating a trench superjunction MOSFET device according to any of claims 1-7, comprising the steps of:

s100, providing an N+ substrate, and stacking an N-epitaxial layer on the N+ substrate;

s200, depositing a first hard mask oxide layer on the surface of the N-epitaxial layer, determining the position of a first type of groove through photoresist and a hard mask plate, etching the exposed hard mask plate, removing the photoresist, and forming the first type of groove by taking the hard mask plate as a blocking etch;

S300, depositing and forming a P-type epitaxial filling layer in all the first type trenches, removing the P-type doped epitaxial layer on the surface of the wafer by a CMP (chemical mechanical polishing) mode, stopping on the surface of the first hard mask oxide layer, removing the first hard mask oxide layer by a wet method mode, and determining a terminal voltage-resistant area and an active area;

s400, defining a P-type body region to be injected through a photoetching process, injecting P-type doping elements through ions, removing photoresist, and pushing the P-type body region to a first target junction depth through a hot push well mode; defining an N+ source region to be injected through a photoetching process, injecting an N-type heavy doping element through ions, removing photoresist, and pushing the N+ source region to a second target junction depth through a hot push well mode;

s500, depositing a second hard mask oxide layer on the surface of the N-epitaxial layer, defining a second type groove region to be etched in the active region through a photoetching process, removing surface silicon dioxide in a dry etching mode, removing silicon through a dry etching process after photoresist is removed to form the second type groove, growing a high-quality gate oxide layer through a gate oxide process, and depositing a groove metal layer in the second type groove;

S600, removing the second hard mask oxide layer by a wet method, depositing a layer of silicon dioxide containing boron and phosphorus elements on the surface of the N-epitaxial layer to serve as an isolation layer of the device, defining a contact hole area to be etched in an active area by a photoetching process, forming a contact hole by a dry etching process, forming a contact hole injection layer by ion injection, depositing to form a contact hole metal layer, and depositing a layer of metal layer on the surface of the isolation layer to form a source electrode metal layer; and adopting a back thinning process, evaporating a metal layer on the back of the N+ substrate to form a drain electrode metal layer.

9. The method for manufacturing the trench super-junction MOSFET device according to claim 8, wherein:

in step S500, if the second type of trench formed by etching is a stripe trench, the stripe trench extends from one side of the N-epi layer to the other side along the second direction, adjacent stripe trenches are isolated from each other, the depth of the first type of trench formed is greater than 3um, and the interval between any two adjacent first type of trenches is greater than 3um;

in step S600, the contact holes formed by etching are a first type contact hole and a second type contact hole, the contact holes are parallel to the second type trenches, and extend from one side of the N-epitaxial layer to the other side along the second direction, the contact holes are connected with all the first type trenches distributed along the second direction in the active region, and the second type trenches are disposed between the adjacent contact holes.

10. The method for manufacturing the trench super-junction MOSFET device according to claim 8, wherein:

in step S500, if the second type of trench formed by etching is a closed trench;

in step S600, the contact holes formed by etching are a first type contact hole and a second type contact hole, wherein the first type contact hole and the second type contact hole are block-shaped, the second type contact hole penetrates through the n+ source region and extends into the P-type body region, and a contact hole injection layer is formed at the contact positions of the second type contact hole and the P-type body region.