CN117854569B

CN117854569B - Performance test system and performance test method for memory

Info

Publication number: CN117854569B
Application number: CN202410245096.1A
Authority: CN
Inventors: 余玉; 许展榕
Original assignee: Hefei Kangxinwei Storage Technology Co Ltd
Current assignee: Hefei Kangxinwei Storage Technology Co Ltd
Priority date: 2024-03-05
Filing date: 2024-03-05
Publication date: 2024-05-24
Anticipated expiration: 2044-03-05
Also published as: CN117854569A

Abstract

The invention provides a performance test system and a performance test method of a memory, wherein the performance test system comprises a performance test end and a host end, wherein the host end is used for pre-building a data writing model, the data writing model is fusion of a plurality of sub writing models, and the performance test end comprises a plurality of memory test seats which are respectively used for installing a plurality of memories; the CPU is used for performing write test on the memories based on the sub-write-in models determined by the host end so as to obtain scene write amplification coefficients corresponding to each sub-write-in model; the host side is also used for summarizing the plurality of scene write amplification factors to generate a data comparison table of the total write amplification factors of the plurality of memories. The invention can build the target application scene of the data writing model simulation memory, and greatly improves the test analysis efficiency and the comprehensiveness of the test data.

Description

Performance test system and performance test method for memory

Technical Field

The present invention relates to the field of memory technologies, and in particular, to a performance testing system and a performance testing method for a memory.

Background

Memories are widely used in various types of end products for storing data. The write amplification factor is a key indicator for evaluating the performance of firmware in the memory, and the closer the write amplification factor is to one, the better the memory performance is. Therefore, the performance difference between different memories can be known by comparing the write amplification coefficients for memories of different manufacturers. However, at present, when the write amplification coefficients of different memories are subjected to test analysis, there are problems that the test analysis efficiency is low and the test data is not comprehensive.

Disclosure of Invention

The invention aims to provide a performance test system and a performance test method for a memory.

The invention provides a performance test system of a memory, which comprises a performance test end and a host end, wherein the performance test end is in communication connection with the host end;

The host side is used for pre-building a data writing model, the data writing model is fusion of a plurality of sub writing models, the plurality of sub writing models comprise a sequential writing model, a random writing model, a ping-pong writing model and a hot spot writing model, the data writing model is used for indicating the data writing proportion of the sequential writing model, the data writing proportion of the random writing model, the data writing proportion of the ping-pong writing model and the data writing proportion of the hot spot writing model, and the performance testing side comprises:

The system comprises a plurality of memory test seats, a data writing model and a data writing model, wherein the memory test seats are respectively used for installing a plurality of memories, the data writing model is built by the host end based on a plurality of target application scenes of the memories, and the target application scenes are scene fusion of sequential writing operation, random writing operation, ping-pong writing operation and hot spot writing operation; and

The central processing unit is in communication connection with the plurality of memory test seats and is used for carrying out writing test on the plurality of memories based on the sub-writing models in the data writing model determined by the host end so as to obtain test data of the plurality of memories and analyzing and processing the test data so as to obtain scene amplification coefficients corresponding to each sub-writing model;

the host side is further configured to receive a plurality of scene write amplification coefficients transmitted by the central processing unit, and perform summarization processing on the plurality of scene write amplification coefficients to generate a data comparison table of total write amplification coefficients of the plurality of memories, where the data comparison table is used to indicate performance differences of the plurality of memories in the same target application scene;

The total write amplification factor of the plurality of memories is expressed as WAI, wai= WAIsw ×a% + WAIrw ×b% + WAIpp ×c% + WAIhs ×d, wherein WAIsw denotes a scene write amplification factor corresponding to the sequential write model, WAIrw denotes a scene write amplification factor corresponding to the random write model, WAIpp denotes a scene write amplification factor corresponding to the ping-pong write model, WAIhs denotes a scene write amplification factor corresponding to the hot spot write model, a% is a data write ratio of the sequential write model, B% is a data write ratio corresponding to the random write model, C% is a data write ratio corresponding to the ping-pong write model, D% is a data write ratio corresponding to the hot spot write model, and a% + B% + C% + D% = 100%.

In an embodiment of the present invention, the performance test system further includes a test board card, wherein a plurality of memory test sockets are integrated on the test board card, the test board card is provided with a plurality of power supply channels and a plurality of digital channels, the power supply channels respectively supply power to the memories, and the central processing unit simultaneously performs write-in test on the memories through the digital channels.

In an embodiment of the present invention, the performance testing terminal further includes:

The central processing unit is used for burning the system image file preset by the host into the flash memory module, and the flash memory module is used for storing the system image file; and

And the memory module is used for storing the operation data of the performance testing end.

In an embodiment of the present invention, the test data includes a data amount written in the memory and a corresponding data amount written in the host at the host side, and the scene write amplification factor is a ratio of the data amount written in the memory to the data amount written in the host.

In an embodiment of the present invention, the host side is configured to pre-build a plurality of data writing models, where the plurality of data writing models respectively correspond to a plurality of target application scenarios, and each of the target application scenarios respectively corresponds to a set of data writing proportions of sequential writing models, random writing models, ping-pong writing models, and hot-spot writing models.

In an embodiment of the present invention, the host side is further configured to determine whether a current write test is completed, and if the current write test is completed, the host side switches the data write model, and makes the central processor perform the write test on the plurality of memories based on the switched data write model, so that the host side generates a data comparison table of the plurality of memories in another target application scenario, where the data comparison table is used to indicate performance differences of the plurality of memories in another target application scenario.

The invention also provides a performance test method of the memory, which is applied to a performance test system of the memory, the performance test system comprises a performance test end and a host end, the performance test end is in communication connection with the host end, the performance test end comprises a plurality of memory test seats and a central processing unit, the central processing unit is in communication connection with the plurality of memory test seats, the performance test method comprises the following steps:

The method comprises the steps that a data writing model is built in advance at a host end, the data writing model is fusion of a plurality of sub-test models, the plurality of sub-writing models comprise a sequential writing model, a random writing model, a ping-pong writing model and a hot spot writing model, and the data writing model is used for indicating the data writing proportion of the sequential writing model, the data writing proportion of the random writing model, the data writing proportion of the ping-pong writing model and the data writing proportion of the hot spot writing model;

A plurality of memories are respectively installed on a plurality of memory test seats, wherein the data writing model is built by the host end based on target application scenes of the memories, and the target application scenes are scene fusion of sequential writing operation, random writing operation, ping-pong writing operation and hot spot writing operation;

The CPU performs writing test on a plurality of memories based on a sub-writing model in the data writing model determined by the host side so as to obtain test data of the memories, and performs analysis processing on the test data so as to obtain scene amplification coefficients corresponding to each sub-writing model;

The host side receives the plurality of scene write amplification coefficients transmitted by the central processing unit and performs summarization processing on the plurality of scene write amplification coefficients to generate a data comparison table of the total write amplification coefficients of the plurality of memories, wherein the data comparison table is used for indicating the performance difference of the plurality of memories under the same target application scene;

As described above, the performance test system and the performance test method for the memory can build the data writing model to simulate the target application scene of the memory when the write amplification coefficients of different memories are tested and analyzed, so that the test analysis of the write amplification coefficients of a plurality of different memories is rapidly and simply performed, and the test analysis efficiency is greatly improved. Meanwhile, the memory can be tested based on the application scene of the memory, and the comprehensiveness of test data is obviously improved.

Of course, it is not necessary for any one product to practice the invention to achieve all of the advantages set forth above at the same time.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a block diagram of a performance testing system for a memory according to an embodiment of the present invention;

FIG. 2 is a diagram of a visual interface of a host according to an embodiment of the invention;

FIG. 3 is a flow chart of a method for testing performance of a memory according to an embodiment of the invention;

fig. 4 is a flowchart of step S20, step S30 and step S40 in fig. 3.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It should be noted that, in practical application, the memory writes data under different target application scenarios, for example, a certain target application scenario is a scenario fusion of Sequential Write operation (Sequential Write) and Random Write operation (Random Write), and a certain application scenario is a scenario fusion of Sequential Write operation (Sequential Write), random Write operation (Random Write), ping-pong Write operation (Pingpong Write) and Hot Spot Write operation (Hot Spot Write), and for example, a certain application scenario is a scenario fusion of Sequential Write operation (Sequential Write), random Write operation (Random Write), and Hot Spot Write operation (Hot Spot Write). When a certain application scene is a scene fusion of Sequential Write operation (Sequential Write), random Write operation (Random Write), ping-pong Write operation (Pingpong Write) and Hot Spot Write operation (Hot Spot Write), a part of data adopts Sequential Write operation (Sequential Write), a part of data adopts Random Write operation (Random Write), a part of data adopts ping-pong Write operation (Pingpong Write), and a part of data adopts Hot Spot Write operation (Hot Spot Write). It should be explained that, the Sequential Write operation (Sequential Write) refers to writing data into consecutive addresses of the memory chip in sequence, the Random Write operation (Random Write) refers to writing data into Random addresses of the memory chip, the ping-pong Write operation (Pingpong Write) refers to writing data into different memory areas alternately, and the Hot Write operation (Hot Spot Write) refers to writing data into part of the memory areas in a concentrated manner.

Referring to fig. 1, fig. 1 is a block diagram of a performance test system of a memory according to the present invention. The performance test system can be applied to a scenario of performing performance tests on a plurality of memories, for example, performing performance tests on eMMC memories of a plurality of different manufacturers. The performance testing system may include a performance testing side 10 and a host side 20. The host 20 may build a data writing model in advance based on an actual application scenario of the memory, that is, a target application scenario, so that the data writing model may be built as a fusion of a plurality of sub writing models such as a sequential writing model, a random writing model, a ping-pong writing model, and a hot spot writing model, so that the data writing model indicates a data writing proportion of the sequential writing model, a data writing proportion of the random writing model, a data writing proportion of the ping-pong writing model, and a data writing proportion of the hot spot writing model, and the sequential writing model represents a sequential writing operation of data, the random writing operation of the random writing model represents a random writing operation of data, the ping-pong writing operation of the ping-pong writing model represents a ping-pong writing operation of data, and the hot spot writing operation of the hot spot writing model represents a hot spot writing operation of data. And setting the data writing proportion of each sub-writing model, so as to simulate the target application scene.

Further, when a certain target application scenario is abstracted to be a fusion of a plurality of sub-write models such as a sequential write model, a random write model, a ping-pong write model, a hot-spot write model, etc., the host 20 can determine a sub-write model each time, and the performance test terminal 10 can perform write tests on memories of a plurality of different manufacturers based on a certain sub-write model determined by the host 20 each time, so as to obtain the scenario write amplification coefficients of a plurality of different memories under each sub-write model. Further, the host side 20 may be communicatively connected to the performance testing side 10, so that the performance testing side 10 may transmit a plurality of scene write amplification coefficients to the host side 20, and the host side 20 may perform summary processing on the plurality of scene write amplification coefficients to generate a total write amplification coefficient of each memory in the target application scene, thereby generating a data comparison table of the total write amplification coefficients of the plurality of memories in the same target application scene, that is, performance differences of the plurality of memories in the same target application scene, and screen out memories with better performance. It should be noted that the memory to be tested may be an eMMC memory, or may be another type of memory, which is not limited herein.

The total write amplification factor of the plurality of memories is a fusion of a plurality of scene write amplification factors, and the fusion rule may be based on a data write ratio corresponding to a sequential write model, a data write ratio corresponding to a random write model, a data write ratio corresponding to a ping-pong write model, and a data write ratio corresponding to a hot spot write model, where the fusion rule is that the total write amplification factor is a fusion parameter, the total write amplification factor may be expressed as WAI, wai= WAIsw ×a% + WAIrw ×b% + WAIpp ×c% + WAIhs ×d%, where WAIsw represents the scene write amplification factor corresponding to the sequential write model, WAIrw represents the scene write amplification factor corresponding to the random write model, WAIpp represents the scene write amplification factor corresponding to the hot spot write model, WAIhs represents the scene write amplification factor corresponding to the hot spot write model, a% is the data write ratio corresponding to the sequential write model, B% is the data write ratio corresponding to the random write model, C% is the data write ratio corresponding to the ping-pong write model, D% is the hot spot write ratio corresponding to the hot spot write model, and D% is +c% =100% =. It can be explained that, to simulate multiple target application scenarios, the host 20 can be built by changing specific ratio values of a%, B%, C% and D%. For example, a% is 30%, B% is 20%, C% is 20%, D% is 30%, in order to simulate a 30% data write ratio sequential write operation, a 20% data write ratio random write operation, a 20% data write ratio ping-pong write operation, and a 30% data write ratio hot spot write operation. For example, when the data write ratio of the ping-pong operation is 0%, the data write ratio of the ping-pong operation is 30%, the data write ratio of the B% is 30%, the data write ratio of the C% is 0%, and only the writing of the sequential writing operation, the random writing operation, and the hot spot writing operation is simulated without performing the ping-pong operation.

Referring to fig. 1, for a performance test terminal 10, specifically, the performance test terminal 10 of the performance test system may be a multi-channel firmware test board, which may include a flash memory module 11, a memory module 12, a plurality of memory test sockets 13, a communication interface 14, and a central processing unit 15. The plurality of memory test sockets 13 may be integrated on a test board to place different memories, so that the performance test terminal 10 may test the plurality of memories, thereby obtaining write amplification coefficients of the plurality of memories, and thus, performance differences between the plurality of different memories may be rapidly compared.

When the memory is prepared for testing, the flash memory module 11 may store a system image file of the performance testing terminal 10, and the cpu 15 executes the system image file to start the performance testing terminal 10, so as to perform subsequent performance testing. The flash memory module 11 may be an SD card or other flash memory unit. The memory module 12 may store the operation data of the performance test terminal 10 to ensure that the performance test terminal 10 can operate normally. The memory module 12 may be a random access memory, such as a DRAM memory or other memory cell.

Furthermore, when the memories are tested, the central processor 15 may be communicatively connected to the plurality of memory test sockets 13, so as to perform a write test on the memories on the memory test sockets 13, and after analyzing the test data of the plurality of memories, obtain the scene write amplification coefficients of each memory under the plurality of sub-write models. The communication interface 14, for example, a USB interface, may enable the central processor 15 to communicate with the host 20, so that the central processor 15 may transmit the scene write amplification factor to the host 20, so that the host 20 performs a summary process on the scene write amplification factors of each different memory, and generates a data comparison table of the total write amplification factors. The data comparison table can display the difference of the total write amplification coefficients of different memories under the same target application scene, namely the performance difference of different memories under the same target application scene. The test system can simply and rapidly compare the performance differences of different memories, and is also convenient for the user of the host 20 to select the model according to the memory requirements under different target application scenes. It should be noted that, the above test board card may be provided with a plurality of power supply channels and a plurality of digital channels, where a plurality of power supply channels may respectively supply power to a plurality of memories, and a plurality of digital channels may be used to transmit data between the memories and the central processing unit 15, so that the central processing unit 15 may perform write test on a plurality of memories through a plurality of digital channels at the same time, thereby further improving test analysis efficiency.

Referring to fig. 1 and fig. 2, for the host 20, specifically, the host 20 may include a system image file and visualization software, when the memory write amplification factor test is required, a correct system image file may be selected at the host 20, and the cpu 15 of the performance testing terminal 10 may burn the selected system image file into the flash memory module 11, so that the cpu 15 executes the system image file to start the performance testing terminal 10. After the performance test terminal 10 performs the write test, the cpu 15 may upload the write amplification coefficients of the plurality of memories to the visualization software of the host 20, where the visualization software may generate a data comparison table for the total write amplification coefficients of the plurality of different memories, where the data comparison table may compare and display the total write amplification coefficients of the plurality of different memories, so that the performance differences between the plurality of different memories may be simply and quickly compared.

Referring to fig. 1 and fig. 2, it should be noted that, when the performance testing terminal 10 tests a plurality of memories, the host terminal 20 can write different data amounts for a plurality of times, so as to quickly obtain the total write amplification coefficients of the plurality of different memories under different data writing amounts. Specifically, during testing, the host 20 writes different amounts of data at different time points, and the test data recorded by the performance testing terminal 10 each time may include the amount of data written by the host 20, the amount of data actually written by each memory, and the test time. The central processing unit 15 calculates the ratio of the actual written data volume of each memory to the data volume to be written into the memory by the host, so as to obtain the scene write amplification factor of each memory under different data writing volumes. After the test, the cpu 15 may send the scene write amplification factors under different data writing amounts and the time of each test to the host 20, so that the host 20 may aggregate the multiple scene write amplification factors of each memory based on the corresponding data writing ratios into the total amplification factor, and aggregate the total amplification factors into a write amplification factor change table according to the time sequence, so as to more comprehensively display the write amplification factor of each memory.

In order to enable the performance test system to more comprehensively test the data of the memory in the actual application scene, the host 20 may build a data writing model in advance based on the target application scene of the memory to perform the test, where the data writing model may be used to indicate the data writing proportion during the writing test. The data write proportions may include data write proportions of sequential write models, random write models, ping-pong write models, and hot spot write models. For example, if the memory is used in an application scenario in which sequential writing tasks are mainly performed, the data writing model may be to increase the data writing proportion of the sequential writing model, decrease the data writing proportion of the random writing model, decrease the data writing proportion of the ping-pong writing model, and decrease the data writing proportion of the hot writing model to perform writing test on the memory. If the memory is used in an application scene for mainly executing the random writing task, the data writing proportion of the random writing model can be improved, the data volume proportion of the sequential writing model can be reduced, the data writing proportion of the ping-pong writing model can be reduced, and the data writing proportion of the hot spot writing model can be reduced to carry out writing test on the memory.

Referring to fig. 2, further, the host 20 may build a plurality of data writing models in advance, where the plurality of data writing models may correspond to a plurality of target application scenarios, and under the plurality of target application scenarios, the data writing models corresponding to each target application scenario may correspond to a set of data writing proportions, that is, the data writing proportions of the sequential writing model, the random writing model, the ping-pong writing model, and the hot-spot writing model, so that the plurality of data writing models may correspond to the plurality of target application scenarios, respectively. So that the user can select a desired application scenario from the host side 20 for testing. Of course, the user can test the memories based on each data writing model in turn, so as to more comprehensively test the write amplification coefficients of the memories in different application scenes. Specifically, each time a test is performed based on a data writing model, the host 20 may determine whether the current writing test is completed, and if the current writing test is completed, the user may switch a new data writing model from the visualization software of the host 20, so that the cpu 15 performs the writing test on the plurality of memories based on the switched data writing model. Therefore, the central processing unit 15 can acquire the total write amplification coefficients of different memories under a plurality of application scenes, and the comprehensiveness of the performance test of the memories is improved.

Referring to fig. 2, specifically, after the visualization software of the host 20 selects a required data writing model, the host 20 then transmits model data of the data writing model to the cpu 15, so that the cpu 15 performs a writing test based on the model data, thereby obtaining scene write amplification coefficients of the corresponding sub-writing models of the plurality of different memories under the data writing model. Furthermore, the cpu 15 uploads the scene write amplification factors of the plurality of sub-write models to the host side, so that the host side 20 analyzes and generates a data comparison table of the total write amplification factors of the plurality of different memories under the same data write model. It should be noted that, after the visual software interface of the host 20 generates the data comparison table corresponding to the data writing model of one type, it indicates that the current writing test is completed, and the next type of data writing model can be continuously selected to perform the test through the visual software interface of the host 20, so as to obtain the total writing amplification coefficients of the multiple different memories under the next type of data writing model. Further, after each test is performed through the data writing models of one type and a data comparison table is generated, the test can be continued by selecting the data writing models of one type from the data writing models which are not tested until all the data writing models are tested. When the method is used for testing, the performance testing system can more comprehensively analyze and compare the total write amplification coefficients of a plurality of different memories under various testing models.

Referring to fig. 2, the cpu 15 may transmit the total write amplification factor obtained by testing each type of data writing model to the visualization software at the host 20, and after the visualization software analyzes the write amplification factor, the visualization interface may display a data comparison table under each type of data writing model, where the data comparison table may display the write amplification factors of a plurality of different memories under each type of data writing model. Further, the plurality of different memories can be tested for multiple times at different times under each type of data writing model, and different data writing amounts are adopted each time, so that the central processing unit 15 can calculate and obtain the scene write amplification coefficients of the memories under different data writing amounts in each type of data writing model. Furthermore, the cpu 15 may upload the multiple scene write amplification factors of the multiple different memories under each type of data writing model to the visualization software, where the visualization software may display the multiple total write amplification factors of the multiple different memories under each type of data writing model.

For example, referring to table 1 below, table 1 below shows the amount of data written into each memory by the host 20 at different time points, the amount of data actually written into each memory, and the corresponding scene write amplification factor for a certain memory under the sub-write model.

TABLE 1

Referring to fig. 2, after the cpu 15 uploads the scene write amplification coefficients of the multiple sub-write models under the data write model to the visualization software of the host 20, the host 20 may perform a summary analysis on the multiple scene write amplification coefficients of the multiple different memories under the multiple sub-write models to obtain a total write amplification coefficient variation line graph of the multiple different memories at different time points under the data write model. Further, a user can view the total write amplification factor change line diagrams of a plurality of different memories under the data writing model on the visual software interface, so that the performance difference of the different memories under the data writing model can be displayed more clearly, and the comprehensiveness of the performance test system is improved.

Referring to fig. 2, in order to improve the operation simplicity of the visual software interface, a system image file 21 selection button, a burn 22 button, a test model 23 selection button, and a test status 24 button may be integrated on the visual software interface. Clicking on the system image file 21 select button selects the correct system image file. Clicking the burn 22 button burns the system image file into the flash module 11. Clicking on the test model 23 select button selects a certain category of data writing model for testing. Clicking on the test status 24 button may view the test status of the memory. Further, the visualized software interface can display the total write amplification factor change line diagram of a plurality of different memories under a certain type of data writing model based on the selection of the host end 20, so that the performance difference of different memories under each type of data writing model can be displayed more clearly, and the comprehensiveness of the performance test system is improved.

Referring to fig. 2, for example, when the data writing model corresponds to an application scenario in which sequential writing tasks are mainly executed, the visual software interface may display a total write amplification factor variation line diagram of the flash memories of four different manufacturers under the data writing model. The four types of memories can be respectively defined as a first type of flash memory, a second type of flash memory, a third type of flash memory and a fourth type of flash memory, the change line graphs of the four types of flash memories can be summarized in a total table, and the abscissa can represent different time points and the ordinate can represent the write amplification factor value, so that the performance difference of the four types of flash memories can be intuitively displayed.

In summary, the performance testing device of the memory can quickly and simply test and analyze the write amplification coefficients of a plurality of different memories, quickly generate performance data, and greatly improve the test and analysis efficiency. Meanwhile, the performance test system can more comprehensively test the data of the memory in various application scenes by constructing various data writing models, more clearly shows the performance differences of different memories in various application scenes, and improves the comprehensiveness of the performance test system.

Referring to fig. 3, fig. 3 is a flowchart illustrating a method for testing performance of a memory according to the present invention. The performance test method of the present invention may be applied to a performance test system of a memory, the performance test system may include a performance test terminal 10 and a host terminal 20, the performance test terminal 10 may include a plurality of memory test sockets 13 and a central processing unit 15, and the method of the present invention may include the following steps:

Step S101, a data writing model is built in advance at a host end, wherein the data writing model is fusion of a plurality of sub-test models, and the plurality of sub-writing models comprise a sequential writing model, a random writing model, a ping-pong writing model and a hot spot writing model.

And S10, respectively installing a plurality of memories on the memory test seats.

And step S20, the CPU performs write-in test on the memories based on a sub-write-in model in the data write-in model determined by the host end so as to acquire test data of the memories.

And step S30, analyzing and processing the test data of the memories by the central processing unit so as to acquire a scene write amplification factor corresponding to each sub-write model.

Step S40, the host receives the plurality of scene write amplification coefficients transmitted by the central processing unit, and performs summarization processing on the plurality of scene write amplification coefficients to generate a data comparison table of the total write amplification coefficients of the plurality of memories, wherein the data comparison table is used for indicating the performance difference of the plurality of memories in the same target application scene.

Referring to fig. 3, in an embodiment of the present invention, when executing step S10, step S20 and step S30, specifically, a plurality of memory test sockets 13 may be provided, and different memories may be placed on the plurality of memory test sockets 13, so that the performance test terminal 10 may test a plurality of memories. The central processor 15 may perform a write test to obtain scene write amplification factors for a plurality of memories under different sub-write models. It should be noted that, when testing the memories, the performance testing terminal 10 may perform write tests on a plurality of different memories through a plurality of memory test sockets 13 at the same time, and record the data amount to be written into each memory by the host of the host terminal 20 and the data amount actually written into each memory during the test. The cpu 15 calculates the ratio of the amount of data actually written into each memory to the amount of data to be written into the memory by the host, thereby obtaining the scene write amplification factor of each memory.

In an embodiment of the present invention, before performing step S10, the method may further include the following steps:

s11, determining a system mirror image file through a host side;

s12, the central processing unit burns the system image file determined by the host into the flash memory module;

In an embodiment of the present invention, when step S11 and step S12 are performed, it should be noted that the performance testing terminal 10 may further include a flash memory module 11 and a memory module 12, and when the memory is prepared for testing, the flash memory module 11 may store a system image file of the performance testing terminal 10, and the cpu 15 executes the system image file to enable the performance testing terminal 10, so as to perform a subsequent performance test. The flash memory module 11 may be an SD card or other flash memory unit. The memory module 12 may store the operation data of the performance test terminal 10 to ensure that the performance test terminal 10 can operate normally. The memory module 12 may be a random access memory, such as a DRAM memory or other memory cell. Furthermore, the host 20 may be pre-configured with a system image file, when the memory write amplification factor test is required, the correct system image file may be selected from the host 20, and the cpu 15 of the performance test terminal 10 may obtain the system image file and burn the system image file into the flash memory module 11, so that the cpu 15 executes the system image file to start the performance test terminal 10.

Referring to fig. 4, in an embodiment of the invention, when executing step S20, step S30 and step S40, the steps may include:

and S21, selecting a data writing model for writing test from a plurality of data writing models by the host side.

Step S22, the CPU executes writing test on the memories based on the sub-writing model in the data writing model selected by the host computer end so as to obtain corresponding test data.

And S23, analyzing and processing the test data by the central processing unit to obtain a scene write amplification factor corresponding to each sub-write model.

And step S24, the host side receives the plurality of scene write amplification coefficients transmitted by the central processing unit and performs summarization processing on the plurality of scene write amplification coefficients so as to generate a data comparison table of the total write amplification coefficients of the plurality of memories.

Step S25, the host end judges whether the current writing test is finished, if the current writing test is finished, the host end switches the data writing model, and the central processing unit performs writing test on a plurality of memories based on the switched data writing model, so that the host end generates a data comparison table of the memories in another target application scene.

Referring to fig. 4, in an embodiment of the present invention, when step S21 is performed, specifically, in order to enable the performance test system to more fully test the data of the memory in the actual application scenario, the host 20 may build a data writing model in advance based on the target application scenario of the memory to perform the test, where the data writing model may be used to indicate the data writing proportion during the writing test. The data write proportions may include data write proportions of sequential write models, random write models, ping-pong write models, and hot spot write models. For example, if the memory is used in an application scenario in which sequential writing tasks are mainly performed, the data writing model may be to increase the data writing proportion of the sequential writing model, decrease the data writing proportion of the random writing model, decrease the data writing proportion of the ping-pong writing model, and decrease the data writing proportion of the hot writing model to perform writing test on the memory. If the memory is used in an application scene for mainly executing the random writing task, the data writing proportion of the random writing model can be improved, the data writing proportion of the sequential writing model can be reduced, the data writing proportion of the ping-pong writing model can be reduced, and the data writing proportion of the hot spot writing model can be reduced to carry out writing test on the memory. Furthermore, the host 20 may build a plurality of data writing models in advance, where the plurality of data writing models may configure different data writing ratios, so that the plurality of data writing models may respectively correspond to a plurality of target application scenarios. So that the user can select a desired application scenario from the host side 20 for testing.

Referring to fig. 4, in an embodiment of the present invention, when executing the steps S22 and S23, specifically, a user may select a required data writing model at the host 20 to simulate a target application scenario, and then the host 20 transmits the data writing ratios of the model data of the data writing model, i.e. the sequential writing model, the random writing model, the ping-pong writing model and the hot spot writing model, to the central processor 15 for the central processor 15 to execute the writing test based on the model data, so as to obtain the scenario writing amplification coefficients of a plurality of sub-writing models of a plurality of different memories under the data writing model.

It should be noted that, the specific limitation of the performance test method of the memory may be referred to the limitation of the test system of the memory, which is not described herein.

In the description of the present specification, the descriptions of the terms "present embodiment," "example," "specific example," and the like, mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

The embodiments of the invention disclosed above are intended only to help illustrate the invention. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best understand and utilize the invention. The invention is limited only by the claims and the full scope and equivalents thereof.

Claims

1. The performance test system of the memory is characterized by comprising a performance test end and a host end, wherein the performance test end is in communication connection with the host end;

The system comprises a plurality of memory test seats, a plurality of data writing models and a plurality of hot spot writing operation, wherein the memory test seats are respectively used for installing a plurality of memories, the data writing models are built by the host end based on target application scenes of the memories, the data writing models respectively correspond to the target application scenes of the memories, and the target application scenes are scene fusion of sequential writing operation, random writing operation, ping-pong writing operation and hot spot writing operation; and

The central processing unit is in communication connection with the plurality of memory test seats and is used for carrying out write-in test on the plurality of memories based on the sub-write-in model in the data write-in model determined by the host end so as to obtain test data of the plurality of memories and analyzing and processing the test data so as to obtain corresponding scene write amplification coefficients of the sequential write model, the random write model, the ping-pong write model and the hot spot write model;

2. The system of claim 1, further comprising a test board, wherein a plurality of memory test sockets are integrated on the test board, the test board is provided with a plurality of power supply channels and a plurality of digital channels, the power supply channels respectively supply power to the memories, and the central processing unit simultaneously performs write-in test on the memories through the digital channels.

3. The system for testing the performance of a memory according to claim 1, wherein said performance testing terminal further comprises:

4. The system of claim 1, wherein the test data includes an amount of data written by the memory and an amount of data written by a host at the host, and the scene write amplification factor is a ratio of the amount of data written by the memory to the amount of data written by the host.

5. The system for testing performance of a memory according to claim 1, wherein the host is configured to pre-build a plurality of data writing models, the plurality of data writing models respectively correspond to a plurality of target application scenarios, and each of the target application scenarios respectively corresponds to a set of data writing proportions of sequential writing models, random writing models, ping-pong writing models, and hot-spot writing models.

6. The system of claim 5, wherein the host is further configured to determine whether a current write test is completed, and if the current write test is completed, the host switches the data write model, and causes the cpu to perform a write test on the plurality of memories based on the switched data write model, so that the host generates a data comparison table of the plurality of memories in another target application scenario, where the data comparison table is used to indicate performance differences of the plurality of memories in another target application scenario.

7. The performance test method for the memory is characterized by being applied to a performance test system of the memory, wherein the performance test system comprises a performance test end and a host end, the performance test end is in communication connection with the host end, the performance test end comprises a plurality of memory test seats and a central processing unit, the central processing unit is in communication connection with the plurality of memory test seats, and the performance test method comprises the following steps:

The host end builds a data writing model in advance, wherein the data writing model is fusion of a plurality of sub writing models, the plurality of sub writing models comprise a sequential writing model, a random writing model, a ping-pong writing model and a hot spot writing model, and the data writing model is used for indicating the data writing proportion of the sequential writing model, the data writing proportion of the random writing model, the data writing proportion of the ping-pong writing model and the data writing proportion of the hot spot writing model;

A plurality of memories are respectively installed on the memory test seats, wherein a plurality of data writing models are built by the host end based on target application scenes of the memories, the data writing models respectively correspond to the target application scenes of the memories, and the target application scenes are scene fusion of sequential writing operation, random writing operation, ping-pong writing operation and hot spot writing operation;

The CPU performs writing test on a plurality of memories based on a sub-writing model in a data writing model determined by the host side so as to obtain test data of the memories, and is used for analyzing and processing the test data so as to obtain corresponding scene amplification coefficients of the sequential writing model, the random writing model, the ping-pong writing model and the hot spot writing model;