CN117851290A - Page table management method, system, electronic component and electronic device - Google Patents
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Abstract
The disclosure provides a page table management method, a system, an electronic component and electronic equipment, wherein the page table management method comprises the following steps: the broadcasting unit receives a page table writing request carrying a first mirror address and page table content for any subsystem, and broadcasts an address to be updated, which is obtained based on the first mirror address, to a subsystem to be synchronized; the first mirror address represents a mirror address of a memory to be written corresponding to the page table content in any subsystem; the number of the subsystems to be synchronized is at least two; and the page table updating unit writes the page table content into a target memory pointed by an address to be updated received by the subsystem to be synchronized, wherein the target memory belongs to a corresponding memory of the subsystem to be synchronized. By the method, time consumption of retrieving corresponding page table entries in the memory of other main equipment by the MMU is reduced, efficiency of cross-memory access of the main equipment is improved, and system performance is further improved.
Description
Technical Field
The disclosure relates to the technical field of chips, and in particular relates to a page table management method, a page table management system, an electronic component and electronic equipment.
Background
In the prior art, each Master (Master) within a System On Chip (SOC), such as a CPU (Central Processing Unit ), GPU (Graphics Processing Unit, graphics processor), DMA (Direct Memory Access direct memory access), etc., may initiate an access request to a memory. Because software generally operates in a virtual address space, when a software issuing command calls each host device to access a memory, the host device generates a memory access request carrying a virtual address and issues the memory access request to an address translation unit (i.e., MMU), and after the MMU translates the virtual address into a physical address based on a page table, the memory access request of the host device can be issued. That is, memory access requests generated by the host device are in a blocked state before the MMU retrieves the page table to complete translation of the virtual address to the physical address.
From the foregoing, it is appreciated that the efficiency of memory access requests by a host device depends on the efficiency with which virtual addresses are translated into physical addresses. However, there is a difference in physical distance between the host device and the memory to be accessed, when the host device has a requirement of cross-memory access, for example, the host device 1 accesses the memory of the host device 2, and since the time consumed for retrieving the page table stored in the memory of the other host device by the MMU is significantly longer than the time consumed for retrieving the page table stored in the memory of the host device, the access request is blocked for a long time, which further causes a larger time delay when the host device performs the cross-memory access, and affects the system performance.
Disclosure of Invention
The purpose of the present disclosure is to provide a page table management method, a system, an electronic component, and an electronic device, which are favorable to reducing the time consumed by an MMU for retrieving corresponding page table entries in the memory of other main devices, and improving the efficiency of the main device for performing cross-memory access, thereby improving the system performance.
According to one aspect of the present disclosure, there is provided a page table management system including a broadcasting unit, a page table updating unit, and a plurality of host devices; a group of main devices in a plurality of main devices belong to the same subsystem, each subsystem comprises a corresponding memory and shares the same mirror image address space, and each mirror image address is unique in the subsystem;
the broadcasting unit is configured to: receiving a page table writing request carrying a first mirror address and page table content for any subsystem, and broadcasting an address to be updated, which is obtained based on the first mirror address, to a subsystem to be synchronized; the first mirror address represents a mirror address of a memory to be written corresponding to the page table content in any subsystem; the number of the subsystems to be synchronized is at least two;
the page table updating unit is configured to: and writing the page table content into a target memory pointed by an address to be updated received by the subsystem to be synchronized, wherein the target memory belongs to a corresponding memory of the subsystem to be synchronized.
In a possible implementation of the present disclosure, the address to be updated is the first mirror address.
In one possible implementation of the present disclosure, each subsystem is further configured with a linear address subspace corresponding to one, and each linear address in each linear address subspace is unique in the page table management system; in case of broadcasting to the subsystem to be synchronized an address to be updated derived based on the first mirror address, the broadcasting unit is specifically configured to: and mapping the first mirror address into a first linear address corresponding to the subsystem to be synchronized based on a mapping relation between the pre-configured mirror address space and the linear address subspaces of the subsystems, and sending the first linear address corresponding to the subsystem to be synchronized to the subsystems, wherein the address to be updated is the corresponding first linear address.
In a possible implementation manner of the present disclosure, the subsystem to be synchronized is a subsystem that is marked in advance in a plurality of subsystems and needs to be updated synchronously; in case of broadcasting to the subsystem to be synchronized an address to be updated derived based on the first mirror address, the broadcasting unit is specifically configured to: broadcasting the address to be updated to the marked subsystem in the subsystems.
In one possible implementation of the present disclosure, the subsystem marked for synchronous update is all of the plurality of subsystems or a portion of the plurality of subsystems.
In one possible implementation of the present disclosure, the page table contents include page table entries or state information for indicating that the page table is invalid.
In one possible implementation of the present disclosure, the main devices of different groups belong to the same SOC, and the corresponding memories of each subsystem belong to the same memory; or, different groups of main devices belong to different SOCs, and the corresponding memories of each subsystem are mutually independent.
In a possible implementation manner of the present disclosure, the page table management system further includes an address translation unit corresponding to the master device, the group of master devices and the group of address translation units corresponding to the master device belong to the same subsystem, each subsystem is further configured with a linear address subspace corresponding to one, and each linear address in each linear address subspace is unique in the page table management system; the address translation unit is configured to: responding to a memory access request of a first main device of a first subsystem where the first main device is located to access a first memory corresponding to the first subsystem or a second memory corresponding to a second subsystem where other main devices are located, reading a page table corresponding to the second mirror address from the first memory based on the second mirror address carried by the memory access request, translating a virtual address carried by the memory access request into the linear address, and then sending the linear address to the first main device.
According to another aspect of the present disclosure, there is further provided a page table management method applied to a page table management system, where the page table management system includes a broadcasting unit, a page table updating unit, and a plurality of host devices; a group of main devices in a plurality of main devices belong to the same subsystem, and each subsystem comprises a corresponding memory; the multiple subsystems share the same mirror address space, and each mirror address is unique within the subsystem; the method comprises the following steps:
the broadcasting unit receives a page table writing request carrying a first mirror address and page table content for any subsystem, and broadcasts an address to be updated, which is obtained based on the first mirror address, to a subsystem to be synchronized; the first mirror address represents a mirror address of a memory to be written corresponding to the page table content in any subsystem; the number of the subsystems to be synchronized is at least two;
and the page table updating unit writes the page table content into a target memory pointed by an address to be updated received by the subsystem to be synchronized, wherein the target memory belongs to a corresponding memory of the subsystem to be synchronized.
In a possible implementation, the address to be updated is the first mirrored address.
In one possible implementation, each of the subsystems further configures a linear address subspace in one-to-one correspondence, each linear address in each linear address subspace being unique within the page table management system; the broadcasting the address to be updated obtained based on the first mirror address to the subsystem to be synchronized includes: the broadcasting unit maps the first mirror address into a first linear address corresponding to the subsystem to be synchronized based on a mapping relation between the pre-configured mirror address space and the linear address subspaces of the subsystems, and sends the first linear address corresponding to the subsystem to be synchronized to the subsystems, wherein the address to be updated is the corresponding first linear address.
In a possible implementation manner, the subsystem to be synchronized is a subsystem which is marked in advance in a plurality of subsystems and needs to be updated synchronously; the broadcasting the address to be updated obtained based on the first mirror address to the subsystem to be synchronized includes: the broadcasting unit broadcasts the address to be updated to a marked subsystem of the plurality of subsystems.
In one possible implementation, the subsystem marked for synchronous update is all or part of the plurality of subsystems.
In one possible implementation, the page table contents include page table entries or state information indicating that the page table is invalid.
In one possible implementation, the main devices of different groups belong to the same SOC, and the corresponding memories of each subsystem belong to the same memory; or, the main devices of different groups belong to different SOCs, and the corresponding memories of each subsystem are mutually independent.
In a possible implementation manner, the page table management system further includes an address translation unit corresponding to the master device, the set of master devices and the set of address translation units corresponding to the master device belong to the same subsystem, each subsystem is further configured with a linear address subspace corresponding to one, and each linear address in each linear address subspace is unique in the page table management system; the method further comprises the steps of: the address translation unit responds to a memory access request of a first main device of a first subsystem where the address translation unit is located to access a first memory of the first subsystem or a second memory of a second subsystem where other main devices are located, reads a page table corresponding to the second mirror address from the first memory based on the second mirror address carried by the memory access request, translates a virtual address carried by the memory access request into the linear address and then sends the linear address to the first main device.
According to another aspect of the present disclosure, there is also provided an electronic component including the page table management system described in any one of the above embodiments. In some use scenarios, the product form of the electronic assembly is embodied as a graphics card; in other use cases, the product form of the electronic assembly is embodied as a CPU motherboard.
According to another aspect of the present disclosure, there is also provided an electronic device including the above-described electronic component. In some use scenarios, the product form of the electronic device is a portable electronic device, such as a smart phone, a tablet computer, a VR device, etc.; in some use cases, the electronic device is in the form of a personal computer, a game console, or the like.
Drawings
FIG. 1 is a schematic diagram of the structure of a page table management system of one embodiment of the present disclosure;
FIG. 2 is a diagram of mirrored address versus linear address for one embodiment of the present disclosure;
fig. 3 is a flow chart illustrating a page table management method according to an embodiment of the present disclosure.
Detailed Description
Before describing embodiments of the present disclosure, it should be noted that:
some embodiments of the disclosure are described as process flows, in which the various operational steps of the flows may be numbered sequentially, but may be performed in parallel, concurrently, or simultaneously.
The terms "first," "second," and the like may be used in embodiments of the present disclosure to describe various features, but these features should not be limited by these terms. These terms are only used to distinguish one feature from another.
The term "and/or," "and/or" may be used in embodiments of the present disclosure to include any and all combinations of one or more of the associated features listed.
It will be understood that when two elements are described in a connected or communicating relationship, unless a direct connection or direct communication between the two elements is explicitly stated, connection or communication between the two elements may be understood as direct connection or communication, as well as indirect connection or communication via intermediate elements.
In order to make the technical solutions and advantages of the embodiments of the present disclosure more apparent, the following detailed description of exemplary embodiments of the present disclosure is provided in conjunction with the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present disclosure, not all embodiments of which are exhaustive. It should be noted that, without conflict, the embodiments of the present disclosure and features of the embodiments may be combined with each other.
In the prior art, the physical distance between each main device and the memory to be accessed has a far-near difference, when the main device has a requirement of cross-memory access, for example, the main device 1 accesses the memory of the main device 2, because the time consumed for retrieving the page table stored in the memory of other main devices by the MMU corresponding to the main device is obviously longer than the time consumed for retrieving the page table stored in the memory of the main device, the access request can be blocked for a long time, and further, a larger time delay exists when the main device performs the cross-memory access, and the system performance is affected.
Based on this, an object of the present disclosure is to provide a page table management scheme, which is favorable to reduce the time consumed by an MMU to retrieve corresponding page table entries in the memory of other main devices, so as to improve the efficiency of the main device in performing cross-memory access, and further improve the system performance.
Specifically, referring to fig. 1, one embodiment of the present disclosure proposes a page table management system including a broadcast unit, a page table update unit, a plurality of masters, and other components (if necessary), such as the network on chip, the address translation unit, etc. shown in fig. 1.
Wherein, a group of master devices in a plurality of master devices belong to the same subsystem, and each subsystem comprises a corresponding memory.
It should be noted that, in the embodiment of the present disclosure, the corresponding memories of the respective subsystems may belong to the same memory, that is, after the same memory is logically divided, the divided portions are respectively allocated to the respective subsystems, and in this case, there is no strict physical location division between the corresponding memories of the respective subsystems.
Corresponding to this case, the product form of the above page table management system may be one SOC including a plurality of masters, and the subsystems are divided by the masters, for example, each group of masters includes at least one master, and the masters of different groups belong to the same SOC; correspondingly, the subsystem to which the group of main devices belongs comprises: corresponding memory, all masters included by the set of masters, network-on-chip, address translation units, etc. In the case where different groups of master devices belong to the same SOC, the networks on chip included in different subsystems are the same network on chip within the same SOC. Each subsystem is a latency domain, meaning that the latency of a master device within the subsystem to access the corresponding memory of the subsystem is less than the latency of the master device to access the corresponding memory of the other subsystems.
In another embodiment of the present disclosure, the corresponding memories of the respective subsystems may belong to different memories, that is, different memories from the same electronic component (for example, a graphics card, a motherboard, etc.) are respectively allocated to the respective subsystems, and accordingly, there is a strict physical boundary between the corresponding memories of the respective subsystems.
In response to this situation, the product form of the above page table management system may be a cascade chip including a plurality of SOCs, and the subsystems are divided by the SOCs, for example, different groups of main devices belong to different SOCs, the same group of main devices belong to the same SOC, and the subsystem to which the group of main devices belongs correspondingly includes: corresponding memory, all masters within the SOC to which the set of masters belongs, network-on-chip, address translation units, etc. Each subsystem is a latency domain, meaning that the latency of a master device within the subsystem to access the corresponding memory of the subsystem is less than the latency of accessing the corresponding memory of the other subsystems.
Alternatively, the memory in any of the above embodiments may be DDR (Double Data Rate) or other readable and writable memory.
It should be noted that in the embodiments of the present disclosure, the page table is stored in the corresponding memory of each subsystem, and the address translation unit may translate the virtual address into the physical address based on the page table entry of the page table.
In the embodiment of the present disclosure, the page table updating unit may be a hardware unit with management capability, such as a processor, for example, may be a CPU core in an SOC, where a program for managing page tables is generally running, and is responsible for managing page tables in corresponding memories of respective subsystems.
Alternatively, the Master device Master in any of the above embodiments may be a unit, such as CPU, DMA, GPU, that may initiate a memory access request to the memory of the present subsystem or the memory of another subsystem, that is, the memory may be regarded as a slave device of the Master.
Of course, it can be understood that, whether the main device in the subsystem accesses the memory of the subsystem or accesses the memory of other subsystems across the memory, the virtual address carried by the memory access request needs to be mapped into a physical address through the address translation unit, and then accesses the memory of the corresponding physical address through the network on chip.
The address translation unit needs to retrieve the corresponding page table entry from memory before mapping the virtual address to the physical address in order to perform an address translation operation based on the retrieved page table entry.
In order to reduce the time consumed by the address translation unit to retrieve the corresponding page table entries in the corresponding memories of other subsystems, in the embodiment of the present disclosure, in any one of the page table configuration stage and the subsequent page table update stage of each subsystem, the page table update unit may respond to the call of the program for managing the page table, and further generate the page table write request and send the page table write request to the broadcast unit, so that the broadcast unit broadcasts information to multiple subsystems, and the page table entries of the page table stored in the corresponding memories of each subsystem are caused to remain the same all the time.
That is, in the embodiments of the present disclosure, the configuration of the page table and the updating (including modification, deletion) of the page table may be applied based on the operation corresponding to the page table write request.
In order to achieve the above-mentioned process, in the embodiment of the disclosure, for each subsystem, a linear address and a mirror address are preconfigured for its corresponding memory, the linear address and the mirror address are both physical addresses, and a mapping relationship between the mirror address and the linear address is preconfigured.
Wherein the linear address of the corresponding memory of each subsystem forms a linear address subspace of the subsystem. The linear address subspaces of all the subsystems form a linear address space corresponding to the whole page table management system, the size of the linear address space is equal to the total capacity of the memory corresponding to the whole page table management system, and the linear address is unique in the whole page table management system. The mirror image address of the corresponding memory of each subsystem forms the mirror image address space of the subsystem, and the subsystems share the same mirror image address space, and the mirror image address is unique in a single subsystem and is not unique in the whole page table management system.
So configured, for the corresponding memory of each subsystem, there is a corresponding mirrored address space and linear address subspace, and there is a mapping relationship between the mirrored address space and the linear address subspace. Then, as shown in fig. 2, after the mirror address is received by a different subsystem (corresponding to the time delay domain in fig. 2), the mirror address can be mapped into different linear addresses by the mapping relationship between the mirror address space and the linear address subspace of the corresponding subsystem, so as to access different memories pointed by different linear addresses in different subsystems.
For example, assume there are a total of 4 subsystems, subsystem 0 through subsystem 3, respectively. The corresponding memory of each subsystem occupies 4GB of space, and the mirrored address space shared by the 4GB address space of each subsystem is 0x4_0000_0000-0x4_FFFF_FFFF.
The linear address space range occupied by the 16GB (4×4GB=16GB) memory space of the subsystem 0 to the subsystem 3 of the whole page table management system is 0x0000_0000 to 0x3_FFFF_FFFF.
The linear address subspace range of the subsystem 0 is 0x0000_0000-0x0_FFFF_FFFF, and the corresponding mirror image address space is 0x4_0000-0x4_FFFF_FFFF and the mirror image address space of other subsystems is the same. The linear address subspace range of the subsystem 1 is 0x1_0000-0x1_FFFF_FFFF, and the corresponding mirror image address space is 0x4_0000-0x4_FFFF_FFFF and the corresponding mirror image address space is the same as the mirror image address space of other subsystems. The linear address subspace range of the subsystem 2 is 0x2_0000-0x2_FFFF_FFFF, and the corresponding mirror image address space is 0x4_0000-0x4_FFFF_FFFF and the mirror image address space of other subsystems is the same. The linear address subspace range of the subsystem 3 is 0x3_0000-0x3_FFFF_FFFF, and the corresponding mirror image address space is 0x4_0000-0x4_FFFF_FFFF and the mirror image address space of other subsystems is the same.
Based on the above configuration, in the case where upper layer software needs to perform a page table configuration or page table update operation for a certain subsystem (hereinafter referred to as a specific subsystem for convenience of distinction), the page table update unit generates a page table write request for the specific subsystem.
In a page table write request, a mirror address (hereinafter referred to as a first mirror address for ease of distinction) and page table contents are carried. Wherein the first mirror address represents the mirror address of the memory to be written to in which page table contents should be written in the specific subsystem.
After receiving the page table writing request, the broadcasting unit broadcasts an address to be updated, which is obtained based on the first mirror address, to the subsystem to be synchronized, so that the page table updating unit writes the page table content which is written into the specific subsystem into the corresponding memory of the subsystem to be synchronized (which is at least two subsystems in a plurality of subsystems), specifically the target memory pointed by the address to be updated in the corresponding memory, and further forms page table item copies of page tables stored in each other in the plurality of subsystems based on the address to be updated. The subsystems to be synchronized may be all the subsystems or some of the subsystems.
Accordingly, a broadcasting unit configured to: receiving a page table writing request carrying a first mirror address and page table content for any subsystem, and broadcasting an address to be updated, which is obtained based on the first mirror address, to a subsystem to be synchronized; the first mirror address represents a mirror address of a memory to be written corresponding to the page table content in any subsystem; the number of the subsystems to be synchronized is at least two;
a page table updating unit configured to: and writing the page table content into a target memory pointed by an address to be updated received by the subsystem to be synchronized, wherein the target memory belongs to a corresponding memory of the subsystem to be synchronized.
In the above process, in the configuration and updating stage of the page table, page table entries of the page table in the memory of the subsystem to be synchronized in the above multiple subsystems are updated synchronously, so that for the subsystem to be synchronized, in the page table stored in the memory of each subsystem to be synchronized, the union of page table entries of the page tables of all the subsystems to be synchronized is actually stored. When the main device in one of the subsystems to be synchronized has the requirement of accessing the memory of the other subsystems to be synchronized, because the memory of the subsystem in which the main device is positioned stores the corresponding page table item, the page table item can be hit in the memory of the subsystem to implement the address translation process in the process of fetching the page table of the address translation unit of the subsystem in which the main device is positioned, and the memory page table of the other subsystems is not required to be fetched any more, thereby being beneficial to reducing the time consumption of the address translation unit to fetch the corresponding page table item in the memory of the other main device, and further improving the efficiency of the main device for performing the cross-memory access and the system performance.
The above process will be described in detail below.
The above-mentioned broadcasting unit broadcasts the address to be updated obtained based on the first mirror address to the subsystem to be synchronized among the plurality of subsystems after receiving the page table write request.
In some embodiments, the address to be updated may be the first mirror address itself, that is, the broadcasting unit directly broadcasts the first mirror address to a plurality of subsystems to be broadcast, that is, the subsystems to be synchronized.
Because the first mirror address is unique in the subsystem, for each subsystem to be synchronized which receives the first mirror address, the target memory corresponding to the first mirror address can be accurately found according to the first mirror address, and then the page table content is written into different target memories of each subsystem to be synchronized by the page table updating unit, so that synchronous configuration or updating of page table items is realized.
In some embodiments, the address to be updated may be a linear address mapped according to the first mirror address.
In the foregoing, a mapping relationship exists between the mirrored address space of the corresponding memory of the subsystem and the linear address subspace. In some implementations of the present disclosure, there are mapping relationships between mirrored address spaces and linear address subspaces of corresponding memories of respective subsystems pre-configured within a broadcast unit, e.g., there are 4 subsystems, there are 4 sets of mapping relationships respectively, and these 4 sets of mapping relationships are pre-configured within the broadcast unit.
In case of broadcasting the address to be updated, which is obtained based on the first mirror address, to the subsystem to be synchronized, the broadcasting unit is specifically configured to: and mapping the first mirror image address into a first linear address corresponding to each subsystem or the subsystem to be synchronized based on the mapping relation between the pre-configured mirror image address space and the linear address subspace of each subsystem, and then sending the first linear address corresponding to each subsystem to be synchronized. In this case, the address to be updated is the corresponding first linear address.
For example, the 4 subsystems are subsystem 0 to subsystem 3, respectively, and the mapping relationship between the mirrored address space and the linear address subspace of each subsystem is shown in table 1.
TABLE 1
Assuming that the subsystems 0 to 3 are all to be synchronized, after the broadcasting unit receives the first image address 0x4_0000_0001, the first image address is mapped to the first linear address 0x_0000_0001 corresponding to the subsystem 0, the first linear address 0x1_0000_0001 corresponding to the subsystem 1, the first linear address 0x2_0000_0001 corresponding to the subsystem 2, and the first linear address 0x3_0000_0001 corresponding to the subsystem 3 according to the mapping relationship, and each first linear address is broadcasted into the corresponding subsystem.
Correspondingly, the page table updating unit writes the same page table content into the first linear address 0x_0000_0001 corresponding to the subsystem 0, the first linear address 0x1_0000_0001 corresponding to the subsystem 1, the first linear address 0x2_0000_0001 corresponding to the subsystem 2, and the first linear address 0x3_0000_0001 corresponding to the subsystem 3.
As for the subsystems to be synchronized, in some implementations, when the subsystems to be synchronized are all the subsystems, the addresses to be updated are directly broadcast to all the subsystems without adding additional configuration.
In other implementations, where the subsystems to be synchronized are part of the subsystems, it may be noted by a register or setting a status bit for each subsystem to record whether each subsystem is marked, and the marked subsystem by default is the subsystem to be synchronized that needs to be updated synchronously. Accordingly, in the case of broadcasting the address to be updated obtained based on the first mirror address to the subsystem to be synchronized, the broadcasting unit is specifically configured to: broadcasting the address to be updated to the marked subsystem in the plurality of subsystems.
Of course, in the case that the subsystems to be synchronized are all subsystems, all the subsystems may be marked in the form of marks.
The foregoing is mentioned that the operations corresponding to the page table write request in the embodiments of the present disclosure may be applicable to the configuration of the page table and the update (including modification and deletion) of the page table.
For configuration and modification of the page table, the page table contents are the corresponding page table entries.
In some embodiments, each page table includes corresponding state information, e.g., vaill, and indicates that the page table is valid when the state information is a first preset character, indicates that the page table is invalid when the state information is a second preset character, e.g., indicates that the corresponding page table is valid when vaill=1, and indicates that the corresponding page table is invalid when vaill=0.
Correspondingly, for deleting the page table, the page table content corresponding to the page table writing request can be state information for indicating that the page table is invalid, and the state information corresponding to the page table is set to be invalid, so that the effect of deleting the page table is achieved.
In addition, when the subsystem 1 stores a memory access request into the corresponding memory of the subsystem on the basis of the synchronous update of page table entries of the page tables of the respective subsystems, the address translation unit 1 of the subsystem 1 may read the corresponding page table entry from the page table stored in the corresponding memory 1 of the subsystem 1 based on the mirror address to complete the address translation operation.
Assuming that the subsystem 2 and the subsystem 1 are both to be synchronized, when the subsystem 1 initiates a cross-memory access request to the subsystem 2, because page table entries of the page table of the subsystem 2 are also synchronously stored in the subsystem 1, the address translation unit 1 of the subsystem 1 can also read corresponding page table entries of the page table stored in the corresponding memory 1 of the subsystem 1 based on the mirror image address to complete address translation operation, thereby reducing time delay of obtaining the page table entries.
As for the mirror address for obtaining the page table, the memory access request generated by the master device is carried. It is of course noted that in embodiments of the present disclosure, the page table may be a single-level page table or a multi-level page table. Whether it is a single-stage page table or a multi-stage page table, the other page tables point to the base mirror address of the next-stage page table, and the contents of the last-stage page table point to the final linear address after translation. In the disclosed embodiments, page table addressing may be performed by mirroring the address.
Accordingly, in some embodiments, the address translation unit of each subsystem is configured to: responding to a memory access request of a first main device of a first subsystem where the first main device is located for accessing a first memory of the first subsystem or a second memory of a second subsystem where other main devices are located, reading a page table corresponding to the second mirror address from the first memory based on the second mirror address carried by the memory access request, translating a virtual address carried by the memory access request into a linear address based on the obtained page table, and then sending the linear address to the first main device.
In addition, based on similar inventive concepts, the embodiments of the present disclosure also provide a page table management method, which is applied to a page table management system, where the page table management system includes a broadcasting unit, a page table updating unit, and a plurality of host devices; a group of main devices in a plurality of main devices belong to the same subsystem, and each subsystem comprises a corresponding memory; the multiple subsystems share the same mirrored address space, and each of the mirrored addresses is unique within the subsystem.
Referring to fig. 3, the method may include:
step S110: the broadcasting unit receives a page table writing request carrying a first mirror address and page table contents for any subsystem, and broadcasts an address to be updated obtained based on the first mirror address to the subsystem to be synchronized.
The first mirror address represents a mirror address of a memory to be written corresponding to the page table content in any subsystem; the number of the subsystems to be synchronized is at least two.
Step S120: and the page table updating unit writes the page table content into a target memory pointed by an address to be updated received by the subsystem to be synchronized, wherein the target memory belongs to a corresponding memory of the subsystem to be synchronized.
In a possible implementation, the address to be updated is the first mirrored address.
In one possible implementation, each of the subsystems further configures a linear address subspace in one-to-one correspondence, each linear address in each linear address subspace being unique within the page table management system; the broadcasting the address to be updated obtained based on the first mirror address to the subsystem to be synchronized includes: the broadcasting unit maps the first mirror address into a first linear address corresponding to the subsystem to be synchronized based on a mapping relation between the pre-configured mirror address space and the linear address subspaces of the subsystems, and sends the first linear address corresponding to the subsystem to be synchronized to the subsystems, wherein the address to be updated is the corresponding first linear address.
In a possible implementation manner, the subsystem to be synchronized is a subsystem which is marked in advance in the plurality of subsystems and needs to be updated synchronously; the broadcasting the address to be updated obtained based on the first mirror address to the subsystem to be synchronized includes: the broadcasting unit broadcasts the address to be updated to a marked subsystem of the plurality of subsystems.
In one possible implementation, the subsystem marked for synchronous update is all or part of the plurality of subsystems.
In one possible implementation, the page table contents include page table entries or state information indicating that the page table is invalid.
In one possible implementation, the plurality of main devices belong to the same SOC, and the corresponding memories of each subsystem belong to the same memory; or, different groups of main devices belong to different SOCs, and the corresponding memories of each subsystem are mutually independent.
In a possible implementation manner, the page table management system further includes an address translation unit corresponding to the master device, the set of master devices and the set of address translation units corresponding to the master device belong to the same subsystem, each subsystem is further configured with a linear address subspace corresponding to one, and each linear address in each linear address subspace is unique in the page table management system; the method further comprises the steps of: the address translation unit responds to a memory access request of a first main device of a first subsystem where the address translation unit is located to access a first memory of the first subsystem or a second memory of a second subsystem where other main devices are located, reads a page table corresponding to the second mirror address from the first memory based on the second mirror address carried by the memory access request, translates a virtual address carried by the memory access request into the linear address and then sends the linear address to the first main device.
In addition, the embodiment of the disclosure further provides an electronic component, which includes the page table management system described in any one of the embodiments. In some use scenarios, the product form of the electronic assembly is embodied as a graphics card; in other use cases, the product form of the electronic assembly is embodied as a CPU motherboard.
In addition, the embodiment of the disclosure also provides electronic equipment, which comprises the electronic component. In some use scenarios, the product form of the electronic device is a portable electronic device, such as a smart phone, a tablet computer, a VR device, etc.; in some use cases, the electronic device is in the form of a personal computer, game console, workstation, server, etc.
While the preferred embodiments of the present disclosure have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the disclosure.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present disclosure without departing from the spirit or scope of the disclosure. Thus, the present disclosure is intended to include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (14)
1. A page table management system comprises a broadcasting unit, a page table updating unit and a plurality of main devices; a group of main devices in a plurality of main devices belong to the same subsystem, each subsystem comprises a corresponding memory and shares the same mirror image address space, and each mirror image address is unique in the subsystem;
the broadcasting unit is configured to: receiving a page table writing request carrying a first mirror address and page table content for any subsystem, and broadcasting an address to be updated, which is obtained based on the first mirror address, to a subsystem to be synchronized; the first mirror address represents a mirror address of a memory to be written corresponding to the page table content in any subsystem; the number of the subsystems to be synchronized is at least two;
the page table updating unit is configured to: and writing the page table content into a target memory pointed by an address to be updated received by the subsystem to be synchronized, wherein the target memory belongs to a corresponding memory of the subsystem to be synchronized.
2. The page table management system of claim 1, the address to be updated being the first mirrored address.
3. The page table management system of claim 1, each of said subsystems further configured with a one-to-one correspondence of linear address subspaces, each linear address in each of said linear address subspaces being unique within said page table management system; in case of broadcasting to the subsystem to be synchronized an address to be updated derived based on the first mirror address, the broadcasting unit is specifically configured to: and mapping the first mirror address into a first linear address corresponding to the subsystem to be synchronized based on a mapping relation between the pre-configured mirror address space and the linear address subspaces of the subsystems, and sending the first linear address corresponding to the subsystem to be synchronized to the subsystems, wherein the address to be updated is the corresponding first linear address.
4. The page table management system of claim 1, wherein the subsystem to be synchronized is a subsystem of a plurality of subsystems that is marked in advance for synchronization update; in case of broadcasting to the subsystem to be synchronized an address to be updated derived based on the first mirror address, the broadcasting unit is specifically configured to: broadcasting the address to be updated to the marked subsystem in the subsystems.
5. The page table management system of claim 4, wherein the marked subsystem requiring synchronous updating is all or part of the plurality of subsystems.
6. The page table management system of claim 1, the page table contents comprising page table entries or status information indicating that a page table is invalid.
7. The page table management system of any of claims 1-6, wherein different groups of masters belong to the same SOC and corresponding memories of each of the subsystems belong to the same memory; or, the main devices of different groups belong to different SOCs, and the corresponding memories of each subsystem are mutually independent.
8. The page table management system of claim 7, further comprising address translation units corresponding to the masters, the set of masters and their corresponding set of address translation units belonging to the same subsystem, each of the subsystems further configured with a one-to-one linear address subspace, each linear address in each linear address subspace being unique within the page table management system; the address translation unit is configured to: responding to a memory access request of a first main device of a first subsystem where the first main device is located to access a first memory corresponding to the first subsystem or a second memory corresponding to a second subsystem where other main devices are located, reading a page table corresponding to the second mirror address from the first memory based on the second mirror address carried by the memory access request, translating a virtual address carried by the memory access request into the linear address, and then sending the linear address to the first main device.
9. An electronic component comprising the page table management system of any of claims 1-8.
10. An electronic device comprising the electronic assembly of claim 9.
11. A page table management method is applied to a page table management system, wherein the page table management system comprises a broadcasting unit, a page table updating unit and a plurality of main devices; a group of main devices in a plurality of main devices belong to the same subsystem, each subsystem comprises a corresponding memory and shares the same mirror image address space, and each mirror image address is unique in the subsystem; the method comprises the following steps:
the broadcasting unit receives a page table writing request carrying a first mirror address and page table content for any subsystem, and broadcasts an address to be updated, which is obtained based on the first mirror address, to a subsystem to be synchronized; the first mirror address represents a mirror address of a memory to be written corresponding to the page table content in any subsystem; the number of the subsystems to be synchronized is at least two;
and the page table updating unit writes the page table content into a target memory pointed by an address to be updated received by the subsystem to be synchronized, wherein the target memory belongs to a corresponding memory of the subsystem to be synchronized.
12. The method of claim 11, each of the subsystems further configuring a one-to-one correspondence of linear address subspaces, each linear address in each linear address subspace being unique within the page table management system; the broadcasting the address to be updated obtained based on the first mirror address to the subsystem to be synchronized includes: the broadcasting unit maps the first mirror address into a first linear address corresponding to the subsystem to be synchronized based on a mapping relation between the pre-configured mirror address space and the linear address subspaces of the subsystems, and sends the first linear address corresponding to the subsystem to be synchronized to the subsystems, wherein the address to be updated is the corresponding first linear address.
13. The method of claim 11, wherein the subsystem to be synchronized is a subsystem of a plurality of subsystems that is marked in advance for synchronization update; the broadcasting the address to be updated obtained based on the first mirror address to the subsystem to be synchronized includes: the broadcasting unit broadcasts the address to be updated to a marked subsystem of the plurality of subsystems.
14. The method of any of claims 11-13, the page table management system further comprising address translation units corresponding to the masters, the set of masters and their corresponding set of address translation units belonging to a same subsystem, each of the subsystems further configured with a one-to-one linear address subspace, each linear address in each linear address subspace being unique within the page table management system; the method further comprises the steps of: the address translation unit responds to a memory access request of a first main device of a first subsystem where the address translation unit is located to access a first memory corresponding to the first subsystem or a second memory corresponding to a second subsystem where other main devices are located, reads a page table corresponding to the second mirror address from the first memory based on the second mirror address carried by the memory access request, translates a virtual address carried by the memory access request into the linear address and then sends the linear address to the first main device.
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