CN110737607A

CN110737607A - Method and device for managing HMB memory, computer equipment and storage medium

Info

Publication number: CN110737607A
Application number: CN201910947374.7A
Authority: CN
Inventors: 吴娴; 韩道静; 王庆
Original assignee: Shenzhen Union Memory Information System Co Ltd
Current assignee: Shenzhen Union Memory Information System Co Ltd
Priority date: 2019-09-30
Filing date: 2019-09-30
Publication date: 2020-01-31
Anticipated expiration: 2039-09-30
Also published as: WO2021062982A1; CN110737607B

Abstract

The invention relates to methods, devices, computer equipment and storage media for managing HMB memories, wherein the method comprises the steps of obtaining a mapping unit to be written in a complete mapping table to obtain attribute information of the mapping unit, screening the management unit with the same offset as the mapping unit according to the attribute information to obtain an initial set, judging whether the initial set has a vacant management unit, if so, selecting the vacant management unit to obtain a target management unit, if not, obtaining the management unit with the maximum Age value as the target management unit, writing the attribute information of the mapping unit into the target management unit to form management information, and writing the mapping unit into a segmented memory space with the same offset in the HMB according to the management information.

Description

Method and device for managing HMB memory, computer equipment and storage medium

Technical Field

The invention relates to the field of SSD mapping table management, in particular to methods and devices for managing an HMB memory, a computer device and a storage medium.

Background

The NVMe (non Volatile Memory express) protocol defines a Host Memory Buffer (HMB) function, which means that a Solid State Disk (SSD) supporting the NVMe protocol can use a Host Memory (DRAM) which is specially allocated to the solid state disk by a Host, so that the solid state disk does not need to be equipped with the DRAM by itself, and the cost and the power consumption can be greatly reduced.

The solid state disk master control supporting the HMB function can obtain use rights of part of host memory, the size of the host memory is obtained by the host and the solid state disk according to respective capabilities, and is not fixed, here, the HMB size is assumed to be 256MB and is used for caching a temporary mapping table, for a solid state disk with the capacity of 1TG, the part of memory can only cache part of mapping tables, a complete mapping table still needs to be stored in a flash memory, the solid state disk master control is responsible for managing the temporary mapping table in the HMB, and the solid state disk firmware is responsible for managing the complete mapping table in the flash memory.

When the host initiates read commands, the master firstly judges whether the mapping information of each LBA is in the HMB according to the management information, if so, the mapping information (data) is read from the HMB to the SSD master through the PCIe bus, the mainstream third generation PCIe bus can provide 1GB/s bus bandwidth, only 4us is needed for transmitting 4KB data, the speed is quite high, if the mapping information is not in the HMB, the SSD master can only read the mapping information from the flash memory of the SSD, the time for reading physical pages is about 80us, the speed is relatively slow, and then the mapping information also needs to be cached in the HMB because the mapping information is Hot (frequently updated data).

There have been proposed methods for managing HMB memory in the existing master design, which divide the full mapping table in SSD into n parts (segments) according to HMB size, where n is the full mapping table size/HMB size, the master's cache (SRAM) allocates management information for each 4KB memory in HMB, where those 4KB mapping units in different segments in the full mapping table that have the same offset compete for the management unit in master SRAM with offset and the 4KB memory in HMB with offset, and enforce the competition principle that new data overwrites old data, as shown in fig. 1, where n is 3 in this example, it can be seen that the size of each segment is equal to the HMB size, and we define an offset (offset) for each 4KB granule in a segment, where the maximum offset is 3 (0-3).

When a new 4KB map unit needs to be stored in the HMB, the controller stores segment _ idx and offset _ idx of the 4KB map unit provided by the firmware into the management information with the offset equal to offset _ idx, transfers the 4KB map unit data to the 4KB host memory with the offset of offset _ idx in the HMB, and then validates the valid location.

In order to achieve the greatest query efficiency, the method for managing the HMB memory in the prior art allows mapping units of the same offset in all segments to compete for management units in masters (corresponding to 4KB memory space in HMBs), so that hot data can be easily discarded, for example, five written hot data [ segment0, offset0], [ segment0, offset2], [ segment1, offset0], [ segment2, offset0], [ segment1, offset2], and finally, only [ segment2, offset0] and [ segment1, offset2] are buffered in the HMBs, and three data are discarded, so that the HMB usage rate is low, which results in resource waste of the HMB.

Disclosure of Invention

The invention aims to overcome the defects of the prior art and provides the method.

In order to achieve the purpose, the invention adopts the following technical scheme that methods for managing the HMB memory comprise the following steps:

acquiring a mapping unit to be written in a complete mapping table to obtain attribute information of the mapping unit;

screening the management units with the same offset as the mapping unit according to the attribute information to obtain an initial set;

judging whether an idle management unit exists in the initial set;

if the idle management unit exists, selecting the idle management unit to obtain a target management unit;

if no idle management unit exists, acquiring a management unit with the largest Age value as a target management unit;

writing the attribute information of the mapping unit into a target management unit to form management information;

setting the Valid value of the target management unit to be 1, setting the Age value to be 0, and setting the Age values of other management units except the target management unit in the initial set to be added with 1;

and writing the mapping unit into the segmented memory space with the same offset in the HMB according to the management information.

Further , before the step of obtaining the mapping unit to be written in the complete mapping table to obtain the attribute information of the mapping unit, the method further includes:

allocating memory spaces as HMBs for storing the mapping units to the host application;

dividing the HMB into N segments to obtain segment sizes;

according to the size of the segment, dividing a complete mapping table in the flash memory into M subsections equally, wherein the segment and the subsection have the same size;

dividing the segment into S segment memory spaces, and dividing the sub-segment into S mapping units, wherein the segment memory spaces and the mapping units have the same size;

defining a segmented memory space for storing the mapping unit in the same offset, and storing the attribute information of the mapping unit as management information in a target management unit with the same offset;

n, M, and S, both represent natural numbers greater than 0.

Further , after the step of writing the mapping unit into the segmented memory space with the same offset in the HMB according to the management information, the method further includes:

acquiring a mapping unit reading command;

analyzing the mapping unit reading command to obtain attribute information of the mapping unit to be read;

inquiring the management unit according to the attribute information to obtain the management unit with the same attribute information;

and reading the mapping unit data of the corresponding position on the HMB according to the management information of the management unit.

, the step of writing the mapping unit into the segmented memory space with the same offset in the HMB according to the management information comprises:

the management units belonging to the same initial collections are stored in SRAM sections with continuous physical addresses.

The invention also adopts the following technical scheme that devices for managing the HMB memory comprise:

the attribute obtaining unit is used for obtaining a mapping unit to be written in the complete mapping table so as to obtain attribute information of the mapping unit;

the screening set unit screens the management units with the same offset as the mapping unit according to the attribute information to obtain an initial set;

the idle judging unit is used for judging whether an idle management unit exists in the initial set or not, if the idle management unit exists, the idle management unit is selected to obtain a target management unit, and if the idle management unit does not exist, the management unit with the largest Age value is obtained to serve as the target management unit;

an information writing unit for writing the attribute information of the mapping unit into the target management unit to form management information;

the assignment unit is used for setting the Valid value of the target management unit to be 1 and the Age value to be 0, and setting the Age values of other management units except the target management unit in the initial set to be added with 1;

and the mapping writing unit is used for writing the mapping unit into the segmented memory space with the same offset in the HMB according to the management information.

, further comprising an HMB setting unit, wherein the HMB setting unit comprises a memory application subunit, a segmentation subunit, a division subunit, a segmentation subunit and a definition subunit;

the memory application subunit is configured to apply for allocating memory spaces as HMBs to the host, so as to store the mapping unit;

the segmentation subunit is configured to divide the HMB equally into N segments to obtain segment sizes;

the subsection subunit is used for equally dividing the complete mapping table in the flash memory into M subsections according to the subsection size, and the subsection size is equal to the subsection size;

the segmentation subunit segments the segment into S segmented memory spaces, segments the subsection into S mapping units, and the segmented memory spaces and the mapping units have the same size;

the definition subunit is used for defining the segmented memory space for storing the mapping unit in the same offset, and the attribute information of the mapping unit is stored in the target management unit with the same offset as the management information;

n, M, and S, both represent natural numbers greater than 0.

, it also includes a data reading unit, the data reading unit includes a command obtaining subunit, an attribute analyzing subunit, an attribute inquiring subunit and a data reading subunit;

the command acquisition subunit is used for acquiring a mapping unit reading command;

the attribute analysis subunit is used for analyzing the mapping unit reading command to obtain the attribute information of the mapping unit to be read;

the attribute inquiry subunit is used for inquiring the management unit according to the attribute information to obtain the management unit with the same attribute information;

and the data reading subunit is used for reading the mapping unit data at the corresponding position on the HMB according to the management information of the management unit.

, it also includes an address adjustment unit for storing the management units belonging to the same initial collections in the SRAM segment with continuous physical addresses.

computer devices, the computer devices include a memory and a processor, the memory stores computer programs, the processor when executing the computer programs realizes the method for managing HMB memory described in any item.

The present invention further provides storage media storing a computer program that, when executed by a processor, implements the method of managing HMB memory as set forth in any of items above.

Compared with the prior art, the invention has the beneficial effects that: according to the method, the HMB is divided into a plurality of segments, and the mapping units with the same offset are correspondingly stored, so that the hot data hit rate of the HMB is greatly increased, and the utilization rate of the HMB is further improved; the management units with the same offset in the main control are mapped to the continuous physical address field of the SRAM, and the parallel implementation of a hardware circuit is matched, so that the query time is shortened, and the data query efficiency is improved.

The invention is further described with reference to the figures and the specific embodiments.

Drawings

In order to more clearly illustrate the technical solution of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.

FIG. 1 is a schematic diagram illustrating an application of a conventional method for managing an HMB memory;

fig. 2 is a flowchart illustrating methods for managing HMB memory according to an embodiment of the present invention;

fig. 3 is a schematic flow chart of an HMB setting sub-process of methods for managing an HMB memory according to an embodiment of the present invention;

fig. 4 is a schematic diagram illustrating a sub-flow of reading a mapping unit of methods for managing an HMB memory according to an embodiment of the present invention;

fig. 5 is a flowchart illustrating a method for managing HMB memory according to another embodiment of the present invention;

fig. 6 is an application schematic diagram of methods for managing HMB memory according to an embodiment of the present invention;

fig. 7 is an application schematic diagram of methods for managing HMB memory according to an embodiment of the present invention;

fig. 8 is a schematic block diagram of apparatuses for managing HMB memory according to an embodiment of the present invention;

fig. 9 is a schematic block diagram of an HMB setting unit of the devices for managing HMB memory according to an embodiment of the present invention ;

FIG. 10 is a schematic block diagram of means for managing HMB memory according to another embodiment of the present invention;

FIG. 11 is a schematic block diagram of a data read unit of devices for managing HMB memory according to another embodiment of the present invention;

FIG. 12 is a schematic block diagram of a computer device provided by an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention.

It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of or more other features, integers, steps, operations, elements, components, and/or groups thereof.

As used in this specification and the appended claims, the singular forms "", "" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should also be further understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of or more of the associated listed items.

Fig. 2 is a schematic flowchart of methods for managing an HMB memory according to an embodiment of the present invention, the methods for managing an HMB memory are applied to an SSD, and the SSD performs data interaction with a host.

Fig. 2 is a flowchart illustrating a method for managing an HMB memory according to an embodiment of the present invention. As shown in fig. 2, the method includes the following steps S110 to S180.

S110, obtaining a mapping unit to be written in the complete mapping table to obtain attribute information of the mapping unit.

In this embodiment, the complete mapping table may be divided into a plurality of mapping units, each having a size KB, each of which is written with corresponding attribute information, where the attribute information includes offset information and belonging branch information. For example, the mapping unit [ segment _ x, offset _ y ] represents that the offset information is offset _ y, the belonging part information is segment _ x, and the attribute information of the mapping unit includes the offset information offset _ y and the belonging part information is segment _ x.

Fig. 3 is a flow chart illustrating an HMB setting sub-process, and referring to fig. 3, the methods for managing an HMB memory according to the present embodiment further include an HMB setting process before step S110, and the HMB setting process includes steps S210 to S250.

S210, allocating memory spaces as HMBs to the host application for storing the mapping units.

In this embodiment, the SSD starts to apply part of the memory space to the host at , which is used as an hmb (host memory buffer), so that the SSD (solid state disk) supporting the NVMe protocol can use the host memory (DRAM) applied from the host, and thus the solid state disk does not need to be equipped with the DRAM, which can greatly reduce the cost and power consumption.

S220, dividing the HMB into N segments equally to obtain segment sizes.

And S230, dividing the complete mapping table in the flash memory into M subsections equally according to the sizes of the subsections, wherein the sizes of the subsections are equal to that of the subsections.

And S240, dividing the segment into S segment memory spaces, dividing the subsection into S mapping units, wherein the segment memory spaces and the mapping units have the same size.

In this embodiment, as for steps S220 to S240, it is different from the conventional method in which the full mapping table on the flash memory is divided into N segments (segments) according to the size of the entire HMB, where N is the size of the full mapping table/the size of the HMB.

As shown in fig. 6, in the present example, the size of the HMB is 24KB, N is 3, the HMB is divided into 3 segments, each segment has a size of 8KB, each segment includes 2 segmented memory spaces of 4KB, the HMB includes 6 segmented memory spaces in total, the size of the complete mapping table is 48KB, the segment is divided into 6 partitions according to the segment size of 8KB, M is 6, each partition is 8KB, each partition includes 2 mapping units of 4KB, includes 12 mapping units in total, the SRAM of the SSD master has 6 management units for managing 6 segmented memory spaces in association, and the management units are configured to correspondingly store attribute information of the mapping units written into the segmented memory spaces as management information, including a segment value and an offset value.

S250, defining the segmented memory space for storing the mapping units in the same offset, and storing the attribute information of the mapping units as management information in target management units with the same offset.

Specifically, M mapping units with offset (x) in the complete mapping table can compete together and are finally stored in N segmented memory spaces with offset (x), and compared with the prior art in which multiple mapping units with offset (x) compete for segmented memory spaces with offset (x), the present solution can store multiple mapping units with the same offset at the same time, thereby better utilizing the memory space of the HMB and improving the hit rate of the HMB.

As shown in fig. 6, the mapping unit with offset equal to x in 6 segments divided by the complete mapping table competes for the memory space with offset equal to x in 3 SETs in the HMB, where x is 0 or 1, so that the HMB can store N (3) mapping units with the same offset equal to x.

Specifically, N, M and S both represent natural numbers greater than 0.

S120, screening the management units with the same offset as the mapping unit according to the attribute information to obtain an initial set.

In this embodiment, the offset information in the attribute information is obtained according to the obtained attribute information, all the management units with the same offset are screened out according to the offset information, and all the management units are used as the initial set to determine the management units in the initial set in step , and the target management unit for writing the management information is determined.

S130, judging whether the initial set has an idle management unit.

S140, if the idle management unit exists, the idle management unit is selected to obtain the target management unit.

S150, if no idle management unit exists, acquiring the management unit with the largest Age value as a target management unit.

In this embodiment, the initial set includes management units having the same offset attribute, and before a mapping unit writes a segmented memory space corresponding to an offset according to the offset, it needs to determine whether there is a free segmented memory space for writing, and therefore it needs to determine whether there is a free management unit in the initial set, where there are two cases, is a free management unit, which represents that there is a segmented memory space in which a mapping unit is not written, and the mapping unit can be directly written into the corresponding segmented memory space, and is required to select a free management unit to obtain a target management unit, and is no free management unit, and segmented memory spaces in which mapping units have been written are eliminated and then written into new mapping units, and at this time, a management unit with the largest Age value needs to be obtained as a target management unit.

Specifically, the method adopts an LRU (Least recently Used) algorithm, introduces an Age value into the management units, the Age value represents the freshness of data in a corresponding segmented memory space, the value is 0 and 1 … N-1, the smaller the value is, the newer the data is, each management unit carries the Age value, and the management unit with the largest Age value (N-1) in the initial set is the oldest management unit and is Used as a target management unit for data elimination and writing in a new mapping unit.

And S160, writing the attribute information of the mapping unit into the target management unit to form management information.

In this embodiment, the attribute information is written into the target management unit to form management information, which is used to subsequently query the corresponding mapping unit according to the attribute information and download the corresponding mapping data.

S170, setting the Valid value of the target management unit to be 1, setting the Age value to be 0, and setting the Age values of other management units except the target management unit in the initial set to be added with 1.

In this embodiment, Valid indicates whether the management information is Valid, a value of 1 indicates that the management information of the management unit is Valid, a value of 0 indicates that the management information of the management unit is invalid, and a value of 1 indicates that the management information of the target management unit is Valid, and the Age value of the management unit is set to 0, and the Age values of the management units other than the target management unit in the initial set are added by 1, that is, each time new mapping units are written, the Age values of the management units not eliminated are added by 1, so that it is ensured that the Age value corresponding to the management unit corresponding to the mapping unit written first is always greater than the Age value corresponding to the management unit corresponding to the mapping unit written later, and the oldest management unit can be screened and eliminated through the Age values.

For example, five mapping units are written in firmware [ segment0, offset0], [ segment0, offset1], [ segment1, offset0], [ segment2, offset0], [ segment1, and offset1], and three pieces of thermal data with final offset equal to 0 are buffered in the HMB according to the above writing and erasing rules. Assuming that the subsequent firmware is written into the mapping unit [ segment5, offset0], the management unit #1 with more elimination rule is eliminated, as shown in FIG. 6.

And S180, writing the mapping unit into the segmented memory space with the same offset in the HMB according to the management information.

In this embodiment, according to the offset information in the management information, mapping units are written into the segmented memory space with the same offset in the HMB, for example, all mapping units with an offset equal to 0 are correspondingly written into the segmented memory space with an offset equal to 0, so as to ensure that a plurality of mapping units with the same offset can be stored, thereby better utilizing the memory space of the HMB and improving the hit rate of the HMB.

Referring to fig. 5, in the embodiment, step S190 is further included after step S180.

And S190, storing the management units belonging to the same initial collections in SRAM sections with continuous physical addresses.

In the embodiment, since the HMB is divided into a plurality of segments, the main control needs to query the address segments of a plurality of SRAMs when querying the management units, which slightly increases the query time, as shown in fig. 7, the present invention stores the management units belonging to the same initial sets in the SRAM segments with continuous physical addresses, and when the hardware circuit of the main control query algorithm is implemented, it can only start queries (starting address plus query length) of the SRAMs, which can effectively shorten the query time and improve the query efficiency.

Fig. 4 is a flowchart illustrating a sub-process of reading the mapping unit, and referring to fig. 4, the methods for managing the HMB memory according to the present embodiment further include a process of reading the mapping information (data) after step S180, where the process of reading the mapping information (data) includes steps S310 to S340.

S310, obtaining a mapping unit reading command.

S320, analyzing the mapping unit reading command to obtain the attribute information of the mapping unit to be read.

S330, inquiring the management unit according to the attribute information to obtain the management unit with the same attribute information.

S340, reading the mapping unit data of the corresponding position on the HMB according to the management information of the management unit.

In the embodiment, when reading the mapping unit data, the mapping unit reading command is obtained, the mapping unit reading command is parsed to obtain the attribute information of the mapping unit to be read, the management unit is queried according to the attribute information to obtain the management unit with the same attribute information, and the mapping unit data at the corresponding position on the HMB is read according to the management information of the management unit.

For example, if the query mapping unit [ segment1, offset0] is in the HMB, the master directly queries whether a segment1 unit exists in the management unit whose offset is 0, and if so, the corresponding HMB data is sent to the firmware, otherwise, the HMB data is not hit, and in this example, the result is a hit in the HMB #3 memory.

Fig. 8 is a schematic block diagram of apparatuses for managing HMB memory according to an embodiment of the present invention, as shown in fig. 8, corresponding to the above method for managing HMB memory, the present invention further provides apparatuses for managing HMB memory, which include a unit for performing the above method for managing HMB memory, and which may be disposed in a desktop computer, a tablet computer, a laptop computer, or the like, and in particular, referring to fig. 8, the apparatuses for managing HMB memory include an attribute obtaining unit 10, a filter aggregation unit 20, a vacancy judging unit 30, an information writing unit 40, an assignment unit 50, a map writing unit 60, and an HMB setting unit 70.

An attribute obtaining unit 10, configured to obtain a mapping unit to be written in the complete mapping table, so as to obtain attribute information of the mapping unit.

The screening aggregation unit 20 screens the management units having the same offset as the mapping unit according to the attribute information to obtain an initial aggregation.

And the idle judging unit 30 is configured to judge whether an idle management unit exists in the initial set, select the idle management unit if an idle management unit exists, to obtain a target management unit, and acquire the management unit with the largest Age value as the target management unit if an idle management unit does not exist.

An information writing unit 40 for writing the attribute information of the mapping unit to the target management unit to form the management information.

And the assigning unit 50 is configured to set the Valid value of the target management unit to 1, set the Age value of the target management unit to 0, and set the Age values of the other management units except the target management unit in the initial set plus 1.

And a mapping writing unit 60, configured to write the mapping unit into the segmented memory space with the same offset in the HMB according to the management information.

Referring to fig. 9, in this embodiment, the apparatus for managing HMB memory further includes an HMB setting unit 70, where the HMB setting unit 70 includes a memory application subunit 71, a segmentation subunit 72, a division subunit 73, a split subunit 74, and a definition subunit 75.

The memory application subunit 71 is configured to allocate memory spaces as HMBs to the host application for storing the mapping units.

A segmentation subunit 72, configured to divide the HMB into N segments equally to obtain the segment size.

And the part subunit 73 is configured to divide the complete mapping table in the flash memory into M parts, where the size of each part is equal to that of each segment.

The segmentation subunit 74 segments the segment into S segmented memory spaces, segments the segment into S mapping units, and the segmented memory spaces and the mapping units have the same size.

In this embodiment, the segmentation subunit 72, the division subunit 73, and the segmentation subunit 74 are different from the conventional method in which the full mapping table on the flash memory is segmented into N segments (segments) according to the size of the entire HMB, where N is the size of the full mapping table/the size of the HMB.

And a defining subunit 75, configured to define a segmented memory space for storing the mapping unit in the same offset, where the attribute information of the mapping unit is stored as management information in a target management unit with the same offset.

Specifically, N, M and S both represent natural numbers greater than 0.

Fig. 10 is a schematic block diagram of devices for managing an HMB memory according to another embodiment of the present invention, and as shown in fig. 10, an address adjustment unit 80 and a data reading unit 90 are added to the HMB memory management device according to the embodiment.

And an address adjusting unit 80, configured to store the management units belonging to the same initial collections in SRAM segments with consecutive physical addresses.

As shown in fig. 11, the data reading unit 90 includes a command acquisition sub-unit 91, an attribute parsing sub-unit 92, an attribute querying sub-unit 93, and a data reading sub-unit 94.

A command obtaining subunit 91, configured to obtain a mapping unit read command.

And the attribute analyzing subunit 92 is configured to analyze the mapping unit reading command to obtain the attribute information of the mapping unit to be read.

And an attribute query subunit 93, configured to query the management unit according to the attribute information to obtain the management units with the same attribute information.

And a data reading sub-unit 94, configured to read mapping unit data at a corresponding position on the HMB according to the management information of the management unit.

It should be noted that, as can be clearly understood by those skilled in the art, the specific implementation process of the apparatus for managing an HMB memory and each unit may refer to the corresponding description in the foregoing method embodiment, and for convenience and conciseness of description, no further description is provided herein.

Referring to fig. 12, fig. 12 is a schematic block diagram of computer devices provided in the embodiment of the present application, where the computer device 500 may be a terminal or a server, where the terminal may be an electronic device with a communication function, such as a smart phone, a tablet computer, a notebook computer, a desktop computer, a personal digital assistant, and a wearable device.

Referring to fig. 12, the computer device 500 includes a processor 502, memory, and a network interface 505 connected by a system bus 501, where the memory may include a non-volatile storage medium 503 and an internal memory 504.

The non-volatile storage medium 503 may store an operating system 5031 and a computer program 5032 the computer program 5032 comprises program instructions that, when executed, cause the processor 502 to perform methods of managing HMB memory.

The processor 502 is used to provide computing and control capabilities to support the operation of the overall computer device 500.

The memory 504 provides an environment for the operation of the computer program 5032 in the non-volatile storage medium 503, and when the computer program 5032 is executed by the processor 502, the processor 502 can be enabled to perform methods for managing the HMB memory.

The network interface 505 is used for network communication with other devices. Those skilled in the art will appreciate that the configuration shown in fig. 12 is a block diagram of only a portion of the configuration associated with the present application and does not constitute a limitation of the computer device 500 to which the present application may be applied, and that a particular computer device 500 may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.

Wherein the processor 502 is adapted to run a computer program 5032 stored in the memory.

It should be understood that, in the embodiment of the present Application, the Processor 502 may be a Central Processing Unit (CPU), and the Processor 502 may also be other general purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), ready-made Programmable arrays (FPGAs) or other Programmable logic devices, discrete or transistor logic devices, discrete hardware components, etc.

It will be understood by those skilled in the art that all or part of the flow of the method implementing the above embodiments may be implemented by associated hardware instructed by a computer program comprising program instructions that may be stored in storage medium being computer readable storage medium for execution by at least processors in the computer system to implement the flow steps of the above embodiments of the method.

Accordingly, the present invention also provides storage media.

The storage medium may be a usb disk, a removable hard disk, a Read-Only Memory (ROM), a magnetic disk, or an optical disk, which can store various computer readable storage media.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of the function for clarity of explanation of interchangeability of hardware and software.

For example, the above-described apparatus embodiments are merely illustrative, for example, the division of the various units, which may be only logical function divisions, may be implemented in practice with additional divisions.

In addition, each functional unit in each embodiment of the invention can be integrated into processing units, or each unit can exist alone physically, or two or more units can be integrated into units.

Based on the understanding that the technical solution of the present invention is essentially or partially contributing to the prior art, or that all or part of the technical solution can be embodied in the form of a software product stored in storage media, and includes several instructions for causing computer devices (which may be personal computers, terminals, or network devices, etc.) to perform all or part of the steps of the methods described in the embodiments of the present invention.

While the invention has been described with reference to specific embodiments, the invention is not limited thereto, and various equivalent modifications and substitutions can be easily made by those skilled in the art within the technical scope of the invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1, A method for managing HMB memory, comprising the steps of:

judging whether an idle management unit exists in the initial set;

2. The method for managing an HMB memory according to claim 1, wherein before the step of obtaining the mapping unit to be written in the complete mapping table to obtain the attribute information of the mapping unit, the method further comprises:

dividing the HMB into N segments to obtain segment sizes;

n, M, and S, both represent natural numbers greater than 0.

3. The method according to claim 1, wherein after the step of writing the mapping unit into the segmented memory space with the same offset in the HMB according to the management information, the method further comprises:

acquiring a mapping unit reading command;

4. The method according to claim 1, wherein the step of writing the mapping unit into the segmented memory space with the same offset in the HMB according to the management information is followed by:

An apparatus for managing HMB memory of the type 5, , comprising:

6. The apparatus of claim 5, further comprising an HMB setup unit, wherein the HMB setup unit comprises a memory application subunit, a segmentation subunit, a division subunit, a split subunit, and a definition subunit;

n, M, and S, both represent natural numbers greater than 0.

7. The apparatus for managing an HMB memory of claim 5, further comprising a data reading unit, wherein the data reading unit comprises a command obtaining subunit, an attribute parsing subunit, an attribute querying subunit, and a data reading subunit;

8. The apparatus for managing HMB memory of claim 5 further comprising an address adjustment unit for storing the management units belonging to the same initial collections in SRAM segments with consecutive physical addresses.

computer device, characterized in that it comprises a memory on which is stored a computer program and a processor which, when it is executed, implements the method of managing HMB memory according to any of claims 1 to 4.

Storage medium , characterized in that it stores a computer program which, when executed by a processor, implements a method of managing HMB memory according to any of claims 1 to 4 to .