CN116701248A - Page table management method, unit, SOC, electronic device and readable storage medium - Google Patents
Page table management method, unit, SOC, electronic device and readable storage medium Download PDFInfo
- Publication number
- CN116701248A CN116701248A CN202210174707.9A CN202210174707A CN116701248A CN 116701248 A CN116701248 A CN 116701248A CN 202210174707 A CN202210174707 A CN 202210174707A CN 116701248 A CN116701248 A CN 116701248A
- Authority
- CN
- China
- Prior art keywords
- page table
- address
- target
- slave
- page
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000007726 management method Methods 0.000 title claims abstract description 54
- 238000013507 mapping Methods 0.000 claims abstract description 69
- 230000008859 change Effects 0.000 claims description 92
- 230000001360 synchronised effect Effects 0.000 claims description 33
- 238000000034 method Methods 0.000 claims description 19
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 238000012544 monitoring process Methods 0.000 claims description 4
- 230000008569 process Effects 0.000 claims description 4
- 238000012986 modification Methods 0.000 description 11
- 230000004048 modification Effects 0.000 description 11
- 238000010586 diagram Methods 0.000 description 9
- 238000004590 computer program Methods 0.000 description 7
- 230000006870 function Effects 0.000 description 7
- 238000012545 processing Methods 0.000 description 6
- 238000004891 communication Methods 0.000 description 4
- 230000003993 interaction Effects 0.000 description 3
- 230000004075 alteration Effects 0.000 description 2
- 238000012423 maintenance Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1009—Address translation using page tables, e.g. page table structures
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
The present disclosure provides a page table management method, unit, SOC, electronic device, and readable storage medium. By adopting the technical scheme, after the homepage table stored in the target address range is confirmed to be changed, other slave page tables related to the changed contents can also automatically update with the master page table, and the master page table needs to be maintained with the same mapping logic automatically.
Description
Technical Field
The disclosure relates to the technical field of page table synchronization, and in particular relates to a page table management method, a unit, an SOC, an electronic device and a readable storage medium.
Background
With the development of technology, an SOC (System On Chip) using a VM (Virtual Memory) may include a plurality of functional modules (IP cores), each IP Core (intellectual property Core) having a corresponding Page Table (Page Table) and an MMU (Memory Management Unit ), each IP Core may access the Virtual address VA (Virtual Address), and convert the VA into a physical address PA (Physical Address) through the corresponding MMU, and finally obtain data from the Memory and return the data to the IP Core to complete one data access. Since there may be a need for data interaction between IP cores within the same SOC, it is desirable to be able to establish a certain association between page tables of different IP cores.
At present, in the stage of configuring page tables for all IP cores, a section of VA < - > PA identical mapping logic is respectively configured for the IP cores needing data interaction, so that the logical mapping relation of VA < - > PA represented by the page tables is identical. After the operation, although a certain connection can be established between page tables of different IP cores, when the configured page tables are in a missing page or a subsequent page changing operation needs to be executed, synchronization between the page tables can be maintained only by manually configuring the page tables corresponding to the IP cores again, errors are easily caused, and maintenance difficulty is increased.
Disclosure of Invention
The purpose of the present disclosure is to provide a page table management method, a unit, an SOC, an electronic device, and a readable storage medium, which can reduce the difficulty of maintaining a page table.
According to one aspect of the present disclosure, there is provided a page table management method, the method comprising: when the homepage table stored in the target address range is confirmed to be changed, obtaining the changing content of the main page table and the changing address of the main page table; determining a target slave page table with synchronous updating relation with the changed content according to the changed address and the read master-slave page table address mapping information which corresponds to each slave page table one by one; updating the target slave page table according to the master-slave page table address mapping information of the target slave page table, the page size of the master page table, the page size of the target slave page table, the change address and the change content.
In one possible implementation of the present disclosure, the master-slave page table address mapping information includes a corresponding slave page table address range to be monitored, and the target address range is a union of all slave page tables address ranges to be monitored; according to the changed address and the read address mapping information of the master page table and the slave page table, which are in one-to-one correspondence with each slave page table, determining a target slave page table with synchronous updating relation with the changed content, comprising: determining a target address range to be monitored containing the changed address from the address range to be monitored contained in the address mapping information of each master-slave page table; and the slave page table corresponding to the master-slave page table address mapping information of the target to-be-monitored address range is the target slave page table.
In one possible implementation of the present disclosure, there may be intersections of the ranges of addresses to be monitored for each slave page table.
In one possible implementation of the present disclosure, the master-slave page table address mapping information includes a corresponding slave page table to-be-monitored address range and a to-be-synchronized start offset address, where the target address range is a union of all slave page table to-be-monitored address ranges; updating the target slave page table according to the master-slave page table address mapping information of the target slave page table, the page size of the master page table, the page size of the target slave page table, the change address and the change content, comprising: determining a target address for storing change contents from an address range for storing the target slave page table according to the change address, a starting address of the target slave page table where the address range to be monitored is located, a starting offset address of the target slave page table to be synchronized, a page size of the master page table and a page size of the target slave page table; the change content is written to the destination address.
In one possible implementation of the present disclosure, the main page table and the target slave page table have different page table formats, and writing the change content to the target address includes: after converting the change content into the page table format of the target slave page table, writing the change content after converting the format into the target address.
In one possible implementation of the present disclosure, determining, from an address range for storing a target slave page table, a target address for storing change contents according to a change address, a start address where a target slave page table is to be monitored, a target slave page table to be synchronized start offset address, a page size of a master page table, and a page size of a target slave page table, includes: when the page size of the master page table is consistent with the page size of the target slave page table, the change address is differed from the initial address of the target slave page table in the address range to be monitored, and a first difference value is obtained; and summing the first difference value and the target to-be-synchronized initial offset address of the page table to obtain a first sum value, wherein the first sum value is the target address.
In one possible implementation of the present disclosure, determining, from an address range for storing a target slave page table, a target address for storing change contents according to a change address, a start address where a target slave page table is to be monitored, a target slave page table to be synchronized start offset address, a page size of a master page table, and a page size of a target slave page table, includes: when the page size of the master page table is determined to be larger than the page size of the target slave page table and is in N times relation with the page size of the target slave page table, the change address is differenced from the initial address of the target slave page table where the address range to be monitored is located, a first difference value is obtained, and N is a positive integer; multiplying the first difference value with N to obtain a first product value; summing the first product value and a target slave page table to-be-synchronized initial offset address to obtain a first sum value; the first sum is increased by steps for N-1 times, the step length is the storage space occupied by one page table, N addresses are obtained, and the N addresses are target addresses;
Correspondingly, writing the change content to the target address comprises the following steps: the change content is written N times to N addresses.
In a possible implementation manner of the present disclosure, the method further includes: monitoring the target address range, and determining that the homepage table stored in the target address range is changed when the condition that the read and/or write operation is performed on the address in the target address range is detected; or alternatively, the process may be performed,
determining that a homepage table stored in a target address range has a change when trigger information for representing reading and/or writing operations for addresses in the target address range is acquired; the trigger information is sent by the function module using the home page table.
According to another aspect of the present disclosure, there is further provided a virtual address management unit, configured to perform the page table management method provided in any one of the foregoing possible implementations.
In one possible implementation manner of the present disclosure, the virtual address management unit may be configured to be in an enabled state or a disabled state, and accordingly, the virtual address management unit is configured to execute the page table management method provided in any one of the possible implementation manners when determining that the virtual address management unit is in the enabled state.
According to another aspect of the present disclosure, there is also provided an SOC including a virtual address management unit, an on-chip bus network, a memory, and a plurality of IP cores provided in any one of the possible implementations, the virtual address management unit being connected to the plurality of IP cores and the memory through the on-chip bus network, page tables of the IP cores being stored in the memory, page tables of any one of the plurality of IP cores being configured as a homepage table, page tables of other IP cores being configured as slave page tables.
In one possible implementation of the present disclosure, there are multiple target address ranges, and the multiple target address ranges are discontinuous, each target address range is used to store different contents of the main page table; the SOC comprises a plurality of virtual address management units, wherein the virtual address management units are in one-to-one correspondence with the target address ranges; each virtual address management unit is configured to execute the page table management method provided in any one of the possible implementations described above with respect to the target address range corresponding to itself.
In one possible implementation of the present disclosure, any of the IP cores described above is a CPU Core.
According to another aspect of the present disclosure, there is also provided an electronic device including the above SOC. In some use scenarios, the product form of the electronic device is a portable electronic device, such as a smart phone, a tablet computer, a VR device, etc.; in some use cases, the electronic device is in the form of a personal computer, a game console, or the like.
According to another aspect of the present disclosure, there is also provided a computer readable storage medium having stored thereon a virtual address management program that, when executed, implements the page table management method provided by any one of the possible implementations described above.
Drawings
FIG. 1 is a schematic diagram of the correspondence between IP Core and page tables according to one embodiment of the present disclosure;
FIG. 2 is a flow diagram of a page table management method according to one embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of an SOC according to an embodiment of the present disclosure.
Detailed Description
Before describing embodiments of the present disclosure, it should be noted that:
some embodiments of the disclosure are described as process flows, in which the various operational steps of the flows may be numbered sequentially, but may be performed in parallel, concurrently, or simultaneously.
The terms "first," "second," and the like may be used in embodiments of the present disclosure to describe various features, but these features should not be limited by these terms. These terms are only used to distinguish one feature from another.
The term "and/or," "and/or" may be used in embodiments of the present disclosure to include any and all combinations of one or more of the associated features listed.
It will be understood that when two elements are described in a connected or communicating relationship, unless a direct connection or direct communication between the two elements is explicitly stated, connection or communication between the two elements may be understood as direct connection or communication, as well as indirect connection or communication via intermediate elements.
In order to make the technical solutions and advantages of the embodiments of the present disclosure more apparent, the following detailed description of exemplary embodiments of the present disclosure is provided in conjunction with the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present disclosure, not all embodiments of which are exhaustive. It should be noted that, without conflict, the embodiments of the present disclosure and features of the embodiments may be combined with each other.
The present disclosure is directed to providing a page table management scheme.
The page table is a special data structure stored in the memory and used for representing the mapping logic between virtual addresses and physical addresses, namely VA < - > PA. Optionally, the page table referred to in the embodiments of the present disclosure may be a primary page table or a multi-stage page table, which is not limited by the present disclosure.
Each page table occupies a certain memory space, and as for the size of the memory space occupied by each page table, the size is determined by the system in which the page table is specifically located, for example, for a 32-bit (bit) system, each page table occupies a memory space of 4 bytes (byte) memory, and for a 64-bit system, each page table occupies a memory space of 8 bytes of memory.
Within an SOC comprising a plurality of IP cores, each IP Core has a corresponding page table, and each IP Core accesses data in memory using the mapping logic of VA < - > PA held in its corresponding page table. For example, in the SOC shown in fig. 1, a Microprocessor uses Microprocessor Page table corresponding thereto to access data in a memory, a GPU Core (Graphics Processing Unit Core, graphics processor Core) uses a GPU Page table corresponding thereto to access data in a memory, and a Video Core (Video processor Core) uses a Video Page table corresponding thereto to access data in a memory.
Because there may be a need for data interaction between different IP cores, there is at least a portion of mapping logic that needs to be kept the same between page tables of the IP cores that need to interact with data. Of course, in some embodiments, there may be a section of mapping logic between page tables of multiple IP cores that need not be data interacted with, which needs to remain the same.
For ease of description, in subsequent embodiments of the present disclosure, if there is at least one segment of mapping logic between multiple page tables that needs to be kept the same, then the multiple page tables are referred to as an associated multiple page tables, and the main page table is specified from the associated multiple page tables.
On this basis, when the homepage table in the associated multiple page tables is changed and the changed contents are within the scope of the mapping logic which needs to be kept the same, other page tables in the associated multiple page tables also need to be changed along with the changed contents of the main page table.
Accordingly, the page table management scheme provided by the present disclosure is used for automatically updating a plurality of page tables that need to maintain the same mapping logic. The page table management scheme provided by the present disclosure will be described in detail below.
As shown in fig. 2, one embodiment of the present disclosure provides a page table management method, which may include:
s110: when the homepage table stored in the target address range is confirmed to be changed, obtaining the changing content of the main page table and the changing address of the main page table;
s120: determining a target slave page table with synchronous updating relation with the changing content according to the changing address and the read master-slave page table address mapping information which corresponds to each slave page table one by one;
s130: and updating the target slave page table according to the master-slave page table address mapping information of the target slave page table, the page size of the homepage table, the page size of the target slave page table, the change address and the change content.
In the present disclosure, the means for performing the above-described page table management method may be referred to as a virtual address management Unit (Virtual Address Management-Unit, VAMU). The VAMU may be directly or indirectly connected to other components (e.g., IP Core, memory, etc.) included in the SOC through an on-chip Bus network Bus included in the SOC.
In some application scenarios, the VAMU may be integrated within the SOC, i.e., the VAMU may be a newly added functional module within the SOC. In other applications, the VAMU may also be a functional module independent of the SOC.
In the present disclosure, the VAMU is used to automatically update an associated plurality of page tables present within the SOC. To achieve this, one of the page tables associated with the SOC may be configured in advance as a master page table, the other page tables of the associated plurality of page tables configured as slave page tables, and each slave page table configured to be automatically updated following a change in local mapping logic of the master page table.
For example, in some usage scenarios, when the SOC includes a CPU Core, since the CPU Core may need to interact data with other IP cores, the page table corresponding to the CPU Core may be configured as a master page table, and correspondingly, other page tables included in the SOC that need to have the same mapping logic as the page table of the CPU Core are configured as slave page tables. Of course, in other usage scenarios, when the SOC includes a CPU Core, the page table corresponding to any other IP Core included in the SOC may be configured as a master page table, and the page table corresponding to the CPU Core may be configured as a slave page table.
After the main page table and the auxiliary page table are designated, the main page table address mapping information corresponding to each auxiliary page table one by one is also required to be configured, and the main page table address mapping information comprises the address range to be monitored of the corresponding auxiliary page table and the initial offset address to be synchronized.
It is worth noting that in some application scenarios, the master-slave page table address mapping information may be configured within the memory of the SOC. In other application scenarios, the VAMU may also include storage space, such as registers, memory, etc., and the master-slave page table address mapping information is configured within the storage space managed by the VAMU.
The address range to be monitored is used for stating that the corresponding slave page table needs to keep synchronous with the mapping logic in which address ranges the homepage table is stored, and the initial offset address to be synchronized is used for stating the initial address of the address range occupied by the mapping logic in the memory, which needs to be synchronized, of the corresponding slave page table.
It should be noted that the address ranges to be monitored of the respective slave page tables may be identical, may be partially identical, or may be completely different, but the address ranges to be monitored of the respective slave page tables are smaller than the address ranges occupied by the entire master page table in the memory.
Each address range formed from the union of the address ranges to be monitored of the page table is a subset of all address ranges occupied by the home page table in the memory, and in this disclosure, the address range corresponding to the subset is referred to as the target address range of the home page table.
Taking a 32bit system as an example, under the 32bit system, the address space occupied by each page table is 0x00000004. Assume that the associated multiple page tables are page table 1, page table 2, page table 3, and page table 4, respectively, and that page table 1 is the master page table, and page table 2, page table 3, and page table 4 are slaves. Assuming that the address range occupied by the whole homepage table in the memory is 0x 80000000-0 x8000 9000; a certain segment of mapping logic (the starting address for storing the segment of mapping logic is 0x8100 0000) included in the page table 2 needs to keep synchronous with the mapping logic stored in the address range of 0x8000 0000-0 x8000 8000 in the main page table, so that the address range to be monitored of the page table 2 is 0x8000 0000-0 x8000 8000, and the starting offset address to be synchronized of the page table 2 is 0x8100 0000; a certain segment of mapping logic (the starting address for storing the segment of mapping logic is 0x8200 0000) included in the page table 3 needs to keep synchronous with the mapping logic stored in the address range of 0x8000 0000-0 x8000 4000 in the homepage table, so that the address range to be monitored of the page table 3 is 0x8000 0000-0 x8000 4000, and the starting offset address to be synchronized of the page table 3 is 0x8200 0000; some segment of mapping logic included in page table 4 (the starting address for storing this segment of mapping logic is 0x8300 0000) needs to keep synchronous with the mapping logic stored in the address range of 0x8000 4000-0 x8000 8000 in the homepage table, then the address range to be monitored of page table 4 is 0x8000 4000-0 x8000, and the starting offset address to be synchronized of page table 4 is 0x8300 0000.
In the above embodiment, the target address range of the main page table is the union of the address ranges to be monitored of page table 2, page table 3 and page table 4, and is 0x8000 0000 to 0x8000 8000.
After the configuration is completed, if the VAMU determines that the homepage table stored in the target address range has a change, the corresponding change content and the change address where the change content is located in the main page table can be obtained, and then the target slave page table which needs to be updated along with the change content at this time is determined through the change address and the master page table address mapping information corresponding to each slave page table. After the target slave page table is determined, the mapping relation in the target slave page table is updated according to the master-slave page table address mapping information of the target slave page table, the page size of the master page table, the change address and the change content, and further the automatic updating of the slave page table along with the change of the local mapping logic of the master page table can be realized.
Now assume that a worker needs to update a page table in the SOC.
If the updated page table does not belong to the plurality of associated page tables, the configuration of the page table is modified by a worker according to the page table management method provided by the present disclosure, and the number of modifications is 1.
If the updated page table is one of the associated multiple page tables in the SOC and the updated contents are the associated multiple page tables, the same mapping logic needs to be maintained. If, in the prior art, there are N page tables to be synchronized with the updated contents of the page table, then the worker needs to modify the configuration of the page table and the N page tables, the number of modifications being n+1. If the page table management method provided by the present disclosure is used, the staff member can modify the mapping logic corresponding to the updated content in the main page table. Since the content of the update is that the plurality of associated page tables need to keep the same mapping logic, the modified content is located in the target address range of the main page table, and the modification operation triggers the main page table stored in the target address range to generate change and be further acquired by the VAMU, so that the slave page table which needs to be synchronously updated with the updated content can be automatically updated according to the page table management method.
That is, in this application scenario, by adopting the page table management method provided by the present disclosure, a worker only needs to modify the configuration of the main page table, and the number of times of modification is still 1, compared with the scheme that n+1 needs to be modified in the prior art, the page table management method provided by the present disclosure can reduce the number of times of modification of the worker, and automatically maintain the page table, thereby reducing the maintenance difficulty and being beneficial to the stability of the SOC.
Details of implementation of the page table management method provided by the present disclosure will be described below.
S110: when the homepage table stored in the target address range is confirmed to be changed, the changing content of the main page table and the changing address of the main page table are acquired.
In one embodiment of the present disclosure, the VAMU may be configured to have a monitoring function, and accordingly, the VAMU may actively monitor the target address range of the home page table through the on-chip bus network after the monitoring function is started. If the VAMU monitors that writing operation is performed on any address in the target address range, the VAMU can determine that the homepage table stored in the target address range is changed, and can continuously read the changing content of the main page table in time through the on-chip bus network and read the changing address for storing the changing content.
In another embodiment of the present disclosure, the VAMU may also determine that there is a change to the home page table maintained within the target address range upon passive receipt of trigger information (e.g., interrupt, notification, etc.) sent by other IP cores. Wherein the trigger information is generated and transmitted by the IP Core using the homepage table.
Taking the main page table as the CPU Core as an example, in this embodiment, a detector may be mounted at the CPU at the exit of the on-chip bus network, or at the entrance of the memory on-chip bus network, so that the CPU may generate trigger information including the change content and the change address for saving the change content to the VAMU according to whether the detector detects that there is a read operation and/or a write operation performed with respect to any address in the target address range, and when the presence is detected.
S120: and determining a target slave page table with synchronous updating relation with the changing content according to the changing address and the read master-slave page table address mapping information which corresponds to each slave page table one by one.
The foregoing mentions that master-slave page table address mapping information is preconfigured in one-to-one correspondence with each slave page table, and that master-slave page table address mapping information includes a range of addresses to be monitored of the corresponding slave page table. The VAMU can read master-slave page table address mapping information of each slave page table stored in the memory through the on-chip bus system.
After the VAMU acquires the change address of the homepage table, the current or past read address range which is included in the master-slave page table address mapping information corresponding to each slave page table one by one is compared with the change address, so that whether the address range to be monitored including the change address exists or not is judged, and the address range to be monitored including the change address is determined as a target address range to be monitored. Correspondingly, the slave page table corresponding to the master-slave page table address mapping information of the target to-be-monitored address range is the target slave page table.
In some cases, since there may be an intersection between the address ranges to be monitored of the slave page tables, a single change of the master page table may result in a plurality of target address ranges to be monitored including the changed address, and accordingly, the slave page tables corresponding to the master page table address mapping information to which each target address range to be monitored belongs are all target slave page tables, that is, a single change of the master page table may result in a plurality of target slave page tables that need to follow the change.
Continuing with the above assumption that the target address range of the home page table is 0x 80000000-0 x8000 8000, if a change of the home page table stored in 0x8000 0004 occurs due to a certain change, the VAMU acquires the change address 0x8000 0004, and then compares the to-be-monitored address ranges 0x8000 0000-0 x8000 8000 with 0x8000 0004, 0x8000 0000-0 x80004000 with 0x8000 0004, and 0x 80004000-0 x8000 with 0x8000 0004 of the to-be-monitored address range of the page table 4, respectively, from the page table 2. Wherein, the address range 0x8000 0000-0 x8000 8000 to be monitored of the slave page table 2 and the address range 0x8000 0000-0 x80004000 to be monitored of the slave page table 3 have intersection, and the change address 0x8000 0004 falls into the range of the intersection, which results in the change address 0x8000 0004 falling within the address range 0x8000 0000-0 x8000 to be monitored of the slave page table 2 and the address range 0x8000 0000-0 x8000 to be monitored of the slave page table 3 respectively, thus the slave page table 2 and the slave page table 3 are the target slave page table of the current change.
S130: and updating the target slave page table according to the master-slave page table address mapping information of the target slave page table, the page size of the homepage table, the page size of the target slave page table, the change address and the change content.
The master-slave page table address mapping information mentioned above for the slave page table includes the start offset address to be synchronized for the corresponding slave page table.
After determining the target slave Page table, for each target slave Page table, the VAMU can calculate the target address of the target slave Page table for storing the change content by combining the starting address of the target slave Page table where the address range to be monitored is located, the initial offset address to be synchronized of the target slave Page table, the Page Size (Page Size) of the target slave Page table, the Page Size of the master Page table and the change address, so as to write the change content into the target address subsequently, and realize automatic update of the target slave Page table.
It is worth noting that the target address is a subset of the total address range that the target occupies in memory from the page table.
When calculating the target address, there are mainly two cases, respectively: the page sizes of the master page table and the target slave page table are the same and the page sizes of the master page table and the target slave page table are different. The page size of each page table is pre-configured in memory, which the VAMU can read to via the on-chip bus system.
For the case that the page size of the master page table is the same as the page size of the target slave page table, the VAMU can make a difference between the change address and the starting address of the target slave page table where the address range to be monitored is located, so as to obtain a first difference value, and then sum the first difference value and the starting offset address of the target slave page table to be synchronized, so as to obtain a first sum value. The first sum is the target address of the target slave page table.
Continuing with the assumption that the target address range of the homepage table is 0x8000 0000-0 x8000 8000, the address range to be monitored of the slave page table 2 is 0x8000 0000-0 x8000 8000, the initial offset address to be synchronized of the slave page table 2 is 0x8100 0000, the address range to be monitored of the slave page table 3 is 0x8000 0000-0 x8000 4000, the initial offset address to be synchronized of the slave page table 3 is 0x8200 0000, if a change causes a change of the homepage table stored in 0x8000 0004, the slave page table of the target slave page table of the current change is determined after the VAMU acquires the change address 0x8000 0004.
Assume that the page sizes of the master page table, slave page table 2, and slave page table 3 are the same, all 4K. In this case, the VAMU calculates the target address from page table 2 as: (0x8000 0004-0x8000 0000) +0x8100 0000=0x8100 0004; the VAMU calculates the target address from page table 3 as (0 x8000 0004-0x8000 0000) +0x8200 0000=0 x8200 0004. Accordingly, the VAMU writes the mapping logic corresponding to the change contents into 0x8100 0004 and 0x8200 0004, respectively, thereby completing the synchronous update of the slave page table 2 and the slave page table 3.
As can be seen from the above example, since the master page table is the same as the target slave page table in page size, the master page table is updated once, and the target slave page table follows the write-once updated contents. As for the specific content written in each write operation, the specific page table format of the master page table and the target slave page table is determined.
Based on the above, in some application scenarios, when the page table format of the master page table is the same as that of the target slave page table, the VAMU directly writes the change content obtained from the master page table into the target address of the target slave page table without performing format conversion; in other application scenarios, when the page table format of the master page table is different from that of the target slave page table, for example, the master page table is a first page table format based on the ARMv8 architecture, and the target slave page table is a second page table format based on the AMD64 architecture. The VAMU is required to convert the change content from the first page table format of the homepage table to the second page table format of the target slave page table, and then write the change content after the conversion format into the target address of the target slave page table.
To achieve the above effect, in the present disclosure, the page table format of each page table is stored in the memory in advance, and the VAMU can read the page table format of each page table through the on-chip bus system. In addition, in the present disclosure, by pre-configuring the page table format parsing rules and page table format conversion rules of each page table within the VAMU, the VAMU is provided with the ability to parse various types of page table formats, as well as the ability to convert the page table of a first page table format into a page table of a second page table format.
For the case that the page size of the master page table is different from the page size of the target slave page table, if the page size of the master page table is smaller than the page size of the target slave page table, the system cannot be used. If the page size of the master page table is larger than that of the target slave page table and the master page table and the target slave page table are in N (N is a positive integer) times relation, the master page table updates a mapping relation, and the target slave page table updates N mapping relations. Based on the above, the VAMU can make a difference between the change address and the initial address of the target slave page table where the address range to be monitored is located, so as to obtain a first difference value; then, multiplying the first difference value with N to obtain a first product value; then summing the first product value and a to-be-synchronized initial offset address of a target slave page table to obtain a first sum value; the first sum is then incremented in steps N-1 times, each increment being in steps holding a memory space occupied by the slave page table, thereby obtaining N addresses, the N addresses being target addresses. Accordingly, when writing the change content to the target address, the change content needs to be written to N addresses N times.
The size of the memory space occupied by each slave page table is determined by the specific system of the slave page table, for example, the memory space of 4 bytes (byte) memory is occupied by each slave page table for a 32-bit (bit) system, and the memory space of 8 bytes memory is occupied by each page table for a 34-bit system.
Continuing with the assumption that the target address range of the homepage table is 0x8000 0000-0 x8000 8000, the address range to be monitored of the slave page table 2 is 0x8000 0000-0 x8000 8000, the initial offset address to be synchronized of the slave page table 2 is 0x8100 0000, the address range to be monitored of the slave page table 4 is 0x 8000-0 x8000, the initial offset address to be synchronized of the slave page table 4 is 0x8300 0000, if a change causes a change of the homepage table stored in the 0x8000, the VAMU acquires the change address 0x80004000, and then the slave page table 2 and the slave page table 4 are both determined as the target slave page tables of the change.
Assuming that the page sizes of the master page table and the slave page table 2 are the same, the page size of the slave page table 4 is 1K. In this case, the VAMU calculates the target address from page table 2 as: (0x8000 4000-0x8000 0000) +0x8100 0000=0x8100 4000, and the VAMU writes the mapping logic corresponding to the change content into the 0x8100 4000, thereby completing the synchronous update from the page table 2.
The VAMU calculates the target address from page table 4 as:
(0x8000 4000-0x8000 4000)*(4/1)+0x8300 0000＝0x8300 0000；
0x8300 0000+0x0000 0004＝0x8300 0004；
0x8300 0004+0x0000 0004＝0x8300 0008；
0x8300 0008+0x0000 0004＝0x8300 0008c。
accordingly, the VAMU writes the mapping logic corresponding to the change content to the positions 0x8300 0000, 0x8300 0004, 0x8300 0008 and 0x8300 000c respectively 4 times to complete the synchronous update from the page table 4.
As can be seen from the above example, since the page size of the master page table is larger than that of the target slave page table and is N times the relationship, the master page table is updated once, and the target slave page table follows writing N times. As for the specific contents written in each writing operation, similar to the above, the specific page table format of the main page table and the target slave page table is determined, and will not be described here.
According to the page table management method provided by the disclosure, after the main page table is determined and the main page table stored in the target address range is changed, other slave page tables related to the changed content can also be automatically updated along with the main page table, and the main page table and the slave page table are automatically maintained to maintain the same mapping logic.
In addition, the embodiment of the disclosure further provides a virtual address management unit VAMU, where the VAMU includes a component capable of executing a software program, so that the VAMU may be used to execute the page table management method provided in any embodiment.
In some embodiments, the VAMU may be configured to have two states, namely an enabled state and a disabled state, and the VAMU is configured to perform the page table management method provided in any of the above embodiments only when determining that the VAMU is in the enabled state.
In addition, the embodiment of the disclosure further provides an SOC, where the SOC includes the virtual address management unit VAMU, the on-chip bus network, the memory, and a plurality of IP cores, such as the CPU Core, the GPU Core (Graphics Processing Unit Core, the graphics processor Core), the Video Core, the Microprocessor, and the like shown in fig. 3.
The VAMU is connected to each IP Core and the memory via an on-chip bus network, and Page tables (Page tables) of each IP Core are stored in the memory.
Of course, the configuration shown in FIG. 3 is illustrative only, and it is understood that the SOC may include more or fewer components in different use scenarios.
Wherein, the page table of any one IP Core in all IP cores included in the SOC is configured as a homepage table, and the page tables of other IP cores are selectively configured as slave page tables according to actual requirements.
In some usage scenarios, any of the IP cores may be a CPU Core, i.e. the page table corresponding to the CPU Core in the SOC may be configured as the main page table. Of course, in other usage scenarios, the page table corresponding to the GPU Core included in the SOC may be configured as the main page table.
It is worth noting that the target address ranges mentioned in the various embodiments of the present disclosure refer to address ranges that are address sequential. The address ranges of the respective slave page tables that need to maintain the synchronization mapping logic with the master page table are also configured to be continuous in view of the system stability and maintainability of the SOC, and accordingly, the SOC typically has one target address range and a corresponding VAMU.
In some application scenarios, it is also possible for the SOC to have multiple target address ranges for the same home page table, each target address range for storing different contents of the main page table, and the multiple target address ranges are not consecutive to each other. For example, the address range occupied by the entire home page table in the memory is 0x8000 0000 to 0x8000 9000, and a first target address range and a second target address range are provided for the home page table. Wherein the first target address range is 0x8000 0000-0 x8000 1000, and the second target address range is 0x8000 3000-0 x8000 8000.
In order to facilitate address management in this case, in some embodiments, a plurality of independent VAMUs may be provided in the SOC, and the VAMUs are in one-to-one correspondence with the target address ranges, so that each of the VAMUs manages the target address ranges corresponding to itself, and when it is determined that there is a change in the home page table stored in the target address range corresponding to itself, the page table management method provided in any of the above embodiments is performed.
In addition, the embodiment of the disclosure also provides an electronic device, which comprises the SOC and other necessary components. In some use scenarios, the product form of the electronic device is a portable electronic device, such as a smart phone, a tablet computer, a VR device, etc.; in some use cases, the electronic device is in the form of a personal computer, game console, workstation, server, etc.
In addition, the embodiment of the present disclosure further provides a computer readable storage medium, on which a virtual address management program is stored, where the virtual address management program, when executed, may implement the page table management method provided in any one of the possible implementations. For specific implementation, reference may be made to the above method embodiments, and details are not repeated here.
In some usage scenarios, the computer readable storage medium may be a memory, an optical disc, a mechanical hard disc, a solid state hard disc, a cloud storage medium, or other suitable readable storage medium.
Based on the virtual address management scheme, after the main page table is determined and the main page table stored in the target address range is changed, other slave page tables related to the changed content can also be automatically updated along with the main page table, and the main page table and the slave page table are automatically maintained to maintain the same mapping logic.
While the preferred embodiments of the present disclosure have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the disclosure.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present disclosure without departing from the spirit or scope of the disclosure. Thus, the present disclosure is intended to include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
It will be appreciated by those skilled in the art that embodiments of the present disclosure may be provided as a method, system, or computer program product. Accordingly, the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present disclosure may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
The present disclosure is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
Finally, it should be noted that the foregoing embodiments are merely for illustrating the technical solution of the present disclosure and not for limiting the scope of protection thereof, and although the present disclosure has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that various changes, modifications or equivalents may be made to the specific embodiments of the invention after reading the present disclosure, and these changes, modifications or equivalents are within the scope of protection of the claims appended hereto.
Claims (15)
1. A method of page table management, the method comprising:
when the homepage table stored in the target address range is confirmed to be changed, obtaining the changing content of the main page table and the changing address of the main page table;
determining a target slave page table with synchronous updating relation with the changing content according to the changing address and the read master-slave page table address mapping information which corresponds to each slave page table one by one;
and updating the target slave page table according to the master-slave page table address mapping information of the target slave page table, the page size of the homepage table, the page size of the target slave page table, the change address and the change content.
2. The method of claim 1, the master-slave page table address mapping information comprising a corresponding slave page table to-be-monitored address range, the target address range being a union of all slave page table to-be-monitored address ranges; the determining, according to the changed address and the read address mapping information of the master-slave page table corresponding to each slave page table, a target slave page table having a synchronous update relationship with the changed content includes:
determining a target address range to be monitored containing the changed address from the address range to be monitored contained in the address mapping information of each master-slave page table; and the slave page table corresponding to the master-slave page table address mapping information of the target to-be-monitored address range is the target slave page table.
3. The method of claim 2, wherein there is an intersection of each of the ranges of addresses to be monitored from the page table.
4. The method of claim 1, the master-slave page table address mapping information comprising a corresponding slave page table to-be-monitored address range and a to-be-synchronized start offset address, the target address range being a union of all slave page table to-be-monitored address ranges; the updating the target slave page table according to the master-slave page table address mapping information of the target slave page table, the page size of the homepage table, the page size of the target slave page table, the change address and the change content comprises the following steps:
determining a target address for storing the change content from an address range for storing the target slave page table according to the change address, a starting address of the target slave page table where the address range to be monitored is located, a starting offset address of the target slave page table to be synchronized, a page size of the master page table and a page size of the target slave page table;
writing the change content to the target address.
5. The method of claim 4, the master page table being in a different page table format than the target slave page table, the writing the change content at the target address comprising:
After the change content is converted into the page table format of the target slave page table, writing the change content after the conversion format into the target address.
6. The method of claim 4 or 5, the determining the target address for saving the change content from the address range for saving the target slave page table based on the change address, the start address where the target slave page table is to be monitored address range, the target slave page table is to be synchronized start offset address, the page size of the master page table, and the page size of the target slave page table, comprising:
when the page size of the master page table is determined to be consistent with the page size of the target slave page table, the change address is differenced from the starting address of the target slave page table where the address range to be monitored is located, and a first difference value is obtained;
and summing the first difference value and the target slave page table to-be-synchronized initial offset address to obtain a first sum value, wherein the first sum value is the target address.
7. The method of claim 4 or 5, the determining the target address for saving the change content from the address range for saving the target slave page table based on the change address, the start address where the target slave page table is to be monitored address range, the target slave page table is to be synchronized start offset address, the page size of the master page table, and the page size of the target slave page table, comprising:
When the page size of the master page table is determined to be larger than the page size of the target slave page table and is in N times relation with the page size of the target slave page table, the change address is differenced from the initial address of the target slave page table where the address range to be monitored is located, a first difference value is obtained, and N is a positive integer;
multiplying the first difference value with N to obtain a first product value;
summing the first product value and the target slave page table to-be-synchronized initial offset address to obtain a first sum value;
the first sum value is increased by steps for N-1 times, the step length is the storage space occupied by one page table, N addresses are obtained, and the N addresses are the target addresses;
correspondingly, the writing the change content to the target address includes:
the modified content is written N times to the N addresses.
8. The method of claim 1, the method further comprising:
monitoring the target address range, and determining that a homepage table stored in the target address range has a change when the condition that the read and/or write operation is performed on the address in the target address range is detected; or alternatively, the process may be performed,
determining that a homepage table stored in the target address range has a change when trigger information for representing a read and/or write operation for an address in the target address range is received; the trigger information is sent by a functional module that uses the main page table.
9. A virtual address management unit for performing the page table management method of any of claims 1-8.
10. The virtual address management unit of claim 9, configured to perform the page table management method of any of claims 1-8 upon determining that itself is in an enabled state.
11. An SOC comprising the virtual address management unit of claim 9 or 10, an on-chip bus network, a memory, and a plurality of IP cores, the virtual address management unit being connected to the plurality of IP cores and the memory through the on-chip bus network, page tables of the IP cores being held in the memory, page tables of any one of the plurality of IP cores being configured as a homepage table, page tables of other IP cores being configured as slave page tables.
12. The SOC of claim 11, there being a plurality of target address ranges and discontinuities between the plurality of target address ranges, each target address range for holding a different content of the home page table; the SOC comprises a plurality of virtual address management units, and the virtual address management units are in one-to-one correspondence with the target address ranges;
Each of the virtual address management units is configured to perform the page table management method of any one of claims 1 to 8 for a target address range corresponding to itself.
13. An SOC according to claim 11 or 12, said any IP Core being a CPU Core.
14. An electronic device comprising the SOC of any of claims 11-13.
15. A computer readable storage medium having stored thereon a virtual address management program which when executed implements the page table management method of any of claims 1-8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210174707.9A CN116701248B (en) | 2022-02-24 | 2022-02-24 | Page table management method, unit, SOC, electronic device and readable storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210174707.9A CN116701248B (en) | 2022-02-24 | 2022-02-24 | Page table management method, unit, SOC, electronic device and readable storage medium |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116701248A true CN116701248A (en) | 2023-09-05 |
| CN116701248B CN116701248B (en) | 2024-04-30 |
Family
ID=87831710
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210174707.9A Active CN116701248B (en) | 2022-02-24 | 2022-02-24 | Page table management method, unit, SOC, electronic device and readable storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116701248B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117851290A (en) * | 2024-03-07 | 2024-04-09 | 北京象帝先计算技术有限公司 | Page table management method, system, electronic component and electronic device |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102819494A (en) * | 2012-07-18 | 2012-12-12 | 山东华芯半导体有限公司 | Optimization method for writing in flash memory in sequence |
| CN109739613A (en) * | 2018-11-22 | 2019-05-10 | 海光信息技术有限公司 | Maintaining method, access control method and the relevant apparatus of nested page table |
| CN110196757A (en) * | 2019-05-31 | 2019-09-03 | 龙芯中科技术有限公司 | TLB filling method, device and the storage medium of virtual machine |
| CN110209603A (en) * | 2019-05-31 | 2019-09-06 | 龙芯中科技术有限公司 | Address conversion method, device, equipment and computer readable storage medium |
| CN111949572A (en) * | 2020-08-24 | 2020-11-17 | 海光信息技术有限公司 | Page table entry merging method and device and electronic equipment |
| CN112328354A (en) * | 2019-08-05 | 2021-02-05 | 阿里巴巴集团控股有限公司 | Virtual machine live migration method and device, electronic equipment and computer storage medium |
| CN112445767A (en) * | 2020-11-30 | 2021-03-05 | 平安科技（深圳）有限公司 | Memory management method and device, electronic equipment and storage medium |
| GB202103329D0 (en) * | 2021-03-10 | 2021-04-21 | Imagination Tech Ltd | A computer system and method using a first page table and a second page table |
-
2022
- 2022-02-24 CN CN202210174707.9A patent/CN116701248B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102819494A (en) * | 2012-07-18 | 2012-12-12 | 山东华芯半导体有限公司 | Optimization method for writing in flash memory in sequence |
| CN109739613A (en) * | 2018-11-22 | 2019-05-10 | 海光信息技术有限公司 | Maintaining method, access control method and the relevant apparatus of nested page table |
| CN110196757A (en) * | 2019-05-31 | 2019-09-03 | 龙芯中科技术有限公司 | TLB filling method, device and the storage medium of virtual machine |
| CN110209603A (en) * | 2019-05-31 | 2019-09-06 | 龙芯中科技术有限公司 | Address conversion method, device, equipment and computer readable storage medium |
| CN112328354A (en) * | 2019-08-05 | 2021-02-05 | 阿里巴巴集团控股有限公司 | Virtual machine live migration method and device, electronic equipment and computer storage medium |
| CN111949572A (en) * | 2020-08-24 | 2020-11-17 | 海光信息技术有限公司 | Page table entry merging method and device and electronic equipment |
| CN112445767A (en) * | 2020-11-30 | 2021-03-05 | 平安科技（深圳）有限公司 | Memory management method and device, electronic equipment and storage medium |
| GB202103329D0 (en) * | 2021-03-10 | 2021-04-21 | Imagination Tech Ltd | A computer system and method using a first page table and a second page table |
Non-Patent Citations (3)
| Title |
|---|
| WANG, TIANZHENG等: "Towards Write-Activity-Aware Page Table Management for Non-volatile Main Memories", 《ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS》, 31 March 2015 (2015-03-31) * |
| 章美仁;: "页置换技术在搜索引擎采集器中的应用", 计算机工程与设计, no. 05, 16 March 2009 (2009-03-16) * |
| 陈咸彰: "面向非易失性内存的文件系统与页面交换机制研究", 《中国博士学位论文全文数据库信息科技辑》, 15 June 2018 (2018-06-15) * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117851290A (en) * | 2024-03-07 | 2024-04-09 | 北京象帝先计算技术有限公司 | Page table management method, system, electronic component and electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116701248B (en) | 2024-04-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10210120B2 (en) | Method, apparatus and system to implement secondary bus functionality via a reconfigurable virtual switch | |
| US10496676B2 (en) | Synchronization cache seeding | |
| US8615614B2 (en) | Message passing using direct memory access unit in a data processing system | |
| US7827343B2 (en) | Method and apparatus for providing accelerator support in a bus protocol | |
| JP6975095B2 (en) | Data storage and processing systems that perform machine learning and how they operate | |
| CN110119304B (en) | Interrupt processing method and device and server | |
| CN116701248B (en) | Page table management method, unit, SOC, electronic device and readable storage medium | |
| CN112163038A (en) | Cross-cluster data synchronization method, device, equipment and storage medium | |
| WO2013075501A1 (en) | Method and device for hot-plugging a node | |
| JP2020194522A (en) | Method, apparatus, device, and medium for processing data | |
| CN114840339A (en) | GPU server, data calculation method and electronic equipment | |
| WO2014190700A1 (en) | Method of memory access, buffer scheduler and memory module | |
| CN111163060B (en) | Application group-based forwarding method, device and system | |
| US20180048732A1 (en) | Techniques for storing or accessing a key-value item | |
| US20080281576A1 (en) | Interface board, simulator, synchronization method, and synchronization program | |
| US20090133010A1 (en) | Virtualized blade flash with management module | |
| CN106484375B (en) | Instruction block loading method, soft switch equipment and system | |
| CN109656674B (en) | Computer equipment, virtualization chip and data transmission method | |
| CN112910910B (en) | Method, device, equipment and storage medium for processing OPCDA protocol message | |
| WO2015035891A1 (en) | Patching method, device, and system | |
| CN112052040A (en) | Processing method, processing device, computer equipment and storage medium | |
| CN113076069A (en) | Double-cache method and device, electronic equipment and computer readable storage medium | |
| CN113630300A (en) | Method and node for message transmission | |
| JP2020113256A (en) | Memory system and data processing system | |
| US20240064202A1 (en) | Methods and apparatus to synchronize touch events |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |