CN117833922A - High-precision multi-gear automatic switching readout circuit - Google Patents
High-precision multi-gear automatic switching readout circuit Download PDFInfo
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- H—ELECTRICITY
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- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
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Abstract
The application provides a high accuracy multispeed automatic switch-over readout circuit, readout circuit includes: the device comprises a photosensitive device, a capacitance feedback transimpedance amplifier circuit, a logic control feedback circuit, a correlated double sampling circuit and an analog-to-digital conversion circuit; the output of the photosensitive device is connected with the input end of the capacitive feedback transimpedance amplifier circuit; the input end of the capacitive feedback transimpedance amplifier circuit is connected with the output end of the photosensitive device and the output end of the logic control circuit, and the output end of the capacitive feedback transimpedance amplifier circuit is connected with the input ends of the related double sampling circuit and the logic control feedback circuit; the input end of the logic control feedback circuit is connected with the output end of the capacitor feedback transimpedance amplifier circuit, the output end of the analog-to-digital conversion and the reference voltage; the input end of the sampling circuit is connected with the output end of the capacitance feedback transimpedance amplifier circuit; the input end of the analog-to-digital conversion circuit is connected with the output end of the sampling circuit. The accuracy of the output voltage corresponding to the original input current is improved.
Description
Technical Field
The application relates to the technical field of integrated circuits, in particular to a high-precision multi-gear automatic switching readout circuit.
Background
The photosensitive device is a device for converting an incident radiation signal into an electrical signal and outputting the electrical signal, and for electromagnetic wave radiation inconvenient to measure, the electromagnetic wave radiation needs to be converted into a tiny electrical signal through the photosensitive device, and then the electrical signal which can be perceived and measured is obtained through a series of processes of a reading circuit. The technology is widely applied to medical diagnosis, fire monitoring, public security investigation and the like.
In the prior art, a readout circuit is generally used to sense a minute photocurrent signal generated by the photosensitive device based on the radiation signal. As shown in fig. 1, the circuit is a topology circuit diagram of a conventional multi-gear automatic switching readout circuit. The capacitive feedback transimpedance amplifier (Capacitive feedbacktransimpedance amplifier, CTIA) circuit comprises an operational amplifier (AV 1), a gear switch, a reset switch and a transconductance capacitor, wherein the micro photocurrent is turned off through the gear switch, is integrated and converted into voltage by the transconductance capacitor, and is finally output at an operational amplifier output end; the sampling circuit is composed of a transmission gate switch, an integrating capacitor and an output buffer, and sampling is completed.
However, in practical applications, the inventors of the present application found that: when the reset switch is turned off, i.e. in the integration stage, the multi-gear automatic switching readout circuit shown in fig. 1 is theoretically turned off, and in fact, as a voltage difference exists between two ends of the integral reset switch, the multi-gear automatic switching readout circuit plays a role of a capacitor, so that part of integral current can be separated, and the perceived voltage is inaccurate, so that the linearity of the circuit is deteriorated; when the sampling clock frequency is increased to a certain degree, the equivalent resistance change of the transmission gate switch can not be ignored any more, so that the sampling signal has certain distortion; and the circuit has low resolution of the subsequent analog-digital conversion due to low differentiation of the integral voltage under the condition of low current due to large second-gear integral capacitance, so that the reading accuracy is low.
Disclosure of Invention
The application provides a high-precision multi-gear automatic switching and reading circuit which can be used for solving the technical problem that the sensing voltage of the multi-gear automatic switching and reading circuit is inaccurate when the gear is switched.
The application provides a high accuracy multispeed automatic switch-over readout circuit, readout circuit includes:
the device comprises a photosensitive device, a capacitance feedback transimpedance amplifier circuit, a logic control feedback circuit, a correlated double sampling circuit and an analog-to-digital conversion circuit;
the output of the photosensitive device is connected with the input end of the capacitive feedback transimpedance amplifier circuit;
the input end of the capacitive feedback transimpedance amplifier circuit is connected with the output end of the photosensitive device and the output end of the logic control circuit, and the output end of the capacitive feedback transimpedance amplifier circuit is connected with the input ends of the related double sampling circuit and the logic control feedback circuit; the pins of the output end of the logic control circuit comprise S 0 、S 1 、S 2 、S 3 、S 4 、……S n ；
The input end of the logic control feedback circuit is connected with the output end of the capacitance feedback transimpedance amplifier circuit, the output end of the analog-digital conversion and the reference voltage (V) LTH 、V HTH )；
The input end of the sampling circuit is connected with the output end of the capacitive feedback transimpedance amplifier circuit;
the input end of the analog-to-digital conversion circuit is connected with the output end of the sampling circuit.
Further, the capacitive feedback transimpedance amplifier comprises an operational amplifier AV1 and a reset switch phi int N gating switches, n integrating capacitors, wherein the positive input of the operational amplifier is connected with the reference voltage V REF The negative input end is connected with the left sides of the gating switch and the resetting switch, the right sides of the gating switch are respectively connected with the left ends of the integrating capacitors one by one, and finally the right ends of the integrating capacitors and the resetting switch are connected with the output end of the operational amplifier;
wherein the gating switches are S respectively 0 、S 1 、S 2 、S 3 、S 4 、……S n The method comprises the steps of carrying out a first treatment on the surface of the The integral capacitance is C respectively int0 、C int1 、C int2 、C int3 、C int4 、……C intn 。
Further, the input end of the logic control circuit is respectively connected with the output end of the ADC and the first threshold reference voltage V HTH Second threshold reference voltage V LTH Are connected; the output end is connected with the gating switch and controls the on and off of the gating switch.
Further, the correlated double sampling circuit comprises a bootstrap switch and a first sampling capacitor C 1 A second sampling capacitor C 2 An output buffer AV2 in which a first sampling capacitor C 1 One end of the second sampling capacitor C is connected with the output end of the bootstrap switch, the other end is connected with the ground end 2 One end of the output buffer is connected with the output end of the bootstrap switch, the other end of the output buffer is connected with the positive input end of the output buffer, and the negative input end of the output buffer is connected with the output end.
Further, the input end of the analog-to-digital conversion circuit is connected with the output end V of the sampling circuit OUT Reference voltage V REF1 And the clock clk signal, and the output end is connected to the input end of the logic control circuit.
Further, the final integrated capacitance of the capacitive feedback transimpedance amplifier circuit is determined by the following method:
the capacitance combination forms larger integration capacitance with more different values by different on-off combinations of the gating switch, and the value of the original integration capacitance is set as C int0 ＝k 0 C，C int1 ＝k 1 C，C int2 ＝k 2 C，C int3 ＝k 3 C，C int4 ＝k 4 C，……C intn ＝k n C, therein C, k 0 、k 1 、k 2 、……k n According to the integral voltage formulaApplication requirements.
Further, the logic control feedback circuit operates in the following manner:
the logic module first sets the circuit in an intermediate gear,
according to pair ADC output, integrated voltage and threshold reference voltage V HTH 、V LTH And judging the comparison result to obtain whether the integration capacitance is larger or smaller than the current at the moment, and then controlling the on and off of the gating switch according to the successive approximation of the integration capacitance.
According to the high-precision multi-gear automatic switching readout circuit, the voltage difference eliminating structure is added at the reset switch, so that when the reset switch is disconnected, no voltage difference exists between two ends, no capacitance is formed, no integral current is divided, the bootstrap switch is used for the sampling switch, and the CDS technology is adopted, so that the noise of the circuit is greatly reduced, and the linearity of an output signal is improved; the original integrating capacitor is split on the basis of not increasing the area of the integrating capacitor, and one gear is split into a plurality of gears to work, so that the range of output voltage corresponding to the original input current is enlarged, the subsequent analog-digital processing is facilitated, and the final reading precision is improved; in the logic control module, the automatic switching of the gear from the middle to the two sides is realized by combining the sampling result of the ADC circuit and the reference voltage comparison, so that the reading efficiency is improved.
Drawings
FIG. 1 is a block diagram of a prior art multi-gear automatic switching readout circuit;
FIG. 2 is a block diagram of a typical high-precision multi-gear automatic switching readout circuit provided by embodiments of the present application;
fig. 3 is a block diagram of a bootstrap PMOS switch according to an embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
Embodiments of the present application will now be described with reference to the accompanying drawings.
The application provides a high accuracy multispeed automatic switch-over readout circuit, readout circuit includes:
a photosensitive device, a capacitive feedback transimpedance amplifier (Capacitive feedbacktransimpedance amplifier, CTIA) circuit, a logic control feedback circuit, a correlated double sampling (Correlated double sampling, CDS) circuit, an analog-to-digital conversion (Analog to digital converter, ADC) circuit;
the output of the photosensitive device is connected with the input end of the capacitive feedback transimpedance amplifier circuit;
the input end of the capacitive feedback transimpedance amplifier circuit is connected with the output end of the photosensitive device and the output end of the logic control circuit, and the output end of the capacitive feedback transimpedance amplifier circuit is connected with the input ends of the related double sampling circuit and the logic control feedback circuit; the pins of the output end of the logic control circuit comprise S 0 、S 1 、S 2 、S 3 、S 4 、……S n ；
The input end of the logic control feedback circuit is connected with the output end of the capacitance feedback transimpedance amplifier circuit, the output end of the analog-digital conversion and the reference voltage (V) LTH 、V HTH )；
The input end of the sampling circuit is connected with the output end of the capacitive feedback transimpedance amplifier circuit;
the input end of the analog-to-digital conversion circuit is connected with the output end of the sampling circuit.
Further, the capacitive feedback transimpedance amplifier comprises an operational amplifier AV1 and a reset switch phi int N gating switches (S) 0 、S 1 、S 2 、S 3 、S 4 、……S n ) N integration capacitors (C int0 、C int1 、C int2 、C int3 、C int4 、……C intn ) Wherein the positive input end of the operational amplifier is connected with the reference voltage V REF The negative input end is connected with the left side of the gating switch and the reset switch, and the gating switch (S 0 、S 1 、S 2 、S 3 、S 4 、……S n ) Respectively and to the right of the integrating capacitor (C) int0 、C int1 、C int2 、C int3 、C int4 、……C intn ) The left ends of the integrating capacitors and the right ends of the reset switches are connected with the output ends of the operational amplifiers one by one;
wherein the gating switches are S respectively 0 、S 1 、S 2 、S 3 、S 4 、……S n The method comprises the steps of carrying out a first treatment on the surface of the The integral capacitance is C respectively int0 、C int1 、C int2 、C int3 、C int4 、……C intn 。
Further, the input end of the logic control circuit is respectively connected with the output end of the ADC and the first threshold reference voltage V HTH Second threshold reference voltage V LTH Are connected; output terminal and gating switch (S) 0 、S 1 、S 2 、S 3 、S 4 、……S n ) And the switch is connected with the control gate switch.
Further, the correlated double sampling circuit comprises a bootstrap switch and a first sampling capacitor C 1 A second sampling capacitor C 2 An output buffer AV2 in which a first sampling capacitor C 1 One end of the second sampling capacitor C is connected with the output end of the bootstrap switch, the other end is connected with the ground end 2 One end of the output buffer is connected with the output end of the bootstrap switch, the other end of the output buffer is connected with the positive input end of the output buffer, and the negative input end of the output buffer is connected with the output end.
Further, the input end of the analog-to-digital conversion circuit is connected with the output end V of the sampling circuit OUT Reference voltage V REF1 And the clock clk signal, and the output end is connected to the input end of the logic control circuit.
Further, the final integrated capacitance of the capacitive feedback transimpedance amplifier circuit is determined by the following method:
by gating a switch (S) 0 、S 1 、S 2 、S 3 、S 4 、……S n ) Different on-off combinations, so that the smaller integrating capacitance (C int0 、C int1 、C int2 、C int3 、C int4 、……C intn ) Combining to form larger integral capacitance with more different values, and the value of the original integral capacitance is set as C int0 ＝k 0 C，C int1 ＝k 1 C，C int2 ＝k 2 C，C int3 ＝k 3 C，C int4 ＝k 4 C，……C intn ＝k n C, therein C, k 0 、k 1 、k 2 、……k n According to the integral voltage formulaAnd the application requirement is determined, so that the integration voltage precision can be improved while the area of the integration capacitor is not increased.
Further, the logic control feedback circuit operates in the following manner:
the logic module first sets the circuit in an intermediate gear,
according to the output of ADC and the integrated voltage and threshold reference voltage V HTH 、V LTH And judging the comparison result to obtain whether the integration capacitor is larger or smaller than the current at the moment, and then controlling the on and off of the gating switch according to the successive approximation of the integration capacitor so as to realize gear matching more quickly.
The invention will now be described by way of example with reference to the accompanying drawings.
In the structure shown in fig. 1, when the reset voltage is disconnected, the voltage difference exists between two ends of the reset switch due to the integral action, so that the reset switch plays a role of a capacitor, and partial integral current is divided, which is equivalent to noise introduction; when the sampling circuit is switched by a transmission gate and the time frequency becomes high, the equivalent resistance change of the transmission gate cannot be ignored, and the resistance change has an effect on the quality of the sampling signal; and by the formulaIt can be seen that when operating in the second gear, the integration capacitance is 7pF, so that when the I change is small +.>The change in (c) is also small, which is detrimental to the subsequent processing of the analog-to-digital conversion, so that the final read-out accuracy is limited.
In view of this, the embodiment of the invention designs a structure for eliminating the voltage difference between two ends of the reset switch when the reset switch is disconnected, and electric leakage is avoided during integration; the transmission gate is replaced by a PMOS bootstrap switch, so that the influence of the capacitive division and integration current taking when the reset switch is disconnected is reduced, the equivalent impedance of the bootstrap switch is stable when sampling is performed, and the influence on the sampling quality is reduced; the second gear is split into seven gears, so that when the current change of the circuit in the second gear is small, the range change of the output voltage is large, the subsequent analog processing is facilitated, and the final reading precision is improved.
Specifically, as shown in fig. 2, a single MOS transistor reset switch is changed into two MOS transistor switches connected in series, and a MOS transistor switch connection V which is always turned on is added in the middle REF When the reset tube is disconnected, the two ends have no voltage difference, so that no electric leakage is formed; as shown in fig. 3, a schematic diagram of a PMOS bootstrap switch, switch M during operation 4 The gate-source voltage of the tube is always kept constant; according to the formulaThe resistor is kept constant, and the sampling quality is not affected when the sampling frequency is higher; as shown in fig. 2, the sampling technique adopts a correlated double sampling (Correlateddouble sampling, CDS) technique, and the final sampled voltage is V 1 -V 2 Noise errors among periods are reduced, and linearity is improved; the original integrating capacitance is shown as C in figure 2 int2 (7 pF) decomposition into C as in FIG. 2 int1 (1pF)、C int2 (1pF)、C int3 (1pF)、C int4 (1pF)、C int5 (1pF)、C int6 (1pF)、C int7 (1 pF), wherein the capacitance C int0 =1 pF, i.e.)>Then the integration capacitor C can be obtained through the combination of the gating switches int ＝1pF、C int ＝2pF、C int ＝3pF、C int ＝4pF、C int ＝5pF、C int ＝6pF、C int ＝7pF、C int =8pf, subdividing the gear without increasing the area of capacitance generation, according to the formulaIt is understood that, when the current I is equally inputted,integrating capacitor C int Becomes smaller, output voltage V OUT The range is enlarged, so that the accuracy of the subsequent analog-digital conversion is improved, and the accuracy of the final read signal is improved; in order not to reduce the reading efficiency of the circuit, a successive approximation idea is adopted to carry out self-adaptive switching of gears, when the circuit is started, the gears are positioned at the fourth gear, and then the output pulse control jumps to the second gear or the sixth gear by combining the comparison of the integral voltage and the upper and lower limit reference voltages and the sampling result of the ADC circuit, so that the successive approximation is carried out, and finally the proper gears are selected.
The high-precision multi-gear automatic switching readout circuit is characterized in that a single MOS tube reset switch is changed into two MOS tube switches connected in series, and a MOS tube switch which is always conducted is added in the middle of the single MOS tube reset switch to be connected with a V REF When the reset tube is disconnected, the two ends have no voltage difference, so that no electric leakage is formed; the transmission gate switch is replaced by a bootstrap switch, so that the equivalent resistance is relatively stable; the sampling circuit adopts CDS sampling measures, which is beneficial to reducing noise and improving the precision of output signals when the readout circuit works; splitting the integrating capacitor into C int0 ≤C int1 ≤C int2 ≤C int3 ≤C int4 ≤……≤C intn Wherein C int0 ＝k 0 C，C int1 ＝k 1 C，C int2 ＝k 2 C，C int3 ＝k 3 C，C int4 ＝k 4 C，……C intn ＝k n C. Through the logic circuit module, different combinations of the gating switches are controlled, and the integration capacitance has more values by utilizing the capacitance with small area, so that the reading accuracy is improved in a wide measuring range. On-off switch (S) 0 、S 1 、S 2 、S 3 、S 4 、……S n ) When any 1 switch is closed, the integral capacitance is k i C (i=0, 1,2,3,4 … … n); when any 2 switches are closed simultaneously, the integrating capacitance is: when any 3 switches are closed at the same time, the integrating capacitance is: /> When any 4 switches are closed at the same time, the integrating capacitance is:… … when n switches are closed simultaneously, the integrating capacitance is:
according to different gating switch combinations, the corresponding gear T is output, so that the reading accuracy is improved on the basis of not increasing the area of the integrating capacitor. The present patent combines but is not limited to the sampling result of the ADC and the reference voltage group to determine on the gear selection, and successively approximates the gear switch through the logic circuit, thereby finally switching to the most suitable gear.
In summary, the high-precision multi-gear automatic switching readout circuit of the invention adds a voltage difference elimination structure at the reset switch, so that when the reset switch is disconnected, no voltage difference exists between two ends, no capacitance is formed, no integral current is separated, the sampling switch is a bootstrap switch, and the CDS technology is adopted, thereby greatly reducing the noise of the circuit and improving the linearity of output signals; the original integrating capacitor is split on the basis of not increasing the area of the integrating capacitor, and one gear is split into a plurality of gears to work, so that the range of output voltage corresponding to the original input current is enlarged, the subsequent analog-digital processing is facilitated, and the final reading precision is improved; in the logic control module, the automatic switching of the gear from the middle to the two sides is realized by combining the sampling result of the ADC circuit and the reference voltage comparison, so that the reading efficiency is improved.
The above-described embodiments of the present application are not intended to limit the scope of the present application.
Claims (7)
1. A high-precision multi-gear automatic switching readout circuit, characterized in that the readout circuit comprises:
the device comprises a photosensitive device, a capacitance feedback transimpedance amplifier circuit, a logic control feedback circuit, a correlated double sampling circuit and an analog-to-digital conversion circuit;
the output of the photosensitive device is connected with the input end of the capacitive feedback transimpedance amplifier circuit;
the input end of the capacitive feedback transimpedance amplifier circuit is connected with the output end of the photosensitive device and the output end of the logic control circuit, and the output end of the capacitive feedback transimpedance amplifier circuit is connected with the input ends of the related double sampling circuit and the logic control feedback circuit; the pins of the output end of the logic control circuit comprise S 0 、S 1 、S 2 、S 3 、S 4 、……S n ；
The input end of the logic control feedback circuit is connected with the output end of the capacitor feedback transimpedance amplifier circuit, the output end of the analog-to-digital conversion and the reference voltage; the reference voltage includes V LTH 、V HTH ；
The input end of the sampling circuit is connected with the output end of the capacitive feedback transimpedance amplifier circuit;
the input end of the analog-to-digital conversion circuit is connected with the output end of the sampling circuit.
2. The readout circuit according to claim 1, wherein the capacitive feedback transimpedance amplifier comprises an operational amplifier AV1, a reset switch Φ int N gating switches, n integrating capacitors, wherein the positive input of the operational amplifier is connected with the reference voltage V REF The negative input end is connected with the left sides of the gating switch and the resetting switch, the right sides of the gating switch are respectively connected with the left ends of the integrating capacitors one by one, and finally the right ends of the integrating capacitors and the resetting switch are connected with the output end of the operational amplifier;
wherein the gating switches are S respectively 0 、S 1 、S 2 、S 3 、S 4 、……S n The method comprises the steps of carrying out a first treatment on the surface of the The integral capacitance is C respectively int0 、C int1 、C int2 、C int3 、C int4 、……C intn 。
3. The sensing circuit of claim 1, wherein the logic control circuit has an input coupled to the output of the ADC and the first threshold reference voltage V, respectively HTH Second threshold reference voltage V LTH Are connected; the output end is connected with the gating switch and controls the on and off of the gating switch.
4. The readout circuit according to claim 1, wherein the correlated double sampling circuit comprises a bootstrap switch, a first sampling capacitor C 1 A second sampling capacitor C 2 An output buffer AV2 in which a first sampling capacitor C 1 One end of the second sampling capacitor C is connected with the output end of the bootstrap switch, the other end is connected with the ground end 2 One end of the output buffer is connected with the output end of the bootstrap switch, the other end of the output buffer is connected with the positive input end of the output buffer, and the negative input end of the output buffer is connected with the output end.
5. The readout circuit according to claim 1, wherein the input of the analog-to-digital conversion circuit is connected to the output V of the sampling circuit OUT Reference voltage V REF1 And the clock clk signal, and the output end is connected to the input end of the logic control circuit.
6. The sensing circuit of claim 2, wherein the final integrated capacitance of the capacitive feedback transimpedance amplifier circuit is determined by:
the capacitance combination forms larger integration capacitance with more different values by different on-off combinations of the gating switch, and the value of the original integration capacitance is set as C int0 ＝k 0 C，C int1 ＝k 1 C，C int2 ＝k 2 C，C int3 ＝k 3 C，C int4 ＝k 4 C，……C intn ＝k n C, therein C, k 0 、k 1 、k 2 、……k n According to the integral voltage formulaApplication requirements.
7. A sensing circuit according to claim 3, wherein the logic control feedback circuit operates in the following manner:
the logic module first sets the circuit in an intermediate gear,
according to the output of ADC and the integrated voltage and threshold reference voltage V HTH 、V LTH And judging the comparison result to obtain whether the integration capacitance is larger or smaller than the current at the moment, and then controlling the on and off of the gating switch according to the successive approximation of the integration capacitance.
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| CN202410013281.8A CN117833922A (en) | 2024-01-04 | 2024-01-04 | High-precision multi-gear automatic switching readout circuit |
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| CN202410013281.8A CN117833922A (en) | 2024-01-04 | 2024-01-04 | High-precision multi-gear automatic switching readout circuit |
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