CN117833637B - Method and circuit for reducing frequency jitter of switch node - Google Patents
Method and circuit for reducing frequency jitter of switch node Download PDFInfo
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- CN117833637B CN117833637B CN202410201286.3A CN202410201286A CN117833637B CN 117833637 B CN117833637 B CN 117833637B CN 202410201286 A CN202410201286 A CN 202410201286A CN 117833637 B CN117833637 B CN 117833637B
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Abstract
The invention discloses a method and a circuit for reducing frequency jitter of a switching node, which belong to the technical field of electric energy conversion and comprise a voltage divider, an error amplifier, a voltage-current converter, a slope current injector, a voltage adder, a comparator and a trigger, wherein the input end of the voltage divider is connected with the output voltage of a conversion circuit, the output end of the voltage divider is connected with the negative input end of the error amplifier, the positive input end of the error amplifier is connected with a reference voltage, the output end of the error amplifier is connected with the input end of the voltage-current converter, the output end of the voltage-current converter is connected with the slope current injector and the voltage adder, the voltage adder is connected with the positive input end of the comparator, the negative input end of the comparator is connected with a first voltage, and the output end of the comparator is connected with the S end of the trigger. The invention can obviously reduce the frequency jitter of the switch node.
Description
Technical Field
The present invention relates to the field of power conversion technologies, and in particular, to a method and a circuit for reducing frequency jitter of a switching node.
Background
In the control of the BUCK conversion circuit, an ACOT valley current mode is generally adopted, that is, an adaptive constant on-time (ACOT) mode is adopted to determine the upper tube on-time T on of the BUCK conversion circuit, and a valley current mode is adopted to determine the upper tube off-time T off. Besides the advantage of quick response of the traditional constant conduction time mode, the self-adaptive constant conduction time mode can enable the switching frequency to be constant, so that inductance is convenient to select, and electromagnetic interference of a system is reduced. The valley current mode controls the closing time T off of the upper tube by detecting the magnitude of the lower tube current, when the load is heavy, the closing time T off of the upper tube ends when the inductance current is larger, namely the closing time T off of the upper tube is shorter, and the inductance current is increased; when the load is light, the upper tube closing time T off ends when the inductor current is small, i.e., the upper tube closing time T off is long, and the inductor current is reduced. However, since the change of the turn-on voltage of the lower tube is very small, the comparator is easily interfered, so that the upper tube and the lower tube connecting node, namely the switch node, generate jitter, as shown by the waveform in fig. 1, the switch node voltage is dithered somewhere, and the problem that the output ripple is enlarged, logic disorder is easily caused by larger jitter, and the like is solved. In addition, jitter phenomenon is more remarkable when the output voltage V OUT of the BUCK conversion circuit is smaller.
Disclosure of Invention
The invention aims to provide a method and a circuit for reducing frequency jitter of a switching node.
In order to achieve the above purpose, the technical scheme of the invention is as follows:
The circuit for reducing the frequency jitter of the switch node is applied to a conversion circuit, the circuit for reducing the frequency jitter of the switch node is connected with the conversion circuit and comprises a voltage divider, an error amplifier, a voltage-current converter, a slope current injector, a voltage adder, a comparator and a trigger, wherein the input end of the voltage divider is connected with the output voltage of the conversion circuit, the output end of the voltage divider is connected with the negative input end of the error amplifier, the positive input end of the error amplifier is connected with a reference voltage, the output end of the error amplifier is connected with the input end of the voltage-current converter, the output end of the voltage-current converter is connected with the slope current injector and the voltage adder, the voltage adder is connected with the positive input end of the comparator, the negative input end of the comparator is connected with a first voltage, and the output end of the comparator is connected with the S end of the trigger.
Further, the circuit for reducing frequency jitter of the switch node further comprises a conduction time controller, wherein the R end of the trigger is connected with the conduction time controller, and the conduction time controller generates the conduction ending time of the upper tube of the conversion circuit.
Further, the circuit for reducing the frequency jitter of the switch node further comprises a logic controller, a first driver and a second driver, wherein the Q end of the trigger is connected with the input end of the logic controller, the first output end of the logic controller is connected with the input end of the first driver, the output end of the first driver drives the first switch of the conversion circuit, the second output end of the logic controller is connected with the input end of the second driver, and the output end of the second driver drives the second switch of the conversion circuit.
In a specific embodiment, the ramp current injector includes a first operational amplifier, a second operational amplifier, a plurality of switches, a second capacitor, a first resistor, a second resistor, and a third driver, wherein a positive input terminal of the first operational amplifier is connected to an output voltage of the conversion circuit, an output terminal of the first operational amplifier is connected to a gate of the third switch, a source of the third switch is grounded through the first resistor, a negative input terminal of the first operational amplifier is connected to a source of the third switch, a first voltage is connected to a source of the fourth switch and a source of the fifth switch, a gate of the fourth switch is connected to a gate of the fifth switch, a drain of the fourth switch is connected to a gate of the seventh switch, a drain of the sixth switch is connected to a gate of the sixth switch, a source of the sixth switch is grounded, a drain of the seventh switch is connected to a drain of the eighth switch is connected to a positive input terminal of the eighth switch, a drain of the fourth switch is connected to a drain of the eighth switch, a drain of the eighth switch is connected to a drain of the eighth switch, the negative input end of the second operational amplifier is connected with the source electrode of the ninth switch, the source electrode of the ninth switch is grounded through the second resistor, the first voltage is connected with the source electrode of the tenth switch and the source electrode of the eleventh switch, the grid electrode of the tenth switch is connected with the grid electrode of the eleventh switch and the drain electrode of the tenth switch, and the drain electrode of the eleventh switch is connected with the output end of the voltage-current converter.
In a specific embodiment, the voltage divider includes a third resistor and a fourth resistor, a first end of the third resistor is connected to the output voltage of the conversion circuit, a second end of the third resistor is connected to the first end of the fourth resistor, a second end of the fourth resistor is grounded, and a first end of the fourth resistor is connected to the negative input end of the error amplifier.
In a specific embodiment, the voltage adder includes a fifth resistor, a first end of the fifth resistor is connected to the output end of the voltage-current converter, a second end of the fifth resistor is connected to a switch node voltage, and the switch node is a connection node of the first switch and the second switch.
In a specific embodiment, the first voltage is generated by a second current source and a sixth resistor, a first end of the sixth resistor is connected to the negative input end of the comparator, a first end of the sixth resistor is connected to the second current source, and a second end of the sixth resistor is grounded.
In a specific embodiment, the voltage-current converter includes a third operational amplifier, a seventh resistor and a plurality of switches, where an output end of the error amplifier is connected to a positive input end of the third operational amplifier, an output end of the third operational amplifier is connected to a gate of the twelfth switch, a negative input end of the third operational amplifier is connected to a source of the twelfth switch, the source of the twelfth switch is grounded through the seventh resistor, the first voltage is connected to the source of the thirteenth switch and the source of the fourteenth switch, a gate of the thirteenth switch is connected to a drain of the thirteenth switch and the gate of the fourteenth switch, a drain of the thirteenth switch is connected to a drain of the twelfth switch, and a drain of the fourteenth switch is an output end of the voltage-current converter.
In a specific embodiment, the circuit for reducing frequency jitter of a switch node further includes a filter, where the filter is connected between an output terminal of the error amplifier and ground.
The invention also provides a method for reducing the frequency jitter of the switch node, which is applied to the circuit for reducing the frequency jitter of the switch node, and comprises the following steps of,
Step S1, sampling the output voltage of a conversion circuit to obtain feedback voltage;
step S2, amplifying the difference value between the reference voltage and the feedback voltage to obtain a second voltage;
step S3, converting the second voltage into a second current with fixed proportion;
Step S4, when the second switch is turned on, the second current and the slope current are overlapped and then are overlapped on the switch node voltage to obtain a third voltage, when the third voltage is larger than the first voltage, the first switch of the driving conversion circuit is turned on, the second switch is turned off, and in the first switch on stage, the slope current is cleared; and after the conduction time of the first switch is over, the first switch is driven to be closed, and the second switch is driven to be conducted.
The method and the circuit for reducing the frequency jitter of the switch node have the beneficial effects that the frequency jitter of the switch node can be obviously reduced, and other designs and peripheral applications of the circuit are not affected.
In order to make the above features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1 is a waveform diagram of switching node jitter.
Fig. 2 is a schematic diagram of a circuit for reducing frequency jitter of a switching node according to an embodiment of the present invention.
FIG. 3 is a schematic diagram of an embodiment of the ramp injector of FIG. 2.
Fig. 4 is a schematic diagram of an embodiment of the voltage-to-current converter in fig. 2.
Fig. 5 (a) is a waveform diagram of frequency jitter of a switching node SW before a circuit for reducing frequency jitter of the switching node using the present invention.
Fig. 5 (b) is a waveform diagram of frequency jitter of the switch node SW after using a circuit for reducing frequency jitter of the switch node according to the present invention.
Fig. 6 is a flow chart of a method of reducing frequency jitter of a switching node according to the present invention.
Detailed Description
In order to make the purpose and technical solutions of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. It will be apparent that the described embodiments are some, but not all, embodiments of the invention. All other embodiments, which can be made by a person skilled in the art without creative efforts, based on the described embodiments of the present invention fall within the protection scope of the present invention.
Fig. 2 is a schematic diagram of a circuit for reducing frequency jitter of a switching node according to an embodiment of the present invention. As shown in fig. 2, the circuit 1 for reducing the frequency jitter of the switching node is connected with a BUCK conversion circuit 2. The circuit 1 for reducing the frequency jitter of the switch node comprises a voltage divider 11, an error amplifier 12, a voltage-current converter 13, a slope current injector 14, a voltage adder 15, a comparator 16, a conduction time controller 17, a trigger 18, a logic controller 19, a first driver 110 and a second driver 111, wherein the input end of the voltage divider 11 is connected with a voltage V OUT, the output end of the voltage divider 11 is connected with the negative input end of the error amplifier 12, the positive input end of the error amplifier 12 is connected with a reference voltage V REF, the output end of the error amplifier 12 is connected with the input end of the voltage-current converter 13, the output end of the voltage-current converter 13 is connected with the slope current injector 14 and the voltage adder 15, the voltage adder 15 is connected with the positive input end of the comparator 16, the negative input end of the comparator 16 is connected with a voltage V B, the output end of the comparator 16 is connected with the S end of the trigger 18, the R end of the trigger 18 is connected with the negative input end of the trigger 17, the output end of the first driver is connected with the Q end of the second driver 12, the output end of the Q driver is connected with the Q end of the Q driver 12, the Q driver is connected with the second driver is connected with the Q end of the Q driver 111, and the Q driver is connected with the Q end of the Q driver 111.
The BUCK conversion circuit 2 includes a switch Q 1, a switch Q 2, an inductor L 1 and a capacitor C 1, where a drain of the switch Q 1 is connected to a power supply V IN, a source of the switch Q 1 is connected to a drain of the switch Q 2 and is a node SW, a source of the switch Q 2 is grounded PGND, a drain of the switch Q 2 is connected to a first end of the inductor L 1, a second end of the inductor L 1 outputs a voltage V OUT, a second end of the inductor L 1 is grounded PGND through a capacitor C 1, and a voltage of the node SW is V SW. Wherein, switch Q 1 is the upper tube, switch Q 2 is the lower tube.
Fig. 3 shows a schematic diagram of an embodiment of the ramp injector 14 of fig. 2. As shown in fig. 3, the node SW is connected to the positive input of the operational amplifier A1 through a resistor R 9, the positive input of the operational amplifier A1 is grounded SGND through a capacitor C 4, the output of the operational amplifier A1 is connected to the gate of the switch Q 3, the source of the switch Q 3 is grounded SGND through a resistor R 1, the negative input of the operational amplifier A1 is connected to the source of the switch Q 3, the voltage Vcc is connected to the source of the switch Q 4, the gate of the switch Q 4 is connected to the gate of the switch Q 4, the gate of the switch Q 4 is connected to the drain of the switch Q 4, the drain of the switch Q 4 is connected to the gate of the switch Q 4, the source of the switch Q 4 is grounded SGND, the drain of the switch Q2 is connected to the source of the I2, the drain of the switch Q 4 is connected to the drain of the switch 4, the drain of the switch 4 is connected to the gate of the switch 4, and the drain of the switch 4 is connected to the gate of the capacitor of the switch 4. The drain electrode of the switch Q 8 is connected with the positive input end of the operational amplifier A2, the output end of the operational amplifier A2 is connected with the grid electrode of the switch Q 9, the negative input end of the operational amplifier A2 is connected with the source electrode of the switch Q 9, the source electrode of the switch Q 9 is grounded SGND through a resistor R 2, the voltage Vcc is connected with the source electrode of the switch Q 10 and the source electrode of the switch Q 11, the grid electrode of the switch Q 10 is connected with the grid electrode of the switch Q 11, the grid electrode of the switch Q 10 is connected with the drain electrode of the switch Q 9 and the drain electrode of the switch Q 10, and the drain electrode of the switch Q 11 outputs a slope current I RAMP.
More specifically, the switch Q 4 and the switch Q 5 constitute a current mirror, the switch Q 6 and the switch Q 7 constitute a current mirror, and the switch Q 10 and the switch Q 11 constitute a current mirror. Alternatively, the mirror ratios of the three sets of current mirrors are each 1:1.
More specifically, the resistor R 9 and the capacitor C 4 form a low-pass filter to filter the voltage V SW, and in this embodiment, the voltage filtered by the resistor R 9 and the capacitor C 4 is the voltage V OUT, that is, the voltage V OUT is connected to the positive input end of the operational amplifier A1.
More specifically, the current source I M is a fixed bias current, when the switch Q 2 is turned ON, i.e. when the down tube ON signal ls_on=1, the switch Q 8 is turned off, the difference between the current I M and the current I N charges the capacitor C 2 to generate a voltage V RAMP, and the voltage V RAMP is clamped by the operational amplifier A2 and divided by the resistor R 2 to generate a ramp current I RAMP. Wherein, the current I N is a current flowing through the drain of the switch Q 7, and the current I N has the following expression:
。
the expression of the voltage V RAMP over time t is as follows:
。
The SLOPE SLOPE_I RAMP of the ramp current I RAMP is expressed as follows:
。
With continued reference to fig. 2, in one embodiment, the voltage divider 11 includes a resistor R 3 and a resistor R 4, a first end of the resistor R 3 is connected to the voltage V OUT, a second end of the resistor R 3 is connected to the first end of the resistor R 4, a second end of the resistor R 4 is grounded PGND, and a first end of the resistor R 4 is connected to the negative input end of the error amplifier 12.
In a specific embodiment, the voltage adder 15 includes a resistor R 5, a first terminal of the resistor R 5 is connected to the output terminal of the voltage-to-current converter 13, and a second terminal of the resistor R 5 is connected to the voltage V SW.
In a specific embodiment, the voltage V B is generated by the current source I B and the resistor R 6, a first terminal of the resistor R 6 is connected to the negative input terminal of the comparator 16, a first terminal of the resistor R 6 is connected to the current source I B, and a second terminal of the resistor R 6 is grounded PGND.
Further, the circuit 1 for reducing frequency jitter of the switching node further includes a filter 112, where the filter 112 is connected between the output terminal of the error amplifier 12 and the ground SGND, the filter 112 includes a resistor R 8 and a capacitor C 3, a first terminal of the resistor R 8 is connected to the output terminal of the error amplifier 12, a second terminal of the resistor R 8 is connected to the first terminal of the capacitor C 3, and a second terminal of the capacitor C 3 is grounded SGND.
Fig. 4 shows a schematic diagram of an embodiment of the voltage-to-current converter 13 in fig. 2. As shown in fig. 4, the output end of the error amplifier 12 is connected to the positive input end of the operational amplifier A3, the output end of the operational amplifier A3 is connected to the gate of the switch Q 12, the negative input end of the operational amplifier A3 is connected to the source of the switch Q 12, the source of the switch Q 12 is grounded SGND via the resistor R 7, the voltage Vcc is connected to the source of the switch Q 13 and the source of the switch Q 14, the gate of the switch Q 13 is connected to the drain of the switch Q 13 and the gate of the switch Q 14, the drain of the switch Q 13 is connected to the drain of the switch Q 12, and the drain of the switch Q 14 outputs the current I VC. Wherein the switch Q 13 and the switch Q 14 form a current mirror, and optionally, the mirror ratio of the current mirror is 1:1.
The working principle of the present invention will be described with reference to fig. 2 to 4.
More specifically, the on-time controller 15 generates the upper tube on-end time T on-end using an adaptive constant on-time mode.
More specifically, the voltage divider 11 divides the voltage V OUT output by the BUCK conversion circuit 2 to generate a feedback voltage V FB, the difference between the reference voltage V REF and the feedback voltage V FB passes through the error amplifier 12 to obtain a voltage V C, and the voltage V C is converted into a current I VC with a fixed proportion by the voltage-to-current converter 13, where the current I VC=VC/R7.
Further, when the switch Q 2 is turned on, the current I VC is superimposed with the ramp current I RAMP, and then passes through the voltage adder 15 and is superimposed on the voltage V SW to obtain a voltage V S, where V S=(IVC+IRAMP)*R5+VSW.
The comparator 16 compares the voltage V S with the voltage V B, when the voltage V S is greater than the voltage V B, the PWM signal output by the comparator 16 is at a high level, the trigger 18 outputs a signal to the logic controller 19, the logic controller 19 makes the upper tube ON signal hs_on=1, the lower tube ON signal ls_on=0, which indicates that the switch Q 1 is turned off for a time T off, the first driver 110 drives the switch Q 1 to be turned ON, and the second driver 111 drives the switch Q 2 to be turned off. During the on phase of switch Q 1, ramp current I RAMP is cleared. Until the ON-time controller outputs the upper tube ON-end time T on-end to be at a high level, the trigger 18 outputs a signal to the logic controller 19, the logic controller 19 makes the upper tube ON signal hs_on=0 and the lower tube ON signal ls_on=1, the first driver 110 drives the switch Q 1 to be turned off, and the second driver 111 drives the switch Q 2 to be turned ON.
When the output voltage V OUT is smaller, the current I N is correspondingly smaller; therefore, the difference between the current I M and the current I N is large, the slopes of the voltage V RAMP and the ramp current I RAMP are large, and the slope of the voltage V S is also increased. Fig. 5 (a) is a waveform diagram of frequency jitter of the switch node SW before using a circuit for reducing frequency jitter of the switch node according to the present invention, and fig. 5 (b) is a waveform diagram of frequency jitter of the switch node SW after using a circuit for reducing frequency jitter of the switch node according to the present invention, it can be seen that the frequency jitter of the switch node SW is significantly reduced.
Therefore, the circuit for reducing the frequency jitter of the switch node can automatically adjust the SLOPE SLOPE_I RAMP of the injected SLOPE current I RAMP according to the output voltage V OUT, and solves the problem of large jitter of the BUCK conversion circuit in the conventional ACOT valley current mode. Meanwhile, the ramp current I RAMP is cleared during the on phase of the switch Q 1, and starts to be generated during the off phase of the switch Q 1, and the ramp current I RAMP and the current I VC are superimposed to determine the load current together, so that the output voltage range of the error amplifier 12 is not affected, and the problem of the output swing of the error amplifier 12 is not caused.
The invention also provides a method for reducing the frequency jitter of the switch node, and fig. 6 shows a flow chart of the method for reducing the frequency jitter of the switch node, which specifically comprises the following steps.
In step S1, the output voltage V OUT of the conversion circuit is sampled to obtain the feedback voltage V FB.
In step S2, the difference between the reference voltage V REF and the feedback voltage V FB is amplified to obtain a voltage V C.
Step S3, converting the voltage V C into a fixed ratio current I VC.
Step S4, when the switch Q 2 is turned on, the current I VC and the slope current I RAMP are overlapped and then overlapped on the voltage V SW to obtain a voltage V S, when the voltage V S is larger than the voltage V B, the switch Q 1 is driven to be turned on, the switch Q 2 is turned off, and in the stage of turning on the switch Q 1, the slope current I RAMP is cleared; after the on time of the switch Q 1 is over, the driving switch Q 1 is turned off and the switch Q 2 is turned on.
Wherein the SLOPE slope_i RAMP of the ramp current I RAMP is inversely related to the output voltage V OUT.
It should be noted that the method and circuit for reducing frequency jitter of a switching node of the present invention can also be applied to Boost conversion circuits and Buck-Boost conversion circuits.
Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but rather is capable of modification and variation without departing from the spirit and scope of the present invention.
Claims (7)
1. The circuit for reducing the frequency jitter of the switch node is applied to a conversion circuit, and is characterized by comprising a voltage divider, an error amplifier, a voltage-current converter, a ramp current injector, a voltage adder, a comparator and a trigger, wherein the input end of the voltage divider is connected with the output voltage of the conversion circuit, the output end of the voltage divider is connected with the negative input end of the error amplifier, the positive input end of the error amplifier is connected with a reference voltage, the output end of the error amplifier is connected with the input end of the voltage-current converter, the output end of the voltage-current converter is connected with the ramp current injector and the voltage adder, the voltage adder is connected with the positive input end of the comparator, the negative input end of the comparator is connected with a first voltage, and the output end of the comparator is connected with the S end of the trigger;
The switching-on time controller is connected with the R end of the trigger, and the switching-on time controller generates the switching-on ending time of the upper tube of the conversion circuit;
the switching device comprises a switching circuit, a first driver, a second driver, a logic controller, a first output end and a second output end, wherein the Q end of the switching circuit is connected with the input end of the logic controller;
The ramp current injector comprises a first operational amplifier, a second operational amplifier, a plurality of switches, a second capacitor, a first resistor, a second resistor and a third driver, wherein the positive input end of the first operational amplifier is connected with the output voltage of the conversion circuit, the output end of the first operational amplifier is connected with the grid electrode of the third switch, the source electrode of the third switch is grounded through the first resistor, the negative input end of the first operational amplifier is connected with the source electrode of the third switch, the first power supply voltage is connected with the source electrode of the fourth switch, the grid electrode of the fourth switch is connected with the grid electrode of the fifth switch, the grid electrode of the fourth switch is connected with the drain electrode of the fourth switch, the grid electrode of the fifth switch is connected with the grid electrode of the seventh switch, the drain electrode of the sixth switch is connected with the grid electrode of the sixth switch, the source electrode of the seventh switch is grounded, the drain electrode of the seventh switch is connected with the source electrode of the seventh switch, the positive input end of the eighth switch is connected with the drain electrode of the eighth switch, the positive input end of the eighth switch is connected with the output end of the eighth switch is connected with the fourth switch, the drain of the eighth switch is connected with the eighth switch, the source electrode of the ninth switch is grounded through the second resistor, the first power supply voltage is connected with the source electrode of the tenth switch and the source electrode of the eleventh switch, the grid electrode of the tenth switch is connected with the grid electrode of the eleventh switch, the drain electrode of the tenth switch and the drain electrode of the ninth switch, and the drain electrode of the eleventh switch is connected with the output end of the voltage-current converter.
2. The circuit for reducing frequency jitter of a switching node of claim 1 wherein said voltage divider comprises a third resistor and a fourth resistor, a first terminal of said third resistor being connected to an output voltage of said conversion circuit, a second terminal of said third resistor being connected to a first terminal of said fourth resistor, a second terminal of said fourth resistor being grounded, and a first terminal of said fourth resistor being connected to a negative input terminal of said error amplifier.
3. The circuit for reducing frequency jitter of a switching node of claim 2 wherein said voltage adder includes a fifth resistor, a first terminal of said fifth resistor being connected to an output of said voltage to current converter, a second terminal of said fifth resistor being connected to a switching node voltage, said switching node being a connection node of said first switch and said second switch.
4. A circuit for reducing frequency jitter of a switching node according to claim 3 wherein the first voltage is generated by a second current source and a sixth resistor, a first terminal of the sixth resistor being connected to the negative input terminal of the comparator, a first terminal of the sixth resistor being connected to the second current source, a second terminal of the sixth resistor being connected to ground.
5. The circuit for reducing frequency jitter of a switching node of claim 4 wherein said voltage to current converter comprises a third operational amplifier, a seventh resistor and a plurality of switches, wherein an output of said error amplifier is connected to a positive input of said third operational amplifier, an output of said third operational amplifier is connected to a gate of a twelfth switch, a negative input of said third operational amplifier is connected to a source of said twelfth switch, said source of said twelfth switch is grounded through said seventh resistor, said first supply voltage is connected to a source of said thirteenth switch and to a source of a fourteenth switch, a gate of said thirteenth switch is connected to a drain of said thirteenth switch and to a gate of said fourteenth switch, a drain of said thirteenth switch is connected to a drain of said twelfth switch, and a drain of said fourteenth switch is an output of said voltage to current converter.
6. A circuit for reducing frequency jitter at a switching node as defined in claim 1 further comprising a filter connected between the output of said error amplifier and ground.
7. A method of reducing switching node frequency jitter, characterized by being applied to a circuit for reducing switching node frequency jitter as claimed in any of claims 1-6, comprising,
Step S1, sampling the output voltage of a conversion circuit to obtain feedback voltage;
step S2, amplifying the difference value between the reference voltage and the feedback voltage to obtain a second voltage;
step S3, converting the second voltage into a second current with fixed proportion;
Step S4, when the second switch is turned on, the second current and the slope current are overlapped and then are overlapped on the switch node voltage to obtain a third voltage, when the third voltage is larger than the first voltage, the first switch of the driving conversion circuit is turned on, the second switch is turned off, and in the first switch on stage, the slope current is cleared; and after the conduction time of the first switch is over, the first switch is driven to be closed, and the second switch is driven to be conducted.
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| US10075073B2 (en) * | 2015-09-08 | 2018-09-11 | Rohm Co., Ltd. | DC/DC converter and switching power supply having overcurrent protection |
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| CN107276570A (en) * | 2017-06-06 | 2017-10-20 | 电子科技大学 | A kind of slope is superimposed PWM comparison circuits |
| CN113437874A (en) * | 2021-08-26 | 2021-09-24 | 上海泰矽微电子有限公司 | BUCK switch converter with IMIN control circuit |
| CN117118203A (en) * | 2023-10-24 | 2023-11-24 | 江苏展芯半导体技术有限公司 | Step-down converter |
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| CN117833637A (en) | 2024-04-05 |
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