CN117832230A - Array substrate, display device and manufacturing method of array substrate - Google Patents

Abstract

The embodiment of the application provides an array substrate with a better display effect and a display device comprising the array substrate, wherein a transistor in the array substrate comprises an auxiliary metal layer, a grid electrode insulating layer, an active layer, a source electrode and a drain electrode which are sequentially stacked from the surface of the substrate. The active layer between the source and drain forms the conductive channel of the transistor. The grid electrode and the substrate are provided with grid electrode pads, and the projection of the source electrode and the drain electrode on the substrate along the direction vertical to the substrate is not overlapped with the projection of the grid electrode on the substrate along the direction vertical to the substrate. The embodiment of the application also provides a manufacturing method of the array substrate.

Description

Array substrate, display device and manufacturing method of array substrate

Technical Field

The present application relates to the field of display technologies, and in particular, to an array substrate, a display device, and a method for manufacturing the array substrate

Background

Currently, display panels are widely used in different display devices, such as Liquid Crystal Display (LCD) panels and OLED display panels, which are widely used in different mobile phones, tablet computers or other display devices, and generally include transistors as driving elements for driving pixel elements. However, in practical applications, a Thin Film Transistor (TFT) as a driving element often cannot provide a data signal to a pixel element according to a preset state, which causes that the pixel element cannot accurately display image data, resulting in poor display effect of the display device.

Disclosure of Invention

In view of the foregoing technical problems, the present application provides an array substrate with a better display effect, a display device and a manufacturing method of the array substrate.

The embodiment of the application discloses array substrate, including a plurality of pixel units that carry out image display, every pixel unit includes a transistor at least, the transistor includes from the auxiliary metal layer, grid, gate insulation layer, active layer, source and the drain electrode that the base plate surface stacks gradually and sets up, wherein, source and drain between the active layer form the conducting channel of transistor, the grid with including the grid pad between the base plate, and the source the drain is along being perpendicular to the base plate direction projection on the base plate with the grid is along being perpendicular to the projection of base plate direction on the base plate does not overlap.

Optionally, the gate pad is made of an insulating material and has an inverted trapezoid structure as a whole.

Optionally, the gate pad includes a first parallel side, a second parallel side, a first oblique side and a second oblique side, where the first parallel side is located on the substrate surface, the second parallel side is parallel to the first parallel side and is far away from the substrate surface relative to the first parallel side, and the length of the first parallel side is smaller than that of the second parallel side, and the first oblique side and the second oblique side are oppositely disposed and are respectively connected to the first parallel side and the second parallel side.

Optionally, the transistor includes two auxiliary metal layers disposed on the surface of the substrate and adjacent to the first oblique side and the second oblique side, respectively; the gate and the gate pad overlap along a projection on the substrate perpendicular to the substrate direction; the projections of the grid electrode and the auxiliary metal layer on the substrate along the direction perpendicular to the substrate are not overlapped and are spaced by a preset distance, and the grid electrode and the auxiliary metal layer are electrically disconnected.

Optionally, the material of the gate pad is a negative photoresist material.

The embodiment of the application also discloses a display device, which comprises the array substrate.

The embodiment of the application also discloses a manufacturing method of the array substrate, which comprises the following steps: providing a substrate, and forming a grid pad on the surface of the substrate; forming an auxiliary metal layer and a grid electrode on the surfaces of the substrate and the grid electrode pad respectively, and forming a grid electrode insulating layer on the surfaces of the auxiliary metal layer and the grid electrode; forming an active layer on the gate insulating layer; forming a source electrode and a drain electrode on the surface of the active layer, wherein the active layer between the source electrode and the drain electrode forms a conductive channel of the transistor; the projection of the source electrode and the drain electrode on the substrate along the direction vertical to the substrate is not overlapped with the projection of the grid electrode on the substrate along the direction vertical to the substrate.

Optionally, forming the gate pad on the substrate surface includes: and forming a negative photoresist layer on the surface of the substrate, and patterning the negative photoresist layer to form a grid pad with an inverted trapezoid structure as a whole.

Optionally, patterning the negative photoresist layer to form a gate pad having an overall inverted trapezoidal structure includes: the grid pad comprises a first parallel edge, a second parallel edge, a first bevel edge and a second bevel edge, wherein the first parallel edge is positioned on the surface of the substrate, the second parallel edge is parallel to the first parallel edge and is opposite to the first parallel edge and is far away from the surface of the substrate, the length of the first parallel edge is smaller than that of the second parallel edge, and the first bevel edge and the second bevel edge are oppositely arranged and are respectively connected with the first parallel edge and the second parallel edge.

Optionally, forming an auxiliary metal layer and a gate electrode on the substrate and the gate pad surface respectively includes: forming a first metal layer on the substrate and the gate pad, patterning the first metal layer to form a gate and an auxiliary metal layer, wherein the auxiliary metal layer is respectively arranged on the surface of the substrate and is respectively adjacent to the first bevel edge and the second bevel edge; the gate and the gate pad overlap along a projection on the substrate perpendicular to the substrate direction; the projections of the grid electrode and the auxiliary metal layer on the substrate along the direction perpendicular to the substrate are not overlapped and are spaced by a preset distance, and the grid electrode and the auxiliary metal layer are electrically disconnected.

Compared with the prior art, in the embodiment of the application, the grid pad is arranged between the substrate and the grid, so that the source electrode, the drain electrode and the grid are mutually isolated in the thickness direction of the array substrate and are not overlapped, parasitic capacitance is prevented from being formed between the source electrode, the drain electrode and the grid, leakage current of the transistor is further reduced, reliability of the transistor and accuracy of data signals provided to the pixel electrode are effectively improved, power consumption of the array substrate and the display device is further reduced, and picture quality of the display device is improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a display device according to an embodiment of the present disclosure;

FIG. 2 is a schematic side view of the display panel shown in FIG. 1;

FIG. 3 is a schematic diagram of a planar layout of the display panel shown in FIG. 2;

FIG. 4 is a schematic diagram of an equivalent circuit of the pixel unit shown in FIG. 3;

FIG. 5 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present disclosure;

fig. 6 to 9 are schematic structural views of the array substrate shown in fig. 5 during the fabrication process;

fig. 10 is a schematic top view of the transistor shown in fig. 9.

Reference numerals illustrate:

the display device comprises a display device 100, a display panel 10, a power module 20, a display area 10a, a non-display area 10b, an array substrate 10C, a counter substrate 10D, a dielectric layer 10e, data lines D1-Dm, scanning lines G1-Gn, a first direction F1, a second direction F2, a timing control circuit 11, a data driving circuit 12, a scanning driving circuit 13, a pixel unit P, a pixel electrode IT, a common electrode Vcom, a display capacitor C1, a storage capacitor C2, an ith scanning line Gi, a jth data line Dj, a substrate 110, a gate pad 120, a negative photoresist layer 120a, a first parallel side a, a second parallel side b, a first oblique side C, a second oblique side D, a first metal layer 130, a gate 131, an auxiliary metal layer 132, a gate insulating layer 140, an active layer 150, a second metal layer 160, a drain electrode 161, a preset drain electrode 161, and a preset channel CH.

Detailed Description

In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Preferred embodiments of the present application are shown in the accompanying drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

The following description of the embodiments refers to the accompanying drawings, which illustrate specific embodiments that can be used to practice the present application. The numbering of the components itself, e.g. "first", "second", etc., is used herein merely to distinguish between the described objects and does not have any sequential or technical meaning. The terms "coupled" and "connected," as used herein, are intended to encompass both direct and indirect coupling (coupling), unless otherwise indicated. Directional terms referred to in this application, such as "upper", "lower", "front", "rear", "left", "right", "inner", "outer", "side", etc., are merely directions referring to the attached drawings, and thus, directional terms are used for better, more clear description and understanding of the present application, rather than indicating or implying that the apparatus or element being referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present application.

In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; may be a mechanical connection; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context. It should be noted that the terms "first," "second," and the like in the description and claims of the present application and in the drawings are used for distinguishing between different objects and not for describing a particular sequential order.

Furthermore, the terms "comprises," "comprising," "includes," "including," "may be" or "including" as used in this application mean the presence of the corresponding function, operation, element, etc. disclosed, but not limited to other one or more additional functions, operations, elements, etc. Furthermore, the terms "comprises" or "comprising" mean that there is a corresponding feature, number, step, operation, element, component, or combination thereof disclosed in the specification, and that there is no intention to exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof. Furthermore, when describing embodiments of the present application, use of "may" means "one or more embodiments of the present application. Also, the term "exemplary" is intended to refer to an example or illustration.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a display device 100 according to the present embodiment.

As shown in fig. 1, the display device 100 includes a display panel 10, a power module 20 and a supporting frame 30, wherein the display panel 10 and the power module 20 are fixed on the supporting frame 30, and the power module 20 is disposed on a back surface of the display panel 10, i.e. a non-display surface of the display panel 10. The power module 20 is used for providing power voltage for the display panel 10 to display images, and the support frame 30 provides fixing and protecting functions for the display panel 10 and the power module 20.

In other embodiments of the present application, the display device 100 may not need to be provided with the support frame 30, for example, a portable electronic device, such as a mobile phone, a tablet computer, and the like.

Referring to fig. 2, fig. 2 is a schematic side view of the display panel 10 shown in fig. 1.

As shown in fig. 2, the display panel 10 includes an image display region 10a and a non-display region 10b. The display area 10a is used for performing image display, and the non-display area 10b is disposed around the display area 10a to provide other auxiliary components or modules, and specifically, the display panel 10 includes an array substrate 10c and an opposite substrate 10d, and a display medium layer 10e sandwiched between the array substrate 10c and the opposite substrate 10 d. In this embodiment, the display medium in the display medium layer 10e is a light emitting semiconductor material such as liquid crystal molecules, OLED, micro LED, mini LED, etc.

Taking the display panel 10 as a liquid crystal display panel as an example, the display medium in the display medium layer 10e is liquid crystal molecules, and the display panel 10 further includes a backlight module 17 (Back light Module, BM), wherein the backlight module 17 is configured to provide light for display to the display medium layer 10e, and the liquid crystal molecules deflect relative angles according to an electric field formed by the data signals, so as to emit the light transmitted by the backlight module 17 to the opposite substrate 10d for performing image display.

Referring to fig. 3, fig. 3 is a schematic plan layout structure of the display panel 10 shown in fig. 2.

As shown in fig. 3, the display area 10a of the display panel 10 includes a plurality of m×n pixel units P, m data lines D1 to Dm and n scan lines G1 to Gn arranged in a matrix, where m and n are natural numbers greater than 1.

The n scan lines G1 to Gn extend along a first direction F1 and are mutually insulated and arranged in parallel along a second direction F2, and the m data lines D1 to Dm extend along the second direction F2 and are mutually insulated and arranged in parallel along the first direction F1, wherein the first direction F1 and the second direction F2 are mutually perpendicular.

The display device 100 further includes a timing control circuit 11 for driving the pixel units to display an image, a data driving circuit 12, and a scan driving circuit 13 provided in the display panel 10, corresponding to the non-display region 10b of the display panel 10.

The timing control circuit 11 is electrically connected to the data driving circuit 12 and the scan driving circuit 13, and is used for controlling the working timings of the data driving circuit 12 and the scan driving circuit 13, i.e. outputting corresponding timing control signals to the data driving circuit 12 to the scan driving circuit 13, so as to control when to output corresponding scan signals and data signals.

The Data driving circuit 12 is electrically connected to the m Data lines D1 to Dm, and is configured to transmit the Data signal (Data) for display to the plurality of pixel units P in the form of Data voltages through the m Data lines D1 to Dm.

The scan driving circuit 13 is electrically connected to the n scan lines G1 to Gn, and is configured to output scan signals through the n scan lines G1 to Gn for controlling when the pixel unit P receives the data signals. The scan driving circuit 13 sequentially outputs scan signals from the n scan lines G1 to Gn in the position arrangement order from the scan lines G1, G2, … …, gn in the scan period.

Referring to fig. 4, fig. 4 is an equivalent circuit schematic diagram of the pixel unit P in the array substrate 10c shown in fig. 3.

As shown in fig. 4, the pixel unit P is any pixel unit arranged in an array in the array substrate 10C, and includes a transistor T, a display capacitor C1, and a storage capacitor C2. The gate 131 of the transistor T is connected to the ith scan line Gi for controlling the transistor T to be turned on or off. The source 161 of the transistor T is connected to the jth data line Dj, and the drain 162 of the transistor T is connected to the pixel electrode IT, for receiving a data signal from the jth data line Dj and transmitting the data signal to the pixel electrode IT under the control of the ith scan line Gi.

IT can be understood that the display capacitor C1 is formed of the pixel electrode IT, the liquid crystal molecules as the display medium layer 10e, and the common electrode Vcom, wherein the display capacitor C1 and the storage capacitor C2 are connected in parallel through the storage capacitor C2 for maintaining the electric field of the display capacitor C1 between the pixel electrode IT and the common electrode Vcom before the next data signal is loaded.

In this embodiment, the transistor T is a thin film transistor (Thin Film Transistor, TFT). Through researches, when the grid electrode of the thin film transistor overlaps with the source electrode and the drain electrode in the thickness direction, namely, when the projection of the source electrode and the drain electrode on the substrate in the thickness direction overlaps, parasitic capacitance is formed between the grid electrode and the source electrode and between the grid electrode and the drain electrode. At the moment when the thin film transistor is turned off, due to parasitic capacitance, according to the law of conservation of charge, the coupling effect between the capacitance can cause that the pixel electrode voltage is pulled down simultaneously to jump when frame inversion driving is carried out, so that the pixel electrode deviates from the center position relative to the common electrode potential, and further, the voltages of the pixel electrode when two adjacent frames of image data are different in polarity are different, and then, the flicker phenomenon and the poor display effect of a picture are caused.

Referring to fig. 5-9, fig. 5 is a flowchart illustrating a method for manufacturing the array substrate 10c according to the present embodiment, and fig. 6-9 are schematic structural diagrams during the manufacturing process of the array substrate 10c shown in fig. 5.

As shown in fig. 5, the method for manufacturing the array substrate 10c includes steps S10 to S40.

As shown in fig. 5, step S10: a substrate 110 is provided, and a gate pad 120 is formed on the substrate 110.

Specifically, as shown in fig. 6, a substrate 110 is provided, and the material of the substrate 110 may be one or more of glass, sapphire, silicon carbide, silicon, gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, germanium, or other materials capable of growing group III nitrides. In this embodiment, the substrate 110 is a glass substrate.

The process of forming the gate pad 120 specifically includes: a negative photoresist layer 120a is formed on the surface of the substrate 110, and the negative photoresist layer 120a is patterned to form a gate pad 120 having an inverted trapezoid structure as a whole. Specifically, as shown in fig. 6, the gate pad 120 includes a first parallel side a, a second parallel side b, a first oblique side c and a second oblique side d, wherein the first parallel side a is located on the surface of the substrate 110, the second parallel side b is parallel to the first parallel side a and is far away from the surface of the substrate 110 relative to the first parallel side a, and the length of the first parallel side a is smaller than that of the second parallel side b. The first inclined edge c and the second inclined edge d are oppositely arranged and respectively connected with the first parallel edge a and the second parallel edge b.

In this embodiment, the material of the gate pad 120 is an insulating material, and preferably, the material of the gate pad 120 is a negative photoresist material. Preferably, the negative photoresist material may be a black matrix material having a thickness of 0.5 μm or more. Since the characteristics of the negative photoresist material are partially preserved during development in the exposure process, the intensity of light received by the photoresist is gradually reduced along with the increase of the thickness, so that the exposure intensity gradually decreases from top to bottom, and the gate pad 120 has an inverted trapezoid structure during development.

Step S20: an auxiliary metal layer 132 and a gate electrode 131 are formed on the upper surfaces of the substrate 110 and the gate pad 120, respectively, and a gate insulating layer 140 is formed on the surfaces of the auxiliary metal layer 132 and the gate electrode 131.

Referring to fig. 5 and fig. 7 together, as shown in fig. 7, the process of forming the gate 131 and the auxiliary metal layer 132 specifically includes:

a first metal layer 130 is formed on the substrate 110 and the gate pad 120, and the first metal layer 130 is patterned to form a gate electrode 131 and an auxiliary metal layer 132 in cooperation with a mask. The first metal layer 130 is made of a metal material, such as aluminum, polysilicon, copper, molybdenum, chromium, or an alloy thereof. Meanwhile, the gate electrode 131 and the auxiliary metal layer 132 may be deposited by PVD (physical vapor deposition ). In this embodiment, the gate electrode 131 and the auxiliary metal layer 132 may be formed by depositing a 300nm molybdenum film on the substrate 110 using a direct current sputtering method, and patterning the molybdenum film by wet etching. Of course, the gate electrode 131 and the auxiliary metal layer 132 may be formed by other methods, which are not particularly limited herein.

As shown in fig. 7, the gate electrode 131 is located on the surface of the gate pad 120, and the auxiliary metal layer 132 is located on the surface of the substrate 110. Because the gate pad 120 has an inverted trapezoid structure, and when the deposition method of PVD (physical vapor deposition ) is adopted, the film forming directionality is strong, the longitudinal film forming rate is far greater than the transverse film forming rate, during the formation of the first metal layer 130, the first metal layer 130 will break outside the first oblique side c and the second oblique side d of the gate pad 120, the first metal layer 130 breaks to form the gate 131 and the auxiliary metal layer 132, the gate 131 completely covers the side of the gate pad 120 far away from the surface of the substrate 110, and the auxiliary metal layer 132 is directly arranged on the surface of the substrate 110 and adjacent to the first oblique side c and the second oblique side d of the gate pad 120. In other words, the projections of the gate electrode 131 and the gate pad 120 on the substrate 110 in the direction perpendicular to the substrate 110 are completely overlapped, the auxiliary metal layer 132 is blanket disposed on the substrate 110, and the auxiliary metal layer 132 is adjacent to the first and second oblique sides c and d, respectively. Since the gate electrode 131 and the auxiliary metal layer 132 are broken, the projections of the gate electrode 131 and the auxiliary metal layer 132 on the substrate 110 along the direction perpendicular to the substrate 110 do not overlap and are spaced apart by a predetermined distance L (refer to fig. 10), and the gate electrode 131 and the auxiliary metal layer 132 are electrically disconnected, i.e. the gate electrode 131 and the auxiliary metal layer 132 are not electrically connected.

In an embodiment, to avoid the first metal layer 130 from being broken incompletely outside the first and second oblique sides c and d of the gate pad 120, a wet etching process may be added after the gate electrode 131 and the auxiliary metal layer 132 are formed, so as to ensure that the first metal layer 130 is broken completely outside the first and second oblique sides c and d of the gate pad 120.

Further, a gate insulating layer 140 is formed on the gate electrode 131 and the auxiliary metal layer 132, and the gate insulating layer 140 is made of an insulating material such as aluminum oxide, silicon nitride, hafnium oxide, zirconium oxide, or titanium oxide. Meanwhile, the gate insulating layer 140 may be deposited by CVD, specifically, in this embodiment, a silicon oxide film with a thickness of 200nm is deposited by plasma enhanced vapor deposition as the gate insulating layer 140, however, the gate insulating layer 140 may be formed by other methods, which is not limited herein.

In this embodiment, the gate 131 is disposed on the surface of the gate pad 120, the auxiliary metal layer 132 is disposed on the surface of the substrate 110, the gate insulating layer 140 is disposed on the surfaces of the gate 131 and the auxiliary metal layer 132, and a step-shaped transition is formed between the surface of the substrate 110 and the gate 131 through the auxiliary metal layer 132, so that the gradient of the gate insulating layer 131 is effectively reduced, and thus the risk of breakage of the gate insulating layer 140 on the sidewall of the gate pad 120 can be effectively prevented, and the reliability and safety of the array substrate 10c are effectively improved.

Step S30: an active layer 150 is formed on the gate insulating layer 140.

Referring to fig. 5 and fig. 8 together, an active layer 150 is formed on the surface of the gate insulating layer 140, that is, the active layer 150 is disposed on a side of the gate insulating layer 140 away from the substrate 110. In this embodiment, the active layer 150 is made of a metal oxide semiconductor material, which may be indium gallium zinc oxide. The indium gallium zinc oxide has high mobility and good uniformity, and the use of the indium gallium zinc oxide as the active layer 150 can improve the resistance transmission capability of the transistor T, thereby improving the on-state current thereof. In other embodiments, the metal oxide semiconductor layer may be another metal oxide semiconductor layer such as zinc oxide, indium oxide, or aluminum oxide, which is not particularly limited herein.

Meanwhile, the projection of the active layer 150 on the substrate 110 along the direction perpendicular to the substrate 110 is located in the projection area of the gate 131 and the auxiliary metal layer 132 on the substrate 110 along the direction perpendicular to the substrate 110, and in an embodiment, when the display device 100 (fig. 1) is a liquid crystal display device, the auxiliary metal layer 132 can shield the light emitted from the backlight module 17 (fig. 2), so that the problem that the active layer 150 generates photo-generated carriers, i.e. photo-leakage, due to the sensitization can be avoided.

Step S40: a source electrode 161 and a drain electrode 162 are formed on the surface of the active layer 150, and the active layer 150 between the source electrode 161 and the drain electrode 162 forms a conductive channel CH of the transistor T.

Referring to fig. 5 and fig. 9 together, the process for forming the source electrode 161 and the drain electrode 162 specifically includes: a second metal layer 160 is formed on the active layer 150, and the source electrode 161 and the drain electrode 162 are formed by patterning the second metal layer 160 in cooperation with a mask. The material of the second metal layer may be aluminum, polysilicon, copper, molybdenum, chromium or an alloy of the above materials. After the source electrode 161 and the drain electrode 162 are formed, the active layer 150 between the source electrode 161 and the drain electrode 162 forms a conductive channel CH of the transistor T.

Referring to fig. 9-10 together, fig. 10 is a schematic top view of the transistor T shown in fig. 9, wherein the second metal layer 160 includes a source 161 and a drain 162, the source 161 and the drain 162 are respectively disposed on a side of the active layer 150 and the gate insulating layer 140 away from the substrate 110, and the source 161 and the drain 162 are respectively disposed on two sides of the gate 131. The projections of the source electrode 161 and the drain electrode 162 on the substrate 110 along the direction perpendicular to the substrate 110 and the projections of the gate electrode 131 on the substrate 110 along the direction perpendicular to the substrate 110 are not overlapped, that is, the distance between the projections of the source electrode 161 and the gate electrode 131 on the substrate 110 along the direction perpendicular to the substrate 110 is greater than or equal to zero, and the distance between the projections of the drain electrode 162 and the gate electrode 131 on the substrate 110 along the direction perpendicular to the substrate 110 is greater than or equal to zero. The distance between the projections of the source electrode 161 and the gate electrode 131 on the substrate 110 along the direction perpendicular to the substrate 110 is equal to the distance between the projections of the drain electrode 162 and the gate electrode 131 on the substrate 110 along the direction perpendicular to the substrate 110, so that the transistor T is symmetrical in structure, and the impedance of the transistor T is reduced.

After the transistor T is fabricated, the array substrate 10C continues to be fabricated to form a pixel electrode, a common electrode, a storage capacitor C2, and other elements, wherein the gate electrode 131 is connected to the scan line Gi through the etched opening, the source electrode 161 is connected to the data line Dj, and the drain electrode 162 is connected to the pixel electrode IT fabricated later.

In this embodiment, by disposing the gate pad 120 between the surface of the substrate 110 and the gate electrode, the source electrode 161, the drain electrode 162 and the gate electrode 131 are isolated from each other in the thickness direction of the array substrate 10c, and there is no overlap, so that parasitic capacitance is prevented from being formed between the source electrode 161, the drain electrode 162 and the gate electrode 131, thereby reducing the leakage current of the transistor T, effectively improving the reliability of the transistor T and the accuracy of the data signal provided to the pixel electrode I T, and further reducing the power consumption of the display device 100, accelerating the response speed of the display device 100, and improving the picture quality of the display device 100.

Further, an auxiliary metal layer 132 is further disposed around the gate electrode 131 and the gate pad 120, and the auxiliary metal layer 132 and the active layer 150 overlap in the thickness direction of the array substrate 10c, so that light entering from the substrate 110 can be effectively prevented from irradiating the active layer 150, and the conductivity of the active layer 150 is ensured. Meanwhile, the auxiliary metal layer 132 relieves the gradient of the gate insulating layer 140 on the side surfaces of the corresponding gate pad 120 and the gate 131, prevents the gate insulating layer 140 from breaking on the side surfaces of the gate pad 120 and the gate 131, and further improves the reliability of the transistor T.

It is to be understood that the invention is not limited in its application to the examples described above, but is capable of modification and variation in light of the above teachings by those skilled in the art, and that all such modifications and variations are intended to be included within the scope of the appended claims.

Claims (10)

1. An array substrate comprising a plurality of pixel units for performing image display, each pixel unit comprising at least one transistor, the transistor comprising an auxiliary metal layer, a gate electrode, a gate insulating layer, an active layer, a source electrode and a drain electrode which are laminated in sequence from the surface of the substrate, wherein the active layer between the source electrode and the drain electrode forms a conductive channel of the transistor, characterized in that a gate pad is included between the gate electrode and the substrate, and the projection of the source electrode and the drain electrode onto the substrate along the direction perpendicular to the substrate and the projection of the gate electrode onto the substrate along the direction perpendicular to the substrate do not overlap.

2. The array substrate of claim 1, wherein the gate pad is made of an insulating material and has an inverted trapezoid structure as a whole.

3. The array substrate of claim 2, wherein the gate pad comprises a first parallel side, a second parallel side, a first oblique side and a second oblique side, wherein the first parallel side is located on the substrate surface, the second parallel side is parallel to the first parallel side and is away from the substrate surface with respect to the first parallel side, and the length of the first parallel side is smaller than the length of the second parallel side, and the first oblique side and the second oblique side are disposed opposite to and connected to the first parallel side and the second parallel side, respectively.

4. The array substrate of claim 1, wherein the transistor comprises two auxiliary metal layers disposed on the substrate surface adjacent to the first oblique side and the second oblique side, respectively;

the gate and the gate pad overlap along a projection on the substrate perpendicular to the substrate direction;

the projections of the grid electrode and the auxiliary metal layer on the substrate along the direction perpendicular to the substrate are not overlapped and are spaced by a preset distance, and the grid electrode and the auxiliary metal layer are electrically disconnected.

5. The array substrate of any one of claims 1-4, wherein the gate pad is a negative photoresist material.

6. A display device comprising the array substrate of any one of claims 1-5.

7. The manufacturing method of the array substrate is characterized by comprising the following steps of:

providing a substrate, and forming a grid pad on the surface of the substrate;

forming an auxiliary metal layer and a grid electrode on the surfaces of the substrate and the grid electrode pad respectively, and forming a grid electrode insulating layer on the surfaces of the auxiliary metal layer and the grid electrode;

forming an active layer on the gate insulating layer;

forming a source electrode and a drain electrode on the surface of the active layer, wherein the active layer between the source electrode and the drain electrode forms a conductive channel of the transistor;

the projection of the source electrode and the drain electrode on the substrate along the direction vertical to the substrate is not overlapped with the projection of the grid electrode on the substrate along the direction vertical to the substrate.

8. The method of claim 7, wherein,

forming a gate pad on the substrate surface includes: and forming a negative photoresist layer on the surface of the substrate, and patterning the negative photoresist layer to form a grid pad with an inverted trapezoid structure as a whole.

9. The method of manufacturing an array substrate according to claim 8, wherein patterning the negative photoresist layer to form a gate pad having an inverted trapezoid structure as a whole comprises:

the grid pad comprises a first parallel edge, a second parallel edge, a first bevel edge and a second bevel edge, wherein the first parallel edge is positioned on the surface of the substrate, the second parallel edge is parallel to the first parallel edge and is opposite to the first parallel edge and is far away from the surface of the substrate, the length of the first parallel edge is smaller than that of the second parallel edge, and the first bevel edge and the second bevel edge are oppositely arranged and are respectively connected with the first parallel edge and the second parallel edge.

10. The method for manufacturing an array substrate according to any one of claims 7 to 9, wherein,

forming an auxiliary metal layer and a gate electrode on the substrate and the gate pad surface, respectively, includes: forming a first metal layer on the substrate and the gate pad, patterning the first metal layer to form a gate and an auxiliary metal layer, wherein the auxiliary metal layer is respectively arranged on the surface of the substrate and is respectively adjacent to the first bevel edge and the second bevel edge; the gate and the gate pad overlap along a projection on the substrate perpendicular to the substrate direction; the projections of the grid electrode and the auxiliary metal layer on the substrate along the direction perpendicular to the substrate are not overlapped and are spaced by a preset distance, and the grid electrode and the auxiliary metal layer are electrically disconnected.