CN117832088A - Preparation method of silicon carbide MOSFET and silicon carbide MOSFET - Google Patents
Preparation method of silicon carbide MOSFET and silicon carbide MOSFET Download PDFInfo
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- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 125
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- 238000002360 preparation method Methods 0.000 title abstract description 8
- 238000005468 ion implantation Methods 0.000 claims abstract description 42
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- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
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Abstract
The invention provides a preparation method of a silicon carbide MOSFET and the silicon carbide MOSFET, comprising the following steps: sequentially growing a buffer layer and a drift region on a silicon carbide substrate; based on a plurality of prefabricated masks, respectively performing ion implantation for a plurality of times through the plurality of masks in sequence to form an integrated diode p region, a pwell region and a source region with gradually increased widths from the edge of the silicon carbide MOSFET chip to the center of the chip; the multiple masks are provided with multiple mask holes with gradually increased widths from the edge of the silicon carbide MOSFET chip to the center of the chip according to the requirement of the injection region. The invention can enhance the conduction performance and the surge current resistance of the diode by forming the p-region of the integrated diode with a plurality of groups of widths gradually increasing from the edge of the silicon carbide MOSFET chip to the central width of the chip, and can effectively reduce the junction temperature of the central part of the chip, so that the temperature difference between the central part of the chip and the edge of the chip with the junction temperature reduced is smaller, and the chip is relatively uniform in temperature as a whole.
Description
Technical Field
The invention belongs to the technical field of semiconductor device protection structures, and particularly relates to a preparation method of a silicon carbide MOSFET and the silicon carbide MOSFET.
Background
While the performance of conventional silicon-based semiconductor devices has gradually approached the physical limits of materials, devices fabricated using third generation semiconductor materials, typically silicon carbide, have excellent operating capabilities such as high frequency, high voltage, high temperature resistance, radiation resistance, and the like. SiC MOSFETs, which are representative of SiC devices, have many excellent characteristics such as low on-loss, fast switching speed, and high operating frequency, and have been gradually popularized and used in application scenarios such as electric vehicles, charging piles, new energy power generation, industrial control, and flexible dc power transmission.
The SiCNOSFET has higher efficiency and power density, and is very suitable for being applied to the field of electric energy conversion. However, due to the effects of higher interface state density, poor reliability and the like of the SiC gate oxide layer, the SiC MOSFET is generally difficult to bear higher junction temperature, and in the working state of the SiCMOSFET chip, due to the difference of heat dissipation efficiency of different areas of the chip, temperature gradient can occur between the different areas of the chip, and the central area of the chip often shows higher junction temperature, so that the SiCMOSFET chip still has high-temperature failure risk under the condition that the junction temperature of part of the areas is not up to the limit, and the reliability of the SiC MOSFET chip is adversely affected.
The SiCNOSFET can avoid external freewheeling diode due to its internal self-contained body diode, thereby reducing the complexity of circuit design and system cost. However, while working efficiency and power density are sought during power electronics system applications, system stability and reliability are another important consideration. When the power electronic system fails, the SiMOSFET device itself needs to bear the surge impact under the condition that the protection circuit does not react or does not exist, and the surge current mainly flows through the body diode of the SiMOSFET, so that the process is short, but the requirement on the device is high. The research shows that when the surge current exceeds the bearing capacity of the device, the SiCNOSFET device has gate-source short circuit, and after dissection, the phenomena of melting of the aluminum electrode on the surface of the chip, disappearance of the source ohmic contact layer, degradation of the Pwell region and the like are found.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention provides a preparation method of a silicon carbide MOSFET, which comprises the following steps:
sequentially growing a buffer layer and a drift region on a silicon carbide substrate;
based on a plurality of prefabricated masks, respectively performing ion implantation for a plurality of times through the plurality of masks in sequence to form an integrated diode p region, a pwell region and a source region with gradually increased widths from the edge of the silicon carbide MOSFET chip to the center of the chip;
the multiple masks are provided with multiple mask holes with gradually increased widths from the edge of the silicon carbide MOSFET chip to the center of the chip according to the requirement of the injection region.
Preferably, the mask plate comprises: a first mask forming a p region of the integrated diode, a second mask forming a pwell region, and a plurality of third masks forming source regions.
Preferably, based on a plurality of prefabricated masks, ion implantation is performed for a plurality of times through the plurality of masks in sequence, so as to form an integrated diode p region, a pwell region and a source region with gradually increased widths from the edge of the silicon carbide MOSFET chip to the center of the chip, including:
performing ion implantation for multiple times in the N-drift region through a plurality of mask holes with different widths of the first mask plate to form an integrated diode p region with gradually increased width from the edge of the silicon carbide MOSFET chip to the center of the chip;
performing ion implantation for multiple times in the N-drift region through a plurality of mask holes with different widths of the second mask plate to form a pwell region with gradually increased width from the edge of the silicon carbide MOSFET chip to the center of the chip;
sequentially carrying out ion implantation for multiple times in the pwell region by utilizing each third mask plate to form a source region with gradually increased width from the edge of the silicon carbide MOSFET chip to the center of the chip;
wherein the source region comprises: an n+ region and a p+ region.
Preferably, the ion doping concentration of the p region of the integrated diode is equal to or higher than the ion doping concentration of the p+ region.
Preferably, the width of the p-region of the integrated diode increases from the edge of the silicon carbide MOSFET chip to the center of the chip at random, each increase being no less than 0.05 μm.
Preferably, the ion doping concentration of the pwell region is lower than that of the p+ region and that of the integrated diode p region.
Preferably, the spacing distance between the adjacent p-region and the pwell region of the integrated diode is 1.0 μm-6.0 μm.
Preferably, the pwell and the integrated diode p region have a shape including at least one or more of the following: bar, circle, ring, regular quadrangle, regular hexagon and regular octagon.
Preferably, the plurality of third reticles includes: forming an n+ mask of an n+ region in the source region and a p+ mask of a p+ region in the source region;
and sequentially carrying out ion implantation for a plurality of times in the pwell region by utilizing each third mask plate to form a source region with gradually increased width from the edge of the silicon carbide MOSFET chip to the center of the chip, wherein the method comprises the following steps:
performing ion implantation for multiple times in the pwell region through a plurality of mask holes with different widths of the n+ mask plate to form a plurality of n+ regions with the same ion doping concentration and gradually increasing from the edge of the silicon carbide MOSFET chip to the center of the chip;
and simultaneously carrying out ion implantation for a plurality of times on the n+ region or the pwell region through a plurality of mask holes with different widths on the p+ mask plate, so as to form a plurality of p+ regions with the same ion doping concentration and gradually increasing the width from the edge of the silicon carbide MOSFET chip to the center of the chip.
Preferably, the minimum width of the n+ region ranges from: 0.1 μm to 3.0 μm; the ion implantation depth of the n+ region is 0.2-0.5 mu m; the ion impurity concentration of the n+ region is 1x10 18 cm -3 -1x10 19 cm -3 。
Preferably, the width of the p+ region increases from the edge of the silicon carbide MOSFET chip to the center of the chip at random, each increasing in width by not less than 0.05 μm.
Preferably, the minimum width of the p+ region ranges from: 0.1 μm to 3.0 μm; the ion implantation depth of the p+ region is 0.2-0.7 mu m; the ion impurity concentration of the p+ region is 2x10 18 cm -3 -2x10 19 cm -3 。
Preferably, after performing ion implantation in the pwell region for multiple times based on mask holes on the prefabricated third reticles to generate a source region, the method further includes:
preparing a gate oxide layer and polysilicon on the drift region, and wrapping an isolation medium layer on the outer surfaces of the gate oxide layer and the polysilicon;
and growing a metal layer on the source electrode region and the isolation dielectric layer, and growing the metal layer below the silicon carbide substrate.
Preferably, the material of the gate oxide layer at least includes one or more of the following: siO (SiO) 2 SiN and Al 2 O 3 ；
Wherein the thickness of the gate oxide layer is 10nm-100nm.
Based on the same inventive concept, the present invention also provides a silicon carbide MOSFET comprising: the semiconductor device comprises a silicon carbide substrate, a buffer layer formed on the silicon carbide substrate, a drift region grown on the buffer layer, and an integrated diode p region, a pwell region and a source region which gradually increase in width from the edge of a silicon carbide MOSFET chip to the center of the chip, wherein the drift region is provided with a silicon carbide MOSFET chip;
wherein the source region comprises: an n+ region and a p+ region, wherein the p+ region is embedded in the n+ region, and the n+ region is embedded in the pwell region.
Preferably, a gate oxide layer is disposed on the JFET region, a portion of the n+ region, a portion of the pwell region, and a portion of the integrated diode p region between adjacent pwell regions and the integrated diode p region; polysilicon is arranged on the gate oxide layer; an isolation medium layer is wrapped on the outer surfaces of the gate oxide layer and the polysilicon; and a metal layer grows on the source electrode area and the isolation medium layer, and a metal layer grows below the silicon carbide substrate.
Preferably, the n+ region has a width of 0.1 μm to 3.0 μm, a depth of 0.2 μm to 0.5 μm, and an impurity concentration of 1×10 18 cm -3 -1x10 19 cm -3 。
Preferably, the p+ region has a width of 0.1 μm to 3.0 μm, a depth of 0.2 μm to 0.7 μm, and an impurity concentration of 2×10 18 cm -3 -2x10 19 cm -3 。
Preferably, the ion doping concentration of the p region of the integrated diode is equal to or higher than the ion doping concentration of the p+ region.
Preferably, the ion doping concentration of the pwell region is lower than that of the p+ region and that of the integrated diode p region.
Preferably, the spacing distance between the adjacent p-region and the pwell region of the integrated diode is 1.0 μm-6.0 μm.
Preferably, the pwell and the integrated diode p region have a shape including at least one or more of the following: bar, circle, ring, regular quadrangle, regular hexagon and regular octagon.
Preferably, the material of the gate oxide layer at least includes one or more of the following: siO (SiO) 2 SiN and Al 2 O 3 ；
Wherein the thickness of the gate oxide layer is 10nm-100nm.
Preferably, the material of the metal layer is Cu.
Compared with the closest prior art, the invention has the following beneficial effects:
1. the invention provides a preparation method of a silicon carbide MOSFET and the silicon carbide MOSFET, comprising the following steps: sequentially growing a buffer layer and a drift region on a silicon carbide substrate; based on a plurality of prefabricated masks, respectively performing ion implantation for a plurality of times through the plurality of masks in sequence to form an integrated diode p region, a pwell region and a source region with gradually increased widths from the edge of the silicon carbide MOSFET chip to the center of the chip; the multiple masks are provided with multiple mask holes with gradually increased widths from the edge of the silicon carbide MOSFET chip to the center of the chip according to the requirement of the injection region. The invention can enhance the conduction performance and the anti-surge current capability of the diode by forming the pwell region and the integrated diode p region with multiple groups of widths gradually increasing from the edge of the silicon carbide MOSFET chip to the central width of the chip, and can effectively reduce the junction temperature of the central part of the chip because the width of the p+ region of the central region of the chip and the width of the p region of the integrated diode are larger, so that the temperature difference between the central part of the chip and the edge of the chip with the junction temperature reduced is smaller, and the chip overall presents relatively uniform temperature.
2. The width of the p+ region of the central region of the chip and the width of the p region of the integrated diode are larger, so that the junction temperature in the center of the chip can be effectively reduced, the temperature difference between the center of the chip and the edge of the chip, which reduces the junction temperature, is smaller, the heat distribution of the existing silicon carbide MOSFET chip is optimized, the power consumption of the existing silicon carbide MOSFET chip is reduced, the problem of uneven internal temperature distribution in the working state of the existing silicon carbide MOSFET chip is improved, meanwhile, the conduction performance and the surge current resistance of the body diode are enhanced while the working performance of the silicon carbide MOSFET is not sacrificed under the condition that the conduction capability of the silicon carbide MOSFET is not influenced, and the optimization and balance between the device performance and the reliability are obtained.
Drawings
FIG. 1 is a flow chart of a method for fabricating a silicon carbide MOSFET according to the present invention;
FIG. 2 is a schematic diagram of a mask in a method for fabricating a silicon carbide MOSFET according to the present invention;
FIG. 3 is a block diagram of a plurality of groups of pwell regions and an integrated diode p region in a method for fabricating a silicon carbide MOSFET according to the present invention;
fig. 4 is a block diagram of a silicon carbide MOSFET according to the present invention.
Detailed Description
The following describes the embodiments of the present invention in further detail with reference to the drawings.
Example 1:
the flow chart of the preparation method of the silicon carbide MOSFET provided by the invention is shown in figure 1, and the preparation method comprises the following steps:
step 1: sequentially growing a buffer layer and a drift region on a silicon carbide substrate;
step 2: based on a plurality of prefabricated masks, respectively performing ion implantation for a plurality of times through the plurality of masks in sequence to form an integrated diode p region, a pwell region and a source region with gradually increased widths from the edge of the silicon carbide MOSFET chip to the center of the chip;
the multiple masks are provided with multiple mask holes with gradually increased widths from the edge of the silicon carbide MOSFET chip to the center of the chip according to the requirement of the injection region.
Specifically, the step 2 includes: performing ion implantation for multiple times in the N-drift region through a plurality of mask holes with different widths of the first mask plate to form an integrated diode p region with gradually increased width from the edge of the silicon carbide MOSFET chip to the center of the chip;
performing ion implantation for multiple times in the N-drift region through a plurality of mask holes with different widths of the second mask plate to form a pwell region with gradually increased width from the edge of the silicon carbide MOSFET chip to the center of the chip;
sequentially carrying out ion implantation for multiple times in the pwell region by utilizing each third mask plate to form a source region with gradually increased width from the edge of the silicon carbide MOSFET chip to the center of the chip;
wherein the source region comprises: an n+ region and a p+ region;
the ion doping concentration of the p region of the integrated diode is equal to or higher than that of the p+ region;
the width of the p region of the integrated diode is random in increasing amplitude from the edge of the silicon carbide MOSFET chip to the center of the chip, and each increasing amplitude is not less than 0.05 mu m;
the ion doping concentration of the pwell region is lower than that of the p+ region and that of the p region of the integrated diode;
wherein the spacing distance between the adjacent integrated diode p region and the pwell region is 1.0 μm-6.0 μm;
the pwell and integrated diode p-region shapes include at least one or more of: bar, circle, ring, regular quadrangle, regular hexagon and regular octagon.
As shown in fig. 2, based on a first mask plate with mask holes with gradually increasing widths from the edge of the silicon carbide MOSFET chip to the center of the chip, ion implantation of the same dose and the same concentration is respectively and simultaneously carried out on a drift region through a plurality of mask holes with different widths of the first mask plate, so as to form an integrated diode p region with gradually increasing widths from the edge of the silicon carbide MOSFET chip to the center of the chip;
the minimum width range of the ion implantation of the p region of the integrated diode is 0.1um-3.0um; the width is gradually increased from the edge of the silicon carbide MOSFET chip to the center of the chip (the width is not increased or reduced in the middle of the increasing process, and the width is not increased or reduced in the middle of the increasing process), and the amplitude of each width increase is random, but each amplitude is not less than 0.05um;
since the width of the integrated diode p-region gradually increases from the edge of the chip to the center of the chip, the width of the integrated diode p-region at the edge of the silicon carbide MOSFET chip is smaller than the width of the integrated diode p-region at the center of the chip;
then, based on a second mask plate with mask holes with gradually increased widths from the edge of the silicon carbide MOSFET chip to the center of the chip, respectively and simultaneously carrying out ion implantation for a plurality of times with the same dosage and the same concentration on the drift region through a plurality of mask holes with different widths of the second mask plate to form a pwell region with gradually increased widths from the edge of the silicon carbide MOSFET chip to the center of the chip;
the shapes formed by the first mask plate, the second mask plate and the third mask plate can be one or more of bar shape, round shape, ring shape, regular quadrangle shape, regular hexagon shape and regular octagon shape, as shown in fig. 2, a plurality of mask plates in the regular quadrangle shape form a nested schematic diagram, the largest mask hole corresponds to a hole in a pwell area, the middle mask hole corresponds to an n+ hole, and the innermost mask hole corresponds to a p+ hole;
thus, as shown in FIG. 3, a plurality of groups of pwell regions and integrated diode p regions with gradually increasing widths are formed on the drift region from the edge of the silicon carbide MOSFET chip to the center of the chip;
wherein each group of pwell regions and the integrated diode p regions have equal widths, and the separation distance between the integrated diode p regions adjacent to the pwell regions from the edge of the silicon carbide MOSFET chip to the center of the chip is 1.0 μm-6.0 μm.
Specifically, the plurality of third reticles in step 2 includes: forming an n+ mask of an n+ region in the source region and a p+ mask of a p+ region in the source region;
and sequentially carrying out ion implantation for a plurality of times in the pwell region by utilizing each third mask plate to form a source region with gradually increased width from the edge of the silicon carbide MOSFET chip to the center of the chip, wherein the method comprises the following steps:
performing ion implantation for multiple times in the pwell region through a plurality of mask holes with different widths of the n+ mask plate to form a plurality of n+ regions with the same ion doping concentration and gradually increasing from the edge of the silicon carbide MOSFET chip to the center of the chip;
performing ion implantation on the n+ region for multiple times through a plurality of mask holes with different widths on the p+ mask plate, so as to form a plurality of p+ regions with the same ion doping concentration and gradually increasing widths from the edge of the silicon carbide MOSFET chip to the center of the chip;
the minimum width range of the n+ region is as follows: 0.1 μm to 3.0 μm; the ion implantation depth of the n+ region is 0.2-0.5 mu m; the ion impurity concentration of the n+ region is 1x10 18 cm -3 -1x10 19 cm -3 ；
The width of the p+ region gradually increases from the edge of the silicon carbide MOSFET chip to the center of the chip, and each increasing amplitude is not less than 0.05 mu m;
the minimum width range of the p+ region is as follows: 0.1 μm to 3.0 μm; the ion implantation depth of the p+ region is 0.2-0.7 mu m; the ion impurity concentration of the p+ region is 2x10 18 cm -3 -2x10 19 cm -3 。
Performing ion implantation of the same dosage and the same concentration on a pwell region through a plurality of mask holes with different widths of the n+ mask plate at the same time on the basis of the n+ mask plate with the mask holes with the width gradually increasing from the edge of the silicon carbide MOSFET chip to the center of the chip, and forming n+ regions in the pwell regions with different widths with the width gradually increasing from the edge of the silicon carbide MOSFET chip to the center of the chip;
finally, based on a p+ mask plate with mask holes with gradually increased widths from the edge of the silicon carbide MOSFET chip to the center of the chip, respectively carrying out ion implantation of the same dose and the same concentration on an n+ region through a plurality of mask holes with different widths of the p+ mask plate at the same time, and respectively forming p+ regions in n+ regions with different widths with gradually increased widths from the edge of the silicon carbide MOSFET chip to the center of the chip;
wherein the minimum width of the ion implantation of the p+ region is 0.1um-3.0um; the width is gradually increased from the edge of the silicon carbide MOSFET chip to the center of the chip (the width is not increased or reduced in the middle of the increasing process, and the width is not increased or reduced in the middle of the increasing process), and the amplitude of each width increase is random, but each amplitude is not less than 0.05um;
since the width of the p+ region gradually increases from the edge of the chip to the center of the chip, the width of the p+ region at the edge of the silicon carbide MOSFET chip is smaller than the width of the p+ region at the center of the chip;
the method comprises the steps of carrying out ion implantation of the same dosage and the same concentration for a plurality of times through a plurality of mask holes with different widths of an n+ mask plate respectively, and carrying out ion implantation of the same dosage and the same concentration for a plurality of times through a plurality of mask holes with different widths of a p+ mask plate on an n+ region respectively, wherein the plurality of times refer to ion implantation of the same dosage and the same concentration in each mask hole at different energy and different dosage, and the implantation depth of the ion implantation can be controlled by adjusting the implantation energy to adjust the dosage of the different energy because the implantation depths of the different energy correspond to each mask hole;
wherein, an n+ region with a width which is suitable for the pwell region is embedded in each pwell region with gradually increasing width from the edge of the silicon carbide MOSFET chip to the center of the chip;
a p+ region with the width corresponding to the n+ region is embedded in the n+ region with the width gradually increasing from the edge of the silicon carbide MOSFET chip to the center of the chip;
the width of the finally formed n+ region is 0.1 μm-3.0 μm, the depth of the n+ region is 0.2 μm-0.5 μm, and the impurity concentration of the n+ region is 1x10 18 cm -3 -1x10 19 cm -3 ；
The width of the p+ region is 0.1 μm-3.0 μm, the depth of the p+ region is 0.2 μm-0.7 μm, and the impurity concentration of the p+ region is 2x10 18 cm -3 -2x10 19 cm -3 。
The invention can enhance the conduction performance and the anti-surge current capability of the diode by forming the p region and the p+ region of the integrated diode with multiple groups of widths gradually increasing from the edge of the silicon carbide MOSFET chip to the central width of the chip, and can effectively reduce the junction temperature of the central part of the chip, thereby enabling the temperature of the central part of the chip with reduced junction temperature to be almost equal to the temperature of the edge of the chip, so that the chip presents relatively uniform temperature as a whole, and the reliability of the silicon carbide MOSFET chip is improved.
Specifically, step 2 further includes: preparing a gate oxide layer and polysilicon on the drift region, and wrapping an isolation medium layer on the outer surfaces of the gate oxide layer and the polysilicon;
growing a metal layer on the source electrode area and the isolation medium layer, and growing the metal layer below the silicon carbide substrate;
the material of the gate oxide layer at least comprises one or more of the following: siO (SiO) 2 SiN and Al 2 O 3 ；
Wherein the thickness of the gate oxide layer is 10nm-100nm.
Preparing a gate oxide layer and polysilicon on the silicon carbide drift layer region, wherein the gate oxide layer grows by a thermal oxidation method;
preparing a gate oxide layer and polysilicon on the drift region, and wrapping an isolation medium layer on the outer surfaces of the gate oxide layer and the polysilicon;
growing a metallization layer on the silicon carbide drift layer region and the isolation dielectric layer region, and also growing the metallization layer below the substrate;
the metallization layer adopts Cu metal material to replace traditional Al metal so as to improve the melting temperature of the electrode material, thereby improving the surge current resistance of the device.
Example 2:
the silicon carbide MOSFET provided by the invention is shown in a schematic structure in fig. 4, and comprises: the semiconductor device comprises a silicon carbide substrate, a buffer layer formed on the silicon carbide substrate, a drift region grown on the buffer layer, and an integrated diode p region, a pwell region and a source region which gradually increase in width from the edge of a silicon carbide MOSFET chip to the center of the chip, wherein the drift region is provided with a silicon carbide MOSFET chip;
wherein the source region comprises: an n+ region and a p+ region, wherein the p+ region is embedded in the n+ region, and the n+ region is embedded in the pwell region.
As shown in fig. 2, a buffer layer, a drift region and a plurality of integrated diode p regions and pwell regions with gradually increased widths from the edge of a silicon carbide MOSFET chip to the center of the chip are sequentially arranged on the upper surface of an n-type 4H-SiC substrate;
wherein the drift region between the p regions of the integrated diode adjacent to the pwell region is a JFET region;
an n+ region which is adaptive to the width of the pwell region is embedded in each pwell region, and a p+ region which is adaptive to the width of the n+ region is embedded in each n+ source region to form a source region;
the widths of the n+ regions and the p+ regions are gradually increased according to a non-uniform distribution rule that the widths gradually increase from the edge of the silicon carbide MOSFET chip to the center of the chip;
a gate oxide layer is covered on the upper end face of the JFET region between the adjacent pwell region and the integrated diode p region, and the gate oxide layer is also covered on part of the n+ region, part of the pwell region and part of the integrated diode p region;
a polysilicon gate is arranged on the upper surface of the gate oxide layer, and an isolation medium layer is wrapped on the outer surfaces of the gate oxide layer and the polysilicon gate together;
a metal layer grows on the source electrode area and the isolation medium layer, and a metal layer grows below the silicon carbide substrate;
the structure of the invention can realize the enhancement of the conduction performance and the surge current resistance of the diode, and the junction temperature in the center of the chip can be effectively reduced because the width of the p+ region in the center region of the chip and the width of the p region of the integrated diode are larger, so that the temperature in the center of the chip with the junction temperature reduced is almost equal to the temperature at the edge of the chip, the whole chip presents relatively uniform temperature, and the reliability of the SiC MOSFET is improved.
It should be noted that the above embodiments are only for illustrating the technical solution of the present invention and not for limiting the scope of protection thereof, and although the present invention has been described in detail with reference to the above embodiments, it should be understood by those skilled in the art that various changes, modifications or equivalents may be made to the specific embodiments of the application after reading the present invention, and these changes, modifications or equivalents are within the scope of protection of the claims appended hereto.
Claims (24)
1. A method of making a silicon carbide MOSFET comprising:
sequentially growing a buffer layer and a drift region on a silicon carbide substrate;
based on a plurality of prefabricated masks, respectively performing ion implantation for a plurality of times through the plurality of masks in sequence to form an integrated diode p region, a pwell region and a source region with gradually increased widths from the edge of the silicon carbide MOSFET chip to the center of the chip;
the multiple masks are provided with multiple mask holes with gradually increased widths from the edge of the silicon carbide MOSFET chip to the center of the chip according to the requirement of the injection region.
2. The method of claim 1, wherein the reticle comprises: a first mask forming a p region of the integrated diode, a second mask forming a pwell region, and a plurality of third masks forming source regions.
3. The method of claim 2, wherein forming an integrated diode p-region, pwell region, and source region having progressively increasing widths from the edge of the silicon carbide MOSFET die to the center of the die by sequentially performing a plurality of ion implants through the plurality of reticles based on the plurality of pre-fabricated reticles, respectively, comprises:
performing ion implantation for multiple times in the N-drift region through a plurality of mask holes with different widths of the first mask plate to form an integrated diode p region with gradually increased width from the edge of the silicon carbide MOSFET chip to the center of the chip;
performing ion implantation for multiple times in the N-drift region through a plurality of mask holes with different widths of the second mask plate to form a pwell region with gradually increased width from the edge of the silicon carbide MOSFET chip to the center of the chip;
sequentially carrying out ion implantation for multiple times in the pwell region by utilizing each third mask plate to form a source region with gradually increased width from the edge of the silicon carbide MOSFET chip to the center of the chip;
wherein the source region comprises: an n+ region and a p+ region.
4. The method of claim 3, wherein the integrated diode p-region has an ion doping concentration equal to or higher than an ion doping concentration of the p+ region.
5. The method of claim 4, wherein the width of the integrated diode p-region increases from the edge of the silicon carbide MOSFET die to the center of the die by a random amount, each increase having an amplitude of not less than 0.05 μm.
6. The method of claim 3 or 4, wherein the pwell region has an ion doping concentration that is lower than the ion doping concentration of the p+ region and the ion doping concentration of the integrated diode p region.
7. The method of claim 3, wherein a separation distance between adjacent ones of the integrated diode p-regions and pwell regions is 1.0 μm to 6.0 μm.
8. The method of claim 7, wherein the pwell and integrated diode p-region shapes include at least one or more of: bar, circle, ring, regular quadrangle, regular hexagon and regular octagon.
9. The method of claim 3, wherein the plurality of third reticles comprises: forming an n+ mask of an n+ region in the source region and a p+ mask of a p+ region in the source region;
and sequentially carrying out ion implantation for a plurality of times in the pwell region by utilizing each third mask plate to form a source region with gradually increased width from the edge of the silicon carbide MOSFET chip to the center of the chip, wherein the method comprises the following steps:
performing ion implantation for multiple times in the pwell region through a plurality of mask holes with different widths of the n+ mask plate to form a plurality of n+ regions with the same ion doping concentration and gradually increasing from the edge of the silicon carbide MOSFET chip to the center of the chip;
and simultaneously carrying out ion implantation for a plurality of times on the n+ region or the pwell region through a plurality of mask holes with different widths on the p+ mask plate, so as to form a plurality of p+ regions with the same ion doping concentration and gradually increasing the width from the edge of the silicon carbide MOSFET chip to the center of the chip.
10. The method of claim 9, wherein the n+ region has a minimum width in the range of: 0.1 μm to 3.0 μm; the ion implantation depth of the n+ region is 0.2-0.5 mu m; the ion impurity concentration of the n+ region is 1x10 18 cm -3 -1x10 19 cm -3 。
11. The method of claim 9, wherein the width of the p+ region increases from the edge of the silicon carbide MOSFET die to the center of the die by a random amount, each increase having an amplitude of not less than 0.05 μm.
12. The method of claim 11, wherein the p+ region has a minimum width in the range of: 0.1 μm to 3.0 μm; the ion implantation depth of the p+ region is 0.2-0.7 mu m; the ion impurity concentration of the p+ region is 2x10 18 cm -3 -2x10 19 cm -3 。
13. The method of claim 1, wherein performing ion implantation multiple times in the pwell region based on mask holes on the prefabricated third plurality of reticles to generate a source region, further comprises:
preparing a gate oxide layer and polysilicon on the drift region, and wrapping an isolation medium layer on the outer surfaces of the gate oxide layer and the polysilicon;
and growing a metal layer on the source electrode region and the isolation dielectric layer, and growing the metal layer below the silicon carbide substrate.
14. The method of claim 13, wherein the material of the gate oxide layer comprises at least one or more of: siO (SiO) 2 SiN and Al 2 O 3 ；
Wherein the thickness of the gate oxide layer is 10nm-100nm.
15. A silicon carbide MOSFET comprising: the semiconductor device comprises a silicon carbide substrate, a buffer layer formed on the silicon carbide substrate, a drift region grown on the buffer layer, and an integrated diode p region, a pwell region and a source region which gradually increase in width from the edge of a silicon carbide MOSFET chip to the center of the chip, wherein the drift region is provided with a silicon carbide MOSFET chip;
wherein the source region comprises: an n+ region and a p+ region, wherein the p+ region is embedded in the n+ region, and the n+ region is embedded in the pwell region.
16. The silicon carbide MOSFET of claim 15 wherein a gate oxide layer is disposed on the JFET region, a portion of the n+ region, a portion of the pwell region, and a portion of the integrated diode p region between adjacent pwell regions and the integrated diode p region; polysilicon is arranged on the gate oxide layer; an isolation medium layer is wrapped on the outer surfaces of the gate oxide layer and the polysilicon; and a metal layer grows on the source electrode area and the isolation medium layer, and a metal layer grows below the silicon carbide substrate.
17. The silicon carbide MOSFET of claim 15, wherein said n+ region has a width of 0.1 μm to 3.0 μm, a depth of 0.2 μm to 0.5 μm, and an impurity concentration of 1x10 18 cm -3 -1x10 19 cm -3 。
18. The silicon carbide MOSFET of claim 15, wherein said p+ region has a width of 0.1 μm to 3.0 μm, a depth of 0.2 μm to 0.7 μm, and an impurity concentration of 2x10 18 cm -3 -2x10 19 cm -3 。
19. The silicon carbide MOSFET of claim 15, wherein the integrated diode p-region has an ion doping concentration equal to or higher than an ion doping concentration of the p+ region.
20. The silicon carbide MOSFET of claim 15 wherein the pwell region has an ion doping concentration that is lower than the ion doping concentration of the p+ region and the ion doping concentration of the integrated diode p region.
21. The silicon carbide MOSFET of claim 15 wherein adjacent ones of said integrated diode p-regions are spaced apart from the pwell region by a distance of 1.0 μm to 6.0 μm.
22. The silicon carbide MOSFET of claim 21 wherein said pwell and integrated diode p-region has a shape comprising at least one or more of: bar, circle, ring, regular quadrangle, regular hexagon and regular octagon.
23. The silicon carbide MOSFET of claim 16, wherein the gate oxide layer material comprises at least one or more of: siO (SiO) 2 SiN and Al 2 O 3 ；
Wherein the thickness of the gate oxide layer is 10nm-100nm.
24. The silicon carbide MOSFET of claim 16, wherein the metal layer is Cu.
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