CN117810179A - Chip packaging structure, integrated circuit board and chip packaging method - Google Patents

Chip packaging structure, integrated circuit board and chip packaging method Download PDF

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Publication number
CN117810179A
CN117810179A CN202311805516.9A CN202311805516A CN117810179A CN 117810179 A CN117810179 A CN 117810179A CN 202311805516 A CN202311805516 A CN 202311805516A CN 117810179 A CN117810179 A CN 117810179A
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CN
China
Prior art keywords
chip
packaging
substrate
conductive
heat conducting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202311805516.9A
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Chinese (zh)
Inventor
郑爽爽
杨琳
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Suzhou Huatai Electronics Co Ltd
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Suzhou Huatai Electronics Co Ltd
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Publication date
Application filed by Suzhou Huatai Electronics Co Ltd filed Critical Suzhou Huatai Electronics Co Ltd
Priority to CN202311805516.9A priority Critical patent/CN117810179A/en
Publication of CN117810179A publication Critical patent/CN117810179A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

The embodiment of the application provides a chip packaging structure, an integrated circuit board and a chip packaging method, wherein the chip packaging structure comprises: a heat conducting block, a chip and a packaging substrate; one side of the chip is connected with the heat conducting block; a conductive bulge is arranged on a bonding pad at the other side of the chip and is correspondingly and electrically connected with an electric connection area on one side surface of the packaging substrate; the other side of the packaging substrate is correspondingly provided with a packaging pin; the chip, the heat conducting block and the packaging substrate are packaged together. The chip packaging structure, the integrated circuit board and the chip packaging method can solve the problem of large parasitic inductance caused by the fact that chip pins need to be led back to the bottom through wiring in a traditional heat dissipation packaging scheme, and the heat conducting block is adopted to realize rapid heat dissipation of chips, so that the working stability and performance of the chips are improved.

Description

Chip packaging structure, integrated circuit board and chip packaging method
Technical Field
The present disclosure relates to chip technologies, and in particular, to a chip packaging structure, an integrated circuit board, and a chip packaging method.
Background
In the design of radio frequency integrated circuit chips, chip heat dissipation has been an important issue. The chip heat dissipation is poor, the chip power consumption can be directly increased, and the efficiency is reduced, so that the output power is reduced, and the normal operation of the chip is seriously affected. Since the power amplifier is one of the chip modules having the greatest heat dissipation capacity, the heat dissipation research of the power amplifier chip has been a popular subject.
The heat dissipation modes of the chip mainly comprise radiation heat dissipation, conduction heat dissipation, convection heat dissipation, evaporation heat dissipation and the like, wherein the conduction heat dissipation is the most important heat dissipation mode of the chip. The power tube on the chip is a heat source, the packaging is a main carrier for conducting and radiating the chip, and the radiating effect of the chip is directly influenced by the way of packaging the radiating path.
Fig. 1 is a schematic diagram of a chip packaging method which is the most mainstream at present. The back of the chip is fixed on a large piece of metal material at the bottom of the package, and an output PAD (PAD) on the chip is connected with the package pin through a bonding wire. The package shell bonds the whole package pins and the package bottom together. The packaged chip is connected to a printed circuit board (Printed Circuit Board, PCB for short) by solder, and the heat of the chip is transferred to the upper surface of the PCB and then transferred to the bottom of the PCB through a metal via hole on the PCB for heat dissipation. The bottom of the PCB is usually provided with a large piece of metal, so that the heat dissipation effect is improved. The heat dissipation mode depends on the number of metal through holes on the PCB and the size of the metal area at the bottom of the PCB. If the number of the metal through holes is small or the metal heat dissipation area is insufficient, heat dissipation generated by the chip cannot be achieved, an additional air cooling or water cooling system is often needed to be additionally added for auxiliary heat dissipation, the cost is increased, and the device structure is also complicated.
With the continuous development and evolution of packaging technology, a new type of Top Side Cooling (TSC) package with upward heat dissipation has been developed in recent years. As shown in fig. 2 and 3, the chip is flip-chip mounted on top of the package, the output PAD on the chip is connected to the package upper leads via bond wires, the package upper leads are connected to the package lower leads via metal posts, and the signal traces on the chip are connected to the PCB. The package shell encapsulates the pins, package top, metal posts, etc. In practice, the top of the chip package is bonded to a heat sink. The heat sink is typically a large piece of metal, which provides a very good carrier for conductive heat dissipation. In this package, the heat generated by the chip is conducted directly upward to the bottom of the package and then to the heat sink, which greatly increases the heat dissipation rate. Fig. 3 differs from fig. 2 in that the package pins are not inside the package, but are led out from outside the package and reconnected to the PCB. The heat dissipation problem is solved by the two packaging modes of fig. 2 and 3, but the signal trace needs to be led back to the bottom to be connected with the PCB in a certain mode, so that a large parasitic inductance is generated, the radio frequency performance is affected, and the working stability of the chip is reduced.
Disclosure of Invention
In order to solve one of the above technical drawbacks, an embodiment of the present application provides a chip packaging structure, an integrated circuit board and a chip packaging method.
According to a first aspect of embodiments of the present application, there is provided a chip package structure, including: a heat conducting block, a chip and a packaging substrate;
one side of the chip is connected with the heat conducting block; a conductive bulge is arranged on a bonding pad at the other side of the chip and is correspondingly and electrically connected with an electric connection area on one side surface of the packaging substrate; the other side of the packaging substrate is correspondingly provided with a packaging pin; the chip, the heat conducting block and the packaging substrate are packaged together.
According to a second aspect of embodiments of the present application, there is provided an integrated circuit board, comprising: printed circuit board and chip packaging structure as described above.
According to a third aspect of the embodiments of the present application, there is provided a method for packaging a chip, including:
connecting one side surface of the chip to the conductive block;
and correspondingly connecting the conductive protrusions corresponding to the bonding pads on the other side surface of the chip with the electric connection areas of the packaging substrate.
According to the technical scheme provided by the embodiment of the application, the heat conducting block is arranged on one side of the chip, the heat conducting block is connected with the chip to conduct and dissipate heat of the chip, the conductive bulge is arranged on the bonding pad on the other side of the chip, and the conductive bulge is correspondingly and electrically connected with the electric connection area on one side surface of the packaging substrate; the other side of the packaging substrate is correspondingly provided with a packaging pin; after the chip, the heat conducting block and the packaging substrate are packaged together, the packaging pins are used as pins of the packaged chip to be connected to the printed circuit board, so that the problem of large parasitic inductance caused by the fact that the pins of the chip need to be led back to the bottom through wiring in the traditional scheme is solved, the heat conducting block is adopted to realize rapid heat dissipation of the chip, and the working stability and performance of the chip are improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:
FIG. 1 is a schematic diagram of a chip package structure in the related art;
FIG. 2 is a schematic diagram of another chip package structure according to the related art;
FIG. 3 is a schematic diagram of another chip package structure according to the related art;
fig. 4 is a schematic diagram of a chip package structure according to an embodiment of the present application;
FIG. 5 is a schematic diagram of another chip package structure according to an embodiment of the present disclosure;
fig. 6 is a schematic top view of another chip package structure according to an embodiment of the present application.
Reference numerals:
1-chip; 11-conductive bumps; 2-a heat conducting block; 3-packaging the substrate; 31-packaging pins; 32-a metal layer; 4-a printed circuit board; 5-a patch device; 6-sintering silver; 7-cooling fins; 71-heat conducting glue.
Detailed Description
In order to make the technical solutions and advantages of the embodiments of the present application more apparent, the following detailed description of exemplary embodiments of the present application is given with reference to the accompanying drawings, and it is apparent that the described embodiments are only some of the embodiments of the present application and not exhaustive of all the embodiments. It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other.
The embodiment provides a chip packaging structure which can be suitable for packaging a chip.
As shown in fig. 4, the chip package structure provided in this embodiment includes: a heat conduction block 2, a chip 1 and a packaging substrate 3. One side of the chip 1 is connected with the heat conducting block 2, specifically, the back of the chip 1 is connected with the heat conducting block 2, and the chip 1 can conduct and dissipate heat through the heat conducting block 2.
The other side of the chip 1 is provided with a bonding pad, the bonding pad is provided with a conductive bump 11, and the conductive bump 11 is electrically connected with the bonding pad.
A plurality of electric connection areas are arranged on one side surface of the packaging substrate 3, and the conductive protrusions 11 on the chip 1 are correspondingly and electrically connected with the electric connection areas. The other side of the package substrate 3 is provided with package pins 31, and the package pins 31 are correspondingly and electrically connected with the electric connection areas. The pads on the chip 1 correspondingly realize the transmission of the electric signals through the conductive bumps 11, the electric connection areas and the package pins 31.
The chip 1, the heat conducting block 2 and the packaging substrate 3 are bonded together through plastic packaging materials, and chip packaging is completed. The package pins 31 serve as pins of the packaged chip and can be soldered to the printed circuit board 4.
According to the technical scheme provided by the embodiment, the heat conducting block is arranged on one side of the chip, the heat conducting block is connected with the chip to conduct and dissipate heat, the conductive bulge is arranged on the bonding pad on the other side of the chip, and the conductive bulge is correspondingly and electrically connected with the electric connection area on one side surface of the packaging substrate; the other side of the packaging substrate is correspondingly provided with a packaging pin; after the chip, the heat conducting block and the packaging substrate are packaged together, the packaging pins are used as pins of the packaged chip to be connected to the printed circuit board, so that the problem of large parasitic inductance caused by the fact that the pins of the chip need to be led back to the bottom through wiring in the traditional scheme is solved, the heat conducting block is adopted to realize rapid heat dissipation of the chip, and the working stability and performance of the chip are improved.
The number of the chips 1 may be one or at least two. When the number of chips 1 is one, one chip 1 is packaged together with the heat conductive block 2 and the package substrate 3. When the number of the chips 1 is at least two, the at least two chips 1 are arranged between the heat conducting block 2 and the packaging substrate 3 at intervals, and are packaged together with the heat conducting block 2 and the packaging substrate 3. The package substrate 3 is disposed in the electrical connection area corresponding to at least two chips 1.
For the package substrate 3, a resin substrate or a glass substrate/silicon-based (Integraed Passive Devices, abbreviated as IPD) plate may be used, or other materials suitable for thin film processes may be used to form the package substrate 3.
The package substrate 3 may have one layer, two layers, or more than three layers.
For the scheme of a layer of packaging substrate 3, a metal layer 32 is arranged on one side surface or both side surfaces of the packaging substrate 3, and the metal layer 32 is divided into electric connection areas on the surface of the packaging substrate 3. The other side of the package substrate 3 is provided with package pins, the package substrate 3 is also provided with conductive holes penetrating through the thickness of the package substrate, and the metal layer 32 on one side surface is electrically connected with the metal layer 32 on the other side surface or the package pins 31 through the conductive holes.
For the package substrate 3 of two or more layers: a metal layer 32 is arranged between the substrates, and a plurality of electric connection areas are arranged on the outer surface of the substrate on the top layer and used as the electric connection areas on the surface of the packaging substrate 3. The substrate at the bottom layer is provided with packaging pins; each metal layer 32 is correspondingly electrically connected by a conductive via through the thickness of the substrate.
The different metal layers included in the package substrate 3 may be patterned, for example, the metal layer 32 forms metal traces and electrical connection regions on the surface of the package substrate 3. The metal layer on the surface of the package substrate 3 is formed by a semiconductor process, such as an IPD thin film process (i.e., plasma enhanced chemical vapor deposition) and the like, so that the thickness or width of the metal layer is relatively small and is far smaller than that of the metal layer on the surface of a common printed circuit board. The thickness of the package substrate 3 is around 200 microns, much smaller than the thickness of the printed circuit board.
As shown in fig. 5 and 6, further, the electrical connection region on the surface of the package substrate 3 may include: a region for connection with the conductive bump 11, and a region for connection with the patch device 5. The chip device 5 can be a chip resistor, a chip capacitor, a chip inductor, other chips and the like, and is welded to the corresponding electric connection area on the surface of the packaging substrate 3 through a chip welding process, so that the functions of the chips can be expanded, and the integration level is improved.
In fig. 6, the perspective effect is shown, where the package leads 31 are actually located on the other side of the package substrate 3, and in actual observation, the package leads 31 are not seen from the top view, and the package leads 31 are seen from the bottom view but the chip or chip device 5 is not seen.
In actual observation, the conductive bump 11 is not seen in a plan view, and the conductive bump 11 is seen in a bottom view of the chip.
In the above solution, the surface area of the conductive bump 2 facing the chip 1 is larger than the surface area of the chip 1 connected to the conductive bump 2. A specific scheme is as follows: the conductive bumps 2 are identical in size to the package substrate 3 and larger than the chip 1. The conductive block 2 has a larger size, so that the chip can be protected, and the heat conduction area of the chip can be increased, and the heat dissipation rate can be improved.
The chip 1 is specifically adhered to the conductive block 2 through the sintered silver 6, and the sintered silver 6 has good heat conduction capability.
And welding the packaged chips on a printed circuit board to form the integrated circuit board. Further, the heat dissipation plate 7 is adhered to the surface, away from the chip 1, of the heat conduction block 2 through the heat conduction glue 71, and the heat conduction glue has good heat conduction capability, is not conductive, and can further improve the heat dissipation rate of the chip. And, the surface area of the heat sink 7 facing the conductive block 2 is larger than the surface area of the conductive block 2, so that the heat dissipation area can be further increased to rapidly and sufficiently dissipate heat of the chip.
On the basis of the above technical solution, this embodiment further provides a method for packaging a chip, including:
and step one, connecting one side surface of the chip to the conductive block.
And step two, correspondingly connecting the conductive protrusions corresponding to the bonding pads on the other side surface of the chip with the electric connection areas of the packaging substrate.
The order of the two steps can be changed, namely, the first step can be executed first, and the second step can be executed first.
Further, before the chip is connected with the package substrate, the method further comprises:
forming a metal layer on one side surface of the packaging substrate, wherein the metal layer is divided into a plurality of electric connection areas; a packaging pin is arranged on the other side of the packaging substrate; and forming conductive holes penetrating through the thickness on the packaging substrate so that the packaging pins are correspondingly and electrically connected with the electric connection areas through the conductive holes.
According to the method, the packaging substrate 3 (or other materials such as glass-based/silicon-based IPD) is added as a packaging bottom carrier, the chip 1 is reversely buckled on the packaging substrate 3 through a flip technology, the back surface of the chip 1 is welded to the lower surface of the heat conducting block 2 through the sintered silver 6, the heat conducting block 2 can be made of cheap and good-heat-conductivity metal materials such as copper or aluminum, and the heat dissipation effect of the top of the chip is enhanced. The heat conducting block 2, the chip 1 and the packaging substrate 3 are bonded together by a mature injection molding mode. The obtained packaged chip can improve the problem of large parasitic inductance of pins, has good heat dissipation effect, and improves the working stability and performance of the chip.
In actual use, the package pins 31 are connected to the printed circuit board PCB by solder. The encapsulated heat conducting block 2 is connected together by a heat conducting glue 71 and a heat sink 7. The heat consumption generated by the operation of the chip 1 is conducted to the heat conducting block 2 through the sintered silver 6, and then is conducted to the heat radiating fin 7 through the heat conducting glue 71, and the heat conductivity of the material passing through the upward heat radiating mode is very good, so that the heat radiating effect is very good.
Furthermore, another great advantage of such a package is that the parasitic introduced by the package is very small. The signal output PAD PAD on the chip is directly connected to the packaging substrate 3 through the conductive bulge 11, the distance of the signal lead is directly shortened by the back-off mode, and the parasitic inductance can be made small, so that the problem that the parasitic inductance is too large introduced into the TSC packaging pin is solved, and the radio frequency performance of the chip is improved. A further advantage of the package of this embodiment over the package of a TSC is that the bottom package substrate 3 can be designed graphically. Signal routing or impedance matching may be performed on the multilayer substrate, and even some Surface Mounted Devices (SMDs) may be substantially made on the multilayer. This greatly increases the flexibility of design and also improves the degree of integration of the overall chip design. This is also a great advantage that TSC packaging cannot achieve.
In the description of the present application, it should be understood that the terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate an orientation or positional relationship based on that shown in the drawings, merely for convenience of description and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be configured and operated in a particular orientation, and thus should not be construed as limiting the present application.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "plurality" is at least two, such as two, three, etc., unless explicitly defined otherwise.
In this application, unless specifically stated and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; may be mechanically connected, may be electrically connected or may communicate with each other; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art as the case may be.
While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the application.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims and the equivalents thereof, the present application is intended to cover such modifications and variations.

Claims (11)

1. A chip package structure, comprising: a heat conducting block, a chip and a packaging substrate;
one side of the chip is connected with the heat conducting block; a conductive bulge is arranged on a bonding pad at the other side of the chip and is correspondingly and electrically connected with an electric connection area on one side surface of the packaging substrate; the other side of the packaging substrate is correspondingly provided with a packaging pin; the chip, the heat conducting block and the packaging substrate are packaged together.
2. The chip package structure according to claim 1, wherein a metal layer is provided on a side surface of the package substrate, the metal layer being divided into a plurality of electrical connection regions; the other side of the packaging substrate is provided with a packaging pin which is correspondingly and electrically connected with the electric connection area through a conductive hole penetrating through the thickness of the packaging substrate.
3. The chip packaging structure according to claim 2, wherein the packaging substrate comprises a plurality of layers of substrates, metal layers are arranged between the layers of substrates, a plurality of electric connection areas are arranged on the outer surface of the substrate positioned at the top layer, and packaging pins are arranged on the substrate positioned at the bottom layer; the metal layers are correspondingly and electrically connected through conductive holes penetrating through the thickness of the substrate.
4. A chip package structure according to claim 3, wherein the substrate is a resin substrate or a glass substrate or a silicon substrate.
5. The chip package structure of claim 2, wherein the electrical connection region comprises: a region for connection with the conductive bump, and a region for connection with the patch device.
6. The chip package structure of claim 1, wherein a surface area of the conductive bumps facing the chip is larger than a surface area of the chip connected to the conductive bumps.
7. The chip package structure according to claim 1, wherein the number of chips is at least two; at least two chips are arranged at intervals and are packaged together with the heat conducting block and the packaging substrate.
8. An integrated circuit board, comprising: a printed circuit board and a chip package structure according to any one of claims 1 to 7.
9. The integrated circuit board of claim 8, further comprising: a heat sink; the radiating fin is adhered to the surface of the heat conducting block, which is away from the chip, through heat conducting glue.
10. A method of packaging a chip, comprising:
connecting one side surface of the chip to the conductive block;
and correspondingly connecting the conductive protrusions corresponding to the bonding pads on the other side surface of the chip with the electric connection areas of the packaging substrate.
11. The packaging method of claim 10, further comprising, prior to the chip being connected to the package substrate:
forming a metal layer on one side surface of the packaging substrate, wherein the metal layer is divided into a plurality of electric connection areas;
a packaging pin is arranged on the other side of the packaging substrate;
and forming conductive holes penetrating through the thickness on the packaging substrate so that the packaging pins are correspondingly and electrically connected with the electric connection areas through the conductive holes.
CN202311805516.9A 2023-12-26 2023-12-26 Chip packaging structure, integrated circuit board and chip packaging method Pending CN117810179A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311805516.9A CN117810179A (en) 2023-12-26 2023-12-26 Chip packaging structure, integrated circuit board and chip packaging method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311805516.9A CN117810179A (en) 2023-12-26 2023-12-26 Chip packaging structure, integrated circuit board and chip packaging method

Publications (1)

Publication Number Publication Date
CN117810179A true CN117810179A (en) 2024-04-02

Family

ID=90419325

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202311805516.9A Pending CN117810179A (en) 2023-12-26 2023-12-26 Chip packaging structure, integrated circuit board and chip packaging method

Country Status (1)

Country Link
CN (1) CN117810179A (en)

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