CN117792141B - High-speed pulse circuit for capacitive and inductive loads - Google Patents
High-speed pulse circuit for capacitive and inductive loads Download PDFInfo
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- CN117792141B CN117792141B CN202410204462.9A CN202410204462A CN117792141B CN 117792141 B CN117792141 B CN 117792141B CN 202410204462 A CN202410204462 A CN 202410204462A CN 117792141 B CN117792141 B CN 117792141B
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- 230000001939 inductive effect Effects 0.000 title claims abstract description 46
- 230000005669 field effect Effects 0.000 claims abstract description 95
- 238000000034 method Methods 0.000 claims description 11
- 238000005520 cutting process Methods 0.000 claims description 4
- 238000007599 discharging Methods 0.000 abstract description 5
- 239000003990 capacitor Substances 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 8
- 239000000463 material Substances 0.000 description 4
- 238000004146 energy storage Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 239000000696 magnetic material Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000036278 prepulse Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Abstract
The invention relates to the technical field of high-voltage pulse, in particular to a high-speed pulse circuit for capacitive and inductive loads. The high-speed pulse circuit comprises a direct-current voltage source V1, a load and a high-speed pulse circuit connected between the direct-current voltage source V1 and the load; the high-speed pulse circuit comprises a first field effect transistor S1, a second field effect transistor S2, a third field effect transistor S3 and a diode D1. The invention controls the on and off of the field effect transistors by arranging the three N-channel field effect transistors and the diode, thereby outputting pulses with different widths and frequencies, simultaneously providing a fast discharging loop for the load capacitor by the simultaneous conduction of part of the field effect transistors according to different switching schemes of load properties, and providing reverse voltage for the load inductor by connecting the diode on the field effect transistor and the diode in the circuit in parallel when the load is inductive.
Description
Technical Field
The invention relates to the technical field of high-voltage pulse, in particular to a high-speed pulse circuit for capacitive and inductive loads.
Background
The basic principle of the pulse power supply is to control long-time accumulation and instantaneous release of charges, and the electric energy stored in the energy storage element is simultaneously released in a short time by using a fast switch, so as to obtain electric pulses with high amplitude. The circuit realizes energy storage through an inductor and a capacitor, and then pulse with a certain width is generated through periodical on and off of a switch. In such a pulse forming circuit, a certain time is required for the pulse voltage to drop to zero due to the discharging effect of the inductance and capacitance of the energy storage element.
In recent decades, power semiconductor devices have rapidly developed in terms of power processing capability and switching speed, and have become dominant switches in pulsed power sources with the advantages of small size, high repetition frequency, easy triggering, strong controllability, long life, high reliability, and the like. The serial-parallel connection of a plurality of devices in the circuit can lead to the increase of the system volume, the increase of the stray inductance and the distributed capacitance of the circuit, the longer discharge time, the increase of the rising edge and the falling edge time of the pulse, the deterioration of the waveform quality of the pulse output, and the further slowing of the falling edge of the pulse under the capacitive and inductive loads.
In a high power pulse trailing edge steepening circuit based on a magnetic switch, the magnetic switch has obvious defects that the magnetic switch is uncontrollable, the magnetic switch must be combined with the excellent controllability of the semiconductor switch to exert the fast on-state characteristic, besides, the magnetic core of the magnetic switch must be reset, the magnetic material is lost, the allowable temperature of the magnetic core can be exceeded when the magnetic switch is operated at the repetition frequency, the switching performance is deteriorated, and meanwhile, the magnetic switch can generate pre-pulses in the circuit.
The tail-biting circuit under capacitive load is only suitable for the condition that the load is capacitive, most of inductive devices are widely applied to production in modern times, and stray inductances are also arranged on the circuit under the condition that the circuit is long, and all inductances in the circuit can play a decisive role on the falling edge of pulses.
Disclosure of Invention
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and the appended drawings.
The invention aims to overcome the defects, and provides a high-speed pulse circuit for capacitive and inductive loads, which is characterized in that three N-channel field effect transistors and a diode are arranged to control the on and off of the field effect transistors, so that pulses with different widths and frequencies can be output, meanwhile, according to different switching schemes of load properties, when the load is capacitive, a loop for rapidly discharging is provided for the load capacitor through the simultaneous on of part of the field effect transistors, the falling process of the pulse is accelerated, the falling edge of the pulse is steeped, when the load is inductive, the diode on the field effect transistor and the diode in the circuit are connected in parallel, the reverse voltage is provided for the load inductor, the falling edge of the pulse is accelerated, and when the load current drops to 0, the field effect transistor is cut off, and the back pressure automatically disappears.
The invention provides a high-speed pulse circuit for capacitive and inductive loads, which comprises a direct-current voltage source V1, a load and a high-speed pulse circuit connected between the direct-current voltage source V1 and the load; the high-speed pulse circuit comprises a first field effect transistor S1, a second field effect transistor S2, a third field effect transistor S3 and a diode D1;
The positive pole of the direct current voltage source V1 is connected with the drain electrode of the first field effect tube S1 and the negative pole of the diode D1, the drain electrode of the second field effect tube S2 is connected with the source electrode of the first field effect tube S1, the positive pole of the diode D1 is connected with the drain electrode of the third field effect tube S3, the negative pole of the direct current voltage source V1 is connected with the source electrode of the second field effect tube S2 and the source electrode of the third field effect tube S3, the positive pole of the load is connected with the drain electrode of the second field effect tube S2 and the source electrode of the first field effect tube S1, and the negative pole of the load is connected with the positive pole of the diode D1 and the drain electrode of the third field effect tube S3.
In some embodiments, the first fet S1, the second fet S2, and the third fet S3 are all N-channel fets.
In some embodiments, the load is a capacitive load or an inductive load.
In some embodiments, when the load is a capacitive load, the output pulse voltage includes three phases:
charging: the direct-current voltage source V1 charges the capacitive load, the first field effect transistor S1 and the third field effect transistor S3 are conducted, and the capacitive load obtains high voltage during the period that the first field effect transistor S1 and the third field effect transistor S3 are conducted simultaneously;
Discharge phase: the first field effect tube S1 is disconnected, the second field effect tube S2 and the third field effect tube S3 are conducted, a closed loop is formed among the capacitive load, the second field effect tube S2 and the third field effect tube S3, the capacitive load is rapidly discharged, and the output pulse voltage dropping process is accelerated;
and (3) zeroing: the capacitive load voltage drops to zero, turning off the second fet S2.
In some embodiments, when the load is an inductive load, the output pulsed voltage comprises two phases:
The charging stage comprises the steps that a direct-current voltage source V1 charges an inductive load, a first field effect tube S1 and a third field effect tube S3 are conducted, and the inductive load obtains high voltage during the period that the first field effect tube S1 and the third field effect tube S3 are conducted simultaneously;
Tail cutting stage: after the inductive load is charged, the first field effect transistor S1 is cut off, and a diode D1 and a diode on the second field effect transistor S2 are connected in parallel to provide reverse voltage for the inductive load, so that a rapid falling edge is obtained.
In some embodiments, during the charging phase, the voltage of the dc voltage source V1 to the inductive load is positive and negative, and during the tail-biting phase, the dc voltage source V1 outputs a reverse voltage to the inductive load, so that the current on the inductor in the inductive load drops rapidly.
In some embodiments, the width and frequency of the output pulses are controlled by controlling the turning on and off of the first fet S1 and the third fet S3.
By adopting the technical scheme, the invention has the beneficial effects that:
the invention controls the on and off of the field effect transistors by arranging the three N-channel field effect transistors and the diode, thereby outputting the pulses with different widths and frequencies, simultaneously effectively reducing the time of the falling edge of the pulse according to different switching schemes of load properties, steepening the falling edge of the pulse, and being suitable for occasions with strict speed requirements on the output edge of the pulse.
The high-speed pulse circuit of the invention provides a fast discharging loop for the load capacitor through the simultaneous conduction of part of the field effect transistors when the load is capacitive, accelerates the pulse falling process, steepens the pulse falling edge, provides reverse voltage for the load inductor through connecting the diode on the field effect transistor with the diode in the circuit in parallel when the load is inductive, accelerates the pulse falling process, steepens the pulse falling edge, cuts off the field effect transistor when the load current drops to 0, and automatically eliminates the back pressure.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
It is apparent that these and other objects of the present invention will become more apparent from the following detailed description of the preferred embodiments, which is to be read in connection with the accompanying drawings and figures.
The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of the preferred embodiments, as illustrated in the accompanying drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate the invention and together with the embodiments of the invention, serve to explain the invention, without limitation to the invention.
In the drawings, like parts are designated with like reference numerals and are illustrated schematically and are not necessarily drawn to scale.
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are only one or several embodiments of the invention, and that other drawings can be obtained according to such drawings without inventive effort to a person skilled in the art.
FIG. 1 is a schematic diagram of a high-speed pulse circuit according to some embodiments of the present invention;
FIG. 2 is a schematic diagram of an equivalent circuit of a load according to some embodiments of the present invention when a high voltage is obtained;
FIG. 3 is a schematic diagram of an equivalent circuit for accelerating the falling edge of a capacitive load according to some embodiments of the invention;
Fig. 4 is a schematic diagram of an equivalent circuit for accelerating the falling edge process of an inductive load according to some embodiments of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described in detail with reference to the following detailed description. It should be understood that the detailed description is presented merely to illustrate the invention, and is not intended to limit the invention.
In addition, in the description of the present invention, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the drawings, are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. However, it is noted that direct connection indicates that the two bodies connected together do not form a connection relationship through a transition structure, but are connected together to form a whole through a connection structure. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
In the present invention, unless expressly stated or limited otherwise, a first feature "up" or "down" a second feature may be the first and second features in direct contact, or the first and second features in indirect contact via an intervening medium. In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Referring to fig. 1, fig. 1 is a schematic diagram of a high-speed pulse circuit according to some embodiments of the invention.
According to some embodiments of the present invention, there is provided a high-speed pulse circuit for capacitive and inductive loads, including a dc voltage source V1, a load, and a high-speed pulse circuit connected between the dc voltage source V1 and the load; the high-speed pulse circuit comprises a first field effect transistor S1, a second field effect transistor S2, a third field effect transistor S3 and a diode D1;
the first field effect transistor S1, the second field effect transistor S2 and the third field effect transistor S3 are N-channel field effect transistors, and the load is capacitive load or inductive load;
The positive pole of the direct current voltage source V1 is connected with the drain electrode of the first field effect tube S1 and the negative pole of the diode D1, the drain electrode of the second field effect tube S2 is connected with the source electrode of the first field effect tube S1, the positive pole of the diode D1 is connected with the drain electrode of the third field effect tube S3, the negative pole of the direct current voltage source V1 is connected with the source electrode of the second field effect tube S2 and the source electrode of the third field effect tube S3, the positive pole of the load is connected with the drain electrode of the second field effect tube S2 and the source electrode of the first field effect tube S1, and the negative pole of the load is connected with the positive pole of the diode D1 and the drain electrode of the third field effect tube S3.
Referring to fig. 2, fig. 2 is an equivalent circuit schematic diagram of a load according to some embodiments of the present invention when a high voltage is obtained.
According to some embodiments of the present invention, optionally, when the load is a capacitive load, the charging stage, the dc voltage source V1 charges the capacitive load, the first fet S1 and the third fet S3 are turned on, and the capacitive load obtains a high voltage during the period in which the first fet S1 and the third fet S3 are turned on simultaneously;
When the load is an inductive load, in a charging stage, the direct-current voltage source V1 charges the inductive load, the first field effect tube S1 and the third field effect tube S3 are conducted, and the inductive load obtains high voltage during the period that the first field effect tube S1 and the third field effect tube S3 are conducted simultaneously;
the width and frequency of the output pulse are controlled by controlling the on and off of the first field effect transistor S1 and the third field effect transistor S3.
Referring to fig. 3, fig. 3 is an equivalent circuit schematic diagram of a capacitive load falling edge process acceleration according to some embodiments of the present invention.
According to some embodiments of the present invention, optionally, when the load is a capacitive load, in a discharging stage, the first fet S1 is turned off, the second fet S2 and the third fet S3 are turned on, a closed loop is formed among the capacitive load, the second fet S2 and the third fet S3, and the capacitive load is rapidly discharged, so as to accelerate a voltage drop process of an output pulse; and in the zeroing stage, the capacitive load voltage is reduced to zero, and the second field effect transistor S2 is disconnected.
Referring to fig. 4, fig. 4 is an equivalent circuit diagram of a process for accelerating a falling edge of an inductive load according to some embodiments of the present invention.
According to some embodiments of the present invention, optionally, when the load is an inductive load, the tail-cutting stage is entered after the inductive load is charged, the first fet S1 is turned off, and a reverse voltage is provided to the inductive load by connecting the diode on the second fet S2 in parallel with the diode D1, so as to obtain a fast falling edge.
In the charging stage, the voltage of the direct-current voltage source V1 to the inductive load is positive and negative, and in the tail cutting stage, the direct-current voltage source V1 outputs reverse voltage to the inductive load, so that the current on the inductor in the inductive load is rapidly reduced.
It is to be understood that the disclosed embodiments are not limited to the specific process steps or materials disclosed herein, but are intended to extend to equivalents of such features as would be understood by one of ordinary skill in the relevant arts. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting.
Reference in the specification to "an embodiment" means that a particular feature, or characteristic, described in connection with the embodiment is included in at least one embodiment of the invention. Thus, appearances of the phrase or "an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment.
Furthermore, the described features or characteristics may be combined in any other suitable manner in one or more embodiments. In the above description, certain specific details are provided, such as thicknesses, numbers, etc., to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention can be practiced without one or more of the specific details, or with other methods, components, materials, etc.
Claims (4)
1. A high-speed pulse circuit for capacitive and inductive loads, which is characterized by comprising a direct-current voltage source V1, a load and a high-speed pulse circuit connected between the direct-current voltage source V1 and the load; the high-speed pulse circuit comprises a first field effect transistor S1, a second field effect transistor S2, a third field effect transistor S3 and a diode D1;
The positive electrode of the direct current voltage source V1 is connected with the drain electrode of the first field effect tube S1 and the negative electrode of the diode D1, the drain electrode of the second field effect tube S2 is connected with the source electrode of the first field effect tube S1, the positive electrode of the diode D1 is connected with the drain electrode of the third field effect tube S3, the negative electrode of the direct current voltage source V1 is connected with the source electrode of the second field effect tube S2 and the source electrode of the third field effect tube S3, the positive electrode of the load is connected with the drain electrode of the second field effect tube S2 and the source electrode of the first field effect tube S1, and the negative electrode of the load is connected with the positive electrode of the diode D1 and the drain electrode of the third field effect tube S3;
When the load is a capacitive load, the output pulse voltage includes three phases:
charging: the direct-current voltage source V1 charges the capacitive load, the first field effect transistor S1 and the third field effect transistor S3 are conducted, and the capacitive load obtains high voltage during the period that the first field effect transistor S1 and the third field effect transistor S3 are conducted simultaneously;
Discharge phase: the first field effect tube S1 is disconnected, the second field effect tube S2 and the third field effect tube S3 are conducted, a closed loop is formed among the capacitive load, the second field effect tube S2 and the third field effect tube S3, the capacitive load is rapidly discharged, and the output pulse voltage dropping process is accelerated;
And (3) zeroing: the capacitive load voltage drops to zero, and the second field effect transistor S2 is disconnected;
when the load is an inductive load, the output pulse voltage includes two phases:
The charging stage comprises the steps that a direct-current voltage source V1 charges an inductive load, a first field effect tube S1 and a third field effect tube S3 are conducted, and the inductive load obtains high voltage during the period that the first field effect tube S1 and the third field effect tube S3 are conducted simultaneously;
Tail cutting stage: after the inductive load is charged, the first field effect transistor S1 is cut off, and a diode D1 and a diode on the second field effect transistor S2 are connected in parallel to provide reverse voltage for the inductive load, so that a rapid falling edge is obtained.
2. The high-speed pulse circuit for capacitive and inductive loads according to claim 1, wherein the first fet S1, the second fet S2, and the third fet S3 are all N-channel fets.
3. The high-speed pulse circuit for capacitive and inductive loads according to claim 1, wherein when the load is an inductive load, the voltage of the dc voltage source V1 to the inductive load is positive and negative during the charging phase, and the dc voltage source V1 outputs a reverse voltage to the inductive load during the tail-biting phase, so that the current on the inductor in the inductive load drops rapidly.
4. The high-speed pulse circuit for capacitive and inductive loads according to claim 1, wherein the width and frequency of the output pulses are controlled by controlling the on and off of the first fet S1 and the third fet S3.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202410204462.9A CN117792141B (en) | 2024-02-24 | 2024-02-24 | High-speed pulse circuit for capacitive and inductive loads |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202410204462.9A CN117792141B (en) | 2024-02-24 | 2024-02-24 | High-speed pulse circuit for capacitive and inductive loads |
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| CN117792141A CN117792141A (en) | 2024-03-29 |
| CN117792141B true CN117792141B (en) | 2024-04-26 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR790002005B1 (en) * | 1975-08-30 | 1979-12-30 | 모리다 아끼오 | Amplifier for pulse width modulated signals |
| CN102970011A (en) * | 2012-11-13 | 2013-03-13 | 海能达通信股份有限公司 | Load device, power line and reverse connection preventing device |
| CN106982048A (en) * | 2017-02-07 | 2017-07-25 | 宁波大学 | Preemphasized signal generation circuit based on current selector |
| CN115800746A (en) * | 2023-01-30 | 2023-03-14 | 海的电子科技(苏州)有限公司 | Hard feedback load voltage compensation circuit and method |
| CN219893307U (en) * | 2023-06-20 | 2023-10-24 | 深圳市一飞通讯技术有限公司 | Drive circuit and drive assembly for magneto-optical switch |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009086143A (en) * | 2007-09-28 | 2009-04-23 | Panasonic Corp | Capacitive load driving circuit and plasma display panel |
| CN116470786A (en) * | 2023-05-05 | 2023-07-21 | 南京理工大学 | Switch capacitance type pulse power supply for electric spark machining |
-
2024
- 2024-02-24 CN CN202410204462.9A patent/CN117792141B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR790002005B1 (en) * | 1975-08-30 | 1979-12-30 | 모리다 아끼오 | Amplifier for pulse width modulated signals |
| CN102970011A (en) * | 2012-11-13 | 2013-03-13 | 海能达通信股份有限公司 | Load device, power line and reverse connection preventing device |
| CN106982048A (en) * | 2017-02-07 | 2017-07-25 | 宁波大学 | Preemphasized signal generation circuit based on current selector |
| CN115800746A (en) * | 2023-01-30 | 2023-03-14 | 海的电子科技(苏州)有限公司 | Hard feedback load voltage compensation circuit and method |
| CN219893307U (en) * | 2023-06-20 | 2023-10-24 | 深圳市一飞通讯技术有限公司 | Drive circuit and drive assembly for magneto-optical switch |
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| CN117792141A (en) | 2024-03-29 |
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