CN111338418B - Variable slope discharge driving circuit - Google Patents
Variable slope discharge driving circuit Download PDFInfo
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- CN111338418B CN111338418B CN202010300236.2A CN202010300236A CN111338418B CN 111338418 B CN111338418 B CN 111338418B CN 202010300236 A CN202010300236 A CN 202010300236A CN 111338418 B CN111338418 B CN 111338418B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
Abstract
A variable slope discharge driving circuit is provided, wherein a main discharge branch circuit using a first withstand voltage NMOS tube as a switching tube and an auxiliary discharge branch circuit comprising a fourth withstand voltage PMOS tube, a third withstand voltage NMOS tube and a third resistor are designed, and the discharge slope of a high-side power tube is controlled in a segmented manner by controlling two discharge branch circuits by utilizing the discharge capacity of different stages in the discharge stage of the high-side power tube. In the initial stage of discharging the high-side power tube, firstly, starting an auxiliary discharging branch to discharge the gate source voltage of the high-side power tube to the Miller platform, and then starting a main discharging branch to enable the high-side power tube to be in stable transition from the Miller platform; then the auxiliary discharge branch is closed, and the high-side power tube is quickly closed by the main discharge branch. The invention realizes that the variable slope segmented discharge drives the power tube, and can effectively avoid EMI interference caused by single-speed rapid discharge power tube grid capacitance; the charge pump is used for replacing a level shifter to obtain a high-voltage signal, so that the circuit is simplified, and the working performance and the safety and reliability of the driving circuit are improved.
Description
Technical Field
The invention belongs to the technical field of analog integrated circuits, and particularly relates to a variable slope discharge driving circuit.
Background
The active control grid driving circuit is one of core circuits of half-bridge application (such as a synchronous buck converter), and directly influences the reliability and performance index of the operation of the switching power supply. For a high-side power transistor, an N-type metal oxide semiconductor field effect transistor (NMOSFET) has higher driving efficiency and smaller device area than a P-type metal oxide semiconductor field effect transistor (PMOSFET), so the NMOSFET is more suitable as a power transistor. For power application, especially high-power application, large dV/dt and dI/dt exist in system driving, EMI radiation is serious, and crosstalk problem is easily caused. One important source of EMI interference (electromagnetic interference) and crosstalk problems is dV/dt and dI/dt interference caused by fast charging and discharging of power switching tubes.
The traditional driving circuit can generate higher EMI interference in the moment of fast switching on and switching off, and has serious influence on the reliability of a chip.
Disclosure of Invention
Aiming at the problem of high EMI during discharge of the traditional drive circuit, the invention provides a variable-slope discharge drive circuit, which controls the discharge slope of a power switch tube by utilizing the discharge capacity of different stages in the discharge stage of the power tube and has the characteristics of high speed, low EMI and high reliability.
The technical scheme of the invention is as follows:
a variable slope discharge drive circuit inputs a gate logic control signal of a high-side power tube in a DC-DC converter, outputs a signal connected with the gate of the high-side power tube, and comprises a level shifter, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a first resistor, a third resistor, a first capacitor, a first NMOS tube, a first voltage-resistant NMOS tube, a second voltage-resistant NMOS tube, a third voltage-resistant NMOS tube, a second voltage-resistant PMOS tube, a third voltage-resistant PMOS tube and a fourth voltage-resistant PMOS tube;
the input end of the level shifter is connected with the input signal of the variable slope discharging driving circuit, and the output end of the level shifter is connected with the input end of the first phase inverter; the level shifter is used for boosting an input signal of the variable slope discharging driving circuit in a low power supply rail voltage domain to a high power supply rail voltage domain, wherein the low power supply rail is from low power supply voltage to ground level, and the high power supply rail is from high power supply voltage to ground level;
the input end of the second inverter is connected with the output end of the first inverter and is connected with the high power supply voltage after passing through the first resistor, and the output end of the second inverter outputs a first control signal and is connected with the input end of the third inverter, the grid electrode of the second withstand voltage NMOS tube and the grid electrode of the second withstand voltage PMOS tube;
the output end of the third inverter outputs a second control signal and is connected with the input end of the fourth inverter and one end of the first capacitor;
charging the second control signal to obtain a third control signal, wherein a power rail of the third control signal obtained after charging is from twice high power voltage to high power voltage; the third control signal is connected with the grid electrode of the first NMOS tube and is used for charging the high-side power tube;
the drain electrode of the first NMOS tube is connected with the source electrode of the second voltage-resistant PMOS tube and the grid electrode of the third voltage-resistant PMOS tube and is connected with the high power supply voltage, and the source electrode of the first NMOS tube is connected with the other end of the first capacitor, the source electrode of the third voltage-resistant PMOS tube and the substrate of the second voltage-resistant PMOS tube;
the drain electrode of the second voltage-resistant NMOS tube is connected with the drain electrode of the second voltage-resistant PMOS tube, the drain electrode of the third voltage-resistant PMOS tube and the grid electrode of the first voltage-resistant NMOS tube, and the source electrode of the second voltage-resistant NMOS tube is connected with the ground level;
the grid electrode of the fourth voltage-withstanding PMOS tube is connected with the source electrode of the first voltage-withstanding NMOS tube and the connection point of the high-side power tube and the low-side power tube in the DC-DC converter, the source electrode of the fourth voltage-withstanding PMOS tube is connected with the drain electrode of the first voltage-withstanding NMOS tube and outputs the output signal of the variable-slope discharge driving circuit, and the drain electrode of the fourth voltage-withstanding PMOS tube is connected with the drain electrode of the third voltage-withstanding NMOS tube after passing through the third resistor;
the grid electrode of the third voltage-resistant NMOS tube is connected with the signal of the output signal of the fourth inverter after passing through the fifth inverter, and the source electrode of the third voltage-resistant NMOS tube is connected with the ground level.
Specifically, the variable slope discharge driving circuit further comprises a first voltage-withstanding PMOS tube, a second resistor and a second capacitor, wherein one end of the second resistor is connected with the high power supply voltage, and the other end of the second resistor is connected with a grid electrode of the first voltage-withstanding PMOS tube and is connected with a ground level through the second capacitor; the source electrode of the first voltage-resistant PMOS tube is connected with the third control signal, and the drain electrode of the first voltage-resistant PMOS tube is connected with the grid electrode of the high-side power tube.
Specifically, the first inverter, the second inverter, the third inverter, the fourth inverter and the fifth inverter are inverters with amplification functions.
The invention has the beneficial effects that: the invention provides variable slope discharge driving for the gate capacitor of a high-side power tube of a DC-DC converter, and two discharge paths are designed to control the discharge speed, so that the purpose of driving the power tube by variable slope sectional discharge is realized, and EMI interference caused by the gate capacitor of the power tube rapidly discharged at a single speed can be effectively avoided; the charge pump is used for replacing a level shifter to obtain a high-voltage signal, so that the circuit is simplified, and the working performance and the safety and reliability of the driving circuit are improved.
Drawings
Fig. 1 is a schematic structural diagram of a variable slope discharge driving circuit according to the present invention.
Fig. 2 is a schematic diagram of a variable slope discharge driving circuit according to the present invention during discharging.
Fig. 3 is a schematic diagram of a variable slope discharging driving circuit according to the present invention during charging.
Detailed Description
The invention is further illustrated with reference to the figures and the specific examples.
The invention provides a variable slope discharge driving circuit which can be applied to a DC-DC converter and is used for controlling a power tube in the DC-DC converter, wherein the DC-DC converter comprises a high-side power tube and a low-side power tube, the connection point of the high-side power tube and the low-side power tube is a switch node SW, and the EMI of the switch node SW mainly comes from the action of the switch tube, so that the variable slope discharge driving circuit can control the discharge speed by driving a grid electrode of the high-side power tube and controlling a discharge branch of a grid capacitor of the high-side power tube.
Fig. 1 is a schematic structural diagram of a variable slope discharge driving circuit according to the present invention, which includes a level shifter LS, a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, a first resistor R1, a third resistor R3, a first capacitor C1, a first NMOS transistor MN1, a first withstand voltage NMOS transistor MHN1, a second withstand voltage NMOS transistor MHN2, a third withstand voltage NMOS transistor MHN3, a second withstand voltage PMOS transistor MHP2, a third withstand voltage PMOS transistor MHP3, and a fourth withstand voltage PMOS transistor MHP 4. The input end of the level shifter LS is connected to the input signal of the variable slope discharging driving circuit, the output end of the level shifter LS is connected to the input end of the first inverter INV1, and the input signal of the variable slope discharging driving circuit is the gate logic control signal H _ ctrl of the high-side power tube in the DC-DC converter. The level shifter is used for lifting an input signal of the variable slope discharging driving circuit in a low power supply rail voltage domain to a high power supply rail voltage domain, wherein the low power supply rail is from a low power supply voltage VDDL to a ground level, and the high power supply rail is from a high power supply voltage VDDH to the ground level; the input end of the second inverter INV2 is connected to the output end of the first inverter INV1, is connected to the high power supply voltage VDDH after passing through the first resistor R1, and the output end thereof outputs the first control signal H _1 and is connected to the input end of the third inverter INV3, the gate of the second withstand voltage NMOS transistor MHN2 and the gate of the second withstand voltage PMOS transistor MHP 2; an output end of the third inverter INV3 outputs a second control signal H _ INV1, and is connected with an input end of the fourth inverter INV4 and one end of the first capacitor C1; charging the second control signal H _ inv1 to obtain a third control signal H _2, wherein the power supply rail of the charged third control signal H _2 is from two times the high power supply voltage 2VDDH to the high power supply voltage VDDH; the third control signal H _2 is connected to the gate of the first NMOS transistor MN1 and is used to charge the high-side power transistor; a drain of the first NMOS transistor MN1 is connected to a source of the second withstand voltage PMOS transistor MHP2 and a gate of the third withstand voltage PMOS transistor MHP3 and is connected to the high power supply voltage VDDH, and a source thereof is connected to the other end of the first capacitor C1, a source of the third withstand voltage PMOS transistor MHP3 and a substrate of the second withstand voltage PMOS transistor MHP 2; the drain electrode of the second withstand voltage NMOS tube MHN2 is connected with the drain electrode of the second withstand voltage PMOS tube MHP2, the drain electrode of the third withstand voltage PMOS tube MHP3 and the grid electrode of the first withstand voltage NMOS tube MHN1, and the source electrode thereof is connected with the ground level; the grid electrode of a fourth voltage-withstanding PMOS tube MHP4 is connected with the source electrode of a first voltage-withstanding NMOS tube MHN1 and a connecting point of a high-side power tube and a low-side power tube in the DC-DC converter, namely an open joint point SW, the source electrode of the fourth voltage-withstanding PMOS tube MHP4 is connected with the drain electrode of a first voltage-withstanding NMOS tube MHN1, an output signal of a variable-slope discharge driving circuit is output and is connected with the grid electrode of the high-side power tube, and the drain electrode of the fourth voltage-withstanding PMOS tube MHP4 is connected with the drain electrode of; the gate of the third voltage-withstanding NMOS MHN3 is connected to the signal of the output signal of the fourth inverter INV4 after passing through the fifth inverter INV5, and the source thereof is connected to ground.
In some embodiments, the variable slope discharge driving circuit further comprises a first voltage-withstanding PMOS transistor MHP1, a second resistor R2, and a second capacitor C2, wherein one end of the second resistor R2 is connected to the high power supply voltage VDDH, and the other end is connected to the gate of the first voltage-withstanding PMOS transistor MHP1 and is connected to the ground level through the second capacitor C2; the source of the first voltage-withstanding PMOS transistor MHP1 is connected to the third control signal H _2, and the drain is connected to the gate of the high-side power transistor. The third control signal H _2 is controlled to charge the gate capacitor of the high-side power transistor by adding a switching function. Although the driving circuit provided by the invention is used for controlling discharging, in order to ensure that the charging branch has sufficient driving capability, the first inverter INV1, the second inverter INV2, the third inverter INV3, the fourth inverter INV4 and the fifth inverter INV5 can also be preferably arranged as inverters with amplification function.
The invention adopts a variable slope discharging strategy, and controls the discharging slope of the power switch tube by utilizing the discharging capability of different stages aiming at the discharging stage of the power tube. The invention mainly comprises two branches, as shown in fig. 2, one branch is a main discharge branch a which takes a first withstand voltage NMOS tube MHN1 as a switching tube and is connected with a load for discharging from the switching node SW, and the other branch is an auxiliary discharge branch b which consists of a fourth withstand voltage PMOS tube MHP4, a third withstand voltage NMOS tube MHN3 and a third resistor R3 and is discharged to the ground. The invention optimizes the grid drive discharge process of the power tube by increasing the discharge branch circuits at the initial discharge stage, thereby realizing the purposes of rapidness, low EMI (electro-magnetic interference) and high reliability. In addition, the main discharging branch circuit of the present invention also utilizes the charge pump capacitor (i.e. the first capacitor C1) to shift the level discharging control signal to turn on the discharging tube in the high-side driving circuit, so as to avoid an additional level shifter to shift the control signal.
The gate logic control signal H _ ctrl of the high-side power transistor is a signal in a voltage domain of the low power supply voltage VDDL, and first the gate logic control signal H _ ctrl in the voltage domain of the low power supply rail, i.e., VDDL, needs to be lifted to the voltage domain of the high power supply rail, i.e., VDDH, through the level shifter LS, where the low level of the voltage domain of VDDL is the ground level GND, the high level of the voltage domain of VDDL is the low power supply voltage VDDL, the low level of the voltage domain of VDDH is the ground level GND, and the high level of the voltage domain of VDDH is the high power supply voltage VDDH.
The grid logic control signal H _ ctrl after being lifted by the level shifter passes through two inverters INV1 and INV2 to obtain a first control signal H _1 which is in phase with the grid logic control signal H _ ctrl, and the first control signal H _1 controls a voltage-withstanding inverter consisting of a second voltage-withstanding PMOS tube MHP2 and a second voltage-withstanding NMOS tube MHN2 to realize charging and discharging of the grid voltage of the first voltage-withstanding NMOS tube MHN 1. The first control signal H _1 passes through the third inverter INV3 to obtain the second control signal H _ INV1 inverted from the gate logic control signal H _ ctrl.
The second control signal H _ inv1 boosts the voltage through the first capacitor C1 to obtain a signal H _3, and the voltage difference between the signal H _3 and the high power supply voltage VDDH controls the switching of the third voltage-withstanding PMOS transistor MHP 3. When the third withstand voltage PMOS transistor MHP3 is turned on, the switch transistor of the main discharge branch, i.e., the gate input capacitor of the first withstand voltage NMOS transistor MHN1, can be connected to the H _3 signal of the upper plate of the first capacitor C1, and the charge on the first capacitor C1 is transferred to the gate input capacitor of the first withstand voltage NMOS transistor MHN1 to charge the first capacitor C1, so that the gate voltage of the first withstand voltage NMOS transistor MHN1 is raised, and therefore the first withstand voltage NMOS transistor MHN1 is quickly turned on by adopting a charge sharing technology. The second voltage-withstanding PMOS transistor MHP2 is turned on during driving discharge, and is used for keeping the grid voltage signal of the first voltage-withstanding NMOS transistor MHN1 stable at the high power supply voltage VDDH, and turning on the first voltage-withstanding NMOS transistor MHN1 to enable the grid driving signal HDRV of the high-side power transistor to discharge the grid capacitor of the high-side power transistor. Even if the gate voltage of the first voltage-withstanding NMOS transistor MHN1 is too high and the second voltage-withstanding PMOS transistor MHP2 is turned on in the reverse direction, the gate of the first voltage-withstanding NMOS transistor MHN1 is discharged to the high power voltage VDDH, but is finally clamped at the high power voltage VDDH by the second voltage-withstanding PMOS transistor MHP 2. Since the drain voltage of second voltage-withstanding PMOS transistor MHP2 can reach higher than high power supply voltage VDDH, in order to ensure the normal use of second voltage-withstanding PMOS transistor MHP2, the substrate of second voltage-withstanding PMOS transistor MHP2 is connected to the highest potential in the module, i.e., the H _3 signal.
The power transistor gate drive includes charging and discharging, the second control signal H _ inv1 is boosted to the third control signal H _2 by the charging branch, and the boosted third control signal H _2 is in phase with the gate logic control signal H _ ctrl in the VDDH-2VDDH voltage domain. The third control signal H _2 is used to control the switching of the first NMOS transistor MN1 and to supplement the charge to the first capacitor C1, and in some embodiments, a first voltage-withstanding PMOS transistor MHP1 is provided, and the third control signal H _2 enables the high-side power transistor gate driving signal HDRV to charge the high-side power transistor gate capacitor by controlling the first voltage-withstanding PMOS transistor MHP 1. The first resistor R1 provides an initial value for the gate driving signal HDRV, and the second resistor R2 and the second capacitor C2 are connected in series to provide a stable VDDH voltage for the gate of the first voltage-withstanding PMOS transistor MHP 1. The second voltage-withstanding NMOS tube MHN2 is used for discharging the grid electrode of the first voltage-withstanding NMOS tube MHN1 when the grid electrode of the high-side power tube is driven to charge, and the main branch of the discharging HDRV is cut off.
An auxiliary discharge branch is composed of a fourth voltage-resistant PMOS tube MHP4 and a third voltage-resistant NMOS tube MHN3, and the discharge current of the fourth voltage-resistant PMOS tube MHP4 and the gate source voltage V of a high-side power tubeGS_MHProportionally, the voltage-ampere characteristics of the transistor in the saturation region. During gate drive discharge, if VGS_MHAnd after the voltage is lower than the threshold voltage of a fourth voltage-resistant PMOS tube MHP4, the discharge branch is turned off.
During the switching of the power tube, the specific charge and discharge processes are driven as follows:
when the gate logic control signal H _ ctrl of the high-side power transistor goes low (GND), the gate driving signal HDRV controlling the high-side power transistor is discharged, and the states of the signals in the circuit are as shown in fig. 2. The first control signal H _1 is jumped low (GND), the third control signal H _2 is jumped low (VDDH), the signal H _3 is jumped high (2VDDH), the second control signal H _ inv1 is jumped high (VDDH), the first voltage-resistant PMOS tube MHP1 is closed, and the discharge branch circuit is controlled to be opened. The variable slope discharge driving circuit comprises two discharge branches, namely a main discharge branch a which is shown in fig. 2 and is discharged from SW back to load by taking a first withstand voltage NMOS tube MHN1 as a switching tube, and an auxiliary discharge branch b which is discharged to the ground and consists of a fourth withstand voltage PMOS tube MHP4, a third withstand voltage NMOS tube MHN3 and a third resistor R3. The specific grid electrode driving discharge process is described by combining two discharge branches, the specific variable-slope discharge driving discharge process is divided into three stages, and a slow-fast segmented driving strategy is adopted:
(1) the source grid voltage of the fourth voltage-resistant PMOS transistor MHP4, i.e. the grid source voltage V of the high-side power transistorGS_MHWhen the high-side power tube is started, the voltage is certainly larger than the threshold voltage, so that the third voltage-withstanding PMOS tube MHP3 is started after the high-side power tube is conducted, the gate logic control signal H _ ctrl jumps low, and after the second control signal H _ inv1 jumps high, the third voltage-withstanding NMOS tube MHN3 is controlled to be started, and the auxiliary discharge branch b from HDRV to GND starts to discharge V towards GNDGS_MHTo the left and right of the miller platform.
(2) When the low side power transistor is off and the high side power transistor is on, the voltage across the first capacitor C1 is charged to the high supply voltage VDDH. When the driving is discharged, after the second control signal H _ inv1 is jumped, the second control signal H _ inv1 controls the signal H _3 to be boosted to 2VDDH, the third voltage-withstanding PMOS tube MHP3 is started, the grid capacitor of the first voltage-withstanding NMOS tube MHN1 and the upper-stage plate of the first capacitor C1 are connected, and the grid voltage of the first voltage-withstanding NMOS tube MHN1 is quickly changed from zero to VDDH. Simultaneously, a third withstand voltage PMOS tube MHP3 which is turned off and a second withstand voltage PMOS tube MHP2 which is turned on are adopted to keep the grid voltage of a first withstand voltage NMOS tube MHN1 stable at VDDH, the first withstand voltage NMOS tube MHN1 slightly delays to turn on a main discharge branch a which discharges from a SW point than the third withstand voltage NMOS tube MHN3, two discharge branches discharge at the same time in the stage, and the main discharge branch a discharges at the V pointGS_MHThe Miller platform area discharges rapidly;
(3)VGS_MHafter lowering below the Miller plateau, wait for VHDRV-VSW<VTH,MHP4Then, the third voltage-resistant PMOS tube MHP3 is turned off, the auxiliary discharge branch b from the discharge HDRV to the GND is turned off in time, and only the discharge from the main discharge branch a is carried out. And the second voltage-withstanding PMOS transistor MHP2 maintains the gate voltage of the first voltage-withstanding NMOS transistor MHN1 to VDDH, ensuring the opening of the main discharge branch a. When the low-side power tube is started, the first withstand voltage NMOS tube MHN1 is kept in a starting state, and the first withstand voltage NMOS tube MHN1 is closed until the HDRV is required to be charged next time to start the high-side power tube, so that the reliability of the high-side power tube in turn-off is ensured.
When the gate logic control signal H _ ctrl goes high (VDDL), the charging of HDRV is controlled, and the states of the signals in the circuit are as shown in fig. 3. The first control signal H _1 is high (VDDH), the third control signal H _2 is high (2VDDH), the signal H _3 is low (VDDH), the second control signal H _ inv1 is low (GND), the discharging branch is controlled to be closed, and the first voltage-resistant PMOS tube MHP1 is turned on to charge HDRV. The second control signal H _ inv1 controls the third withstand voltage NMOS tube MHN3 to be turned off, and the auxiliary discharge branch b is turned off; meanwhile, the first NMOS transistor MN1 is turned on, the first capacitor C1 is connected to VDDH to supplement charges to the first capacitor C1, the second control signal H _ inv1 is raised to VDDH through the first capacitor C1, the signal H _3 controls the third withstand voltage PMOS transistor MHP3 to be turned off, the first control signal H _1 controls the second withstand voltage NMOS transistor MHN2 to be turned on, the second withstand voltage PMOS transistor MHP2 to be turned off, the gate of the first withstand voltage NMOS transistor MHN1 is discharged to the ground, the first withstand voltage NMOS transistor MHN1 is guaranteed to be turned off, and the main discharging branch a is turned off.
Through the above analysis of the variable slope gate discharge process of the power switching tube, it can be seen that: firstly, the grid source voltage of the high-side power tube is quickly reduced to a Miller platform by utilizing gradually reduced current, when the high-side power tube needs to be turned off, the grid logic control signal H _ ctrl of the high-side power tube is low, at the moment, the first control signal H _1 is low, the third control signal H _2 is low, the second control signal H _ inv1 is high, the auxiliary discharge tube, namely the third voltage-resistant NMOS tube MHN3 is firstly controlled to be turned on, and the grid source voltage V of the high-side power tube is discharged to GND through a path formed by the auxiliary discharge tube MHN3, the third resistor R3 and the fourth voltage-resistant PMOS tube MHP4GS_MH(═ HDRV-SW) to miller platform. Then, the second control signal H _ inv1 is boosted to 2VDDH by the charge pump capacitor, i.e., the first capacitor C1, and the signal H _3 makes the third voltage-withstanding PMOS transistor MHP3 conductive, connects the gate of the first voltage-withstanding NMOS transistor MHN1 and the upper board of the first capacitor C1, turns on the main discharging branch MHN1, and makes the power transistor smoothly transit from the miller platform by gradually increasing the current and adopting a moderate discharging speed. Wait for VHDRV-VSW(high side power tube VGS) And when the voltage is lower than the threshold value of a fourth voltage-resistant PMOS tube MHP4, the fourth voltage-resistant PMOS tube MHP4 is turned off, the auxiliary discharge branch MHN3 is turned off, and the second voltage-resistant NMOS tube MHN2 continues to discharge HDRV, so that the segmented variable-slope discharge is realized. Finally, the first withstand voltage NMOS MHN1 quickly turns off the high-side power transistor. Therefore, the variable slope discharge driving electric power provided by the inventionThe circuit effectively avoids EMI interference caused by gate capacitance of a single-speed quick discharge power tube, the auxiliary discharge branch which discharges to GND is additionally arranged at the initial discharge stage to accelerate the discharge speed of the main discharge branch before starting, and a charge pump, namely a first capacitor C1, is utilized to replace a level shifter in a traditional drive circuit to obtain a high-voltage signal, so that the circuit is simplified, and the working performance and the safety and reliability of the drive circuit are improved. The inverter formed by the second withstand voltage PMOS tube MHP2 and the second withstand voltage NMOS tube MHN2 controlled by the first control signal H _1 is arranged, so that the circuit function can be ensured when the grid of the first withstand voltage NMOS tube MHN1 is discharged or clamped when needed; in addition, because the invention adopts a structure that the grid electrode of the first withstand voltage NMOS tube MHN1 is charged through the charge pump, the grid electrode of the first withstand voltage NMOS tube MHN1 is not opened very fast, so the invention also adds a discharge path where the fourth withstand voltage PMOS tube MHP4 and the third withstand voltage NMOS tube MHN3 are positioned, can solve the problem that the discharge is driven to be slow at first due to the slow opening of the grid electrode of the first withstand voltage NMOS tube MHN1, and can form a variable-slope discharge function by controlling the two discharge paths.
Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.
Claims (3)
1. A variable slope discharge drive circuit inputs a gate logic control signal of a high-side power tube in a DC-DC converter, outputs a signal connected with the gate of the high-side power tube, and is characterized in that the variable slope discharge drive circuit comprises a level shifter, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a first resistor, a third resistor, a first capacitor, a first NMOS tube, a first withstand voltage NMOS tube, a second withstand voltage NMOS tube, a third withstand voltage NMOS tube, a second withstand voltage PMOS tube, a third withstand voltage PMOS tube and a fourth withstand voltage PMOS tube;
the input end of the level shifter is connected with the input signal of the variable slope discharging driving circuit, and the output end of the level shifter is connected with the input end of the first phase inverter; the level shifter is used for boosting an input signal of the variable slope discharging driving circuit in a low power supply rail voltage domain to a high power supply rail voltage domain, wherein the low power supply rail is from low power supply voltage to ground level, and the high power supply rail is from high power supply voltage to ground level;
the input end of the second inverter is connected with the output end of the first inverter and is connected with the high power supply voltage after passing through the first resistor, and the output end of the second inverter outputs a first control signal and is connected with the input end of the third inverter, the grid electrode of the second withstand voltage NMOS tube and the grid electrode of the second withstand voltage PMOS tube;
the output end of the third inverter outputs a second control signal and is connected with the input end of the fourth inverter and one end of the first capacitor;
charging the second control signal to obtain a third control signal, wherein a power rail of the third control signal obtained after charging is from twice high power voltage to high power voltage; the third control signal is connected with the grid electrode of the first NMOS tube and is used for charging the high-side power tube;
the drain electrode of the first NMOS tube is connected with the source electrode of the second voltage-resistant PMOS tube and the grid electrode of the third voltage-resistant PMOS tube and is connected with the high power supply voltage, and the source electrode of the first NMOS tube is connected with the other end of the first capacitor, the source electrode of the third voltage-resistant PMOS tube and the substrate of the second voltage-resistant PMOS tube;
the drain electrode of the second voltage-resistant NMOS tube is connected with the drain electrode of the second voltage-resistant PMOS tube, the drain electrode of the third voltage-resistant PMOS tube and the grid electrode of the first voltage-resistant NMOS tube, and the source electrode of the second voltage-resistant NMOS tube is connected with the ground level;
the grid electrode of the fourth voltage-withstanding PMOS tube is connected with the source electrode of the first voltage-withstanding NMOS tube and the connection point of the high-side power tube and the low-side power tube in the DC-DC converter, the source electrode of the fourth voltage-withstanding PMOS tube is connected with the drain electrode of the first voltage-withstanding NMOS tube and outputs the output signal of the variable-slope discharge driving circuit, and the drain electrode of the fourth voltage-withstanding PMOS tube is connected with the drain electrode of the third voltage-withstanding NMOS tube after passing through the third resistor;
the grid electrode of the third voltage-resistant NMOS tube is connected with the signal of the output signal of the fourth inverter after passing through the fifth inverter, and the source electrode of the third voltage-resistant NMOS tube is connected with the ground level.
2. The variable slope discharge driving circuit according to claim 1, further comprising a first voltage-withstanding PMOS transistor, a second resistor and a second capacitor, wherein one end of the second resistor is connected to the high power voltage, and the other end of the second resistor is connected to the gate of the first voltage-withstanding PMOS transistor and connected to ground through the second capacitor; the source electrode of the first voltage-resistant PMOS tube is connected with the third control signal, and the drain electrode of the first voltage-resistant PMOS tube is connected with the grid electrode of the high-side power tube.
3. The variable slope discharge driving circuit according to claim 1 or 2, wherein the first inverter, the second inverter, the third inverter, the fourth inverter and the fifth inverter are inverters with amplification function.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010300236.2A CN111338418B (en) | 2020-04-16 | 2020-04-16 | Variable slope discharge driving circuit |
Applications Claiming Priority (1)
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| CN111555595B (en) * | 2020-06-29 | 2023-02-07 | 电子科技大学 | GaN power tube gate drive circuit with controllable opening rate |
| CN114765415A (en) * | 2021-01-11 | 2022-07-19 | 北京兆易创新科技股份有限公司 | Charge pump circuit and nonvolatile memory |
| CN113824437B (en) * | 2021-09-28 | 2023-05-26 | 电子科技大学 | Gate drive circuit |
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