CN117766605A - Low-gain avalanche detector and manufacturing method thereof - Google Patents
Low-gain avalanche detector and manufacturing method thereof Download PDFInfo
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- CN117766605A CN117766605A CN202311629187.7A CN202311629187A CN117766605A CN 117766605 A CN117766605 A CN 117766605A CN 202311629187 A CN202311629187 A CN 202311629187A CN 117766605 A CN117766605 A CN 117766605A
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- 238000000034 method Methods 0.000 claims abstract description 31
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- 238000002513 implantation Methods 0.000 claims abstract description 16
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- 239000010410 layer Substances 0.000 claims description 85
- 238000005468 ion implantation Methods 0.000 claims description 24
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Abstract
The invention relates to a low-gain avalanche detector and a manufacturing method thereof. The method comprises the following steps: forming a P+ gain layer in the prefabricated semiconductor structure; the prefabricated semiconductor structure comprises a substrate, a P-type doped layer, an oxide layer, photoresist and at least one groove, wherein the P-type doped layer, the oxide layer and the photoresist are vertically stacked on the upper surface of the substrate in sequence; the groove penetrates through the photoresist but does not penetrate through the oxide layer, so that the oxide layer comprises a field oxide layer forming the side wall of the groove and a trap oxide layer forming the bottom wall of the groove; the groove is provided with an inclined side wall, so that the groove is in a shape with a large opening and a small bottom; the method for forming the P+ gain layer comprises the following steps: and implanting P-type ions into the P-type doped layer at the groove, wherein the included angle between the implantation direction and the side wall of the groove is less than or equal to 10 degrees. The invention improves the yield of the LGAD detector and ensures that the detector has better breakdown voltage uniformity.
Description
Technical Field
The invention relates to the field of detectors, in particular to a low-gain avalanche detector and a manufacturing method thereof.
Background
With the continuous development of high-energy particle detection technology, in order to realize the smooth upgrade of a high-brightness large-sized hadron collision machine (HL-LHC), a Low-gain avalanche detector (Low-Gain Avalanche Detector, LGAD for short) is proposed, and has moderate gain, superior time resolution and easy integration, so that the high-energy particle detection technology is widely focused in the research of semiconductor detectors in recent years, and therefore, the action mechanism and the manufacturing process of the high-energy particle detection technology deserve to be studied intensively. Since the field intensity required by electron multiplication is lower than that required by hole multiplication, it is most feasible to adjust the gain in such a way that electron multiplication is dominant, and avalanche generation at higher electric fields can be avoided. LGAD usually adopts an n-in-p structure, so that the multiplication process is better controlled, the jitter sensitivity of the gain to the working voltage is lower, and the LGAD can work very stably. Therefore, to meet the needs of high-energy physical experiments on large-scale detectors required by high-energy particle detection, the manufacturing process or structure of the device needs to be optimized to ensure the yield of the device.
For this purpose, the present invention is proposed.
Disclosure of Invention
The invention mainly aims to provide a low-gain avalanche detector and a manufacturing method thereof, which improve the yield of an LGAD detector and ensure that the detector has better breakdown voltage uniformity.
In order to achieve the above object, the present invention provides the following technical solutions.
The first aspect of the present invention provides a method for fabricating a low gain avalanche detector, forming a p+ gain layer in a prefabricated semiconductor structure; the prefabricated semiconductor structure comprises a substrate, a P-type doped layer, an oxide layer, photoresist and at least one groove, wherein the P-type doped layer, the oxide layer and the photoresist are vertically stacked on the upper surface of the substrate in sequence; the groove penetrates through the photoresist but does not penetrate through the oxide layer, so that the oxide layer comprises a field oxide layer forming the side wall of the groove and a trap oxide layer forming the bottom wall of the groove; the groove is provided with an inclined side wall, so that the groove is in a shape with a large opening and a small bottom;
the method for forming the P+ gain layer comprises the following steps:
and implanting P-type ions into the P-type doped layer at the groove, wherein the included angle between the implantation direction and the side wall of the groove is less than or equal to 10 degrees.
Therefore, the invention designs the inclined side wall (namely the side wall of the groove) at the edge of the ion implantation area, so that implantation in the inclined direction can be performed when the P+ gain layer is formed by ion implantation, thereby avoiding the short channel effect of the device, avoiding the generation of ion implantation shadow due to the compensation effect of the inclined side wall, and further avoiding the voltage instability caused by the shadow. In a word, the uniformity of breakdown voltage of the LGAD detector is greatly improved by the 'edge correction' ion implantation mode, and the qualification rate of products is improved.
Further, the included angle between the injection direction and the side wall of the groove is less than or equal to 2 degrees.
Further, the injection direction is parallel to the sidewalls of the recess.
In theory, the uniformity of breakdown voltage is better when the ion implantation direction is parallel to the side wall of the groove, but the parallelism under the ideal state may not be realized in the actual process, and the equipment type can be properly controlled to be as parallel as possible.
Furthermore, the side wall of the groove is formed by splicing a plurality of planes, and in the process of implanting the P-type ions, ion implantation is performed for a plurality of times in a direction parallel to each plane in sequence.
The above process may be accomplished by rotating the ion implantation apparatus or rotating the wafer tray (carrying the prefabricated semiconductor structures). By performing ion implantation multiple times parallel to each of the planes in turn, the shadow areas may be formed in none, or a smaller shadow area in each region of the device.
Further, during the implantation of P-type ions, the prefabricated semiconductor structure is rotated such that the implantation direction is in turn parallel to each plane.
Further, the bottom surface of the groove is square, and the side wall of the groove consists of four planes. In the scheme, the groove is square bucket-shaped.
Further, the prefabricated semiconductor structure further includes:
the shallow surface layer of the P-type doped layer is embedded with a plurality of junction terminal extensions, and the groove is positioned between two adjacent junction terminal extensions.
Further, the prefabricated semiconductor structure further includes: the shallow surface layer of the P-type doped layer is embedded with a P-type blocking area, and the P-type blocking area is positioned at one side of the junction terminal extending away from the groove.
Further, after forming the p+ gain layer, the method further comprises:
forming an N-type doped layer;
removing the well oxygen layer and the photoresist;
and an extraction electrode.
A second aspect of the invention provides a low gain avalanche detector produced using the method of manufacture provided in the first aspect.
In conclusion, compared with the prior art, the invention achieves the following technical effects: the uniformity of the breakdown voltage of the chip can be obviously improved by changing the angle and the edge correction process during ion implantation, so that the yield is improved.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention.
FIG. 1 is a schematic diagram of an LGAD;
FIG. 2 is a schematic diagram of a prefabricated semiconductor structure provided by the present invention;
FIG. 3 is a schematic view of the direction of ion implantation in the structure of FIG. 2;
FIG. 4 is a schematic diagram of a structure of forming a P+ gain layer based on FIG. 2;
FIG. 5 is a schematic view of a groove with vertical sidewalls;
FIG. 6 is a schematic diagram of a structure of forming a P+ gain layer based on FIG. 5;
fig. 7 shows the voltage distribution of the detector according to the present invention and the conventional art.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is only exemplary and is not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure.
Various structural schematic diagrams according to embodiments of the present disclosure are shown in the drawings. The figures are not drawn to scale, wherein certain details are exaggerated for clarity of presentation and may have been omitted. The shapes of the various regions, layers and relative sizes, positional relationships between them shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. In addition, if one layer/element is located "on" another layer/element in one orientation, that layer/element may be located "under" the other layer/element when the orientation is turned.
The structure of the LGAD is shown in FIG. 1, and the avalanche effect is achieved by introducing a P+ gain layer 10 of relatively high concentration near the PN junction of the PIN structure, so that a strong electric field is formed only in the region of the P+ gain layer 10. The width of this P + gain layer 10 may be in the order of a few microns or the depth may be in the order of a few microns.
The p+ gain layer 10 is typically prepared by ion implantation, and ions are implanted at normal incidence (i.e., perpendicular to the surface of the layer to be implanted) in conventional processes, which may cause short channel effects and thus non-uniform device voltage distribution.
Therefore, the ion implantation direction is inclined at a certain angle (for example, 2-10 degrees) by the adjusting process so as to avoid the short channel effect of the device. However, since the implantation angle in the vertical direction is adjusted, a shadow effect is generated in the device production process, which affects the distribution of impurities, resulting in unstable breakdown voltage. Based on the method, the edge is corrected on the basis of the inclined injection angle, and a shadow area is avoided from being formed during inclined injection through the compensation effect, so that the uniformity of breakdown voltage of the LGAD detector is improved, and the qualification rate of products is improved.
Specifically, the invention provides a manufacturing method of a low-gain avalanche detector, which forms a P+ gain layer in a prefabricated semiconductor structure.
The prefabricated semiconductor structure refers to a structure in which a P layer in a PIN structure is formed, and specifically as shown in fig. 2, the structure comprises a substrate 11, a P-type doped layer 12, an oxide layer, a photoresist 16 and at least one groove 17, which are vertically stacked in sequence on the upper surface of the substrate; the recess 17 penetrates the photoresist 16 but not the oxide layer, such that the oxide layer includes a field oxide layer 151 forming recess sidewalls 171 and a well oxide layer 152 forming a recess bottom wall; the recess has sloped side walls 171 so that the recess 17 has a shape with a small open bottom.
The method for forming the P+ gain layer in the above structure includes:
p-type ions are implanted into the P-type doped layer 12 at the grooves, and the angle between the implantation direction and the side wall 171 of the grooves is less than or equal to 10 degrees, and ions are implanted in the direction of the arrows shown in fig. 3, so as to form a p+ gain layer 18 as shown in fig. 4.
Therefore, the invention designs the inclined side wall (namely the side wall of the groove) at the edge of the ion implantation area, so that implantation in the inclined direction can be performed when the P+ gain layer is formed by ion implantation, thereby avoiding the short channel effect of the device, avoiding the generation of ion implantation shadow due to the compensation effect of the inclined side wall, and further avoiding the voltage instability caused by the shadow. In a word, the uniformity of breakdown voltage of the LGAD detector is greatly improved by the 'edge correction' ion implantation mode, and the qualification rate of products is improved.
If the sidewall of the recess in the structure of fig. 2 is set to be vertical, as shown in fig. 5, the sidewall 21 is vertical to the surface, and in this structure, when ions are implanted at the same inclination angle, a shadow region 23 shown in fig. 6, that is, a shadow region 23 spaced at the left side of the p+ gain layer 22 is generated, which affects the distribution of impurities, resulting in unstable breakdown voltage of the detector.
In theory, the uniformity of breakdown voltage is better when the ion implantation direction is parallel to the side wall of the groove, but the parallelism under the ideal state may not be realized in the actual process, and the equipment type can be properly controlled to be as parallel as possible.
For example, in some embodiments, the implant direction is at an angle of 2 ° or less from the sidewall of the recess.
In some embodiments, the implantation direction is parallel to the sidewalls of the recess.
In some embodiments, all of the sidewalls of the groove are sloped sidewalls. The term "sloped side wall" in the present invention means that the side wall is not perpendicular to the bottom wall of the recess. In some embodiments, the grooves are regular in shape, e.g., resembling a square bucket.
In some embodiments, the side wall of the groove is formed by splicing a plurality of planes, and during the process of implanting P-type ions, ion implantation is performed for a plurality of times in a direction parallel to each plane in sequence. Assuming that the sidewall of the recess includes n planes, the ion implantation device or the prefabricated semiconductor structure is rotated n times, and ions are implanted in a direction parallel to one of the planes each time, and the total implantation amount of n times is ensured to meet the requirement of the p+ gain layer.
In summary, the above process may be accomplished by rotating the ion implantation apparatus or rotating the wafer tray (carrying the prefabricated semiconductor structures). By performing ion implantation multiple times parallel to each plane in turn, shadow regions may not be formed in individual regions of the device, or may be formed smaller.
In some embodiments, the prefabricated semiconductor structure is rotated during implantation of P-type ions such that the implantation direction is parallel to each plane in turn.
In some embodiments, as shown in fig. 2, the bottom surface of the groove is square, and the side wall thereof is composed of four planes. The groove is similar to a square bucket shape.
In some embodiments, the prefabricated semiconductor structure further comprises:
the shallow surface of the P-doped layer 12 is embedded with a plurality of junction termination extensions 13 (JTE), with a recess 17 between two adjacent junction termination extensions 13.
In some embodiments, the prefabricated semiconductor structure further comprises: the shallow surface of the P-doped layer 12 is embedded with a P-stop region 14, the P-stop region 14 being located on the side of the junction termination 13 that extends away from the recess.
The junction termination extension 13, P-type blocking region 14 above is typical of an LGAD detector.
In general, the p+ gain layer and the junction terminal extension in the LGAD detector are all distributed in an array, so that all the p+ gain layer units and all the junction terminal extension units can be formed synchronously.
In some embodiments, the field oxide layer and the well oxide layer are typically formed in steps.
To obtain complete LGAD detection, in some embodiments, the following steps are typically included after the formation of the P+ gain layer.
First, an N-type doped layer is formed.
And secondly, removing the trap oxygen layer and the photoresist, and then carrying out annealing treatment, so that on one hand, ions can be more uniformly diffused, and on the other hand, material defects can be repaired.
And thirdly, leading out the electrode, depositing an interlayer medium in advance when leading out the electrode, photoetching a contact area, and depositing a conductor material such as metal to form the electrode.
The structure shown in fig. 2 can be produced by the following procedure:
first, a substrate, typically a P-type substrate, is prepared, and has a doping concentration greater than the P-type doped layer to be formed.
A P-doped layer is then epitaxially grown on the substrate.
And continuing to deposit a thin oxide layer on the P-type doped layer to serve as a trap oxygen layer so as to facilitate the subsequent ion implantation.
Ions are then implanted into the P-doped layer in combination with photolithographic means to form a plurality of Junction Termination Extensions (JTEs), i.e., an array of JTEs.
And then, by combining a photoetching means, implanting ions into the P-type doped layer to form a P-type blocking area, and performing reheat annealing treatment to promote ion diffusion.
Next, an oxide material is deposited, which acts as a field oxide layer.
And (3) coating photoresist on the field oxide layer, and simultaneously carrying out patterning treatment on the field oxide layer and the photoresist, wherein the thicknesses of the photoresist and the oxide layer gradually decrease from the edge of the device to the middle in a step-like manner to form the structure shown in fig. 2.
Comparing the voltage distribution of the LGAD detector manufactured by the present invention with that of the LGAD detector manufactured by the conventional process (the LGAD detector manufactured on the basis of fig. 5 is different from the present invention except for the step of forming the gain layer), the result is shown in fig. 7, the voltage distribution of the LGAD detector obtained by the conventional process is shown on the left side, and the breakdown voltage uniformity of the present invention is obviously improved, and the yield of the product is greatly improved.
The embodiments of the present disclosure are described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the disclosure, and such alternatives and modifications are intended to fall within the scope of the disclosure.
Claims (10)
1. A manufacturing method of a low-gain avalanche detector is characterized in that a P+ gain layer is formed in a prefabricated semiconductor structure; the prefabricated semiconductor structure comprises a substrate, a P-type doped layer, an oxide layer, photoresist and at least one groove, wherein the P-type doped layer, the oxide layer and the photoresist are vertically stacked on the upper surface of the substrate in sequence; the groove penetrates through the photoresist but does not penetrate through the oxide layer, so that the oxide layer comprises a field oxide layer forming the side wall of the groove and a trap oxide layer forming the bottom wall of the groove; the groove is provided with an inclined side wall, so that the groove is in a shape with a large opening and a small bottom;
the method for forming the P+ gain layer comprises the following steps:
and implanting P-type ions into the P-type doped layer at the groove, wherein the included angle between the implantation direction and the side wall of the groove is less than or equal to 10 degrees.
2. The method of claim 1, wherein the implant direction is at an angle of 2 ° or less from the sidewall of the recess.
3. The method of claim 2, wherein the implantation direction is parallel to a sidewall of the recess.
4. The method according to claim 1, wherein the sidewall of the recess is formed by splicing a plurality of planes, and ion implantation is performed a plurality of times in a direction parallel to each of the planes in sequence during the P-type ion implantation.
5. The method of claim 4, wherein the pre-fabricated semiconductor structure is rotated during the implantation of P-type ions such that the implantation direction is sequentially parallel to each plane.
6. The method according to any one of claims 1 to 5, wherein the bottom surface of the recess is square, and the side wall thereof is composed of four planes.
7. The method of any of claims 1-5, wherein the prefabricated semiconductor structure further comprises:
the shallow surface layer of the P-type doped layer is embedded with a plurality of junction terminal extensions, and the groove is positioned between two adjacent junction terminal extensions.
8. The method of manufacturing of claim 7, wherein the prefabricated semiconductor structure further comprises: the shallow surface layer of the P-type doped layer is embedded with a P-type blocking area, and the P-type blocking area is positioned at one side of the junction terminal extending away from the groove.
9. The method of any one of claims 1-5, further comprising, after forming the p+ gain layer:
forming an N-type doped layer;
removing the well oxygen layer and the photoresist;
and an extraction electrode.
10. A low gain avalanche detector obtainable by the method according to any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311629187.7A CN117766605A (en) | 2023-11-30 | 2023-11-30 | Low-gain avalanche detector and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202311629187.7A CN117766605A (en) | 2023-11-30 | 2023-11-30 | Low-gain avalanche detector and manufacturing method thereof |
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| CN117766605A true CN117766605A (en) | 2024-03-26 |
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| CN202311629187.7A Pending CN117766605A (en) | 2023-11-30 | 2023-11-30 | Low-gain avalanche detector and manufacturing method thereof |
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- 2023-11-30 CN CN202311629187.7A patent/CN117766605A/en active Pending
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