CN117765858A - Display panel driving power saving circuit and method - Google Patents

Abstract

The invention provides a display panel driving power saving circuit and a method, comprising an OP control module arranged on the output side of an operational amplifier OP and a charge sharing control module arranged on the output side of the OP control module, wherein all the charge sharing control modules are connected together; the OP control module is used for responding to an OP output enabling signal and driving the OP output to the source line; the charge sharing control module is used for shorting all the source lines together in response to a charge sharing enabling signal, and saving electricity through charge sharing of all the source lines; wherein the OP output enable signal is opposite in level to the charge sharing enable signal. According to the invention, the OP control module and the charge sharing control module are arranged, so that the source lines are short-circuited together, and the charges in one row on the display panel are shared to the next row, thereby realizing power saving.

Description

Display panel driving power saving circuit and method

Technical Field

The invention relates to the technical field of display screens, in particular to a power saving circuit and a power saving method for driving a display panel.

Background

At present, a thin film transistor (ThinFilmTransistor, TFT) display panel with a size of more than 5 inches adopts a single gate driving structure, and each source line in the single gate driving structure needs to be pushed by an operational amplifier, so that the area of a display panel driving chip is generally larger, meanwhile, the source lines on the display panel are more in wiring, and the fan-out type packaging height is larger.

In the double-gate driving structure, one source line can drive two sub-pixels, and the number of the required operational amplifiers and the source lines is less than half of that of the single-gate driving structure under the same resolution, so that the area of a driving chip of the display panel and the fan-out packaging height are reduced.

However, the power consumption of the dual gate driving structure is much greater than that of the single gate driving structure.

Disclosure of Invention

The invention provides a power-saving circuit and a power-saving method for driving a display panel, which are used for solving the defect that the power consumption is increased greatly in the prior art although the area of a driving chip of the display panel and the fan-out type packaging height are reduced by a double-gate driving structure.

The invention provides a display panel driving power-saving circuit, which comprises an OP control module arranged on the output side of an operational amplifier OP and a charge sharing control module arranged on the output side of the OP control module, wherein all the charge sharing control modules are connected together;

the OP control module is used for responding to an OP output enabling signal and driving the OP output to the source line;

the charge sharing control module is used for shorting all the source lines together in response to a charge sharing enabling signal, and saving electricity through charge sharing of all the source lines;

wherein the OP output enable signal is opposite in level to the charge sharing enable signal.

Preferably, the OP control module is a switching circuit formed by two triodes, and the circuit structure of the OP control module is the same as that of the charge sharing control module.

Preferably, the input side of the operational amplifier is also connected with a data latch module, a level shift module and a DAC module;

the data latch module is used for latching display driving data in response to a data latch enabling signal to obtain latch driving data, and outputting the latch driving data to the level shift module;

the level shift module is used for shifting the voltage of the latch driving data to a preset voltage and outputting the latch driving data after the voltage shift to the DAC module;

the DAC module is used for converting the latched driving data after voltage displacement into analog driving data and outputting the analog driving data to the operational amplifier.

Preferably, the device further comprises a charge sharing data control module, wherein the charge sharing data control module is connected in series with the charge sharing control module and is used for shorting the source lines corresponding to the analog driving data meeting preset conditions together.

Preferably, the charge sharing data control module is a switching circuit formed by two triodes, and the circuit structure of the charge sharing data control module is the same as that of the charge sharing data control module.

Preferably, the input terminal of the data latch module is connected with a data latch control module, and the data latch control module is used for responding to the charge sharing enabling signal, the data latch enabling signal and the latch driving data, and pausing the data latch during the charge sharing period.

Preferably, the driving structure of the display panel is a single gate driving structure or a double gate driving structure.

The invention also provides a power saving method for driving the display panel, which comprises the following steps:

an OP control module and a charge sharing control module are arranged between an operational amplifier and a source line, wherein the charge sharing control module is arranged at the output side of the OP control module, and all the charge sharing control modules are connected together;

driving an OP output to a source line based on the OP control module in response to an OP output enable signal;

in response to a charge sharing enabling signal, shorting all the source lines together based on the charge sharing control module, and realizing power saving through charge sharing of all the source lines;

wherein the OP output enable signal is opposite in level to the charge sharing enable signal.

According to the display panel driving power saving circuit and the method, the OP control module and the charge sharing control module are arranged, the source lines are in short circuit, and the charges of one row of sub-pixels on the display panel are shared to the current row of sub-pixels, so that power saving is realized.

Drawings

In order to more clearly illustrate the invention or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of pixel control of a display panel with a dual gate driving structure;

FIG. 2 is a timing control schematic of a display panel with dual gate driving structure;

FIG. 3 is a schematic diagram of pixel control of a display panel with a single gate driving structure;

FIG. 4 is a timing control schematic of a display panel with a single gate driving structure;

FIG. 5 is a schematic circuit diagram of a power saving circuit for driving a display panel according to the present invention;

FIG. 6 is a timing control schematic diagram of a power saving circuit for driving a display panel according to the present invention;

fig. 7 is a schematic circuit diagram of a front stage circuit of the operational amplifier provided by the invention;

FIG. 8 is a schematic circuit diagram of an improved display panel driving power saving circuit provided by the present invention;

FIG. 9 is a timing control schematic diagram of an improved display panel driving power saving circuit according to the present invention;

FIG. 10 is a schematic circuit diagram of an operational amplifier improved pre-stage circuit provided by the present invention;

fig. 11 is a flowchart illustrating a power saving method for driving a display panel according to an embodiment of the invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the embodiments of the present application. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.

Fig. 1 is a schematic diagram of pixel control of a display panel with a dual gate driving structure, as shown in fig. 1, in which each source line (i.e. source line) is connected to two sub-pixels in the same row, for example, a first source line S1 simultaneously controls two sub-pixels R and G, wherein the switch of the sub-pixel R is controlled by G1, and the switch of the sub-pixel G is controlled by G2.

Fig. 2 is a timing control schematic diagram of a display panel with a dual gate driving structure, as shown in fig. 2, taking a first source line S1 as an example, a high level control sub-pixel R and a low level control sub-pixel G of S1.

Fig. 3 is a schematic diagram of pixel control of a display panel with a single gate driving structure, fig. 4 is a schematic diagram of timing control of a display panel with a single gate driving structure, as shown in fig. 3 and 4, when a display image of the display panel is pure red, assuming that the highest gray level is 5V, the lowest gray level is 0V, the gate scanning order is G1- > G2- > G3- > G4, the source lines S1, S4, S7, S10 are always kept unchanged at 5V, the other source lines Sn are always kept unchanged at 0V, the AC power consumption consumed on the display panel is substantially 0, and other pure colors are similar.

However, in the dual gate driving structure, when the display image of the display panel is pure red, assuming that the highest gray level is 5V, the lowest gray level is 0V, the gate scanning order is G1- > G2- > G3- > G4- > G5- > G6- > G7- > G8, it is known with reference to fig. 2 that the source lines S1, S2, S4, S5 are inverted at a line frequency of 5V/0V, the other source lines S3 and S6 are always maintained at 0V, the calculation formula of the AC average current of the source lines S1, S2, S4, S5 is i= cvf, c is the capacitance capacity of the driving tube, V is the voltage value, and f is the line frequency. Assuming that c=100pf, v=5v, f=100deg.C, the average current required for each source line is 50uA, if a solid color image is to be displayed, only four source lines will produce AC power consumption, which translates to each source line, and each of the six source lines will require an average current of 33 uA. If the resolution of the display panel is 720RGB, the dual gate driving structure needs 1080 source lines, and the average current of all source lines is 36mA, and this current consumption is very large for the display panel driving chip.

Fig. 5 is a schematic circuit diagram of a power saving circuit for driving a display panel, and fig. 6 is a schematic timing control diagram of a power saving circuit for driving a display panel, as shown in fig. 5 and 6, wherein the power saving circuit for driving a display panel comprises an OP control module arranged at an output side of an OP control amplifier OP and a charge sharing control module arranged at an output side of the OP control module, and all the charge sharing control modules are connected together;

the OP control module is used for responding to an OP output enabling signal and driving the OP output to the source line; the OP output enable signal may be denoted OE.

The charge sharing control module is used for shorting all the source lines together in response to a charge sharing enabling signal, and saving electricity through charge sharing of all the source lines; the charge SHARE enable signal may be denoted as c_share.

Wherein the OP output enable signal is opposite in level to the charge sharing enable signal.

The circuit provided by the invention can be applied to a display panel with a single-gate driving structure or a double-gate driving structure, namely the driving structure of the display panel is the single-gate driving structure or the double-gate driving structure.

The working principle of the invention is explained below by taking a double-gate driving structure as an example:

in the dual gate driving structure, when the display image of the display panel is pure red, during the gate scan G1, the states of the source lines S1 to S6 are {5V, 0V }, the state of S1-S6 becomes {0V, 5V,0V } during the period G2.

OE is an OP output enable signal, and when OE is high, the OP output is driven to the display panel; when the charge SHARE enable signal c_share is high, the charge SHARE switch is turned on, all data lines are shorted together, and charge is shared.

The source lines S <1> -S <6> are output data lines connected to the display panel, when a gate scan Gn is high, a corresponding whole row of TFT switches are turned on, the output data lines start to charge the liquid crystal storage capacitor, and the data voltage is latched at the storage capacitor along the edge under Gn. Each row starts c_share=1, shorting all S <1> -S <6> together so that the charge of S1-S2 during G1 will average onto S <1> -S <6>, simply calculating: the power saving=2/6=1/3, which is equivalent to 1/3 saving, and according to the previous calculation, the charge sharing technology can save 12mA if the pure color AC power consumption is 36mA at HD resolution.

It can be understood that the invention realizes power saving by setting the OP control module and the charge sharing control module, shorting the source lines together and sharing the charges of one row on the display panel to the next row.

Preferably, the OP control module is a switching circuit formed by two triodes, and the circuit structure of the OP control module is the same as that of the charge sharing control module. In other embodiments, the OP control module and the charge sharing control module may also use a switching circuit formed by MOS transistors.

Fig. 7 is a schematic circuit diagram of a front stage circuit of the operational amplifier provided by the invention, and as shown in fig. 7, preferably, the input side of the operational amplifier is further connected with a data latch module, a level shift module and a DAC module;

the data latch module is used for latching display driving data in response to a data latch enabling signal to obtain latch driving data, and outputting the latch driving data to the level shift module; the data latch enable signal is LE, and when the data latch enable signal is high, the display drive data D [7:0] is latched into the data latch module latch, which outputs the latch drive data Q [7:0].

The level shift module is used for shifting the voltage of the latch driving data to a preset voltage and outputting the latch driving data after the voltage shift to the DAC module; specifically, the level shift module shifts the voltage 0/VDD of the latch driving data to 0/VSP. VDD is the power supply of the chip, and may be 1.2V, 1.3V, 1.5V according to different processes; VSP is an analog module power supply, typically ranging from 5V to 6V.

The DAC module is used for converting the latched driving data after voltage displacement into analog driving data and outputting the analog driving data to the operational amplifier. Specifically, GRAY [255:0] is 256 GRAY scale voltages, the digital signal DA [7:0] is converted into the analog voltage VIN through the DAC module, and finally the analog voltage VIN is outputted and driven through the OP. Wherein GRAY [255:0] is gamma reference voltage, 0-255 corresponds to data 00 h-FFH, 0-255 GRAY scale voltages drive the panel liquid crystal to obtain 256 brightnesses, and 0-255 brightness changes are used for correcting nonlinearity of human eyes, commonly called gamma correction (gamma).

It will be appreciated that by providing a data latch, it is ensured that the display panel can accurately display the corresponding image sub-pixels while charge sharing.

Fig. 8 is a circuit schematic diagram of the improved power saving circuit for driving a display panel, and fig. 9 is a timing control schematic diagram of the improved power saving circuit for driving a display panel, as shown in fig. 8 and 9, preferably, the circuit schematic diagram further includes a charge sharing data control module connected in series with the charge sharing control module, for shorting together the source lines corresponding to the analog driving data meeting a preset condition.

The working principle of the invention is explained as follows in combination with an improved display panel driving power saving circuit:

in combination with the foregoing, when the display panel displays pure red, S <3> and S <6> are always 0V, and charging is not required, and all S <1> to S <6> are shorted during charge sharing, so that power consumption is reduced, and the improved display panel driving power saving circuit increases a charge sharing data control module, and only charges share a data channel with the highest data bit being 1, namely a high level.

Preferably, the charge sharing data control module is a switching circuit formed by two triodes, and the circuit structure of the charge sharing data control module is the same as that of the charge sharing data control module. In other embodiments, the charge sharing data control module and the charge sharing control module may also use a switching circuit formed by MOS transistors.

Fig. 10 is a circuit schematic diagram of the improved pre-stage circuit of the operational amplifier provided by the invention, as shown in fig. 10, preferably, the input end of the data latch module is connected with a data latch control module, and the data latch control module is used for suspending data latch during charge sharing in response to the charge sharing enable signal, the data latch enable signal and the latch driving data.

The improved front-end circuit of the operational amplifier adds a data latch control module, if the highest data bit of the last row is 1, during the charge sharing period (c_share=1), the LE is turned off, and the data is not updated temporarily.

Combining fig. 8 and fig. 10, during the initial charge sharing period of each row, the data channel with the highest bit of the data of the previous row being 1 and the data channel with the highest bit of the data of the current row being 1 are charge-shared together, and the actual time sequence after optimization is referred to fig. 9, if the highest bit of the data of the previous row is 1, the data can be latched into the latch after the charge sharing is finished; in a simple calculation, taking pure red as an example, since S <3> and S <6> are always 0V and do not participate in charge sharing, the power supply of the final com after the charge sharing is finished is 5V/2, 50% of power consumption can be saved, and 18mA can be saved by the charge sharing technology if the pure-color AC power consumption is 36 mA.

Referring to fig. 8 and 10, when the highest data (bit 7 is high) of the previous row is high, meaning that the data of the previous row is greater than 80h, the analog voltage obtained by the DAC conversion is greater than 128 gray levels (the voltage is higher than the middle gray level), the data latch is closed during the charge sharing of the current row, the voltage output by the channel is kept unchanged during the charge sharing, and referring to fig. 10, it can be seen that the charge sharing switch is turned on when the highest data is high, and the channel output is communicated to the COM (charge sharing common terminal) terminal during the charge sharing of the current row; in addition, assuming another channel, the output voltage of the previous row is lower (bit 7 is low), the highest bit of the data of the current row (bit 7 is high) is high, the data latch is opened during the charge sharing of the current row, the data is refreshed, and the charge sharing switch in fig. 10 is also turned on, and the channel output is communicated to the COM (charge sharing common) terminal during the charge sharing of the current row, so that the two channels realize charge sharing during the charge sharing; and the channels with the highest data of the upper row and the current row which are both low do not participate in charge sharing, so that the efficiency is improved.

The charge sharing is for all source line channels, only solid color pictures are analyzed above, and in practice the charge sharing technique is applicable for all pictures.

In other embodiments, the data latch control module of fig. 10 and the charge sharing data control module of fig. 8 are only one of the circuit implementations, and may be other implementations, which are substantially as follows: and judging whether to update the data in a delayed manner by using the data of the previous row, so that the charge of the panel of the previous row is shared on a channel needing to be charged in the current row, and the channel needing to be charged does not participate in sharing (the data of the previous row and the current row are both in a low-gray area), thereby realizing power saving with greater efficiency.

The power saving method for driving a display panel provided by the invention is described below, and the power saving method for driving a display panel described below and the power saving circuit for driving a display panel described above can be referred to correspondingly.

Fig. 11 is a schematic flow chart of a power saving method for driving a display panel according to an embodiment of the present invention, and as shown in fig. 11, the present invention also provides a power saving method for driving a display panel, which is implemented based on a power saving circuit for driving a display panel according to any one of the above embodiments, and includes:

an OP control module and a charge sharing control module are arranged between an operational amplifier and a source line, wherein the charge sharing control module is arranged at the output side of the OP control module, and all the charge sharing control modules are connected together;

driving an OP output to a source line based on the OP control module in response to an OP output enable signal;

in response to a charge sharing enabling signal, shorting all the source lines together based on the charge sharing control module, and realizing power saving through charge sharing of all the source lines;

wherein the OP output enable signal is opposite in level to the charge sharing enable signal.

The power saving method for driving the display panel provided by the invention is realized based on the power saving circuit for driving the display panel corresponding to any one of the embodiments, has the technical effect corresponding to the power saving circuit for driving the display panel, and is not repeated.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims (8)

1. The power-saving circuit for driving the display panel is characterized by comprising an OP control module arranged on the output side of the operational amplifier OP and a charge sharing control module arranged on the output side of the OP control module, wherein all the charge sharing control modules are connected together;

the OP control module is used for responding to an OP output enabling signal and driving the OP output to the source line;

the charge sharing control module is used for shorting all the source lines together in response to a charge sharing enabling signal, and saving electricity through charge sharing of all the source lines;

wherein the OP output enable signal is opposite in level to the charge sharing enable signal.

2. The power saving circuit of claim 1, wherein the OP control module is a switching circuit formed by two transistors, and the circuit structure of the OP control module is the same as the circuit structure of the charge sharing control module.

3. The display panel driving power saving circuit according to claim 1, wherein the input side of the operational amplifier is further connected with a data latch module, a level shift module and a DAC module;

the data latch module is used for latching display driving data in response to a data latch enabling signal to obtain latch driving data, and outputting the latch driving data to the level shift module;

the level shift module is used for shifting the voltage of the latch driving data to a preset voltage and outputting the latch driving data after the voltage shift to the DAC module;

the DAC module is used for converting the latched driving data after voltage displacement into analog driving data and outputting the analog driving data to the operational amplifier.

4. The display panel driving power saving circuit according to claim 3, further comprising a charge sharing data control module connected in series with the charge sharing control module for shorting together the source lines corresponding to the analog driving data meeting a preset condition.

5. The power saving circuit of claim 4, wherein the charge sharing data control module is a switching circuit comprising two transistors, and the switching circuit has the same circuit structure as the charge sharing control module.

6. The display panel driving power saving circuit of claim 3, wherein the input terminal of the data latch module is connected to a data latch control module for suspending data latching during charge sharing in response to the charge sharing enable signal, the data latch enable signal and the latch driving data.

7. The power saving circuit for driving a display panel according to any one of claims 1 to 6, wherein the driving structure of the display panel is a single gate driving structure or a double gate driving structure.

8. A power saving method for driving a display panel, comprising:

an OP control module and a charge sharing control module are arranged between an operational amplifier and a source line, wherein the charge sharing control module is arranged at the output side of the OP control module, and all the charge sharing control modules are connected together;

driving an OP output to a source line based on the OP control module in response to an OP output enable signal;

in response to a charge sharing enabling signal, shorting all the source lines together based on the charge sharing control module, and realizing power saving through charge sharing of all the source lines;

wherein the OP output enable signal is opposite in level to the charge sharing enable signal.