CN117765829A

CN117765829A - LED lamp panel structure

Info

Publication number: CN117765829A
Application number: CN202310800391.4A
Authority: CN
Inventors: 张海波; 何胜斌; 顾伟
Original assignee: Jiangxi Zhaochi Jingxian Co ltd
Current assignee: Jiangxi Zhaochi Jingxian Co ltd
Priority date: 2022-07-05
Filing date: 2023-06-30
Publication date: 2024-03-26
Also published as: CN116631298A; CN116758828A; FR3137791A3; CN115100970A; WO2024007400A1; DE202023103730U1; CN220189177U

Abstract

The embodiment of the invention discloses an LED lamp panel structure, which comprises a PCB and a plurality of LED lamp beads. The LED lamp bead array comprises a PCB board, a plurality of data lines, a plurality of scanning lines and a plurality of through holes, wherein the data lines are arranged on the surface layer of the PCB board, the scanning lines are arranged on the inner layer or the bottom layer of the PCB board to form a plurality of through hole rows and a plurality of through hole columns, two data lines are arranged between every two adjacent through hole rows, a plurality of LED lamp beads are arranged on the PCB board to form a plurality of LED lamp bead rows and a plurality of LED lamp bead columns, each LED lamp bead column comprises a plurality of LED lamp bead groups, and each LED lamp bead group comprises two adjacent LED lamp beads; the adjacent LED lamp beads are sequentially arranged along the second direction to form a plurality of luminous pixels; the LED lamp bead comprises a common electrode end and a non-common electrode end; the two common electrode ends of the LED lamp bead group are connected with the same through hole, and all the common electrode ends in each LED lamp bead column are connected with one scanning line through the through holes; all non-common electrode ends in each LED lamp bead row are connected with a data line. The size of the PCB is reduced, and the yield of the PCB is improved.

Description

LED lamp panel structure

Technical Field

The invention relates to the technical field of LED display, in particular to an LED lamp panel structure.

Background

The LED display screen is a flat panel display, and consists of small LED lamp beads and is used for displaying various information such as characters, images, videos and the like. The LED electronic display screen integrates microelectronic technology, computer technology and information processing, and has the advantages of bright color, wide dynamic range, high brightness, long service life, stable and reliable operation and the like. The LED display screen is widely applied to commercial media, cultural performance markets, stadiums, information dissemination, news release, securities trade and the like.

In the design process of the existing LED display screen, the scanning lines and the data lines on the PCB board are crossed, so that the scanning lines are generally arranged on the surface layer of the PCB board, through the arrangement of the through holes on the PCB board, the data lines are arranged on the inner layer or the bottom layer of the PCB board, and the number of the through holes is equal to that of the LED lamp beads on the PCB board. Because the number of the through holes on the PCB determines the yield of the PCB, the more the through holes are, the higher the reject ratio of the PCB is, therefore, how to reduce the number of the through holes on the PCB, so as to improve the yield of the PCB, reduce the waste of materials and reduce the manufacturing cost of the PCB is a technical problem to be solved urgently at present.

Disclosure of Invention

In order to solve the above problems, an embodiment of the present invention provides an LED lamp panel structure, including:

the PCB is provided with a plurality of data lines, a plurality of scanning lines and a plurality of through holes, wherein the data lines are arranged on the surface layer of the PCB, the data lines extend along a first direction, the scanning lines are arranged on the inner layer or the bottom layer of the PCB, the scanning lines extend along a second direction, a plurality of through holes are arranged in an array manner in the first direction and the second direction to form a plurality of through hole rows and a plurality of through hole columns, the through hole rows extend along the first direction, the through hole columns extend along the second direction, and two data lines are arranged between every two adjacent through hole rows;

The LED lamp beads are arranged on the PCB and are arrayed in the first direction and the second direction to form a plurality of LED lamp bead rows and a plurality of LED lamp bead columns, the LED lamp bead rows extend along the first direction, the LED lamp bead columns extend along the second direction, each LED lamp bead column comprises a plurality of LED lamp bead groups, and each LED lamp bead group comprises two adjacent LED lamp beads; the adjacent LED lamp beads are sequentially arranged along the second direction to form a plurality of luminous pixels; the LED lamp beads comprise a common electrode end and a non-common electrode end;

the common electrode ends of two LED lamp beads of the LED lamp bead group are connected with the same through hole, and the common electrode ends of all the LED lamp beads in each LED lamp bead column are connected with a scanning line through the through holes;

and the non-common electrode ends of all the LED lamp beads in each LED lamp bead row are connected with a data line.

Optionally, a plurality of connection patterns are arranged on the surface of the PCB, one connection pattern is arranged beside each via hole, and the connection patterns are connected with the via holes and the common ends of the two LED lamp beads of the LED lamp bead group.

In a second aspect, embodiments of the present application further provide an LED lamp panel structure, including:

PCB board for install a plurality of LED lamp pearls, PCB board includes:

m data lines, wherein the data lines are positioned on the surface layer of the PCB, extend along the first direction, and M is more than or equal to 4 and is an integer;

n scanning lines which are positioned at the inner layer or the bottom layer of the PCB and extend along the second direction, wherein N is more than or equal to 2 and is an integer;

the plurality of terminal pairs are arranged in an array in the first direction and the second direction to form M rows of terminal pairs and N columns of terminal pairs, each terminal pair comprises a first terminal pattern and a second terminal pattern, the first terminal patterns of all the terminal pairs in the ith row of terminal pairs are connected to an ith data line, the second terminal patterns of all the terminal pairs in the jth column of terminal pairs are connected to a jth scanning line through a via hole, and the second terminal patterns of adjacent terminal pairs in the jth column of terminal pairs are connected to the same via hole;

and in the thickness direction of the PCB, orthographic projections of the ith data line and the (i+1) th data line are positioned between orthographic projections of the ith row of terminal pairs and the (i+1) th row of terminal pairs.

Optionally, the plurality of vias are arranged in an array in the first direction and the second direction to form a plurality of via rows and a plurality of via columns, the via rows extend along the first direction, the via columns extend along the second direction, and two data lines are arranged between adjacent via rows.

Optionally, the intervals between adjacent through holes in the through hole columns are the same;

and/or, the intervals between the adjacent through holes of the via Kong Hangna are the same.

Optionally, the intervals between adjacent terminal pairs in the ith row of terminal pairs are the same;

and/or, the interval between adjacent terminal pairs in the j-th column of terminal pairs is the same.

Optionally, the via includes a first side and a second side that are oppositely disposed, and the second terminal patterns of all the terminal pairs in the j-th column of the terminal pairs are located on the first side of the via or the second terminal patterns of all the terminal pairs in the j-th column of the terminal pairs are located on the second side of the via.

Optionally, the second terminal patterns of all the terminal pairs in each column of the terminal pairs are located on a first side of the via or the second terminal patterns of all the terminal pairs in each column of the terminal pairs are located on a second side of the via;

Or, the second terminal patterns of all the terminal pairs in the j-th column are located on the first side of the via hole, and the second terminal patterns of all the terminal pairs in the j+1th column are located on the second side of the via hole.

Optionally, the width of the scan line is greater than the width of the terminal pair.

Optionally, the first terminal patterns of all the terminal pairs in the j-th column are located on the same column, the second terminal patterns of all the terminal pairs are located on the same column, and the second terminal patterns are closer to the via than the first terminal patterns;

or, the first terminal patterns of all the terminal pairs in the j-th column are positioned on the same column, the second terminal patterns of all the terminal pairs are positioned on the same column, and the first terminal patterns are closer to the via holes than the second terminal patterns;

alternatively, the first terminal pattern of any one of the terminal pairs in all the j-th columns is located on the same column as the second terminal pattern of the other terminal pair.

Optionally, two second terminal patterns connected to the same via are identical;

Or, two second terminal patterns connected to the same via hole are different;

or, the first terminal pattern and the second terminal pattern of the terminal pair are the same;

or, the first terminal pattern and the second terminal pattern of the terminal pair are different.

Optionally, the shape of the second terminal pattern is rectangular or circular;

or, the shape of the first terminal pattern is rectangular or circular.

Optionally, the two second terminal patterns connected to the same via hole are respectively located at two ends of the same rectangular pattern, and the rectangular pattern is connected to the via hole near the middle position.

Compared with the prior art, the LED lamp panel structure provided by the embodiment of the invention has the advantages that the data lines extending along the first direction, the scanning lines extending along the second direction and the through holes are arranged on the PCB, the data lines and the scanning lines are positioned on different layers of the PCB, the LED lamp beads which are arranged in the array according to the first direction and the second direction are arranged on the PCB to form the LED lamp bead rows and the LED lamp bead columns, the adjacent LED lamp beads are sequentially arranged along the second direction to form the plurality of luminous pixels, the common electrode ends of all the LED lamp beads in each LED lamp bead row are connected with one scanning line through the through holes, the non-common electrode ends of all the LED lamp beads in each LED lamp bead column are connected with one data line, each LED lamp bead column comprises a plurality of LED lamp bead groups, each LED lamp bead group comprises two LED lamp groups, the common electrode ends of the two LED lamp beads in each LED lamp bead group are connected with one through hole, the number of the through holes is reduced, the number of the through holes is arranged between the adjacent through holes, the data lines are arranged between the two data lines, the data lines are connected with the data lines through the through holes, the size of the PCB is reduced, the material cost is reduced, and the material cost is reduced.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a related art LED lamp panel structure;

FIG. 2 is another schematic diagram of a related art LED lamp panel structure;

fig. 3 is a schematic diagram of an LED lamp panel structure according to an embodiment of the present invention;

fig. 4 is a schematic diagram of an LED lamp panel structure according to another embodiment of the present invention;

fig. 5 is a schematic diagram of an LED lamp panel structure according to another embodiment of the present invention;

fig. 6 is a schematic diagram of an LED lamp panel structure according to another embodiment of the present invention;

fig. 7 is a schematic diagram of an LED lamp panel structure according to another embodiment of the present invention;

fig. 8 is a schematic diagram of an LED lamp panel structure according to another embodiment of the present invention.

Fig. 9 is a schematic structural diagram of a PCB board according to an embodiment of the present invention.

Fig. 10 is a schematic surface layer diagram of a PCB board according to an embodiment of the present invention.

Fig. 11 is a schematic diagram of an inner layer of a PCB board according to an embodiment of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

In the description of the invention, it should be understood that the terms "center," "lateral," "upper," "lower," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "column," "row," and the like indicate or are based on the orientation or positional relationship shown in the drawings, merely to facilitate describing the invention and simplify the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operate in a particular orientation, and therefore should not be construed as limiting the invention.

In the present invention, the term "some embodiments" is used to mean "serving as an example, instance, or illustration. Any embodiment described herein as exemplary is not necessarily to be construed as preferred or advantageous over other embodiments. The following description is presented to enable any person skilled in the art to make and use the invention. In the following description, details are set forth for purposes of explanation. It will be apparent to one of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well-known structures and processes have not been described in detail so as not to obscure the description of the invention with unnecessary detail. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles disclosed herein.

It should be noted that, in the embodiment of the present application, the first direction and the second direction are perpendicular to each other, the first direction may be a column direction or a row direction, and similarly, the second direction corresponds to a row direction or a column direction, and the first direction and the second direction may be interchanged in practical application. When the first direction is the x direction identified in fig. 1-7, the second direction is the y direction identified in fig. 1-7, the LED beads are arranged in rows in the row diagram, the LED beads are arranged in columns in the diagram, and the x direction in fig. 1-7 is the row direction and the y direction is the column direction.

Referring to fig. 1, fig. 1 is a schematic diagram of a related art LED lamp panel structure. As shown in fig. 1, a plurality of light emitting pixels 20 with the same structure are arranged on the PCB board 10 in an array manner, each light emitting pixel 20 is formed by three LED beads with different light emitting colors, namely, a red LED bead, a blue LED bead and a green LED bead form one light emitting pixel 20, so that the LED beads and the light emitting pixels 20 are arranged on the PCB board 10 in an array manner. The common ends of all the LED lamp beads in each row of the pixels 20 are electrically connected on the surface layer of the PCB 10 to form a row scan line, and the non-common ends of the LED lamp beads with the same light emitting color in each column of the pixels 20 are electrically connected on the inner layer or the bottom layer of the PCB 10 through the via holes 101 on the PCB 10 to form a column data line. The gate chip scans the pixels on the PCB 10 line by line through the scan lines 30, and the driving chip applies different currents through the data lines 40 to obtain different colors in each of the light emitting pixels 20, thereby obtaining a complete image on the PCB 10.

As can be seen from fig. 1, the number of vias 101 on the PCB 10 is determined by the number of LED beads, and three vias 101 are required for each pixel 20 to achieve routing of the data lines 40 to the inner or bottom layer of the PCB 10.

Referring to fig. 2, fig. 2 is another schematic diagram of a related art LED lamp panel structure. As shown in fig. 2, a plurality of light emitting pixels 20 with the same structure are arranged on the PCB board 10 in an array manner, each light emitting pixel 20 is formed by three LED beads with different light emitting colors, namely, a red LED bead, a blue LED bead and a green LED bead form one light emitting pixel 20, so that the LED beads and the light emitting pixels 20 are arranged on the PCB board 10 in an array manner. The common electrode ends of all the LED lamp beads in each row of the pixels 20 are electrically connected at the inner layer or the bottom layer of the PCB 10 through the via holes 101 on the PCB 10 to form a row of scan lines, and the non-common electrode ends of the LED lamp beads with the same light emitting color in each column of the pixels 20 are electrically connected at the surface layer of the PCB 10 to form a column of data lines 40.

As can be seen from fig. 2, in order to avoid the problem of crossing the scan lines 30 and the data lines 40, and in order to reduce the number of vias 101 on the PCB 10, two data lines 40 in each row of pixels 20 need to pass between the anode and the cathode of one or more LED beads. Although only one via 101 is required for each pixel 20 in fig. 2, the size of the LED lamp bead is necessarily increased due to the constraint of the routing rule of the PCB board 10 when the data line 40 passes between the anode and the cathode of the LED lamp bead, thereby causing a steep increase in cost. Taking the conventional COB chip 0408 (4 mil×8 mil) as an example, the distance between the positive and negative electrodes of the COB chip is only 75 μm, and the pitch of the design pads on the PCB 10 is generally smaller than that of the COB chip to prevent misalignment, so this value is generally 70 μm. According to the technical level of the PCB 10, the line width and the line distance of the common routing are both 100 μm, if two data lines 40 pass through the space between the positive and negative electrodes of the COB chip, the distance between the positive and negative electrodes of the COB chip is at least 500 μm, and the COB chip must be far larger than the original 75 μm design size of the diode, so that the diode becomes very large, and the manufacturing cost increases sharply.

Referring to fig. 3 and fig. 4, fig. 3 is a schematic diagram of an LED lamp panel structure according to an embodiment of the present invention; fig. 4 is a schematic diagram of an LED lamp panel structure according to another embodiment of the present invention. As shown in fig. 3 and 4, an LED lamp panel structure includes a PCB board 10 and a plurality of LED lamp beads 201.

The above-mentioned PCB board 10 is provided with a plurality of scan lines 30, a plurality of data lines 40 and a plurality of vias 101, the data lines 40 extend along a first direction, the scan lines 30 extend along a second direction, a plurality of data lines 40 are arranged at intervals along the second direction, a plurality of scan lines 30 are arranged at intervals along the first direction, the data lines 40 and the scan lines 30 are respectively located at different layers of the PCB board 10, the scan lines 30 can be arranged at an inner layer or a bottom layer of the PCB board 10, and the data lines 40 are arranged at a surface layer of the PCB board 10. The plurality of vias 101 are arranged in an array in the first direction and the second direction to form a plurality of via rows 101a and a plurality of via columns 101b, the via rows 101a extend in the first direction, the via columns 101b extend in the second direction, and two data lines 40 are arranged between adjacent via rows 101 a. Wherein the first direction intersects a second direction, such as the first direction and the second direction are 90 degrees from each other, the first direction is an X-axis direction, the second direction is a Y-axis direction,

The plurality of LED lamp beads 201 are arranged on the PCB 10, the plurality of LED lamp beads 201 are arranged in an array in a first direction and a second direction to form a plurality of LED lamp bead rows 201a and a plurality of LED lamp bead columns 201b, the LED lamp bead rows 201a extend along the first direction, the LED lamp bead columns 201b extend along the second direction, the plurality of LED lamp bead rows 201a are arranged at intervals along the second direction, the plurality of LED lamp bead columns 201b are arranged at intervals along the first direction, each LED lamp bead column 201b comprises a plurality of LED lamp bead groups 201c, and each LED lamp bead group 201c comprises two adjacent LED lamp beads 201; adjacent LED lamp beads 201 are sequentially arranged along the second direction to form a plurality of luminous pixels 20; the LED lamp bead 201 includes a common terminal 2011 and a non-common terminal 2012; the common electrode ends 2011 of two LED lamp beads 201 of the LED lamp bead group 201c are connected with the same through hole 101, and the common electrode ends 2011 of all the LED lamp beads 201 in each LED lamp bead column 201b are connected with one scanning line 30 through the through holes 101; the non-common ends 2012 of all the LED beads 201 within each LED bead row 201a form one data line 40.

According to the LED lamp panel structure provided by the embodiment of the invention, the plurality of LED lamp beads 201 which are arranged in the array according to the first direction and the second direction are arranged on the PCB 10, the adjacent LED lamp beads 201 are sequentially arranged along the second direction to form the plurality of luminous pixels 20, two data lines 40 are arranged between the adjacent via hole rows 101a, the LED lamp beads 201 are not arranged between the two data lines 40 between the adjacent via hole rows 101a, and the distance between the two data lines 40 is smaller, so that the size of the PCB 10 is reduced, and the manufacturing cost of the PCB is reduced. The two LED lamp beads 201 are connected with the same through hole 101, so that the number of the through holes 101 on the PCB 10 is smaller than that of the LED lamp beads 201, the yield of the PCB 10 is improved, the waste of materials is reduced, and the manufacturing cost of the PCB 10 is reduced.

The through holes 101 on the whole PCB 10 are arranged in an array, so that the through holes 101 are convenient to process, the through holes 101 can be arranged on the scanning lines 30 of the PCB 10, the formed through hole columns 101b correspond to the scanning lines 30, the distance between the through hole columns 101b and the scanning lines 30 along the first direction is small, and the size of the PCB 10 is further reduced.

Specifically, when all the LED lamp beads 201 are arranged in the manner shown in fig. 3, that is, the common electrode end 2011 of the LED lamp beads 201 is located at the left side of the LED lamp beads 201, the non-common electrode end 2012 of the LED lamp bead row 201a is located at the right side of the LED lamp beads 201, at this time, the non-common electrode ends 2012 of the LED lamp bead row 201a are all electrically connected to the surface layer of the PCB board 10, and form a data line 40 along the first direction, the data line 40 can directly run between the two LED lamp beads 201 without passing through the gap area between the cathode and the anode of any one of the LED lamp beads 201 on the PCB board 10, and by electrically connecting the common electrode ends 2011 of all the LED lamp beads 201 in the first row on the surface layer of the PCB board 10 without increasing the size of the LED lamp beads 201, and forming a scan line 30 along the second direction, each LED lamp bead 201 in the first row is not required to be provided with a via hole 101, so that the common electrode end 2011 of all the LED lamp beads 201 in the first row can be electrically connected to the surface layer of the PCB board 10, and the number of via holes 101 on the PCB board 10 can be reduced.

Similarly, when all the LED lamp beads 201 are arranged in the manner shown in fig. 4, that is, the common electrode end 2011 of the LED lamp bead 201 is located on the right side of the LED lamp bead 201, the non-common electrode end 2012 of the LED lamp bead 201 in the LED lamp bead row 201a is located on the left side of the LED lamp bead 201, all the non-common electrode ends 2012 of the LED lamp beads 201 in the LED lamp bead row 201a are electrically connected on the surface layer of the PCB board 10, and a data line 40 is formed along the first direction, the data line 40 can directly run between two LED lamp beads 201 without passing through the gap area between the cathode and the anode of any one of the LED lamp beads 201 on the PCB board 10, and the common electrode end 2011 of the last row of all the LED lamp beads 201 in the second direction is electrically connected on the surface layer of the PCB board 10 on the premise of not increasing the size of the LED lamp bead 201, and a scanning line 30 is formed along the second direction, and each LED lamp bead 201 in the last row is also not required to be provided with a via hole 101, so that the number of via holes 101 on the surface layer of the PCB board 10 can be reduced.

Wherein, every LED lamp pearl 201 on PCB board 10 in this application all can be the same size's LED lamp pearl 201, also can be the not unidimensional LED lamp pearl 201. The arrangement modes of the LED lamp beads 201 on the PCB 10 may be the same or different, and when the arrangement modes of the LED lamp beads 201 on the PCB are different, the common electrode ends 2011 of the two adjacent rows of the LED lamp beads 201 in the plurality of groups may be adjacent or the non-common electrode ends 2012 of the two adjacent rows of the LED lamp beads 201 in the second direction may be adjacent. As shown in fig. 5, the non-common electrode end 2012 of the first row of LED lamp beads 201 in the second direction may be adjacent to the non-common electrode end 2012 of the second row of LED lamp beads 201, the common electrode end 2011 of the second row of LED lamp beads 201 may be adjacent to the common electrode end 2011 of the third row of LED lamp beads 201, and the common electrode ends 2011 of the plurality of rows of LED lamp beads 201 in the second direction may also be electrically connected through the via holes 101 to form a scan line 30 along the second direction, and the non-common electrode end 2012 of each row of LED lamp beads 201 in the first direction is electrically connected to form a data line 40 along the first direction on the surface layer of the PCB board 10, so that the number of the via holes 101 on the PCB board 10 is smaller than the number of the LED lamp beads 201, thereby improving the yield of the PCB board 10, reducing the waste of materials, and reducing the manufacturing cost of the PCB board 10.

Meanwhile, the common electrode end 2011 of the LED lamp bead 201 may be a common cathode or a common anode; the gap area between the two rows of LED beads 201 in the first direction may be used for one data line 40 or two data lines 40 may be placed.

In addition, after the non-common electrode ends 2012 of each row of LED beads 201 in the first direction are electrically connected on the surface layer of the PCB board 10 to form one data line 40 along the first direction, each row of LED beads 201 needs to be LED beads 201 with the same light emitting color, so that the scanning line 30 in the LED display screen is changed from a row scanning line to a column scanning line, and the data line 40 is changed from a column data line to a row data line.

In some embodiments, the surface of the PCB board 10 is provided with a plurality of connection patterns, one connection pattern is disposed beside each via hole 101, and the connection patterns connect the via holes 101 and the common ends of the two LED lamp beads of the LED lamp bead group 201 c.

It can be appreciated that the scan lines 30 and the data lines 40 are respectively located on different layers of the PCB 10, such as the scan lines 30 are located on the inner side or the bottom layer of the PCB 10, the data lines 40 are located on the inner surface layer of the PCB 10, the non-common electrode end 2012 of the LED lamp bead 201 is connected with the data line 40 on the surface layer of the PCB 10, the common electrode end 2011 of the LED lamp bead 201 is connected with the scan lines 30 through the via 101, and the common electrode end 2011 of the LED lamp bead 201 is also connected on the surface layer of the PCB 10, if the common electrode end 2011 of the LED lamp bead 201 is connected with the via 101, the surface of the PCB 10 is necessarily provided with a connection pattern, the common electrode end 2011 of the LED lamp bead 201 is connected with the via 101 through the connection pattern, so that the LED lamp bead 201 and the PCB 10 are assembled conveniently, and the operation is simple.

The via row 101b includes a first side and a second side that are disposed opposite to each other, and the connection patterns corresponding to all the vias 101 in the same via row 101b are located on the first side or the second side.

In the adjacent via rows 101b, the connection patterns corresponding to all the vias 101 in one via row 101b are located on the first side, and the connection patterns corresponding to all the vias 101 in the other via row 101b are located on the second side. Alternatively, in all the via columns 101b, the connection pattern corresponding to each via column 101b is located on the first side of the corresponding via column 101b or the connection pattern corresponding to each via column 101b is located on the second side of the corresponding via column 101 b.

The pitch between adjacent vias 101 in the via row 101b is the same; and/or the pitch between adjacent vias 101 within a via row 101a is the same.

In some embodiments, two adjacent rows of LED light beads 201a in the first direction form a first LED light bead row group 210, and the data line 40 corresponding to each row of LED light beads 201 in the first LED light bead row group 210 passes through the first LED light bead row group 210 along the first direction. Specifically, the data line 40 corresponding to each row of LED beads 201a in the first LED bead row group 210 passes through the gap area of two rows of LED beads 201a in the first LED bead row group 210 along the first direction, at this time, the common terminal 2011 of one row of LED beads 201a in the first LED bead row group 210 and the common terminal 2011 of the LED bead row 201a above the common terminal 2011 of the first row of LED beads can be electrically connected on the surface layer of the PCB 10, and the common terminal 2011 of the other row of LED beads 201a in the first LED bead row group 210 and the common terminal 2011 of the LED beads 201a below the common terminal 2011 of the first row of LED beads can form the scanning line 30 along the second direction through the via hole 101 on the PCB 10, so that the number of the via holes 101 on the PCB 10 can be further reduced, and the yield of the PCB 10 can be improved.

In some embodiments, in the first LED light bead row group 210, the common electrode ends 2011 of the plurality of LED light beads 201 in any row are electrically connected through the via holes 101, so as to realize that the plurality of scanning lines 30 in the corresponding positions in the first LED light bead row group 210 are located in the inner layer or the bottom layer of the PCB board 10. Specifically, the first LED light bead row group 210 does not need to configure a via hole 101 on the PCB board 10 for all the LED light beads 201, and the common electrode end 2011 of part of the LED light beads 201 in the first LED light bead row group 210 can be routed on the surface layer of the PCB board 10 with the common electrode end 2011 of the LED light beads 201 below, and the common electrode end 2011 of the remaining LED light beads 201 in the first LED light bead row group 210 can directly pass through the via hole 101 on the PCB board 10 to perform a routing on the inner layer or the bottom layer of the PCB board 10.

It can be understood that, in the first direction, all the first LED light bead row groups 210 are formed by two adjacent LED light bead rows 201a, a group of first LED light bead row groups 210 may be present on the PCB board 10, and also a plurality of groups of first LED light bead row groups 210 may be present, where the number of groups of the first LED light bead row groups 210 may be specifically selected according to practical applications, which is not specifically limited in this application.

It may be further understood that, in the first direction, any two adjacent LED light bead rows 201a may form a first LED light bead row group 210, the first LED light bead row 201a and the second LED light bead row 201a may form a first LED light bead row group 210 as shown in fig. 3 and fig. 4, the second LED light bead row 201a and the third LED light bead row 201 may form a first LED light bead row group 210 as shown in fig. 6, and the formation mode of the first LED light bead row group 210 may be specifically selected according to practical applications, which is not specifically limited in this application.

Meanwhile, in order to reduce the number of the through holes 101 on the PCB 10 as much as possible, if the LED lamp beads 201 exist above the first LED lamp bead row group 210, the common electrode terminal 2011 of the LED lamp bead 201 adjacent to the upper side in the first LED lamp bead row group 210 and the common electrode terminal 2011 of the LED lamp bead 201 above may share one through hole 101, that is, a wire is routed between two common electrode terminals 2011 on the surface layer of the PCB 10, where one common electrode terminal 2011 is electrically connected with the common electrode terminal 2011 of other rows in the memory or bottom layer of the PCB 10 through the through hole 101; if the LED lamp beads 201 are present below the first LED lamp bead row group 210, the common electrode terminal 2011 of the LED lamp beads 201 adjacent to the lower side in the first LED lamp bead row group 210 may share one via hole 101 with the common electrode terminal 2011 of the LED lamp beads 201 below, that is, a line is routed between the two common electrode terminals 2011 on the surface layer of the PCB board 10, where one common electrode terminal 2011 may be electrically connected with the common electrode terminal 2011 of other rows in the memory or the bottom layer of the PCB board 10 through the via hole 101.

In some embodiments, in the LED lamp panel structure, two adjacent rows of LED lamp beads 201a in the first direction form a second LED lamp bead row group 220, and common electrode ends 2011 of two adjacent rows of LED lamp beads 201 in the second LED lamp bead row group 220 are electrically connected on the surface layer of the PCB board 10.

It can be appreciated that the second LED light bead row group 220 in the first direction may also be formed by two adjacent LED light bead rows 201a, and the gap area between the two adjacent LED light bead rows 201a may be used to route the common electrode ends 2011 of the two adjacent LED light beads 201 on the surface layer of the PCB 10, so as to realize that the two adjacent LED light beads 201 share one via hole 101 on the PCB 10, thereby reducing the number of via holes 101 on the PCB 10, improving the yield of the PCB 10, and reducing the manufacturing cost of the PCB 10.

It may be further understood that, in the first direction, all the second LED light bead row groups 220 are formed by two adjacent LED light bead rows 201a, a group of second LED light bead row groups 220 may be present on the PCB board 10, and also, a plurality of groups of second LED light bead row groups 220 may be present, any two adjacent LED light bead rows 201 may form a second LED light bead row group 220, the first row of LED light beads 201a and the second row of LED light beads 201a may form a second LED light bead row group 220 as shown in fig. 6, the second row of LED light beads 201a and the third row of LED light beads 201a may form a second LED light bead row group 220 as shown in fig. 3 and 4, and the number of groups of the second LED light bead row groups 220 and the forming mode of the second LED light bead row group 220 may all be specifically selected according to practical applications.

In some embodiments, as shown in fig. 7, the common electrode ends 2011 of some LED lamp beads 201 in the LED lamp bead columns 201b may all pass through the vias 101 on the PCB board 10 to form the scan line 30 along the second direction, as shown in fig. 8, except for the leftmost LED lamp bead column 201b in the LED lamp bead columns 201b in each column, the common electrode ends 2011 of the LED lamp beads 201 of the rest of LED lamp bead columns 201b may all pass through the vias 101 on the PCB board 10 to form the scan line 30 along the second direction. Compared with the arrangement mode of the LED lamp beads 201 in the prior art, the arrangement mode of the LED lamp beads 201 in fig. 7 and 8 can reduce the number of the through holes 101 on the PCB 10.

In some embodiments, the light emitting pixels 20 are arranged in an array in the first direction and the second direction. Wherein, LED lamp pearl 201 can be red LED lamp pearl, blue LED lamp pearl, green LED lamp pearl any one of, and every luminescent pixel 20 can be the same in this embodiment, and every luminescent pixel 20 can comprise red LED lamp pearl, blue LED lamp pearl, green LED lamp pearl, and red LED lamp pearl, blue LED lamp pearl, green LED lamp pearl can follow the second direction in proper order and vertically arrange from last down, and then make the left and right sides visual angle symmetry of LED display screen, and the visual angle is the biggest about the LED display screen after making the finished product.

It will be appreciated that the arrangement of the LED beads 201 in fig. 3 to 8 may be rotated 90 degrees in practical applications, that is, the column scan lines formed in fig. 3 to 7 become row scan lines, the row data lines become column data lines, and the LED beads 201 in each pixel 20 become laterally arranged.

It may be further understood that, in the LED lamp panel structure provided by the embodiment of the present invention, the LED lamp beads 201 may be packaged on the PCB 10 in a COB manner, or may be packaged on the PCB 10 in an SMD manner, and the actual application may be selected according to the specific situation, which is not specifically limited in this application.

Referring to fig. 8, 9 and 10, fig. 8 is a schematic structural diagram of a PCB board provided by an embodiment of the present invention, fig. 9 is a schematic surface layer diagram of the PCB board provided by the embodiment of the present invention, and fig. 10 is a schematic inner layer diagram of the PCB board provided by the embodiment of the present invention.

The embodiment of the application also provides an LED lamp panel structure, which comprises a PCB 10 for installing a plurality of LED lamp beads 201, wherein the PCB 10 comprises M data lines 40, N scanning lines 30 and a plurality of terminal pairs 110. The data lines 40 extend along the first direction, M is more than or equal to 4, and is an integer, and a plurality of data lines 40 are arranged at intervals along the second direction; the scan lines 30 extend along a second direction, N is greater than or equal to 2, and is an integer, and the plurality of scan lines 30 are arranged at intervals along a first direction, the second direction intersects the first direction, such as the first direction and the second direction are 90 degrees, the first direction is an X-axis direction, and the second direction is a Y-axis direction. The plurality of terminal pairs 110 are located on the surface layer of the PCB board 10, the plurality of terminal pairs 110 are arranged in an array in a first direction and a second direction to form M rows of terminal pairs 110 and N columns of terminal pairs 110, the rows formed by the plurality of terminal pairs 110 extend in the first direction, the M rows of terminal pairs are arranged at intervals in the second direction, the columns formed by the plurality of terminal pairs 110 extend in the second direction, and the N columns of terminal pairs 110 are arranged at intervals in the first direction. Each of the terminal pairs 110 includes a first terminal pattern 111 and a second terminal pattern 112, the first terminal pattern 111 of all the terminal pairs 110 in the ith row of terminal pairs 110 is connected to the ith data line 40, the second terminal pattern 112 of all the terminal pairs 110 in the jth column of terminal pairs 110 is connected to the jth scan line 30, the jth column of terminal pairs 110 includes a plurality of terminal pair groups including two adjacent terminal pairs 110, and two second terminal patterns 112 within a terminal pair group are connected to the same via 101. In the thickness direction of the PCB 10, the orthographic projections of the ith data line 40 and the (i+1) th data line 40 are located between the orthographic projections of the ith row of terminal pairs 110 and the (i+1) th row of terminal pairs 110.

It can be understood that the PCB board 10 is provided with M data lines 40, N scan lines 30 and a plurality of terminal pairs 110, each terminal pair 110 includes a first terminal pattern 111 and a second terminal pattern 112, the first terminal pattern 111 is used for connecting the non-common electrode 2012 of the LED lamp bead 201, the second terminal pattern 112 is used for connecting the common electrode 2011 of the LED lamp bead 201, the first terminal pattern 111 is connected with the data lines 40, the first terminal pattern 111 is disposed on the data lines 40 and located at one side of the data lines 40, two data lines 40 are located between the ith row of terminal pairs 110 and the i+1th row of terminal pairs 110 in the M data lines 40, and the two data lines 40 are respectively the ith data line 40 and the (i+1th) th data line 40. The first terminal patterns 111 of all the terminal pairs 110 in the ith row of terminal pairs 110 are located at one side of the ith data line 40, the first terminal patterns 111 of all the terminal pairs 110 in the (i+1) th row of terminal pairs 110 are located at one side of the (i+1) th data line 40, the first terminal patterns 111 on the (i+1) th data line 40 are disposed opposite to the first terminal patterns 111 on the (i+1) th data line 40, and the first terminal patterns 111 on the (i-1) th data line 40 are disposed opposite to the first terminal patterns 111 on the (i) th data line 40, and two rows of terminal pairs 110 are disposed between the (i-1) th data line 40 and the (i) th data line 40.

Through set up the orthographic projection of ith data line 40 and the ith +1th data line 40 on the PCB board, all be located between the orthographic projection of ith row terminal pair 110 and the ith +1th row terminal pair 110, reduced the distance between ith data line 40 and the ith +1th data line 40, reduced the size of PCB board 10, same via 101 is connected to the second terminal pattern 112 of two adjacent terminal pairs 10, reduced the quantity of via 101, improved the yields of PCB board 10, reduced the waste of material, reduced the manufacturing cost of PCB board 10.

In some embodiments, referring to fig. 9, M data lines 40 are located on the surface layer of the PCB board 10, N scan lines 30 are located on the inner layer or bottom layer of the PCB board 10, and the second terminal patterns 112 of all the terminal pairs 110 in the j-th column of terminal pairs 110 are connected to the j-th scan lines 30 through vias 101.

The terminal pair 110 is disposed on the surface layer of the PCB 10, and the second terminal pattern 112 of the terminal pair 110 is connected with the scan line 30 in a cross-layer manner, so that a plurality of vias 101 are disposed on the PCB 10, the second terminal pattern 112 is connected with the scan line 30 through the vias 101, the processing technology of the terminal pair 110 is simple, and the connection operation with the LED lamp beads 201 is convenient.

In some embodiments, the PCB board 10 is provided with a plurality of vias 101, where the plurality of vias 101 are arranged in an array in a first direction and a second direction to form a via row 101a and a via column 101b, the via row 101a extends along the first direction, the via column 101b extends along the second direction, and two data lines 40 are disposed between adjacent via rows 101 a.

It will be appreciated that the plurality of vias 101 are arranged in an array in the first direction and the second direction to form M rows of via rows 101a and N columns of via columns 101b, the number M of the via 101 is half the number M of the terminal pairs 110, the number of columns of the vias 101 is the same as the number of columns of the terminal pairs 110, the second terminal pattern 112 of the j-th column of the terminal pairs 110 is connected to the j-th column of the vias 101, the j-th column of the terminal pairs 110 is located beside the j-th column of the vias 101, and the i-th data line 40 and the i+1-th data line 40 are disposed between the adjacent via rows 101 a. Compared with the number of the through holes 101 connected with the second terminal patterns 112 of one terminal pair 110, the number of the formed through hole rows 101a is increased, the two second terminal patterns 112 are connected with one through hole 101, and two data lines 40 are arranged between the adjacent through hole rows 101a, so that the number of the through hole rows 101a is reduced, the yield of the PCB 10 is improved, the waste of materials is reduced, and the manufacturing cost of the PCB 10 is reduced.

In some embodiments, the spacing between adjacent vias 101 within a via column 101b is the same. And/or the spacing between adjacent vias 101 within a via row 101a is the same.

It is understood that the vias 101 may be circular or rectangular, such as circular, and that the spacing between adjacent vias 101 refers to the distance between the centers of the adjacent vias 101. The spacing between adjacent vias 101 within a via column 101b is the same or approximately the same, such as a pitch error between adjacent vias 101 within + -10% of the set point may be considered the same pitch. The spaces between the adjacent vias 101 in the via hole rows 101a are the same, the spaces between the LED beads 201 in the LED bead rows 201a are uniform, and the brightness is uniform in the display area.

In some embodiments, the spacing between adjacent ones 110 of the i-th row of terminal pairs 110 is the same. And/or, the j-th column terminal pair 110 has the same interval between adjacent terminal pairs 110 112.

In the i-th row of terminal pairs 110, the pitch between adjacent terminal pairs 110 refers to the distance between the inner edges of the adjacent terminal pairs 110, and the pitches formed between the terminal pairs 110 are the same or approximately the same, for example, the pitch error between the adjacent terminal pairs 1101 is within ±10% of the set value, which can be considered as the same pitch, so that the routing on the PCB board 10 is convenient to process, and the processing technology is simple.

In the j-th column of terminal pairs 110, the distance between adjacent terminal pairs 110 refers to the distance between the lower edge of the i-th row of terminal pairs and the upper edge of the i+1-th row of terminal pairs, the distances between the terminal pairs 110 are identical or approximately identical, for example, the distances between adjacent terminal pairs 1101 can be considered identical within +/-10% of the set value, the routing on the PCB board 10 is convenient to process, and the processing technology is simple.

In some embodiments, the via 101 includes a first side and a second side that are oppositely disposed, and the second terminal pattern 112 of all terminal pairs 110 in the j-th column of terminal pairs 110 is located on the first side of the aligned via 101 or the second terminal pattern 112 of all terminal pairs in the j-th column of terminal pairs is located on the second side of the aligned via 101.

It can be understood that, along the first direction, the first side and the second side of the via hole 101 are arranged opposite to each other at intervals, the second terminal patterns 112 of the j-th row of terminal pairs 110 are also located in the same row, and the row where the second terminal patterns 112 of the j-th row of terminal pairs 110 are located is located on the first side or the second side of the via hole 101, so that the second terminal patterns 112 can be conveniently processed on the PCB board 10, and the processing technology is simple.

In some embodiments, the second terminal patterns 112 of all terminal pairs 110 in each column of terminal pairs 110 are located on the first side of the via 101 or the second terminal patterns 112 of all terminal pairs in each column of terminal pairs are located on the second side of the via 101; or, the second terminal patterns 112 of all the terminal pairs in the j-th column are located at the first side of the via 101, and the second terminal patterns 112 of all the terminal pairs in the j+1-th column are located at the second side of the via 101.

The PCB board 10 has a plurality of rows of terminal pairs 110, the positional relationship between each row of terminal pairs 110 and the aligned via 101 may be the same, such as the second terminal patterns 112 of all terminal pairs 110 in each row of terminal pairs 110 are located on the first side of the via 101 or the second terminal patterns 112 of all terminal pairs in each row of terminal pairs are located on the second side of the via 101, or the positional relationship between different rows of terminal pairs 110 and the aligned via 101 may be different, such as the second terminal patterns 112 of all terminal pairs in the j-th row of terminal pairs are located on the first side of the via 101, and the second terminal patterns 112 of all terminal pairs in the j+1-th row of terminal pairs are located on the second side of the via 101.

In some embodiments, the first terminal patterns 111 of all the terminal pairs 110 in the j-th column of terminal pairs are located on the same column, the second terminal patterns 112 of all the terminal pairs 110 are located on the same column, and the second terminal patterns 112 are closer to the via 101 than the first terminal patterns 111; or, the first terminal patterns 111 of all the terminal pairs 110 in the j-th column of terminal pairs are located on the same column, the second terminal patterns 112 of all the terminal pairs 110 are located on the same column, and the first terminal patterns 111 are closer to the via 101 than the second terminal patterns 112; alternatively, the first terminal pattern 111 of any one of the terminal pairs 110 is located on the same column as the second terminal pattern 112 of the other terminal pair 110 in all the j-th column.

In some embodiments, the width of the scan line 30 is greater than the width of the terminal pair 110, wherein the width of the scan line 30 refers to the distance between the edges of the two sides of the scan line 30 along the first direction, and the width of the terminal pair 110 refers to the distance between the edge of the first terminal pattern 111 and the edge of the second terminal pattern 112 along the first direction. The width of the scan line 30 is designed to be larger than the width of the terminal pair 110, and the impedance can be reduced during the use of the PCB board 10.

In some embodiments, the plurality of scanning lines are connected to one port of the driving circuit board through the same PAD, and the plurality of data lines are connected to one port of the driving circuit board through the same PAD, so that the utilization rate of the pins of the driving chip on the driving circuit board can be improved; optionally, the scan lines and the data lines of the common ports are disposed in an edge area of the panel, where the contrast requirement of the area on the image is relatively low, and pixels in the area are divided into driving units according to the size of a (parallel scan line data) ×b (parallel data line number), and the driving units are sent to the driving unit as a whole.

In some embodiments, two second terminal patterns 112 connecting the same via 101 are identical; or, two second terminal patterns 112 connected to the same via 101 are different; or, the first terminal pattern 111 and the second terminal pattern 112 of the terminal pair are the same; or, the first terminal pattern 111 and the second terminal pattern 112 of the terminal pair are different. Such as the shape of the second terminal pattern 112 is rectangular or circular, or the shape of the first terminal pattern 111 is rectangular or circular.

It can be appreciated that the second terminal pattern 112 is connected to the via hole 101 through an intermediate pattern, the intermediate pattern is "character-shaped", the intermediate pattern has two first ends and one second end arranged along the first direction, the two second terminal patterns 112 are respectively located at the first ends of the intermediate pattern, the second ends of the intermediate pattern are connected to the via hole 101, the two second terminal patterns 112 are arranged at intervals along the first direction and are respectively located at two ends of the intermediate pattern, the two second terminal patterns 112 can be round or rectangular, one of the two second terminal patterns can be round, the other one of the two second terminal patterns is rectangular, and the two second terminal patterns can be flexibly designed according to the space of the PCB board, thereby having wide application range.

In some embodiments, two second terminal patterns 112 connected to the same via 101 are respectively located at both ends of the same rectangular pattern, and a middle position of the rectangular pattern is connected to the via. The middle position of the rectangular pattern refers to the middle point position of the side edge of the rectangular pattern extending along the first direction.

It will be appreciated that the two second terminal patterns 112 are located at two ends of the same rectangular pattern, the rectangular pattern extends in the first direction, the rectangular pattern is connected to the via 101 through an intermediate pattern, the intermediate pattern is also rectangular, one end of the intermediate pattern is connected to the middle position of the rectangular pattern, and the other end of the intermediate pattern is connected to the via 101.

In some embodiments, the ith data line 40 and the (i+1) th data line 40 trisect the spacing between the ith row of terminal pairs 110 and the (i+1) th row of terminal pairs 110.

It will be appreciated that the first terminal pattern 111 on the ith data line 40 is disposed opposite to the first terminal pattern 111 on the ith+1 data line 40, the first terminal patterns 111 of all the terminal pairs 110 in the ith row of terminal pairs 110 are disposed on a side of the ith data line 40 facing away from the ith+1 data line 40, the first terminal patterns 111 of all the terminal pairs 110 in the ith+1 row of terminal pairs 110 are all disposed on a side of the ith+1 data line 40 facing away from the ith data line 40, and the distances between the first terminal patterns 111 of the ith row of terminal pairs 110 and the first terminal patterns 111 of the ith+1 row of terminal pairs 110 are all equal to an even number, i.e., the distances between the ith row of terminal pairs 110 and the ith data line 40, the distances between the ith data line 40 and the ith+1 data line 40, and the distances between the ith+1 row of terminal pairs 110, wherein i is equal to an even number.

Referring to fig. 9, the minimum unit of the PCB board 10 includes 4 data lines 40, 2 scan lines 30, 8 terminal pairs 110 and 4 vias 101, the data lines 40 extend along the X-axis direction, 4 data lines 40 are arranged at intervals along the Y-axis direction, the scan lines 30 extend along the Y-axis direction, 2 scan lines 30 are arranged at intervals along the X-axis direction, 8 terminal pairs 110 are arranged in an array along the X-axis direction and the Y-axis direction to form 4 row terminal pairs 110 and 2 column terminal pairs 110, all first terminal sub-patterns 111 of the i-th row terminal pairs 110 are connected with the i-th row data lines 40, the 2-row data lines 40 and 3-th row data lines 40 are located between the 2-row terminal pairs 110 and the 3-th row terminal pairs 110, such as all first terminal sub-patterns 111 of the 2-row terminal pairs 110 are located at a side of the 2-row data lines 40 facing away from the 3-row data lines 40, all first terminal patterns 111 of the 3-row terminal pairs 110 are located at a side of the 3-row data lines 40 facing away from the 2-row data lines 40, and are connected with the 3-row data lines 40. The j-th column terminal pair 110 is located at one side of the j-th column scan line 30, and all the second terminal patterns 112 in the j-th column terminal pair 110 are connected to the j-th column scan line 30. The 4 vias 101 are arranged in an array along the X-axis direction and the Y-axis direction to form 2 rows of vias 101 and 2 columns of vias 101, the j-th column of vias 101 is located on the j-th column of scan lines 30, the second terminal pattern 112 in the j-th column of terminal pairs 110 is connected with the j-th column of vias 101, the second terminal pattern 112 of the 1 st row of terminal pairs 110 and the second terminal pattern 112 of the 2 nd row of terminal pairs 110 are connected with the 1 st row of vias 101, and the second terminal pattern 112 of the 3 rd row of terminal pairs 110 and the second terminal pattern 112 of the 4 th row of terminal pairs 110 are connected with the 2 nd row of vias 101.

In the implementation, each unit or structure may be implemented as an independent entity, or may be implemented as the same entity or several entities in any combination, and the implementation of each unit or structure may be referred to the foregoing embodiments and will not be repeated herein.

The above describes in detail an LED lamp panel structure provided by the embodiments of the present invention, and specific examples are applied herein to illustrate the principles and embodiments of the present invention, where the above description of the embodiments is only for helping to understand the method and core ideas of the present invention; meanwhile, the contents of the present specification should not be construed as limiting the present invention in view of the fact that those skilled in the art can vary in specific embodiments and application scope according to the ideas of the present invention.

Claims

1. An LED lamp panel structure, comprising:

2. The LED light bead structure of claim 1, wherein a plurality of connection patterns are provided on the surface of the PCB board, one connection pattern is provided beside each via hole, and the connection patterns connect the via holes and the common ends of the two LED light beads of the LED light bead group.

3. An LED lamp panel structure, comprising:

PCB board for install a plurality of LED lamp pearls, PCB board includes:

4. The LED lamp panel structure of claim 3, wherein,

the plurality of through holes are arranged in an array manner in the first direction and the second direction to form a plurality of through hole rows and a plurality of through hole columns, the through hole rows extend along the first direction, the through hole columns extend along the second direction, and two data lines are arranged between every two adjacent through hole rows.

5. The LED lamp panel structure of claim 4, wherein,

the interval between adjacent through holes in the through hole columns is the same;

6. A LED lamp panel structure according to claim 3, wherein the spacing between adjacent ones of the i-th row of terminal pairs is the same;

7. The LED lamp panel structure of claim 3, wherein the via includes oppositely disposed first and second sides, the second terminal pattern of all of the terminal pairs in the j-th column of the terminal pairs being located on the first side of the via or the second terminal pattern of all of the terminal pairs in the j-th column of the terminal pairs being located on the second side of the via.

8. The LED lamp panel structure of claim 7, wherein the second terminal patterns of all of the terminal pairs of each column of the terminal pairs are located on a first side of the via or the second terminal patterns of all of the terminal pairs of each column of the terminal pairs are located on a second side of the via;

9. The LED lamp panel structure of claim 7, wherein the scan line has a width that is greater than a width of the terminal pair.

10. The LED lamp panel structure of claim 3, wherein the first terminal patterns of all of the terminal pairs in the j-th column of the terminal pairs are on the same column, the second terminal patterns of all of the terminal pairs are on the same column, and the second terminal patterns are closer to the via than the first terminal patterns;

11. The LED lamp panel structure of claim 3, wherein two of the second terminal patterns connecting the same via are identical;

or, two second terminal patterns connected to the same via hole are different;

12. The LED lamp panel structure of claim 3 or 11, wherein the second terminal pattern is rectangular or circular in shape;

or, the shape of the first terminal pattern is rectangular or circular.

13. The LED lamp panel structure of claim 3, wherein two second terminal patterns connected to the same via are respectively located at two ends of the same rectangular pattern, and a middle position of the rectangular pattern is connected to the via.