CN117747556A - 具有粘合层的封装结构及其封装方法 - Google Patents
具有粘合层的封装结构及其封装方法 Download PDFInfo
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- CN117747556A CN117747556A CN202311080413.0A CN202311080413A CN117747556A CN 117747556 A CN117747556 A CN 117747556A CN 202311080413 A CN202311080413 A CN 202311080413A CN 117747556 A CN117747556 A CN 117747556A
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- 239000012790 adhesive layer Substances 0.000 title claims abstract description 101
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 37
- 238000000034 method Methods 0.000 title claims abstract description 32
- 239000010410 layer Substances 0.000 claims abstract description 146
- 238000007789 sealing Methods 0.000 claims description 45
- 229910000679 solder Inorganic materials 0.000 claims description 45
- 239000000853 adhesive Substances 0.000 claims description 28
- 230000001070 adhesive effect Effects 0.000 claims description 28
- 238000003466 welding Methods 0.000 claims description 26
- 239000013078 crystal Substances 0.000 claims description 19
- 238000004519 manufacturing process Methods 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 14
- 238000003825 pressing Methods 0.000 claims description 10
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 238000005520 cutting process Methods 0.000 claims 2
- 239000000758 substrate Substances 0.000 description 12
- 238000007906 compression Methods 0.000 description 11
- 230000006835 compression Effects 0.000 description 10
- 238000005476 soldering Methods 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 230000008054 signal transmission Effects 0.000 description 3
- 239000002904 solvent Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000000155 melt Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 229920006336 epoxy molding compound Polymers 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 238000007731 hot pressing Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 238000003032 molecular docking Methods 0.000 description 1
- 229920000620 organic polymer Polymers 0.000 description 1
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- H—ELECTRICITY
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
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Abstract
本发明是一种具有粘合层的封装结构及其封装方法。该具有粘合层的封装结构包含第一重分布线路层、粘合层及第一电子元件,该第一重分布线路层具有第一上表面及第一下表面,该第一上表面具有多个上凸块,该第一下表面具有多个导接垫,该粘合层位于该第一重分布线路层的该第一上表面,且该粘合层围绕所述多个上凸块,该第一电子元件设置于该粘合层上,该第一电子元件具有第一主动面及多个导接件,所述多个导接件显露于该第一主动面上,该第一主动面朝向该第一上表面,且各该导接件连接各该上凸块,其中该粘合层的两个粘接面分别粘接该第一上表面及该第一主动面。
Description
技术领域
本发明是关于一种封装结构及其封装方法,特别是关于一种具有粘合层的封装结构及其封装方法。
背景技术
目前半导体封装朝向更高密度的结构进行发展,以提高半导体芯片的信号传播速率及功率密度,常见的封装结构是通过硅穿孔(TSV)让不同晶粒能够垂直堆叠并借由硅穿孔中的金属进行信号传输,又或是通过重分布线路层(RDL)让不同晶粒能够设置在同一封装结构中。其中,在晶粒与重分布线路层进行热压合时,容易因为晶粒本身的应力而翘曲,导致接合强度受到影响,另外,由于晶粒的焊接凸块与重分布线路层的接合凸块之间也容易产生位置偏差,导致凸块与凸块之间接触面积较小而影响其接合强度。
发明内容
本发明的主要目的在于借由粘合层粘接重分布线路层及电子元件,以大幅提高两个元件间的接合强度,而能够完成更加复杂的封装结构。
本发明的一种具有粘合层的封装结构包含第一重分布线路层、粘合层及第一电子元件,该第一重分布线路层具有第一上表面及第一下表面,该第一上表面具有多个上凸块,该第一下表面具有多个导接垫,该粘合层位于该第一重分布线路层的该第一上表面,且该粘合层围绕所述多个上凸块,该第一电子元件设置于该粘合层上,该第一电子元件具有第一主动面及多个导接件,所述多个导接件显露于该第一主动面上,该第一主动面朝向该第一上表面,且各该导接件连接各该上凸块,其中该粘合层的两个粘接面分别粘接该第一上表面及该第一主动面。
较佳地,该粘合层是由有机粘合材料固化形成。
较佳地,包含多个导接元件,所述多个导接元件位于该第一重分布线路层的该第一下表面,且各该导接元件连接各该导接垫。
较佳地,该第一电子元件具有第一密封体、第一晶粒及多个第一焊接凸块,所述多个第一焊接凸块位于该第一晶粒上,该第一密封体围绕该第一晶粒及所述多个第一焊接凸块,且该第一密封体的第一显露表面显露各该第一焊接凸块的第一连接面,该第一显露表面即为该第一电子元件的该第一主动面,所述多个第一焊接凸块即为该第一电子元件的所述多个导接件。
较佳地,该第一电子元件具有第二重分布线路层,该第二重分布线路层具有第二下表面及第二上表面,该第二下表面的多个下重分布导接垫连接所述多个上凸块,该第二上表面的多个上重分布导接垫连接所述多个第一焊接凸块,该第二下表面即为该第一电子元件的该第一主动面,所述多个下重分布导接垫即为该第一电子元件的所述多个导接件。
较佳地,包含第二电子元件及第三重分布线路层,该第二电子元件具有第二密封体、第二晶粒及多个第二焊接凸块,该第二晶粒具有下导接面及上导接面,所述多个第二焊接凸块的两端分别连接该下导接面及该第三重分布线路层的多个上导接垫,该第二密封体围绕该第二晶粒及该第二焊接凸块,且该第二晶粒的该上导接面及该第二焊接凸块的第二连接面显露于该第二密封体外,该第二晶粒的该上导接面连接该第一重分布线路层的所述多个导接垫。
较佳地,包含多个导接元件,所述多个导接元件连接第三重分布线路层的多个下导接垫。
本发明的一种具有粘合层的封装结构的封装方法包含提供第一重分布线路层,该第一重分布线路层具有第一上表面及第一下表面,该第一上表面具有多个上凸块,该第一下表面具有多个导接垫;在该第一重分布线路层上形成粘合层,该粘合层位于该第一重分布线路层的该第一上表面,且该粘合层围绕所述多个上凸块;平坦化该粘合层,使所述多个上凸块显露于该粘合层;设置第一电子元件于该粘合层上,该第一电子元件具有第一主动面及多个导接件,所述多个导接件显露于该第一主动面上,该第一主动面朝向该第一上表面;以及热压合该第一电子元件及该第一重分布线路层,使各该导接件连接各该上凸块,其中该粘合层的两个粘接面在热压合中分别粘接该第一上表面及该第一主动面。
较佳地,在该第一重分布线路层上形成该粘合层包含:涂布有机粘合材料于该第一重分布线路层上;加热并冷却该有机粘合材料使其固化为该粘合层。
较佳地,平坦化该粘合层是以飞切工艺(Fly-cut)对该粘合层进行切削。
较佳地,在热压合该第一电子元件及该第一重分布线路层后另包含再次对该粘合层进行升温及冷却而完成最终固化。
较佳地,包含设置多个导接元件于该第一重分布线路层的该第一下表面,且各该导接元件连接各该导接垫。
较佳地,该第一电子元件的制造方法为:在第一晶粒上形成多个第一焊接凸块;形成第一密封体包覆该第一晶粒及所述多个第一焊接凸块;平坦化该第一密封体而形成第一显露表面,该第一显露表面显露各该第一焊接凸块的第一连接面,且该第一显露表面即为该第一电子元件的该第一主动面,所述多个第一焊接凸块即为该第一电子元件的所述多个导接件。
较佳地,该第一电子元件的制造方法为:在第一晶粒上形成多个第一焊接凸块;形成第一密封体包覆该第一晶粒及所述多个第一焊接凸块;平坦化该第一密封体而形成第一显露表面,该第一显露表面显露各该第一焊接凸块的第一连接面;形成第二重分布线路层于该第一显露表面上,该第二重分布线路层具有第二下表面及第二上表面,该第二上表面的多个上重分布导接垫连接所述多个第一焊接凸块,该第二下表面即为该第一电子元件的该第一主动面,该第二下表面的多个下重分布导接垫即为该第一电子元件的所述多个导接件,其中,当该第一电子元件及该第一重分布线路层热压合时,该第二下表面的多个下重分布导接垫连接所述多个上凸块。
较佳地,该第一重分布线路层是设置于第二电子元件及第三重分布线路层上,该第二电子元件具有第二密封体、第二晶粒及多个第二焊接凸块,该第二晶粒具有下导接面及上导接面,所述多个第二焊接凸块的两端分别连接该下导接面及该第三重分布线路层的多个上导接垫,该第二密封体围绕该第二晶粒及该第二焊接凸块,且该第二晶粒的该上导接面及该第二焊接凸块的第二连接面显露于该第二密封体外,该第二晶粒的该上导接面连接该第一重分布线路层的所述多个导接垫。
较佳地,包含设置多个导接元件于该第三重分布线路层的多个下导接垫上,使各该导接元件连接各该下导接垫。
本发明借由该粘合层粘接该第一重分布线路层及该第一电子元件,可大幅提高该第一重分布线路层及该第一电子元件之间的接合强度,让该封装结构能够设计得更为复杂及紧凑,以提高信号传输速率及功率密度。
附图说明
图1:依据本发明的第一实施例,一封装结构的剖视图。
图2:依据本发明的第二实施例,一封装结构的剖视图。
图3:依据本发明的第三实施例,一封装结构的剖视图。
图4:依据本发明的第四实施例,一封装结构的剖视图。
图5a、图5b及图5c:依据本发明的该第一实施例,该封装结构的封装方法的流程图。
图6a、图6b及图6c:依据本发明的该第三实施例,该封装结构的封装方法的流程图。
图7a、图7b及图7c:依据本发明的该第四实施例,该封装结构的封装方法的流程图。
【主要元件符号说明】
100:具有粘合层的封装结构 110:第一重分布线路层
111:第一上表面 111a:上凸块
112:第一下表面 112a:导接垫
120:粘合层 130:第一电子元件
131:第一密封体 131a:第一显露表面
132:第一晶粒 133:第一焊接凸块
133a:第一连接面 134:第二重分布线路层
134a:第二下表面 134b:第二上表面
134c:下重分布导接垫 134d:上重分布导接垫
140:导接元件 150:第二电子元件
151:第二密封体 152:第二晶粒
152a:下导接面 152b:上导接面
153:第二焊接凸块 153a:第二连接面
160:第三重分布线路层 161:上导接垫
162:下导接垫 t1:第一粘合胶
s1:第一承载基板 t2:第二粘合胶
s2:第二承载基板
具体实施方式
请参阅图1,其为本发明的第一实施例,一种具有粘合层的封装结构100的剖视图,其包含第一重分布线路层110、粘合层120及第一电子元件130。该第一重分布线路层110具有第一上表面111及第一下表面112,该第一上表面111具有多个上凸块111a,该第一下表面112具有多个导接垫112a。其中,该第一重分布线路层110还具有至少一个线路层及绝缘层,该线路层用以提供各该上凸块111a及各该导接垫112a之间的电性连接,该绝缘层则用以提供该些金属层承载及绝缘,由于该第一重分布线路层110内部的该线路层的实施方式多变并非本案主要的技术特征,因此图中仅以多个方块示意。
该粘合层120位于该第一重分布线路层110的该第一上表面111,且该粘合层120围绕所述多个上凸块111a,在本实施例中,该粘合层120是由有机粘合材料固化形成,较佳的,该粘合层120的热膨胀系数与该第一重分布线路层110的该绝缘层相似,以避免后续高温工艺导致热膨胀不均而翘曲的问题发生。该第一电子元件130设置于该粘合层120上,该第一电子元件130具有第一主动面及多个导接件,所述多个导接件显露于该第一主动面上,该第一主动面朝向该第一上表面111,且各该导接件连接各该上凸块111a,其中该粘合层120的两个粘接面分别粘接该第一上表面111及该第一主动面。
请参阅图1,在本实施例中,该第一电子元件130具有第一密封体131、第一晶粒132及多个第一焊接凸块133,所述多个第一焊接凸块133位于该第一晶粒132上,该第一密封体131围绕该第一晶粒132及所述多个第一焊接凸块133,且该第一密封体131的第一显露表面131a显露各该第一焊接凸块133的第一连接面133a。其中,该第一密封体131的该第一显露表面131a即为该第一电子元件130的该第一主动面,所述多个第一焊接凸块133即为该第一电子元件130的所述多个导接件。在本实施例中,该第一密封体131为封装环氧树脂(EpoxyMolding Compound,EMC),所述多个第一焊接凸块133则为金属合金或单一金属。
本实施例通过热压合使该第一电子元件130的各该第一焊接凸块133与该第一重分布线路层110的各该上凸块111a共晶连接,且热压合的加热温度让该粘合层120再次融化并粘接该第一电子元件130的该第一显露表面131a及该第一重分布线路层110的该第一上表面111,该粘合层120并在热压合完成后冷却固化,通过热压合的加温,能让该粘合层120的溶剂挥发使其硬度提升。本实施例通过该粘合层120粘接该第一电子元件130及该第一重分布线路层110让两个元件之间不仅是借由金属凸块的共晶相互连接而大幅提高两个元件间的接合强度,可避免该第一电子元件130在热压合工艺中翘曲进而能让该具有粘合层的封装结构100达成更高复杂度的设计。
请再参阅图1,该具有粘合层的封装结构100另包含多个导接元件140,所述多个导接元件140位于该第一重分布线路层110的该第一下表面112,且各该导接元件140连接各该导接垫112a。借由所述多个导接元件140能够让该具有粘合层的封装结构100与其他电子元件,例如与电路板或软性电路板相互连接并传输信号。在本实施例中,所述多个导接元件140为焊接锡球,而在其他实施例中,所述多个导接元件140亦可为焊接凸块、异方向性导电膜(ACF)或打线封装(Wire bonding)。
请参阅图1,在第一实施例中,该第一密封体131中具有两个该第一晶粒132,在其他实施例中,该第一密封体131中仅具有一个或多个第一晶粒132,该第一晶粒132的数量并非本案的所限。或者,请参阅图2,其为本发明的第二实施例,其与第一实施例的差异在于该第一重分布线路层110上具有两个该第一电子元件130,该两个第一电子元件130可分别为CPU芯片及内存芯片,且该两个电子元件130可借由该第一重分布线路层110相互电性连接或是导接至位于该第一重分布线路层110的该第一下表面112的所述多个导接元件140,而可达成SiP(System in Package)的结构。
请参阅图3,其为本发明的第三实施例,其与第一实施例的差异在于该第一电子元件130另具有第二重分布线路层134,该第二重分布线路层134具有第二下表面134a及第二上表面134b,该第二下表面134a的多个下重分布导接垫134c连接所述多个上凸块111a,该第二上表面134b的多个上重分布导接垫134d连接所述多个第一焊接凸块133。在本实施例中,该第二下表面134a即为该第一电子元件130的该第一主动面,所述多个下重分布导接垫134c即为该第一电子元件130的所述多个导接件。借由该第二重分布线路层134的设置,可提高各该下重分布导接垫134c与各该上凸块111a之间的接触面积,让第一电子元件130与该第一重分布线路层110之间有着更灵活的线路布局。此外,较佳的,该第二重分布线路层134亦具有用以提供支撑及绝缘的绝缘体,且该绝缘体也是由有机粘合材料或是与该粘合层120的热膨胀系数相似的有机聚合物制成,同样地可避免该第二重分布线路层134与该粘合层120在热压合时因为热膨胀系数不同而剥离。
请参阅图4,其为本发明的第四实施例,其与第三实施例的差异在于另包含第二电子元件150及第三重分布线路层160,该第二电子元件150具有第二密封体151、第二晶粒152及多个第二焊接凸块153,该第二晶粒152具有下导接面152a及上导接面152b,所述多个第二焊接凸块153的两端分别连接该下导接面152a及该第三重分布线路层160的多个上导接垫161,该第二密封体151围绕该第二晶粒152及该第二焊接凸块153,且该第二晶粒152的该上导接面152b及该第二焊接凸块153的第二连接面153a显露于该第二密封体151外,该第二晶粒152的该上导接面152b连接该第一重分布线路层110的所述多个导接垫112a。在本实施例中,所述多个导接元件140是连接该第三重分布线路层160的多个下导接垫162,以借由所述多个导接元件140让该第一电子元件130及该第二电子元件150对外传输信号。
本发明借由该粘合层120粘接该第一重分布线路层110及该第一电子元件130,可大幅提高该第一重分布线路层110及该第一电子元件130之间的接合强度,让该具有粘合层的封装结构100能够设计得更为复杂及紧凑,以提高信号传输速率及功率密度。
请参阅图5a、图5b及图5c,其为本发明第一实施例的该具有粘合层的封装结构100的制作流程,请先参阅图5a,提供第一重分布线路层110,该第一重分布线路层110通过第一粘合胶t1设置于第一承载基板s1上,该第一重分布线路层110具有第一上表面111及第一下表面112,该第一上表面111具有多个上凸块111a,该第一下表面112具有多个导接垫112a。接着,在该第一重分布线路层110上形成粘合层120,该粘合层120位于该第一重分布线路层110的该第一上表面111,且该粘合层120围绕所述多个上凸块111a。在本实施例中,形成该粘合层120包含:涂布有机粘合材料于该第一重分布线路层110上;及加热该有机粘合材料并使其冷却固化为该粘合层120。最后,平坦化该粘合层120,使所述多个上凸块111a显露于该粘合层120上,较佳的,本实施例是以飞切工艺(Fly-cut)对固化的该粘合层120进行切削。
请参阅图5b,第一实施例的该第一电子元件130的制造方法是先通过第二粘合胶t2将多个第一晶粒132设置于第二承载基板s2上,并在所述多个第一晶粒132上形成多个第一焊接凸块133。接着,形成第一密封体131包覆该第一晶粒132及所述多个第一焊接凸块133。最后,平坦化该第一密封体131而形成第一显露表面131a,该第一显露表面131a显露各该第一焊接凸块133的第一连接面133a,且该第一显露表面131a即为该第一电子元件130的该第一主动面,所述多个第一焊接凸块133即为该第一电子元件130的所述多个导接件。
完成图5a及图5b的流程后,请参阅图5c,将该第一电子元件130反置于该粘合层120上,使该第一密封体131的该第一显露表面131a及各该第一焊接凸块133的该第一连接面133a朝向该第一上表面111后,热压合该第一电子元件130及该第一重分布线路层110,使各该第一焊接凸块133与各该上凸块111a共晶连接。其中,该粘合层120会在热压合的高温下再次融化,使得该粘合层120的两个粘接面在热压合中分别粘接该第一上表面111及该第一显露表面131a,且在热压合完成后该粘合层120再次冷却固化成型。
此外,由形成该粘合层120的该有机粘合材料的特性而定,若该热压合的温度不足以让该有机粘合材料内的溶剂完全挥发时,则在热压合该第一电子元件130及该第一重分布线路层110后另包含再次对该粘合层120进行升温让剩余的溶剂挥发再冷却而完成最终固化的步骤。最终,移除该第一粘合胶t1、该第一承载基板s1并设置多个导接元件140于该第一重分布线路层110的该第一下表面112,使各该导接元件140连接各该导接垫112a后,移除该第二粘合胶t2及该第二承载基板s2而完成该具有粘合层的封装结构100的制作。
参阅图6a、图6b及图6c,其为本发明第三实施例的该具有粘合层的封装结构100的制作流程,其中图6a的制作流程与第一实施例的图5a相同,因此不再赘述。请参阅图6b,为第三实施例的该第一电子元件130的制造方法,首先通过第二粘合胶t2将多个第一晶粒132设置于第二承载基板s2上,并在各该第一晶粒132上形成所述多个第一焊接凸块133;接着,形成第一密封体131包覆该第一晶粒132及所述多个第一焊接凸块133;接着,平坦化该第一密封体131而形成第一显露表面131a,该第一显露表面131a显露各该第一焊接凸块133的第一连接面133a;最后,形成第二重分布线路层134于该第一显露表面131a上,该第二重分布线路层134具有第二下表面134a及第二上表面134b,该第二上表面134b的多个上重分布导接垫134d连接所述多个第一焊接凸块133,该第二下表面134a即为该第一电子元件130的该第一主动面,该第二下表面134a的多个下重分布导接垫134c即为该第一电子元件130的所述多个导接件。
完成图6a及图6b的流程后,请参阅图6c,将该第一电子元件130反置于该粘合层120上,使该第二重分布线路层134的该第二下表面134a朝向该第一上表面111,热压合该第一电子元件130及该第一重分布线路层110,使该第二下表面134a的各该下重分布导接垫134c与各该上凸块111a共晶连接,其中,该粘合层120会在热压合的高温下再次融化,使得该粘合层120的两个粘接面在热压合中分别粘接该第一上表面111及该第二下表面134a,且在热压合结束后该粘合层120再次固化成型。
最后,移除该第一粘合胶t1、该第一承载基板s1并设置多个导接元件140于该第一重分布线路层110的该第一下表面112,使各该导接元件140连接各该导接垫112a后,移除该第二粘合胶t2及该第二承载基板s2而完成该具有粘合层的封装结构100的制作。
参阅图7a、图7b及图7c,其为本发明第四实施例的该具有粘合层的封装结构100的制作流程,其中图7b的制作流程与第三实施例的图6b相同,因此不再赘述。请先参阅图7a,提供第一重分布线路层110,在本实施例中,该第一重分布线路层110是设置于第二电子元件150及第三重分布线路层160上,其中该第二电子元件150具有第二密封体151、第二晶粒152及多个第二焊接凸块153,该第二晶粒152具有下导接面152a及上导接面152b,所述多个第二焊接凸块153的两端分别连接该下导接面152a及该第三重分布线路层160的多个上导接垫161,该第二密封体151围绕该第二晶粒152及该第二焊接凸块153,且该第二晶粒152的该上导接面152b及该第二焊接凸块153的第二连接面153a显露于该第二密封体151外,该第二晶粒152的该上导接面152b连接该第一重分布线路层110的所述多个导接垫112a。该第一重分布线路层110、该第二电子元件150及该第三重分布线路层160通过第一粘合胶t1设置于第一承载基板s1上。接着,在该第一重分布线路层110上形成粘合层120,该粘合层120位于该第一重分布线路层110的该第上表面111,且该粘合层120围绕所述多个上凸块111a。在本实施例中,形成该粘合层120包含:涂布有机粘合材料于该第一重分布线路层110上;加热并冷却该有机粘合材料使其固化为该粘合层120。最后,平坦化该粘合层120,使所述多个上凸块111a显露于该粘合层120,较佳的,本实施例是以飞切工艺(Fly-cut)对该粘合层120进行切削。
完成图7a及图7b的流程后,请参阅图7c,将该第一电子元件130反置于该粘合层120上,使该第二重分布线路层134的该第二下表面134a朝向该第一上表面111,并热压合该第一电子元件130及该第一重分布线路层110,使该第二下表面134a的各该下重分布导接垫134c与各该上凸块111a共晶连接,其中,该粘合层120会在热压合的高温下再次融化,使得该粘合层120的两个粘接面在热压合中分别粘接该第一上表面111及该第二下表面134a,且在热压合结束后该粘合层120再次固化成型。
最后,移除该第一粘合胶t1、该第一承载基板s1并设置多个导接元件140于该第三重分布线路层160的多个下导接垫162上,使各该导接元件140连接各该下导接垫162后,移除该第二粘合胶t2及该第二承载基板s2而完成该具有粘合层的封装结构100的制作。
本发明在该第一重分布线路层110上形成该粘合层120,且该粘合层120在热压合该第一电子元件130于该第一重分布线路层110上时会因高温融化而粘接该第一电子元件130及该第一重分布线路层110而大幅提高接合强度,能让该具有粘合层的封装结构100设计具有密度更高、更为复杂的结构。
以上所述,仅是本发明的较佳实施例而已,并非对本发明做任何形式上的限制,虽然本发明已以较佳实施例揭露如上,然而并非用以限定本发明,任何熟悉本专业的技术人员,在不脱离本发明技术方案范围内,当可利用上述揭示的技术内容做出些许更动或修饰为等同变化的等效实施例,但凡是未脱离本发明技术方案的内容,依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化与修饰,均仍属于本发明技术方案的范围内。
Claims (16)
1.一种具有粘合层的封装结构,其特征在于,包含:
第一重分布线路层,具有第一上表面及第一下表面,该第一上表面具有多个上凸块,该第一下表面具有多个导接垫;
粘合层,位于该第一重分布线路层的该第一上表面,且该粘合层围绕所述多个上凸块;以及
第一电子元件,设置于该粘合层上,该第一电子元件具有第一主动面及多个导接件,所述多个导接件显露于该第一主动面上,该第一主动面朝向该第一上表面,且各该导接件连接各该上凸块,其中该粘合层的两个粘接面分别粘接该第一上表面及该第一主动面。
2.根据权利要求1所述的具有粘合层的封装结构,其特征在于:该粘合层是由有机粘合材料固化形成。
3.根据权利要求1所述的具有粘合层的封装结构,其特征在于:包含多个导接元件,所述多个导接元件位于该第一重分布线路层的该第一下表面,且各该导接元件连接各该导接垫。
4.根据权利要求1所述的具有粘合层的封装结构,其特征在于:该第一电子元件具有第一密封体、第一晶粒及多个第一焊接凸块,所述多个第一焊接凸块位于该第一晶粒上,该第一密封体围绕该第一晶粒及所述多个第一焊接凸块,且该第一密封体的第一显露表面显露各该第一焊接凸块的第一连接面,该第一显露表面即为该第一电子元件的该第一主动面,所述多个第一焊接凸块即为该第一电子元件的所述多个导接件。
5.根据权利要求4所述的具有粘合层的封装结构,其特征在于:该第一电子元件具有第二重分布线路层,该第二重分布线路层具有第二下表面及第二上表面,该第二下表面的多个下重分布导接垫连接所述多个上凸块,该第二上表面的多个上重分布导接垫连接所述多个第一焊接凸块,该第二下表面即为该第一电子元件的该第一主动面,所述多个下重分布导接垫即为该第一电子元件的所述多个导接件。
6.根据权利要求5所述的具有粘合层的封装结构,其特征在于:包含第二电子元件及第三重分布线路层,该第二电子元件具有第二密封体、第二晶粒及多个第二焊接凸块,该第二晶粒具有下导接面及上导接面,所述多个第二焊接凸块的两端分别连接该下导接面及该第三重分布线路层的多个上导接垫,该第二密封体围绕该第二晶粒及该第二焊接凸块,且该第二晶粒的该上导接面及该第二焊接凸块的第二连接面显露于该第二密封体外,该第二晶粒的该上导接面连接该第一重分布线路层的所述多个导接垫。
7.根据权利要求6所述的具有粘合层的封装结构,其特征在于:包含多个导接元件,所述多个导接元件连接第三重分布线路层的多个下导接垫。
8.一种具有粘合层的封装结构的封装方法,其特征在于:包含:
提供第一重分布线路层,该第一重分布线路层具有第一上表面及第一下表面,该第一上表面具有多个上凸块,该第一下表面具有多个导接垫;
在该第一重分布线路层上形成粘合层,该粘合层位于该第一重分布线路层的该第一上表面,且该粘合层围绕所述多个上凸块;
平坦化该粘合层,使所述多个上凸块显露于该粘合层;
设置第一电子元件于该粘合层上,该第一电子元件具有第一主动面及多个导接件,所述多个导接件显露于该第一主动面上,该第一主动面朝向该第一上表面;以及
热压合该第一电子元件及该第一重分布线路层,使各该导接件连接各该上凸块,其中该粘合层的两个粘接面在热压合中分别粘接该第一上表面及该第一主动面。
9.根据权利要求8所述的具有粘合层的封装结构的封装方法,其特征在于:在该第一重分布线路层上形成该粘合层包含:涂布有机粘合材料于该第一重分布线路层上;加热并冷却该有机粘合材料使其固化为该粘合层。
10.根据权利要求8所述的具有粘合层的封装结构的封装方法,其特征在于:平坦化该粘合层是以飞切工艺对该粘合层进行切削。
11.根据权利要求8所述的具有粘合层的封装结构的封装方法,其特征在于:在热压合该第一电子元件及该第一重分布线路层后另包含再次对该粘合层进行升温及冷却而完成最终固化。
12.根据权利要求8所述的具有粘合层的封装结构的封装方法,其特征在于:包含设置多个导接元件于该第一重分布线路层的该第一下表面,且各该导接元件连接各该导接垫。
13.根据权利要求8所述的具有粘合层的封装结构的封装方法,其特征在于:该第一电子元件的制造方法为:在第一晶粒上形成多个第一焊接凸块;形成第一密封体包覆该第一晶粒及所述多个第一焊接凸块;平坦化该第一密封体而形成第一显露表面,该第一显露表面显露各该第一焊接凸块的第一连接面,且该第一显露表面即为该第一电子元件的该第一主动面,所述多个第一焊接凸块即为该第一电子元件的所述多个导接件。
14.根据权利要求8所述的具有粘合层的封装结构的封装方法,其特征在于:该第一电子元件的制造方法为:在第一晶粒上形成多个第一焊接凸块;形成第一密封体包覆该第一晶粒及所述多个第一焊接凸块;平坦化该第一密封体而形成第一显露表面,该第一显露表面显露各该第一焊接凸块的第一连接面;形成第二重分布线路层于该第一显露表面上,该第二重分布线路层具有第二下表面及第二上表面,该第二上表面的多个上重分布导接垫连接所述多个第一焊接凸块,该第二下表面即为该第一电子元件的该第一主动面,该第二下表面的多个下重分布导接垫即为该第一电子元件的所述多个导接件,其中,当该第一电子元件及该第一重分布线路层热压合时,该第二下表面的多个下重分布导接垫连接所述多个上凸块。
15.根据权利要求14所述的具有粘合层的封装结构的封装方法,其特征在于:该第一重分布线路层是设置于第二电子元件及第三重分布线路层上,该第二电子元件具有第二密封体、第二晶粒及多个第二焊接凸块,该第二晶粒具有下导接面及上导接面,所述多个第二焊接凸块的两端分别连接该下导接面及该第三重分布线路层的多个上导接垫,该第二密封体围绕该第二晶粒及该第二焊接凸块,且该第二晶粒的该上导接面及该第二焊接凸块的第二连接面显露于该第二密封体外,该第二晶粒的该上导接面连接该第一重分布线路层的所述多个导接垫。
16.根据权利要求15所述的具有粘合层的封装结构的封装方法,其特征在于:包含设置多个导接元件于该第三重分布线路层的多个下导接垫上,使各该导接元件连接各该下导接垫。
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