CN117747532A - Semiconductor structure and forming method thereof - Google Patents

Abstract

The application discloses a semiconductor structure and a forming method thereof; the method for forming the semiconductor structure comprises the following steps: forming a plurality of first grooves and second grooves in the substrate of the logic area and the array area respectively; forming a dielectric liner in the first trench and in the second trench; forming a plurality of first coating blocks and second coating blocks in the first groove and the second groove respectively; forming a cap layer over the first and second coating blocks; forming a plurality of oxide structures over the cap layer; removing the partial oxidation structure and the cover layer; a semiconductor layer is formed in the array region, the semiconductor layer being disposed over the substrate and between the oxide structure. The method and the device can effectively prevent the isolation structure of the semiconductor structure from being broken to form defects, and further improve the overall yield of the semiconductor structure.

Description

Semiconductor structure and forming method thereof

Technical Field

The present invention relates to a semiconductor structure and a method for forming the same, and more particularly, to a method for forming a semiconductor structure and a semiconductor structure formed by the same, which can prevent an oxide layer of the semiconductor structure from being broken to form defects.

Background

In the fabrication of semiconductor structures, isolation structures (e.g., shallow trench isolation (shallow trench isolation, STI) structures) may be formed by coating Spin On Glass (SOG) on dielectric liners. However, in subsequent processes, the isolation structure and the dielectric liner may crack due to stress caused by heat, thereby forming defects, which may result in shorting of subsequently formed conductive structures (e.g., control gates).

Disclosure of Invention

The embodiment of the application provides a method for forming a semiconductor structure, which can effectively prevent the isolation structure of the semiconductor structure from cracking to form defects by forming a dielectric liner and a cover layer on the isolation structure of the semiconductor structure, thereby improving the overall yield of the semiconductor structure.

Some embodiments of the present application include a method for forming a semiconductor structure having an array region and a logic region disposed around the array region, the method comprising: providing a substrate; forming a plurality of first trenches in the substrate of the logic region and a plurality of second trenches in the substrate of the array region; forming a dielectric liner in the first trench and over the second trench; forming a plurality of first coating blocks in the first grooves and a plurality of second coating blocks in the second grooves; forming a cap layer over the first and second coating blocks; forming a plurality of oxide structures over the cap layer; removing a portion of the oxidized structure and a portion of the cap layer; a semiconductor layer is formed in the array region, the semiconductor layer being disposed over the substrate and between the oxide structure.

Some embodiments of the present application include a semiconductor structure having an array region and a logic region disposed around the array region. The semiconductor structure comprises a substrate, a plurality of first coating blocks and a plurality of second coating blocks. The first coating block is arranged in the substrate and located in the logic area, and the second coating block is arranged in the substrate and located in the array area. The semiconductor structure also includes a plurality of dielectric pads and a plurality of cap layers, wherein the dielectric pads and the cap layers cover the first coating region or the second coating region. The semiconductor structure further comprises a plurality of oxidation structures and a semiconductor layer, wherein the oxidation structures are arranged on the second coating block, and the semiconductor layer is arranged between the oxidation structures.

Drawings

Fig. 1A, 2A, 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, and 12A are partial cross-sectional views illustrating stages of a method of forming a logic region of a semiconductor structure according to some embodiments of the present application.

Fig. 1B, 2B, 3B, 4B, 5B, 6B, 7B, 8B, 9B, 10B, 11B, 12B are partial cross-sectional views illustrating stages of a method of forming an array region of a semiconductor structure according to some embodiments of the present application.

Reference numerals

100 semiconductor structure

100A array region

100L logical area

10 substrate

10T top surface of substrate

12 first nitride layer

12T top surface of the first nitride layer

14 dielectric liner

16 coating layer

16-1 first coating block

16-1T top surface of first coating block

16-2 second coating block

16-2T top surface of second coating block

18 cover layer

20 Pre-pad

22 first oxide layer

22S oxidation structure

22ST top surface of oxidized structure

23 tunneling oxide layer

24 semiconductor layer

24M semiconductor material layer

24T top surface of semiconductor layer

26 barrier layer

26H holes

28 second oxide layer

30 second nitride layer

T1 first groove

T2:second trench

Width of bottom of semiconductor layer W24B

W24T width of top of semiconductor layer

WT1 opening width of first trench

WT2 opening width of second trench

Detailed Description

The semiconductor structure 100 (as shown in fig. 12A and 12B) of the embodiment of the present application has an array region (array region) 100A and a logic region (logic region) 100L, wherein the logic region 100L is disposed around the array region 100A, so that the logic region 100L may also be referred to as a periphery region (peripheral region). For simplicity, some components of the semiconductor structure 100 have been omitted in fig. 1A, 1B, 2A, 2B, 3A, 3B, 4A, 4B, 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, 11A, 11B, 12A, and 12B.

Referring to fig. 1A and 1B, a first nitride layer 12 is formed over a substrate 10. The substrate 10 comprises, for example, a semiconductor substrate, a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or a composite substrate formed of different materials. The substrate 10 may be doped (e.g., using a p-type or n-type dopant) or undoped.

The first nitride layer 12 may comprise silicon nitride and may be formed over the substrate 10 by a deposition process. The deposition process includes, for example, chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, liquid phase epitaxy, similar processes, or combinations of the foregoing, but the application is not limited thereto.

Referring to fig. 2A and 2B, a plurality of first trenches T1 (only one is shown in fig. 2A) are formed in the logic region 100L and a plurality of second trenches T2 are formed in the array region 100A. In some embodiments, the opening width WT1 of the first trench T1 is greater than the opening width WT2 of the second trench T2. In addition, the number and density of the first trenches T1 per unit area may be smaller than those of the second trenches T2 per unit area, but the present application is not limited thereto.

A masking layer (not shown) may be disposed over the first nitride layer 12 to perform an etching process as an etching mask to etch the first trench T1 and the second trench T2 in the substrate 10 and the first nitride layer 12. For example, the mask layer may comprise a photoresist or a hard mask. The masking layer may be a single layer or a multi-layer structure.

The masking layer may be formed by, for example, a deposition process, a photolithography process, other suitable processes, or a combination of the foregoing. Here, the deposition process includes spin-on coating (spin-on coating), chemical vapor deposition, atomic layer deposition, the like, or a combination of the foregoing; the photolithographic process may include photoresist coating (e.g., spin coating), soft baking (soft baking), mask alignment (mask alignment), exposure (PEB), post-exposure baking (post-PEB), development (development), rinsing (ringing), drying (e.g., hard baking), other suitable processes, or combinations of the foregoing, but the application is not limited thereto.

Next, a dielectric liner 14 is formed in the first trenches T1, in the second trenches T2 and over the first nitride layer 12. The dielectric liner 14 comprises, for example, an insulating material (e.g., silicon oxide, silicon nitride, or silicon oxynitride) and may be formed by a deposition process, although the application is not limited thereto. Then, a heat treatment process is performed. For example, a thermal anneal (RTP) process or rapid thermal processing (rapid thermal processing, RTP) may be performed to harden the dielectric liner 14.

Referring to fig. 3A and 3B, a coating layer 16 is formed over the dielectric liner 14. The coating layer 16 includes, for example, an insulating material (e.g., spin-on glass (SOG)), but the application is not limited thereto. In detail, the coating layer 16 may be formed on the top surface of the dielectric liner 14 and fills the first trench T1 and the second trench T2.

Referring to fig. 4A and 4B, a portion of the dielectric liner 14 and a portion of the coating layer 16 are removed to form a plurality of first coating blocks 16-1 (only one is shown in fig. 4A) in the first trench T1 and a plurality of second coating blocks 16-2 in the second trench T2. In some embodiments, the top surface 16-1T of the first coating block 16-1 is higher than the top surface 10T of the substrate 10, while the top surface 16-2T of the second coating block 16-2 is lower than the top surface 10T of the substrate 10. Here, the top surface 16-1T of the first coating block 16-1 is, for example, a flat surface, and the top surface 16-2T of the second coating block 16-2 is, for example, a concave surface. The location of the top surface 16-2T of the second coating block 16-2 may be considered as the location of the lowest point of the recessed surface.

Specifically, in some embodiments, a planarization process is performed to remove the dielectric liner 14 and the coating layer 16 located over the top surface 12T of the first nitride layer 12 such that the coating layer 16 is substantially coplanar with the first nitride layer 12. Next, in some embodiments, a wet etching (wet etching) process is performed to remove the portion of the coating layer 16 located in the first trench T1 and leave a first coating block 16-1, and to remove the portion of the coating layer 16 located in the second trench T2 and leave a second coating block 16-2. The planarization process includes, for example, a chemical mechanical polishing (chemical mechanical polishing, CMP) process, while the wet etch process may include a dilute hydrofluoric acid clean (dilute HF cleaning, DHF) process. Since the dielectric liner 14 and the coating layer 16 have etching selectivity, the etching liquid has different etching speeds for the dielectric liner 14 and the coating layer 16. Thus, after the wet etching process, the dielectric liner 14 may remain on the sidewalls of the first trench T1 and the second trench T2.

Referring to fig. 5A and 5B, a cap layer 18 is formed over the first coating block 16-1, the second coating block 16-2, and the first nitride layer 12. For example, the material and method of formation of the cap layer 18 may be the same as or similar to the material and method of formation of the dielectric liner 14. In other words, the cap layer 18 may be formed over the first coating block 16-1, the second coating block 16-2 and the first nitride layer 12 by a deposition process, but the present application is not limited thereto. In some embodiments, the cap layer 18 over the first coating block 16-1 has a planar structure, and the cap layer 18 over the second coating block 16-2 has a recessed structure.

Next, in some embodiments, a heat treatment process is performed. For example, a thermal annealing process or a rapid thermal process, which may be referred to as a thermal densification (thermal densifying) process, may be performed to harden cap layer 18. Here, the cap layer 18 (and part of the dielectric liner 14) may be used as an etch stop layer in a subsequent process, but the present application is not limited thereto.

Referring to fig. 6A and 6B, a pre-pad 20 is formed over cap layer 18. Next, a first oxide layer 22 is formed over cap layer 18 and pre-pad 20. In other words, the pre-pad 20 is disposed between the cap layer 18 and the first oxide layer 22. In some embodiments, the bottommost portion of the first oxide layer 22 in the logic region 100L and the array region 100A is lower than the topmost portion of the cap layer 18 and the pre-pad 20. The pre-pad 20 and the first oxide layer 22 may comprise an oxide, such as silicon oxide, for example. In addition, the pre-pad 20 and the first oxide layer 22 may be sequentially formed over the cap layer 18 by a deposition process.

As shown in fig. 6A and 6B, in some embodiments, a portion of the first oxide layer 22 fills in the first trench T1 and the second trench T2 to form a plurality of oxide structures 22S, and in the array region 100A, a bottommost portion of each oxide structure 22S is located below the top surface 10T of the substrate 10. Next, in some embodiments, the first oxide layer 22 is subjected to a high density plasma (high density plasma).

Referring to fig. 7A and 7B, in some embodiments, portions of first oxide layer 22, portions of pre-liner 20, and portions of cap layer 18 located over top surface 12T of first nitride layer 12 are removed. For example, a planarization process (e.g., a chemical mechanical polishing process) is performed to remove a portion of the first oxide layer 22, a portion of the pre-pad 20, and a portion of the cap layer 18 that are located over the top surface 12T of the first nitride layer 12. Next, in some embodiments, the first nitride layer 12 is removed. For example, phosphoric acid (phosphoric acid) may be used as an etching solution, and the first nitride layer 12 may be removed by a wet etching process, but the present application is not limited thereto.

Referring to fig. 8A and 8B, in some embodiments, a pre-cleaning process is performed to remove the remaining pre-liner 20 and oxide structure 22S over the cap layer 18 (over the first coating block 16-1) in the logic region 100L, such that the remaining dielectric liner 14 and cap layer 18 surround the first coating block 16-1. In some embodiments, the remaining pre-liner 20 and oxide structure 22S on the cap layer 18 (located on the first coating block 16-1) in the logic region 100L may also be removed by a previous planarization process. In performing the planarization or pre-cleaning process, since the structure of the logic region 100L is relatively empty, a dishing effect (dishing effect) is generated, so that the oxide structure 22S in the logic region 100L is removed. In some embodiments, after the pre-clean process is completed, the top surface of the cap layer 18 remaining in the logic region 100L is a planar structure.

Compared to the logic region 100L, the oxide structure 22S in the array region 100A is only partially or not affected by the planarization or pre-cleaning process due to the different pattern size of the array region 100A and the logic region 100L. Accordingly, the oxide structure 22S in the array region 100A is only partially removed or not removed.

In addition, a pre-cleaning process is performed to remove the dielectric liner 14 or cap layer 18 and a portion of the pre-liner 20 on both sides of the oxidized structure 22S (located above the substrate 10) in the array region 100A, such that the remaining oxidized structure 22S forms an approximately vertical profile with the pre-liner 20, e.g., the sidewalls of the remaining pre-liner 20 have an angle of 85 degrees to 95 degrees with the substrate 10. After performing the pre-cleaning process, the pre-pad 20 forms an upwardly tapered structure. The pre-clean process, for example, but not limited to, includes a wet etch process (e.g., a dilute hydrofluoric acid rinse (DHF) process).

Referring to fig. 9A and 9B, a tunnel oxide layer 23 and a semiconductor material layer 24M are sequentially formed over the substrate 10. In detail, the semiconductor material layer 24M is formed on the substrate 10, the first coating block 16-1 and the second coating block 16-2. In addition, in the array region 100A, the tunnel oxide layer 23 and the semiconductor material layer 24M are disposed between the oxide structure 22S and the substrate 10. The tunnel oxide layer 23 and the semiconductor material layer 24M may be formed by a deposition process.

For example, the semiconductor material layer 24M may include an elemental semiconductor (e.g., silicon, germanium, etc.), a compound semiconductor (e.g., silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP), etc.), an alloy semiconductor (e.g., silicon germanium (SiGe), silicon germanium carbide (SiGeC), gallium arsenide phosphide (GaAsP), or indium gallium phosphide (GaInP), etc.), other suitable semiconductors, or combinations of the foregoing, but the present application is not limited thereto.

Next, as shown in fig. 9A, in some embodiments, a barrier layer 26 is formed in the logic region 100L, the barrier layer 26 having a plurality of holes 26H (only one shown in fig. 9A) corresponding to the first coating block 16-1. In other words, the hole 26H may expose a portion of the semiconductor material layer 24M corresponding to the first coating block 16-1.

For example, the barrier layer 26 comprises a nitride, such as silicon nitride. In addition, a mask layer (not shown) may be disposed over the barrier material as an etch mask for performing an etching process to form the barrier layer 26 having a plurality of holes 26H. The masking layer may be formed by, for example, a deposition process, a photolithography process, other suitable processes, or a combination of the foregoing.

Referring to fig. 10A and 10B, in some embodiments, a planarization process is performed. Specifically, a planarization process is performed to remove a portion of the semiconductor material layer 24M in the array region 100A to form the semiconductor layer 24 and expose the top surface 22ST of the oxide structure 22S. For example, the planarization process may include a chemical mechanical polishing process, but the application is not limited thereto.

In the logic region 100L, the high selectivity of the polishing slurry (slurry) to the barrier layer 26 is utilized to allow the barrier layer 26 to protect the structure of the logic region 100L from being excessively removed. Therefore, only the portion of the semiconductor material layer 24M exposed by the hole 26H is removed, the semiconductor material layer 24M under the barrier layer 26 may be left to form the semiconductor layer 24, and the barrier layer 26 is only partially or hardly removed in the planarization process. The barrier layer 26 in the logic region 100L may then be removed, for example, using phosphoric acid as an etching solution, and by a wet etching process.

As shown in fig. 10B, in some embodiments, semiconductor layer 24 is disposed between oxide structures 22S, and a top surface 24T of semiconductor layer 24 is substantially coplanar with a top surface 22ST of oxide structure 22S, but the application is not limited thereto.

Referring to fig. 11A and 11B, a second oxide layer 28 and a second nitride layer 30 are sequentially formed over the semiconductor layer 24 and the oxide structure 22S. The material and forming method of the second oxide layer 28 may be the same as or similar to the material and forming method of the first oxide layer 22, and the material and forming method of the second nitride layer 30 may be the same as or similar to the material and forming method of the first nitride layer 12.

Refer to fig. 12A. In some embodiments, the second nitride layer 30, the second oxide layer 28, and the semiconductor layer 24 (or the semiconductor material layer 24M) in the logic region 100L are removed to form the semiconductor structure 100. For example, the array region 100A may be masked and a dry etching process may be performed on the logic region 100L to sequentially remove the second nitride layer 30, the second oxide layer 28 and the semiconductor layer 24.

Referring to fig. 12A and 12B, the semiconductor structure 100 includes a substrate 10, a plurality of first coating blocks 16-1 (only one is shown in fig. 12A) and a plurality of second coating blocks 16-2, wherein the first coating blocks 16-1 are disposed in the substrate 10 and located in the logic region 100L, and the second coating blocks 16-2 are disposed in the substrate 10 and located in the array region 100A.

The semiconductor structure 100 also includes a plurality of dielectric liners 14 and a plurality of cap layers 18, each dielectric liner 14 and cap layer 18 encapsulating a corresponding first coating block 16-1 or second coating block 16-2. In some embodiments, the dielectric liner 14 is disposed on a sidewall of the first coating block 16-1 or the second coating block 16-2, and the cap layer 18 is disposed on a top surface of the first coating block 16-1 or the second coating block 16-2. In some embodiments, dielectric liner 14 and cap layer 18 are hardened oxide layers.

The first coating block 16-1 may be considered an isolation structure (e.g., a Shallow Trench Isolation (STI) structure) of the semiconductor structure 100. Since the dielectric liner 14 and the cap layer 18 cover the first coating region 16-1 (i.e., the isolation structure), the isolation structure of the semiconductor structure is effectively prevented from being broken to form defects. In some embodiments, the dielectric liner 14 and the cap layer 18 may serve as an etch stop layer during the fabrication process, thereby improving the overall yield of the semiconductor structure 100.

The semiconductor structure 100 further includes a plurality of oxide structures 22S and a semiconductor layer 24, the oxide structures 22S are disposed on the second coating region 16-2 (and the cap layer 18), and the semiconductor layer 24 is disposed between the oxide structures 22S. As shown in fig. 12B, in some embodiments, semiconductor layer 24 has a substantially constant width.

Due to the dielectric liner 14 and the cap layer 18, the oxide structure 22S remaining in the array region 100A forms a substantially vertical profile with the pre-liner 20 during the pre-cleaning process (fig. 8B), such that the subsequently formed semiconductor layer 24 may have substantially vertical sidewalls (i.e., have a substantially constant width) that is more uniform than the semiconductor layer 24 formed by the prior art, and a seam (sea) is less likely to occur. In some embodiments, the ratio of the width W24T of the top of the semiconductor layer 24 to the width W24B of the bottom of the semiconductor layer 24 is between about 0.9 and about 1.1.

In the method for forming the semiconductor structure according to the embodiment of the invention, the dielectric liner and the cover layer are formed on the isolation structure of the semiconductor structure, so that the isolation structure of the semiconductor structure is effectively prevented from being broken to form defects, and the overall yield of the semiconductor structure is improved.

The foregoing outlines components of several embodiments so that those skilled in the art may better understand the aspects of the embodiments of the present application. Those skilled in the art will appreciate that they may be able to devise and modify other arrangements and processes based on the embodiments herein to achieve the same purpose and/or advantage as the embodiments described herein.

The described features, advantages, and characteristics of the application may be combined in any suitable manner in one or more embodiments. Those skilled in the art will appreciate from the description herein that the present application may be practiced without one or more of the specific features or advantages of a particular embodiment. In other instances, additional features and advantages may be recognized in certain embodiments that may not be present in all embodiments of the application.

Claims (16)

1. A method for forming a semiconductor structure, the semiconductor structure having an array region and a logic region disposed around the array region, the method comprising:

providing a substrate;

forming a plurality of first trenches in the substrate of the logic region and a plurality of second trenches in the substrate of the array region;

forming a dielectric liner in the first plurality of trenches and in the second plurality of trenches;

forming a plurality of first coating blocks in the plurality of first grooves and a plurality of second coating blocks in the plurality of second grooves;

forming a cap layer over the plurality of first coating blocks and the plurality of second coating blocks;

forming a plurality of oxide structures over the cap layer;

removing a portion of the plurality of oxidized structures and a portion of the cap layer; and

a semiconductor layer is formed in the array region, wherein the semiconductor layer is disposed between the plurality of oxidized structures.

2. The method of claim 1, wherein forming the plurality of first coating blocks and the plurality of second coating blocks comprises:

forming a coating layer over the dielectric liner;

performing a planarization process to remove a portion of the dielectric liner and a portion of the coating layer; and

A wet etch process is performed to remove portions of the coating layer in the first plurality of trenches and leave the first plurality of coating blocks, and to remove portions of the coating layer in the second plurality of trenches and leave the second plurality of coating blocks.

3. The method of forming a semiconductor structure of claim 1, further comprising:

performing a heat treatment process after forming the dielectric liner; and

After forming the cap layer, another heat treatment process is performed.

4. The method of forming a semiconductor structure of claim 1, further comprising:

a pre-pad is formed over the cap layer, wherein the pre-pad is disposed between the cap layer and the plurality of oxidized structures.

5. The method of forming a semiconductor structure of claim 1, further comprising:

forming a first oxide layer over the cap layer, wherein a portion of the first oxide layer fills in the plurality of second trenches to form the plurality of oxide structures; and

And performing high-density plasma treatment on the first oxide layer.

6. The method of claim 5, wherein a planarization process is performed to remove a portion of the first oxide layer and a portion of the cap layer.

7. The method of forming a semiconductor structure of claim 1, further comprising:

a tunnel oxide layer is formed between the semiconductor layer and the substrate.

8. The method of forming a semiconductor structure of claim 1, wherein the step of forming the semiconductor layer comprises:

forming a semiconductor material layer over the substrate, the plurality of first coating blocks, and the plurality of second coating blocks;

forming a barrier layer in the logic region, wherein the barrier layer has a plurality of holes corresponding to the plurality of first coating blocks;

performing a planarization process to remove a portion of the semiconductor material layer in the array region to form the semiconductor layer and expose top surfaces of the plurality of oxide structures; and

The layer of semiconductor material in the logic region is removed.

9. The method of forming a semiconductor structure of claim 1, further comprising:

and forming a second oxide layer and a nitride layer on the semiconductor layer and the oxide structures in sequence.

10. The method of forming a semiconductor structure of claim 1, further comprising:

a first nitride layer is formed over the substrate, wherein the first nitride layer is located between the substrate and the dielectric liner.

11. A semiconductor structure having an array region and a logic region disposed around the array region, the semiconductor structure comprising:

a substrate;

a plurality of first coating blocks arranged in the substrate and located in the logic area;

a plurality of second coating blocks arranged in the substrate and positioned in the array area;

a plurality of dielectric liners and a plurality of cover layers coating the plurality of first coating blocks or the plurality of second coating blocks;

a plurality of oxidation structures disposed over the plurality of second coating blocks; and

and the semiconductor layer is arranged between the oxidation structures.

12. The semiconductor structure of claim 11, wherein a ratio of a width of a top portion to a width of a bottom portion of the semiconductor layer is between 0.9 and 1.1.

13. The semiconductor structure of claim 11, wherein a material of the plurality of dielectric liners is the same as a material of the plurality of cap layers.

14. The semiconductor structure of claim 11, wherein the plurality of dielectric liners and the plurality of cap layers are hardened oxide layers.

15. The semiconductor structure of claim 11, wherein a top surface of the plurality of first coating blocks is higher than a top surface of the substrate and a top surface of the plurality of second coating blocks is lower than the top surface of the substrate.

16. The semiconductor structure of claim 11, wherein a bottommost portion of each of the plurality of oxide structures is located below a top surface of the substrate in the array region.