CN117728781B - Power amplifier - Google Patents
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- CN117728781B CN117728781B CN202410178672.5A CN202410178672A CN117728781B CN 117728781 B CN117728781 B CN 117728781B CN 202410178672 A CN202410178672 A CN 202410178672A CN 117728781 B CN117728781 B CN 117728781B
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- 239000003990 capacitor Substances 0.000 claims description 32
- PHLXSNIEQIKENK-UHFFFAOYSA-N 2-[[2-[5-methyl-3-(trifluoromethyl)pyrazol-1-yl]acetyl]amino]-4,5,6,7-tetrahydro-1-benzothiophene-3-carboxamide Chemical compound CC1=CC(C(F)(F)F)=NN1CC(=O)NC1=C(C(N)=O)C(CCCC2)=C2S1 PHLXSNIEQIKENK-UHFFFAOYSA-N 0.000 description 9
- 101100230601 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) HBT1 gene Proteins 0.000 description 9
- 238000004891 communication Methods 0.000 description 4
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- 230000007423 decrease Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- VKJLWXGJGDEGSO-UHFFFAOYSA-N barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[Ti+4].[Ba+2] VKJLWXGJGDEGSO-UHFFFAOYSA-N 0.000 description 1
- 239000008358 core component Substances 0.000 description 1
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- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Abstract
The invention provides a power amplifier, which comprises a signal input end, an input matching circuit, a driving stage amplifier, an interstage matching circuit, a power stage amplifier, a first output matching circuit, a second output matching circuit, a signal output end and a bias circuit network, wherein the signal input end is connected with the first output matching circuit; the bias circuit network comprises a logic control circuit, a first bias circuit and a second bias circuit; the logic control circuit is used for respectively controlling the first bias voltage output by the first bias circuit and the second bias voltage output by the second bias circuit according to external control voltage; the first bias circuit is used for providing the first bias voltage for the driving stage amplifier; the second bias circuit is configured to provide the second bias voltage to the power stage amplifier. The power amplifier can ensure that the efficiency of the back-off area is improved under the condition of enough output power.
Description
Technical Field
The present invention relates to the field of wireless communications technologies, and in particular, to a power amplifier.
Background
The power amplifier is an amplifying circuit capable of providing enough signal power for the antenna, and has the main functions of amplifying and feeding low-power radio frequency signals generated by the modulation oscillation circuit to the antenna to radiate, is the most core component of the radio frequency front end of the wireless communication equipment, and the performance of the power amplifier directly determines the communication distance, the signal quality and the standby time (or the power consumption) of the wireless terminal, and is also the device with the maximum power consumption of the radio frequency front end.
In the development of wireless communication, in order to fully utilize spectrum resources, various complex modulation techniques are generated, however, modulation signals applied to the complex modulation techniques generally have a relatively high peak-to-average power ratio (Peak to Average Power Ratio, PAPR), for example, the peak-to-average power ratio of an LTE signal (4G signal) may reach 10 dB. The peak-to-average power ratio signal forces the Power Amplifier (PA) to operate in the back-off region, but the peak efficiency of the PA is at the power saturation point, and the efficiency at the power back-off point is very low, so how to improve the efficiency of the PA in the back-off region is an important development direction.
However, the improvement of the efficiency of the power amplifier in the back-off region is a difficult and difficult problem, because the conversion process from dc power to rf power faces too many challenges, including inherent loss of the device, loss caused by frequency conversion, and heat loss emitted by signal transmission.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention provides a novel power amplifier to solve the problem that the efficiency of the power amplifier in the related art in a rollback area is low.
In order to solve the technical problems, the invention adopts the following technical scheme:
The invention provides a power amplifier, which comprises a signal input end, an input matching circuit, a driving stage amplifier, an interstage matching circuit, a power stage amplifier, a first output matching circuit, a second output matching circuit, a signal output end and a bias circuit network, wherein the signal input end is connected with the first output matching circuit;
The input end of the input matching circuit is connected to the signal input end;
The input end of the driving stage amplifier is connected to the output end of the input matching circuit, the first output end of the driving stage amplifier is connected to the working voltage, and the second output end of the driving stage amplifier is grounded;
The input end of the interstage matching circuit is connected to the second output end of the driving stage amplifier;
the input end of the power stage amplifier is connected to the first output end of the interstage matching circuit, the first output end of the power stage amplifier is connected to the working voltage, and the second output end of the power stage amplifier is grounded;
the input end of the first output matching circuit is connected to the second output end of the power stage amplifier;
The input end of the second output matching circuit is connected to the second output end of the interstage matching circuit;
The signal output end is respectively connected to the output end of the first output matching circuit and the output end of the second output matching circuit;
The bias circuit network comprises a logic control circuit, a first bias circuit and a second bias circuit;
The input end of the logic control circuit is connected to an external control voltage; the logic control circuit is used for respectively controlling the first bias voltage output by the first bias circuit and the second bias voltage output by the second bias circuit according to external control voltage;
The input end of the first bias circuit is connected to the first output end of the logic control circuit, and the output end of the first bias circuit is connected to the input end of the driver stage amplifier; the first bias circuit is used for providing the first bias voltage for the driving stage amplifier;
The input end of the second bias circuit is connected to the second output end of the logic control circuit, and the output end of the second bias circuit is connected to the input end of the power stage amplifier; the second bias circuit is configured to provide the second bias voltage to the power stage amplifier.
Preferably, the logic control circuit comprises a first resistor, a second resistor, a first triode and a second triode;
the first end of the first resistor is connected with the second end of the second resistor and is used as an input end of the logic control circuit;
the base electrode of the first triode is connected to the second end of the first resistor, the emitter electrode of the first triode is grounded, and the collector electrode of the first triode is used as a first output end of the logic control circuit;
The base electrode of the second triode is connected to the second end of the second resistor, the emitting electrode of the second triode is grounded, and the collecting electrode of the second triode is used as the second output end of the logic control circuit.
Preferably, the first bias circuit includes a third resistor, a third triode, a fourth resistor, a fifth resistor and a sixth resistor;
the first end of the third resistor is connected to a reference voltage;
the second end of the third resistor, the collector of the third triode and the base of the fourth triode are connected and serve as input ends of the first bias circuit, the emitter of the triode is grounded, and the collector of the fourth triode is connected to working voltage;
The first end of the fourth resistor is connected to the base electrode of the third triode;
The first end of the fifth resistor is connected to the emitter of the fourth triode and the second end of the fourth resistor respectively, and the second end of the fifth resistor is grounded;
The first end of the sixth resistor is connected to the second end of the fourth resistor, and the second end of the sixth resistor serves as an output end of the first bias circuit.
Preferably, the second bias circuit includes a seventh resistor, a fifth triode, a sixth triode, an eighth resistor, a ninth resistor, and a tenth resistor;
a first end of the seventh resistor is connected to a reference voltage;
The second end of the seventh resistor, the collector electrode of the fifth triode and the base electrode of the sixth triode are connected; the emitter of the fifth triode is grounded, and the collector of the sixth triode is connected to the working voltage;
the first end of the eighth resistor is connected to the base electrode of the fifth triode;
the first end of the ninth resistor is connected to the emitter of the sixth triode and the second end of the eighth resistor respectively, and the second end of the ninth resistor is grounded;
The first end of the tenth resistor is connected to the second end of the eighth resistor and serves as an input end of the second bias circuit, and the second end of the tenth resistor serves as an output end of the second bias circuit.
Preferably, the driver stage amplifier includes a seventh transistor; the base electrode of the seventh triode is used as the input end of the driving stage amplifier, the collector electrode of the seventh triode is used as the first output end of the driving stage amplifier, and the emitter electrode of the seventh triode is used as the second output end of the driving stage amplifier.
Preferably, the inter-stage matching circuit comprises a first capacitor, a first inductor and a second capacitor;
a first end of the first capacitor is used as an input end of the inter-stage matching circuit, and a second end of the first capacitor is used as a second output end of the inter-stage matching circuit;
a first end of the first inductor is connected to a second end of the first capacitor, and a second end of the first inductor is grounded;
The first end of the second capacitor is connected to the second end of the first capacitor, and the second end of the second capacitor serves as a first output end of the inter-stage matching circuit.
Preferably, the power stage amplifier includes an eighth transistor; the base electrode of the eighth triode is used as the input end of the power stage amplifier, the collector electrode of the eighth triode is used as the first output end of the power stage amplifier, and the emitter electrode of the eighth triode is used as the second output end of the power stage amplifier.
Preferably, the second output matching circuit includes a second inductor and a third capacitor;
The first end of the second inductor is used as an input end of the second output matching circuit, and the second end of the second inductor is used as an output end of the second output matching circuit;
the first end of the third capacitor is connected to the first end of the second inductor, and the second end of the third capacitor is grounded.
Preferably, the power amplifier further comprises a third inductor; the first end of the third inductor is connected to the working voltage, and the second end of the third inductor is connected to the first output end of the driver stage amplifier.
Preferably, the power amplifier further comprises a fourth inductor; the first end of the fourth inductor is connected to the working voltage, and the second end of the fourth inductor is connected to the first output end of the power stage amplifier.
Compared with the related art, the power amplifier in the invention comprises a signal input end, an input matching circuit, a driving stage amplifier, an inter-stage matching circuit, a power stage amplifier, a first output matching circuit, a second output matching circuit, a signal output end and a bias circuit network, wherein the bias circuit network comprises a logic control circuit, a first bias circuit and a second bias circuit, the logic control circuit is defined to respectively control a first bias voltage output by the first bias circuit and a second bias voltage output by the second bias circuit according to an external control voltage, and the first bias circuit is also defined to provide the first bias voltage for the driving stage amplifier, and the second bias circuit is defined to provide the second bias voltage for the power stage amplifier. Therefore, the first bias voltage input to the driving stage amplifier and the second bias voltage input to the power stage amplifier can be respectively controlled by the logic control circuit, so that the efficiency of the rollback region of the power amplifier is improved under the condition that the power amplifier has enough output power.
Drawings
The present invention will be described in detail with reference to the accompanying drawings. The foregoing and other aspects of the invention will become more apparent and more readily appreciated from the following detailed description taken in conjunction with the accompanying drawings. In the accompanying drawings:
fig. 1 is a diagram of an overall circuit of a power amplifier according to an embodiment of the present invention;
fig. 2 is a circuit configuration diagram of a bias circuit network in a power amplifier according to an embodiment of the present invention;
Fig. 3 is a schematic diagram illustrating efficiency improvement of a power amplifier according to an embodiment of the present invention.
Detailed Description
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used in the description of the applications herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the terms "comprising" and "having" and any variations thereof in the description of the application and the claims and the description of the drawings above are intended to cover a non-exclusive inclusion. The terms first, second and the like in the description and in the claims or in the above-described figures, are used for distinguishing between different objects and not necessarily for describing a sequential or chronological order.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The present invention provides a power amplifier 100, which is shown in connection with fig. 1 to 3, and includes a signal input terminal Rfin, an input matching circuit 1, a driver stage amplifier 2, an inter-stage matching circuit 3, a power stage amplifier 4, a first output matching circuit 5, a second output matching circuit 6, a signal output terminal Rfout, and a bias circuit network 7.
An input terminal of the input matching circuit 1 is connected to a signal input terminal Rfin.
An input terminal of the driver stage amplifier 2 (driver stage power amplifier) is connected to an output terminal of the input matching circuit 1, a first output terminal of the driver stage amplifier 2 is connected to an operating voltage Vcc, and a second output terminal of the driver stage amplifier 2 is grounded.
An input of the inter-stage matching circuit 3 is connected to a second output of the driver stage amplifier 2.
An input terminal of the power stage amplifier 4 (power stage power amplifier) is connected to a first output terminal of the inter-stage matching circuit 3, a first output terminal of the power stage amplifier 4 is connected to an operating voltage Vcc, and a second output terminal of the power stage amplifier 4 is grounded.
The input of the first output matching circuit 5 is connected to the second output of the power stage amplifier 4.
An input of the second output matching circuit 6 is connected to a second output of the inter-stage matching circuit 3.
The signal output terminal Rfout is connected to the output terminal of the first output matching circuit 5 and the output terminal of the second output matching circuit 6, respectively.
The bias circuit network 7 includes a logic control circuit 71, a first bias circuit 72, and a second bias circuit 73.
An input terminal of the logic control circuit 71 is connected to an external control voltage Vmode; the logic control circuit 71 is configured to control the first Bias voltage Bias1 output from the first Bias circuit 72 and the second Bias voltage Bias2 output from the second Bias circuit 73, respectively, according to the external control voltage Vmode.
An input terminal of the first bias circuit 72 is connected to a first output terminal of the logic control circuit 71, and an output terminal of the first bias circuit 72 is connected to an input terminal of the driver stage amplifier 2; the first Bias circuit 72 is configured to provide a first Bias voltage Bias1 to the driver stage amplifier 2.
An input of the second bias circuit 73 is connected to a second output of the logic control circuit 71, and an output of the second bias circuit 73 is connected to an input of the power stage amplifier 4; the second Bias circuit 73 is configured to provide the second Bias voltage Bias2 to the power stage amplifier 4.
Specifically, the logic control circuit 71 includes a first resistor R1, a second resistor R2, a first transistor HBT1, and a second transistor HBT2.
The first terminal of the first resistor R1 and the second terminal of the second resistor R2 are connected and serve as input terminals of the logic control circuit 71.
The base of the first transistor HBT1 is connected to the second end of the first resistor R1, the emitter of the first transistor HBT1 is grounded, and the collector of the first transistor HBT1 serves as a first output end of the logic control circuit 71.
The base of the second transistor HBT2 is connected to the second end of the second resistor R2, the emitter of the second transistor HBT2 is grounded, and the collector of the second transistor HBT2 serves as the second output of the logic control circuit 71.
Specifically, the first bias circuit 72 includes a third resistor R3, a third transistor HBT3, a fourth transistor HBT4, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6.
The first end of the third resistor R3 is connected to the reference voltage Vref.
The second end of the third resistor R3, the collector of the third transistor HBT3 and the base of the fourth transistor HBT4 are connected and serve as input terminals of the first biasing circuit 72, the emitter of the third transistor HBT3 is grounded, and the collector of the fourth transistor HBT4 is connected to the operating voltage Vcc.
The first terminal of the fourth resistor R4 is connected to the base of the third transistor HBT 3.
The first end of the fifth resistor R5 is connected to the emitter of the fourth triode HBT4 and the second end of the fourth resistor R4 respectively, and the second end of the fifth resistor R5 is grounded.
The first end of the sixth resistor R6 is connected to the second end of the fourth resistor R4, and the second end of the sixth resistor R6 serves as the output end of the first bias circuit 72.
Specifically, the second bias circuit 73 includes a seventh resistor R7, a fifth transistor HBT5, a sixth transistor HBT6, an eighth resistor R8, a ninth resistor R9, and a tenth resistor R10.
The first end of the seventh resistor R7 is connected to the reference voltage Vref.
The second end of the seventh resistor R7, the collector of the fifth triode HBT5 and the base of the sixth triode HBT6 are connected; the emitter of the fifth transistor HBT5 is grounded and the collector of the sixth transistor HBT6 is connected to the operating voltage Vcc.
The first terminal of the eighth resistor R8 is connected to the base of the fifth transistor HBT 5.
The first end of the ninth resistor R9 is connected to the emitter of the sixth triode HBT6 and the second end of the eighth resistor R8, respectively, and the second end of the ninth resistor R9 is grounded.
The first end of the tenth resistor R10 is connected to the second end of the eighth resistor R8 and serves as an input end of the second bias circuit 73, and the second end of the tenth resistor R10 serves as an output end of the second bias circuit 73.
In this embodiment, the driver stage amplifier 2 includes a seventh transistor HBT7; the base of the seventh transistor HBT7 serves as an input of the driver stage amplifier 2, the collector of the seventh transistor HBT7 serves as a first output of the driver stage amplifier 2, and the emitter of the seventh transistor HBT7 serves as a second output of the driver stage amplifier 2.
In the present embodiment, the inter-stage matching circuit 3 includes a first capacitor C1, a first inductor L1, and a second capacitor C2.
The first end of the first capacitor C1 is used as the input end of the inter-stage matching circuit 3, and the second end of the first capacitor C1 is used as the second output end of the inter-stage matching circuit 3.
The first end of the first inductor L1 is connected to the second end of the first capacitor C1, and the second end of the first inductor L1 is grounded.
The first end of the second capacitor C2 is connected to the second end of the first capacitor C1, and the second end of the second capacitor C2 serves as the first output end of the inter-stage matching circuit 3.
In this embodiment, the power stage amplifier 4 includes an eighth triode HBT8; the base of the eighth transistor HBT8 serves as an input of the power stage amplifier 4, the collector of the eighth transistor HBT8 serves as a first output of the power stage amplifier 4, and the emitter of the eighth transistor HBT8 serves as a second output of the power stage amplifier 4.
In this embodiment, the second output matching circuit 6 includes a second inductor L2 and a third capacitor C3.
The first end of the second inductor L2 is used as the input end of the second output matching circuit 6, and the second end of the second inductor L2 is used as the output end of the second output matching circuit 6.
The first end of the third capacitor C3 is connected to the first end of the second inductor L2, and the second end of the third capacitor C3 is grounded.
In this embodiment, the power amplifier 100 further includes a third inductor L3 and a fourth inductor L4; the first end of the third inductor L3 is connected to the working voltage Vcc, and the second end of the third inductor L3 is connected to the first output end of the driving stage amplifier 2; the first end of the fourth inductor L4 is connected to the operating voltage Vcc, and the second end of the fourth inductor L4 is connected to the first output of the power stage amplifier 4.
In this embodiment, the third resistor R3 and the fourth resistor R4 of the first Bias circuit 72 of the power amplifier 100 form a negative feedback loop for the fourth triode HBT4, so as to ensure that the emitter current of the fourth triode HBT4 remains stable, thereby providing a stable first Bias voltage Bias1 for the driver stage amplifier 2; accordingly, the seventh resistor R7 and the eighth resistor R8 of the second Bias circuit 73 provide a feedback loop for the sixth transistor HBT6, thereby providing a stable second Bias voltage Bias2 for the power stage amplifier 4.
The logic control circuit 71 of the power amplifier 100 in this embodiment is specifically configured to switch between a high power mode and a low power mode, and when the input power level is high (high power mode, high power region), the external control voltage Vmode is set to a voltage lower than a certain threshold value, so that the first transistor HBT1 and the second transistor HBT2 are turned off, and at this time, the first bias circuit 72 and the second bias circuit 73 operate normally; in case of a low input power level (low power mode, low power region), to increase the back-off efficiency, the external control voltage Vmode is set to a voltage higher than a certain threshold value, so that the first transistor HBT1 and the second transistor HBT2 are turned on, and for the first Bias circuit 72, there is a mirror relationship with the first transistor HBT1 and the third transistor HBT3, the current in the third transistor HBT3 will decrease, so that the current of the first Bias voltage Bias1 supplied to the driver stage amplifier 2 decreases, and for the second Bias circuit 73, the turning on of the second transistor HBT2 will cause the second Bias voltage Bias2 supplied to the power stage amplifier 4 to decrease directly to 0, i.e. the power amplifier 100 is in the low power mode, and only the driver stage amplifier 2 amplifies the radio frequency signal with a low Bias, so that the efficiency of the back-off region of the power amplifier 100 is increased.
In the specific use process of the power amplifier 100 in this embodiment, a power threshold P0 is determined first for dividing a high power mode and a low power mode of the power amplifier 100; when the input power is in the high power mode, in order to ensure that the power amplifier 100 has enough output power, the external control voltage Vmode is set to be less than 2.5V, at this time, the first triode HBT1 and the second triode HBT2 will be turned off, the first bias circuit 72 and the second bias circuit 73 operate normally to provide the driver stage amplifier 2 and the power stage amplifier 4 with proper bias voltages, and the flow chart of the power is shown as A1 in fig. 1; when the input power is in the low power mode, to increase the efficiency in this power range, the external control voltage Vmode is set to be greater than 2.5V, at this time, the first transistor HBT1 and the second transistor HBT2 are turned on, the first Bias voltage Bias1 is reduced compared to the voltage in the high power mode, and the second Bias voltage Bias2 is approximately equal to 0, so that the driver stage amplifier 2 operates at the low Bias voltage, the power stage amplifier 4 is turned off, and the power flow is shown as A2 in fig. 1.
The Bias voltage flow direction 1 in fig. 2 is the flow direction of the first Bias voltage Bias1 to the driver stage amplifier 2, and the Bias voltage flow direction 2 in fig. 2 is the flow direction of the second Bias voltage Bias2 to the power stage amplifier 4.
The power amplifier 100 in the present embodiment is configured by designing the signal input terminal Rfin, the input matching circuit 1, the driver stage amplifier 2, the inter-stage matching circuit 3, the power stage amplifier 4, the first output matching circuit 5, the second output matching circuit 6, the signal output terminal Rfout, and the Bias circuit network 7, and defining the Bias circuit network 7 to include the logic control circuit 71, the first Bias circuit 72, and the second Bias circuit 73, and defining the logic control circuit 71 to control the first Bias voltage Bias1 output by the first Bias circuit 72 and the second Bias voltage Bias2 output by the second Bias circuit 73 according to the external control voltage Vmode, respectively, and further defining the first Bias circuit 72 to provide the first Bias voltage Bias1 for the driver stage amplifier 2, and the second Bias circuit 73 to provide the second Bias voltage Bias2 for the power stage amplifier 4. In this way, the logic control circuit 71 can control the first Bias voltage Bias1 input to the driver stage amplifier 2 and the second Bias voltage Bias2 input to the power stage amplifier 4, respectively, so as to ensure that the power amplifier 100 has enough output power and improve the efficiency of the back-off region. Meanwhile, compared with the envelope tracking power amplifier in the related art, the logic control circuit 71 thereof is simpler, and the limitation on bandwidth is also reduced.
It should be noted that the above embodiments described above with reference to the drawings are only for illustrating the present invention and not for limiting the scope of the present invention, and it should be understood by those skilled in the art that modifications or equivalent substitutions to the present invention are intended to be included in the scope of the present invention without departing from the spirit and scope of the present invention. Furthermore, unless the context indicates otherwise, words occurring in the singular form include the plural form and vice versa. In addition, unless specifically stated, all or a portion of any embodiment may be used in combination with all or a portion of any other embodiment.
Claims (7)
1. The power amplifier is characterized by comprising a signal input end, an input matching circuit, a driving stage amplifier, an interstage matching circuit, a power stage amplifier, a first output matching circuit, a second output matching circuit, a signal output end and a bias circuit network;
The input end of the input matching circuit is connected to the signal input end;
The input end of the driving stage amplifier is connected to the output end of the input matching circuit, the first output end of the driving stage amplifier is connected to the working voltage, and the second output end of the driving stage amplifier is grounded;
The input end of the interstage matching circuit is connected to the second output end of the driving stage amplifier;
the input end of the power stage amplifier is connected to the first output end of the interstage matching circuit, the first output end of the power stage amplifier is connected to the working voltage, and the second output end of the power stage amplifier is grounded;
the input end of the first output matching circuit is connected to the second output end of the power stage amplifier;
The input end of the second output matching circuit is connected to the second output end of the interstage matching circuit;
The signal output end is respectively connected to the output end of the first output matching circuit and the output end of the second output matching circuit;
The bias circuit network comprises a logic control circuit, a first bias circuit and a second bias circuit;
The input end of the logic control circuit is connected to an external control voltage; the logic control circuit is used for respectively controlling the first bias voltage output by the first bias circuit and the second bias voltage output by the second bias circuit according to external control voltage;
The input end of the first bias circuit is connected to the first output end of the logic control circuit, and the output end of the first bias circuit is connected to the input end of the driver stage amplifier; the first bias circuit is used for providing the first bias voltage for the driving stage amplifier;
The input end of the second bias circuit is connected to the second output end of the logic control circuit, and the output end of the second bias circuit is connected to the input end of the power stage amplifier; the second bias circuit is used for providing the second bias voltage for the power stage amplifier;
the logic control circuit comprises a first resistor, a second resistor, a first triode and a second triode;
the first end of the first resistor is connected with the second end of the second resistor and is used as an input end of the logic control circuit;
the base electrode of the first triode is connected to the second end of the first resistor, the emitter electrode of the first triode is grounded, and the collector electrode of the first triode is used as a first output end of the logic control circuit;
The base electrode of the second triode is connected to the second end of the second resistor, the emitter electrode of the second triode is grounded, and the collector electrode of the second triode is used as the second output end of the logic control circuit;
The first bias circuit comprises a third resistor, a third triode, a fourth resistor, a fifth resistor and a sixth resistor;
the first end of the third resistor is connected to a reference voltage;
the second end of the third resistor, the collector of the third triode and the base of the fourth triode are connected and serve as input ends of the first bias circuit, the emitter of the triode is grounded, and the collector of the fourth triode is connected to working voltage;
The first end of the fourth resistor is connected to the base electrode of the third triode;
The first end of the fifth resistor is connected to the emitter of the fourth triode and the second end of the fourth resistor respectively, and the second end of the fifth resistor is grounded;
The first end of the sixth resistor is connected to the second end of the fourth resistor, and the second end of the sixth resistor is used as the output end of the first bias circuit;
the second bias circuit comprises a seventh resistor, a fifth triode, a sixth triode, an eighth resistor, a ninth resistor and a tenth resistor;
a first end of the seventh resistor is connected to a reference voltage;
The second end of the seventh resistor, the collector electrode of the fifth triode and the base electrode of the sixth triode are connected; the emitter of the fifth triode is grounded, and the collector of the sixth triode is connected to the working voltage;
the first end of the eighth resistor is connected to the base electrode of the fifth triode;
the first end of the ninth resistor is connected to the emitter of the sixth triode and the second end of the eighth resistor respectively, and the second end of the ninth resistor is grounded;
The first end of the tenth resistor is connected to the second end of the eighth resistor and serves as an input end of the second bias circuit, and the second end of the tenth resistor serves as an output end of the second bias circuit.
2. The power amplifier of claim 1, wherein the driver stage amplifier comprises a seventh transistor; the base electrode of the seventh triode is used as the input end of the driving stage amplifier, the collector electrode of the seventh triode is used as the first output end of the driving stage amplifier, and the emitter electrode of the seventh triode is used as the second output end of the driving stage amplifier.
3. The power amplifier of claim 1, wherein the inter-stage matching circuit comprises a first capacitor, a first inductance, and a second capacitor;
a first end of the first capacitor is used as an input end of the inter-stage matching circuit, and a second end of the first capacitor is used as a second output end of the inter-stage matching circuit;
a first end of the first inductor is connected to a second end of the first capacitor, and a second end of the first inductor is grounded;
The first end of the second capacitor is connected to the second end of the first capacitor, and the second end of the second capacitor serves as a first output end of the inter-stage matching circuit.
4. The power amplifier of claim 1, wherein the power stage amplifier comprises an eighth transistor; the base electrode of the eighth triode is used as the input end of the power stage amplifier, the collector electrode of the eighth triode is used as the first output end of the power stage amplifier, and the emitter electrode of the eighth triode is used as the second output end of the power stage amplifier.
5. The power amplifier of claim 1, wherein the second output matching circuit comprises a second inductance and a third capacitance;
The first end of the second inductor is used as an input end of the second output matching circuit, and the second end of the second inductor is used as an output end of the second output matching circuit;
the first end of the third capacitor is connected to the first end of the second inductor, and the second end of the third capacitor is grounded.
6. The power amplifier of claim 1, wherein the power amplifier further comprises a third inductor; the first end of the third inductor is connected to the working voltage, and the second end of the third inductor is connected to the first output end of the driver stage amplifier.
7. The power amplifier of claim 6, wherein the power amplifier further comprises a fourth inductor; the first end of the fourth inductor is connected to the working voltage, and the second end of the fourth inductor is connected to the first output end of the power stage amplifier.
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| CN117728781B true CN117728781B (en) | 2024-04-26 |
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| CN214281338U (en) * | 2019-12-27 | 2021-09-24 | 株式会社村田制作所 | Power amplifying module |
| CN114978067A (en) * | 2022-05-19 | 2022-08-30 | 深圳飞骧科技股份有限公司 | Power amplifier and chip |
| CN116647198A (en) * | 2023-04-28 | 2023-08-25 | 深圳飞骧科技股份有限公司 | power amplifier circuit |
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| US6806767B2 (en) * | 2002-07-09 | 2004-10-19 | Anadigics, Inc. | Power amplifier with load switching circuit |
| US7839216B2 (en) * | 2008-05-27 | 2010-11-23 | Rayspan Corporation | RF power amplifiers with linearization |
| KR101119374B1 (en) * | 2009-11-26 | 2012-03-06 | 한국과학기술원 | Asymmetrical Power Divider |
| JP2012129592A (en) * | 2010-12-13 | 2012-07-05 | Mitsubishi Electric Corp | Power amplifier |
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| CN214281338U (en) * | 2019-12-27 | 2021-09-24 | 株式会社村田制作所 | Power amplifying module |
| CN114978067A (en) * | 2022-05-19 | 2022-08-30 | 深圳飞骧科技股份有限公司 | Power amplifier and chip |
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