CN117725867B - Chip design method, chip, main board and electronic equipment - Google Patents
Chip design method, chip, main board and electronic equipment Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 46
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- 229910000679 solder Inorganic materials 0.000 claims abstract description 246
- 238000004806 packaging method and process Methods 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 230000005540 biological transmission Effects 0.000 claims abstract description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 11
- 229910052802 copper Inorganic materials 0.000 claims description 11
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Abstract
The invention provides a chip design method, a chip, a main board and electronic equipment, and belongs to the technical field of chip packaging. The packaging structure comprises a plurality of circles of solder balls which are arranged around the bare chip on the packaging substrate, and the position of each solder ball corresponds to at least one through hole. The chip design method comprises the following steps: dividing different parts in the packaging structure into corresponding circuit grid units in a three-dimensional space, wherein each circuit grid unit corresponds to one equivalent resistor; determining the serial-parallel connection relation of each equivalent resistor to form a circuit model; calculating the proportionality coefficient of the through hole resistance value corresponding to each of the inner ring solder ball and the outer ring solder ball in the circuit model when the transmission current of the inner ring solder ball and the outer ring solder ball surrounding the bare core in the circuit model is the same; and determining the number of the through holes at the positions of the corresponding solder balls through the proportionality coefficient. The chip design method provided by the embodiment of the invention is beneficial to improving the phenomenon of unbalanced current of the solder balls at different positions far from and near the bare chip, and can improve the working stability and reliability of the chip.
Description
Technical Field
The present invention relates to the field of chip packaging technologies, and in particular, to a chip design method, a chip, a motherboard, and an electronic device.
Background
With the advent of strong demand for use, chip products tend to develop toward low voltage and high current, and accordingly, the difficulty in designing the power supply network of the chip increases.
In order to ensure the high-frequency transient current demand, in such a chip product applied to a high-power scene, when a BGA (Ball GRID ARRAY, ball-shaped pin grid array) package structure is adopted, a capacitor is usually placed at the position, opposite to a die, of the bottom layer of the package structure, so that no solder balls are directly under the die, and the solder balls are distributed around the periphery of the die at the bottom layer of the package structure. In particular applications, excessive solder ball current near the die may cause a series of problems such as electromigration, ball melting, and the like.
Therefore, the chip packaged by adopting the mode has the phenomenon of unbalanced current of solder balls at different positions far from and near from the bare chip, and the phenomenon of unbalanced current in the chip can lead to poor working stability and reliability of the chip.
Disclosure of Invention
In view of this, the present invention provides a chip design method, a chip, a motherboard and an electronic device, so as to at least solve the problem that the chip has unbalanced current of solder balls at different positions far from and near from the die, and the chip has poor working stability and reliability.
In order to achieve the above purpose, the technical scheme of the invention is realized as follows:
In a first aspect, the present invention discloses a chip design method, where a package structure of a chip includes a plurality of circles of solder balls disposed around a bare chip on a package substrate, and a position of each solder ball corresponds to at least one via hole, the method includes:
Dividing different parts in the packaging structure into corresponding circuit grid units in a three-dimensional space, wherein each circuit grid unit corresponds to one equivalent resistor;
determining the serial-parallel connection relation of the equivalent resistors to form the circuit model;
Calculating the proportionality coefficient of the through hole resistance value corresponding to each of the inner ring solder ball and the outer ring solder ball in the circuit model when the transmission current of the inner ring solder ball and the outer ring solder ball surrounding the bare chip in the circuit model is the same;
And determining the number of the through holes at the positions of the corresponding solder balls through the proportionality coefficient.
Optionally, the dividing different parts in the packaging structure into corresponding circuit grid units in three-dimensional space includes:
When the X direction and the Y direction of the packaging structure are the same, dividing circuit grid units in a two-dimensional plane formed by the X direction or the Y direction and the Z direction of the packaging structure;
When the X-direction structure and the Y-direction structure of the packaging structure are different, dividing circuit grid units in two-dimensional planes formed by the X-direction structure, the Y-direction structure and the Z-direction structure respectively;
wherein the Z direction is the thickness direction of the packaging structure, and X, Y and Z are perpendicular to each other.
Optionally, the circuit grid unit at least includes a first grid unit, a second grid unit and a third grid unit, where the first grid unit is a grid unit corresponding to a via hole where one inner ring solder ball of the package structure bare chip is located, the second grid unit is a grid unit corresponding to a via hole where one outer ring solder ball adjacent to the inner ring solder ball is located, and the third grid unit is a grid unit between the inner ring solder ball and the outer ring solder ball.
Optionally, the determining the serial-parallel relationship of the equivalent resistances forms the circuit model, including:
Determining a first resistor corresponding to the first grid cell, a second resistor corresponding to the second grid cell and a third resistor corresponding to the third grid cell;
The second resistor and the third resistor are connected in series to form a first series branch, and the first series branch and the first resistor are connected in parallel to form the circuit model.
Optionally, the calculating a scaling factor of the via resistance value corresponding to each of the inner ring solder ball and the outer ring solder ball in the circuit model includes:
Determining a first relation when the resistance of the first series branch and the first resistor are the same;
And calculating the proportionality coefficients of the first resistor and the second resistor according to the first relation.
Optionally, the circuit grid unit further includes a fourth grid unit, a fifth grid unit and a sixth grid unit, where the fourth grid unit is a grid unit corresponding to a via hole where one inner ring solder ball of the package structure die is located, the fifth grid unit is a grid unit corresponding to a via hole where one outer ring solder ball adjacent to the inner ring solder ball is located, and the sixth grid unit is a grid unit between the inner ring solder ball and the outer ring solder ball;
And connecting lines of the inner ring solder balls corresponding to the first grid unit and the outer ring solder balls corresponding to the second grid unit are positioned in the X direction, and connecting lines of the inner ring solder balls corresponding to the fourth grid unit and the outer ring solder balls corresponding to the fifth grid unit are positioned in the Y direction.
Optionally, the determining the serial-parallel relationship of the equivalent resistances forms the circuit model, and further includes:
Determining a fourth resistor corresponding to the fourth grid cell, a fifth resistor corresponding to the fifth grid cell and a sixth resistor corresponding to the sixth grid cell;
the fifth resistor and the sixth resistor are connected in series to form a second series branch, the second series branch is connected in parallel with the fourth resistor, and the first series branch, the first resistor, the second series branch and the fourth resistor jointly form the circuit model.
Optionally, the calculating a scaling factor of the via resistance value corresponding to each of the inner ring solder ball and the outer ring solder ball in the circuit model further includes:
determining a second relation when the resistance values of the second serial branch and the fourth resistor are the same;
And calculating the proportionality coefficients of the fourth resistor and the fifth resistor according to the second relation.
In a second aspect, the invention discloses a chip prepared according to any one of the chip design methods of the first aspect.
In a third aspect, the present invention discloses a motherboard, which includes the chip described in the foregoing second aspect.
In a fourth aspect, the invention discloses an electronic device, which comprises the chip in the second aspect.
Compared with the prior art, the chip design method, the chip, the main board and the electronic equipment provided by the embodiment of the invention have the following advantages:
In the embodiment of the invention, different parts of the packaging structure of the chip are divided into the corresponding circuit grid units, a circuit model is established according to the serial-parallel connection relation of the equivalent resistance corresponding to each circuit grid unit, and the proportionality coefficient of the via resistance values corresponding to the inner ring solder balls and the outer ring solder balls at different positions far and near the bare chip in the packaging structure can be obtained by calculation through the circuit model, so that the number of the via holes at the positions of the corresponding solder balls is calculated and determined, the reasonable distribution of the number of the via holes at different positions far and near the bare chip is realized, the phenomenon of unbalanced current of the solder balls at different positions far and near the bare chip is facilitated, and the working stability and reliability of the chip can be improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention. In the drawings:
FIG. 1 is a flow chart of a first chip design method in an embodiment of the invention;
FIG. 2 is a schematic cross-sectional view of a chip package structure according to an embodiment of the invention;
FIG. 3 is a schematic diagram of a chip package structure in three dimensions according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a bottom structure of a chip package according to an embodiment of the invention;
FIG. 5 is a flow chart of a second chip design method according to an embodiment of the invention;
FIG. 6 is a schematic diagram of a first circuit model in an embodiment of the invention;
FIG. 7 is a flow chart of a third chip design method according to an embodiment of the invention;
FIG. 8 is a schematic diagram of a second circuit model in an embodiment of the invention;
fig. 9 is a schematic diagram of a third circuit model in an embodiment of the invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged, as appropriate, such that embodiments of the present invention may be implemented in sequences other than those illustrated or described herein, and that the objects identified by "first," "second," etc. are generally of a type, and are not limited to the number of objects, such as the first object may be one or more. Furthermore, in the description and claims, "and/or" means at least one of the connected objects, and the character "/", generally means that the associated object is an "or" relationship.
It should be appreciated that reference throughout this specification to "one embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrase "in one embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
The chip design method of the embodiment of the invention can be used for determining the number of the through holes at the positions of the solder balls, thereby improving the phenomenon of uneven current of the solder balls at the positions near and far from the bare chip. The following describes in detail a chip design method, a chip, a motherboard and an electronic device provided by the invention by listing specific embodiments.
Example 1
As shown in fig. 1, a chip design method according to an embodiment of the present invention specifically includes:
step S101, dividing different parts in the packaging structure into corresponding circuit grid cells in a three-dimensional space, wherein each circuit grid cell corresponds to one equivalent resistor.
Referring to the simplified illustration of fig. 2, for a chip, the package structure 10 mainly includes a package substrate 101 and a die 102 fixed on the package substrate 101, where the die 102 is covered by a package housing 103. DIE 102, commonly known in the chip industry as DIE, are unpackaged dice that are small pieces of particles cut from a wafer with a laser, each DIE being an independent functional chip, also known as a DIE, etc.
After the die 102 is packaged by the BGA technology, a plurality of solder balls 104 are formed on the surface of the package substrate 101 facing away from the die 102, as shown in fig. 3, the solder balls 104 are distributed in the peripheral area of the die 102, it should be noted that, the solder balls 104 are located on the package substrate 101, for each solder ball 104, one or more via holes corresponding to the solder ball 104 are provided on the package substrate 101, the via hole corresponds to the location of each solder ball 104, and the via holes penetrate through the package substrate 101 to form a power network through each via hole, so as to transmit a power supply current, wherein the location of the solder ball 104 refers to the contact range of the solder ball and the package substrate 101.
It will be readily appreciated that the copper layer structure between any via and adjacent vias can be equivalent to individual resistors. Therefore, based on the physical position relation between different through holes and the physical position relation between the copper layer and the through holes, a corresponding circuit model can be constructed. The circuit model is a virtual circuit constructed based on the actual package structure 10, and can reflect the connection relation of the resistors corresponding to the physical structures of the via hole and the copper layer in the package structure 10.
Referring to the schematic diagram of fig. 3, before different portions in the package structure are divided into corresponding circuit grid cells in three-dimensional space, a three-dimensional space coordinate system is created, that is, an arbitrary position on a plane where the package substrate 101 is located may be taken as an origin of coordinates (for example, one corner portion of the package structure 10 is taken as an origin of coordinates in fig. 3), the package structure 10 is placed in the three-dimensional space coordinate system, so that the package substrate 101 is parallel to the XOY plane, and at this time, the Z direction is the thickness direction of the package structure 10. It is readily understood that in such a three-dimensional space coordinate system, the axis of the via is parallel to the Z-direction. Along the Z direction, each via hole has a resistance value，/>Wherein/>For the resistivity of the via copper material,/>S is the via depth, i.e., the dimension of the via in the Z direction, and s is the cross-sectional area of the via. The resistance between adjacent solder balls is/>，/>Wherein/>Is the resistivity of the copper material in the horizontal direction,/>The length of the copper material in the horizontal direction between the two solder balls is W, the width of the copper layer between the two solder balls is W, and the thickness of the copper layer in the Z direction is H.
In the three-dimensional space coordinate system illustrated in fig. 3, the vias at different positions in the package structure 10 and the connection portions between the adjacent vias may be divided into corresponding circuit grid cells, each corresponding to an equivalent resistance.
Referring to fig. 2 and fig. 4, around the die 102, a portion of the solder balls 104 is closer to the die 102, such as the illustrated near solder balls 1041, and another portion of the solder balls 104 is farther from the die 102, such as the illustrated far solder balls 1042, and the circuit model also includes vias corresponding to the near solder balls 1041 and the far solder balls 1042. The near solder balls 1041 are the inner bump balls closer to the die 102, and the far solder balls 1042 are the outer bump balls farther from the die 102. The near-far relationship or the inner-outer relationship between the near solder ball 1041 and the far solder ball 1042 are both referred to the same portion of the die 102, the geometric center of the die 102, or the edges of the die 102.
It should be noted that, in the embodiment of the present invention, for any solder ball 104, it may correspond to a plurality of vias, and each via has the same shape and structural characteristics in the Z direction. Therefore, when the individual solder balls 104 are used for circuit grid division, one solder ball 104, that is, a plurality of vias disposed at the positions of the solder balls 104, may correspond to one circuit grid unit.
Illustratively, for a near solder ball 1041, there are a plurality of vias corresponding to a circuit grid cell, i.e., the grid cell corresponding to the near solder ball 1041, having a corresponding equivalent resistance. Similarly, for a remote solder ball 1042, there are also corresponding vias corresponding to another circuit grid cell, i.e. the grid cell corresponding to the remote solder ball 1042, having a corresponding another equivalent resistance.
It should be noted that, when the distances between the X-direction inner ring solder balls 1041 and the Y-direction inner ring solder balls 1041 of the package structure 10 and the die 102 are the same, and the distances between the X-direction outer ring solder balls 1042 and the Y-direction outer ring solder balls 1042 and the die 102 are the same, the package structure 10 is completely the same structure in the X-direction and the Y-direction, and the circuit grid units may be divided only in one two-dimensional plane of the XOZ plane and the YOZ plane, and then the calculation result may be multiplexed to the other two-dimensional plane.
When the distances between the X-direction inner ring solder balls 1041 and the Y-direction inner ring solder balls 1041 of the package structure 10 and the die 102 are different, or the distances between the X-direction outer ring solder balls 1042 and the Y-direction outer ring solder balls 1042 and the die 102 are different, the package structure 10 has a difference between the X-direction and the Y-direction, and the circuit grid units need to be divided in two-dimensional planes of the XOZ plane and the YOZ plane respectively to perform the calculation in different directions respectively. For example, in the X direction, the center distance between two solder balls isAlong the Y direction, the center distance of the two solder balls is/>In combination with the foregoing/>The calculation formula of (2) is easy to obtain: the resistance in the X direction between adjacent solder balls isResistance in Y direction between adjacent solder balls is/>。
And step S102, determining the serial-parallel connection relation of the equivalent resistances to form a circuit model.
Specifically, in the circuit model established based on the actual package structure 10, the equivalent resistance corresponding to the inner ring solder ball 1041, the equivalent resistance corresponding to the outer ring solder ball 1042, and the equivalent resistance corresponding to the copper layer trace between the inner ring solder ball 1041 and the outer ring solder ball 1042 are included. In the circuit model corresponding to the package structure 10, the transmission and distribution of the supply current are realized through circuits formed by serial-parallel connection among the equivalent resistors. Therefore, the circuit model can be constructed and built by determining the serial-parallel connection relation of the equivalent resistances.
Step S103, when the transmission current of one inner ring solder ball and one outer ring solder ball surrounding the bare chip in the circuit model is the same, calculating the proportionality coefficient of the through hole resistance value corresponding to each inner ring solder ball and each outer ring solder ball in the circuit model.
With reference to fig. 2 to fig. 4, the scaling factor of the via resistance value corresponding to one inner ring solder ball 1041 and one outer ring solder ball 1042 can be calculated by configuring the circuit model to be the same in the transmission current flowing through the solder balls 104 at different positions, so as to realize the differential design of the via Kong Zu value corresponding to the solder balls 104 at different positions.
Step S104, determining the number of the through holes at the positions of the corresponding solder balls through the proportionality coefficient.
It should be noted that, for any solder ball 104, if there are M vias at the solder ball 104, and the resistance value of each via is R, then the equivalent resistance value at the solder ball 104Is the resistance value after M via holes are connected in parallel,/>. In determining the resistance value/>, of each viaIn this case, the resistance calculation formula r=ρ/>, based on the depth, aperture and conductivity parameters of the via structure, may be combinedWherein L can be the depth of the via hole, ρ is the resistivity of the via hole structure, s is the sectional area of the via hole, and the via hole can be any shape such as a round shape or a square shape. It will be appreciated that R herein is as defined above/>The meaning is the same and can represent the resistance corresponding to a single via. Of course, when the resistance value R of each via hole is actually calculated, ρ, L and s required in the formula can be specifically determined according to different research theories, so as to obtain the more accurate resistance value R of the via hole by analysis and comparison.
Assuming that the number of the through holes corresponding to the adjacent inner ring solder balls 1041 is a preset known parameter, the equivalent resistance of the through holes corresponding to the inner ring solder balls 1041 can also be calculated, and according to the condition that the transmission currents of the inner ring solder balls 1041 and the outer ring solder balls 1042 flowing through the inner ring solder balls 1041 and the outer ring solder balls 1042 are the same, the equivalent resistance of the through holes corresponding to the outer ring solder balls 1042 can also be calculated after the proportionality coefficient of the equivalent resistance of the inner ring solder balls 1041 and the outer ring solder balls 1042 is obtained. The equivalent resistance corresponding to the solder balls 104 far from the die 102 can be obtainedBy using the above-mentioned calculation relation of equivalent resistance, the number of vias at the positions of the solder balls 104 far from the die 102 can be easily obtained, thereby providing a via design parameter basis for the packaging process.
In the embodiment of the invention, different parts of the packaging structure of the chip are divided into the corresponding circuit grid units, a circuit model is established according to the serial-parallel connection relation of the equivalent resistance corresponding to each circuit grid unit, and the proportionality coefficient of the via resistance values corresponding to the inner ring solder balls and the outer ring solder balls at different positions far and near the bare chip in the packaging structure can be obtained by calculation through the circuit model, so that the number of the via holes at the positions of the corresponding solder balls is calculated and determined, the reasonable distribution of the number of the via holes at different positions far and near the bare chip is realized, the phenomenon of unbalanced current of the solder balls at different positions far and near the bare chip is facilitated, and the working stability and reliability of the chip can be improved.
Example two
As shown in fig. 5, another chip design method according to an embodiment of the present invention specifically includes:
Step S201, dividing different parts in the package structure into corresponding circuit grid cells in a three-dimensional space, where each circuit grid cell corresponds to an equivalent resistor.
The implementation of step S201 is similar to step S101 of the previous embodiment, and reference is made to the description of step S101.
It should be noted that, when the distances between the X-direction inner ring solder balls 1041 and the Y-direction inner ring solder balls 1041 of the package structure 10 and the die 102 are the same, and the distances between the X-direction outer ring solder balls 1042 and the Y-direction outer ring solder balls 1042 and the die 102 are the same, the package structure 10 is completely the same structure in the X-direction and the Y-direction, and the circuit grid units may be divided only in one two-dimensional plane of the XOZ plane and the YOZ plane, and then the calculation result may be multiplexed to the other two-dimensional plane.
When the distances between the X-direction inner ring solder balls 1041 and the Y-direction inner ring solder balls 1041 of the package structure 10 and the die 102 are different, or the distances between the X-direction outer ring solder balls 1042 and the Y-direction outer ring solder balls 1042 and the die 102 are different, the package structure 10 has a difference between the X-direction and the Y-direction, and the circuit grid units need to be divided in two-dimensional planes of the XOZ plane and the YOZ plane respectively to perform the calculation in different directions respectively. For example, in the X direction, the center distance between two solder balls isAlong the Y direction, the center distance of the two solder balls is/>In combination with the foregoing/>The calculation formula of (2) is easy to obtain: the resistance in the X direction between adjacent solder balls isResistance in Y direction between adjacent solder balls is/>。
Illustratively, when the X-direction and Y-direction structures of the package structure 10 are the same, the foregoing circuit grid unit includes at least a first grid unit, a second grid unit and a third grid unit, where the first grid unit is a grid unit corresponding to a via hole where one inner ring of solder balls 1041 of the die of the package structure is located, the second grid unit is a grid unit corresponding to a via hole where one outer ring of solder balls 1042 is located adjacent to the inner ring of solder balls 1041, and the third grid unit is a grid unit between the inner ring of solder balls 1041 and the outer ring of solder balls 1042.
The inner ring of solder balls 1041 may be a circle of solder balls immediately surrounding the die 102 from inside to outside, and the outer ring of solder balls 1042 may be the remaining peripheral solder balls except for the inner ring of solder balls 1041. Of course, the inner ring of solder balls 1041 may be two or more rings of solder balls immediately surrounding the die 102 from inside to outside, and the outer ring of solder balls 1042 is the remaining peripheral solder balls. Referring to fig. 4, one solder ball 104 at the innermost ring is used as an inner ring solder ball 1041, and the other solder ball 104 adjacent thereto is used as an outer ring solder ball 1042.
One or more via structures at the positions of the inner ring solder balls 1041 correspond to the first grid unit, one or more via structures at the positions of the outer ring solder balls 1042 correspond to the second grid unit, and a copper layer connection structure between the inner ring solder balls 1041 and the outer ring solder balls 1042 corresponds to the third grid unit.
Step S202, determining a first resistance corresponding to the first grid cell, a second resistance corresponding to the second grid cell, and a third resistance corresponding to the third grid cell.
As illustrated in fig. 6, the first grid cell has a first resistance R 1, and when the first grid cell corresponds to the plurality of vias, R 1 is a parallel resistance of the plurality of vias. The second grid cell has a second resistance R 2, and when the second grid cell corresponds to the plurality of vias, R 2 is a parallel resistance of the plurality of vias. The third grid cell has a third resistance R 3,R3, i.e., the lateral resistance between two adjacent solder balls.
In step S203, the second resistor R 2 and the third resistor R 3 are connected in series to form a first serial branch, and the first serial branch and the first resistor R 1 are connected in parallel to form the circuit model.
As shown in fig. 6, the first resistor R 1 is a resistor closer to the die 102, one end of which is connected to the power pin of the die 102, and the other end of which is connected to the inner ring solder balls 1041 on the surface of the package substrate 101. The second resistor R 2 is a resistor far from the die 102, one end of the second resistor R 2 is connected in series with the third resistor R 3 to form a first series branch and then connected with a power pin of the die 102, and the other end of the second resistor R 2 is connected with the outer ring solder ball 1042 on the surface of the package substrate 101. Thus, for chips having the same package structure in the X-direction and the Y-direction, a circuit model of this kind as illustrated in fig. 6 can be built up.
Step S204, determining a first relation when the resistance of the first series branch and the first resistor R 1 are the same.
In conjunction with the circuit model illustrated in fig. 6, it is easy to understand that, to ensure that the currents flowing through the inner ring solder balls 1041 and the outer ring solder balls 1042 are the same, the resistances of the first series branch and the first resistor R 1 are designed to be the same, that is, the first relational expression of R 1=R2+R3 needs to be satisfied.
Step S205, calculating a scaling factor of the first resistor and the second resistor according to the first relation.
Assuming that the number of vias corresponding to the inner ring solder balls 1041 closer to the die 102 is m and the number of vias corresponding to the outer ring solder balls 1042 farther to the die 102 is n, R 1 =，R2=/>R 3 can be determined by the foregoing/>And (5) calculating to obtain the product. Substituting the above parameters into R 1=R2+R3 to obtain/>The ratio of the first resistor to the second resistor can be obtained.
In step S206, the number of vias at the positions of the corresponding solder balls is determined according to the scaling factor.
According to the above relationThe resulting scaling factor is jointly determined by m and n, where m and n are unknown parameters. When designing a chip, after the currents flowing through the inner ring solder balls 1041 and the outer ring solder balls 1042 are determined according to the application requirements, the first resistance and the second resistance of the corresponding positions can be determined, and the third resistance can be calculated and determined, so that the ratio of m to n is also a determined value. At this time, the number of vias corresponding to the solder balls at the other position can be obtained correspondingly by only determining the number of vias corresponding to the solder balls at any position of the inner ring solder balls 1041 and the outer ring solder balls 1042. Thus, according toOnly one of the parameters m and n needs to be determined according to the design requirement, and the other parameter can be determined accordingly.
The method for designing the through holes of the packaging structure can design reasonable through holes for chips with the same packaging structure in the X direction and the Y direction, and based on the calculated through holes, the chip products with more uniform and stable power supply current can be obtained by corresponding packaging.
Example III
As shown in fig. 7, another chip design method according to an embodiment of the present invention specifically includes:
Step S301, dividing different parts in the package structure into corresponding circuit grid cells in a three-dimensional space, wherein each circuit grid cell corresponds to an equivalent resistor.
The implementation of step S301 is similar to step S101 of the previous embodiment, and reference is made to the description of step S101.
Optionally, the circuit grid unit further includes a fourth grid unit, a fifth grid unit, and a sixth grid unit, where the fourth grid unit is a grid unit corresponding to a via hole where one inner ring solder ball 1041 of the package structure die is located, the fifth grid unit is a grid unit corresponding to a via hole where one outer ring solder ball 1042 adjacent to the inner ring solder ball 1041 is located, and the sixth grid unit is a grid unit between the inner ring solder ball 1041 and the outer ring solder ball 1042;
the connection line between the inner ring solder balls 1041 corresponding to the first grid unit and the outer ring solder balls 1042 corresponding to the second grid unit is located in the X direction, and the connection line between the inner ring solder balls 1041 corresponding to the fourth grid unit and the outer ring solder balls 1042 corresponding to the fifth grid unit is located in the Y direction.
Illustratively, when the X-direction and Y-direction structures of the package structure 10 are different, it is necessary to divide the circuit grid cells in both one two-dimensional plane of the XOZ plane and the YOZ plane and the other two-dimensional plane when dividing the circuit grid cells. The circuit grid cells at this time include a fourth grid cell, a fifth grid cell, and a sixth grid cell in addition to the aforementioned first grid cell, second grid cell, and third grid cell. The connection line between the inner ring solder ball 1041 corresponding to the first grid unit and the outer ring solder ball 1042 corresponding to the second grid unit is located in the X direction, and the connection line between the inner ring solder ball 1041 corresponding to the fourth grid unit and the outer ring solder ball 1042 corresponding to the fifth grid unit is located in the Y direction.
Step S302, determining a first resistance corresponding to the first grid cell, a second resistance corresponding to the second grid cell, a third resistance corresponding to the third grid cell, a fourth resistance corresponding to the fourth grid cell, a fifth resistance corresponding to the fifth grid cell, and a sixth resistance corresponding to the sixth grid cell.
As illustrated in fig. 8, the first grid cell has a first resistance R 1, and when the first grid cell corresponds to the plurality of vias, R 1 is a parallel resistance of the plurality of vias. The second grid cell has a second resistance R 2, and when the second grid cell corresponds to the plurality of vias, R 2 is a parallel resistance of the plurality of vias. The third grid cell has a third resistance R 3,R3, i.e., the lateral resistance between two adjacent solder balls 104 in the X-direction.
The third grid cell has a third resistance R 3, and when the third grid cell corresponds to the plurality of vias, R 3 is a parallel resistance of the plurality of vias. The fourth grid cell has a fourth resistance R 4, and when the fourth grid cell corresponds to the plurality of vias, R 4 is a parallel resistance of the plurality of vias. The fifth grid cell has a fifth resistance R 5,R5, i.e., the lateral resistance between two adjacent solder balls 104 in the Y-direction.
Step S303, the second resistor and the third resistor are connected in series to form a first series branch, and the first series branch is connected in parallel with the first resistor; the fifth resistor and the sixth resistor are connected in series to form a second series branch, and the second series branch is connected in parallel with the fourth resistor; the first series leg, the first resistor, the second series leg, and the fourth resistor collectively form the circuit model.
As shown in fig. 8 or fig. 9, along the X direction, the first resistor R 1 is a resistor closer to the die 102, one end of which is connected to the power pin of the die 102, and the other end of which is connected to the inner ring solder ball 1041 on the surface of the package substrate 101. The second resistor R 2 is a resistor far from the die 102, one end of the second resistor R 2 is connected in series with the third resistor R 3 to form a first series branch and then connected with a power pin of the die 102, and the other end of the second resistor R 2 is connected with the outer ring solder ball 1042 on the surface of the package substrate 101. Along the Y direction, the fourth resistor R 4 is a resistor closer to the die 102, one end of which is connected to the power pin of the die 102, and the other end of which is connected to the inner ring solder ball 1041 on the surface of the package substrate 101. The fifth resistor R 5 is a resistor far from the die 102, one end of the fifth resistor R 5 is connected in series with the sixth resistor R 6 to form a second series branch, and then connected to the power pin of the die 102, and the other end is connected to the outer ring solder ball 1042 on the surface of the package substrate 101.
When the inner ring solder balls 1041 at the same position are selected in the mesh division, the first mesh unit and the fourth mesh unit are the same mesh unit, and at this time, the first resistor R 1 and the fourth resistor R 4 are the same resistor, so that the circuit model shown in fig. 8 can be formed. If two inner ring solder balls 1041 at different positions are selected, the first grid cell and the fourth grid cell are different grid cells, and at this time, the first resistor R 1 and the fourth resistor R 4 may be different resistors, so that a circuit model as shown in fig. 9 may be formed.
In either fig. 8 or fig. 9, the second resistor R 2 is connected in series with the third resistor R 3 to form a first series branch, which is connected in parallel with the first resistor R 1. The fifth resistor R 5 and the sixth resistor R 6 are connected in series to form a second series branch, and the second series branch is connected in parallel with the fourth resistor R 4. The first series leg, the first resistor R 1, the second series leg, and the fourth resistor R 4 collectively form a circuit model.
Thus, for chips having different package structures in the X-direction and the Y-direction, a circuit model of the type illustrated in fig. 8 or 9 can be created, and the resistance relationship in the circuit can be calculated from the three directions X, Y and Z.
Step S304, determining a first relation when the resistances of the first serial branch and the first resistor are the same, and determining a second relation when the resistances of the second serial branch and the fourth resistor are the same.
In conjunction with the circuit model illustrated in fig. 8 or 9, it is easy to understand that, for the X direction, if the currents flowing through the inner ring solder balls 1041 and the outer ring solder balls 1042 are guaranteed to be the same, the resistances of the first series branch and the first resistor R 1 need to be designed to be the same, that is, the first relational expression of R 1= R2+R3 needs to be satisfied. For the Y direction, to ensure that the currents flowing through the inner ring solder balls 1041 and the outer ring solder balls 1042 are the same, the resistance values of the second series branch and the fourth resistor R 4 are designed to be the same, that is, the second relation of R 4=R5+R6 needs to be satisfied.
Step S305, calculating the proportionality coefficients of the first resistor and the second resistor according to the first relation, and calculating the proportionality coefficients of the fourth resistor and the fifth resistor according to the second relation.
Taking the circuit model illustrated in fig. 9 as an example, assuming that the number of through holes corresponding to the inner ring solder balls 1041 closer to the die 102 in the X direction is m, and the number of through holes corresponding to the outer ring solder balls 1042 farther from the die 102 is n, R 1 =，R2=R 3 can be determined by the foregoing/>And (5) calculating to obtain the product. Substituting the above parameters into R 1=R2+R3 to obtainThe ratio of the first resistor R 1 to the second resistor R 2 can be obtained.
Assuming that the number of vias corresponding to the inner ring solder balls 1041 closer to the die 102 in the Y direction is p, and the number of vias corresponding to the outer ring solder balls 1042 farther from the die 102 is q, R 4 =，R5=/>R 6 can be determined by the foregoing/>And (5) calculating to obtain the product. Substituting the above parameters into R 4=R5+R6 to obtain/>The ratio of the fourth resistor R 4 to the fifth resistor R 5 is obtained.
Step S306, determining the number of the through holes at the positions of the corresponding solder balls according to the proportionality coefficient.
According to the above relationThe resulting ratio of the first resistor R 1 to the second resistor R 2 is commonly determined by m and n, where m and n are unknown parameters. When the chip is designed, after the currents flowing through the inner ring solder balls 1041 and the outer ring solder balls 1042 along the X direction are determined according to the application requirements, the first resistor R 1 and the second resistor R 2 at the corresponding positions can be determined, and the third resistor R 3 can be determined by calculation, so that the ratio of m to n is also a determined value. At this time, the number of vias corresponding to the solder balls at the other position can be obtained correspondingly by only determining the number of vias corresponding to the solder balls at any position in the inner ring solder ball 1041 and the outer ring solder ball 1042 in the X direction.
According to the above relationThe resulting ratio of the fourth resistor R 4 to the fifth resistor R 5 is commonly determined by p and q, where p and q are unknown parameters. When the chip is designed, after the currents flowing through the inner ring solder balls 1041 and the outer ring solder balls 1042 along the Y direction are determined according to the application requirements, the fourth resistor R 4 and the fifth resistor R 5 at corresponding positions can be determined, and the sixth resistor R 6 can be determined by calculation, so that the ratio of p to q is also a determined value. At this time, the number of vias corresponding to the solder balls at the other position can be obtained correspondingly by only determining the number of vias corresponding to the solder balls at any position in the inner ring solder balls 1041 and the outer ring solder balls 1042 in the Y direction.
The method for designing the through holes of the packaging structure can design reasonable through holes for chips with different packaging structures in the X direction and the Y direction, and based on the calculated through holes, the chip products with more uniform and stable power supply current can be obtained by corresponding packaging.
In addition, it should be noted that, the above embodiments of the method may be used for the proportional relationship between the numbers of the through holes corresponding to the adjacent two circles of solder balls, so as to determine the numbers of the through holes corresponding to the solder balls. In connection with the chip package structure 10 and the description of the relative positional relationship between the inner ring of solder balls 1041 and the outer ring of solder balls 1042 in the foregoing embodiments, it is easy to understand that two adjacent rings of solder balls can be regarded as one group, and the number of vias can be calculated for any one group of two adjacent rings of solder balls by the method described above, so that the number of vias corresponding to each solder ball in the package structure 10 can be obtained.
For example, around the die, the number of vias corresponding to the solder balls at the inner and outer adjacent positions in N 2 and N 1 can be obtained by the method described above, the number of vias corresponding to the solder balls at the inner and outer adjacent positions in N 3 and N 2 can be obtained by the method described above, and so on, the number of vias corresponding to the solder balls at the inner and outer adjacent positions in N i and N 2 can be obtained by the method described above, the number of vias corresponding to the solder balls at the inner and outer adjacent positions in N i and N i-1 can be obtained by the method described above, by the method described above.
Example IV
The embodiment of the invention also discloses a chip, which is prepared according to the chip design method of the embodiment.
By applying the design method in the preparation process of the chip, the distribution quantity of the through holes in the chip packaging structure is more reasonable, the stability and the reliability of a chip power network are improved, and the working performance of the chip is improved. Such a chip may be a high-power processor such as a CPU or GPU used in the server.
Example five
The embodiment of the invention also discloses a main board, which comprises the chip.
The chip with more uniform power supply current is used on a circuit board, so that a mainboard with stable and reliable work can be manufactured, and the stability and reliability of data processing are ensured.
Example six
The embodiment of the invention also discloses electronic equipment which comprises the chip.
In the artificial intelligence industry, the chip with more uniform power supply current can be used for electronic equipment such as a server with high calculation power, and the operation stability and reliability of the electronic equipment can be improved.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or terminal device that comprises the element.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, alternatives, and improvements that fall within the spirit and scope of the invention.
Claims (11)
1. The chip design method is characterized in that the packaging structure of the chip comprises a plurality of circles of solder balls arranged around a bare chip on a packaging substrate, and the position of each solder ball corresponds to at least one through hole, and the method comprises the following steps:
dividing different parts in the packaging structure into corresponding circuit grid units in a three-dimensional space, wherein each circuit grid unit corresponds to an equivalent resistor, and the different parts in the packaging structure comprise a via hole at the position of an inner ring solder ball, a via hole at the position of an outer ring solder ball and a copper layer wiring between the inner ring solder ball and the outer ring solder ball;
Determining the serial-parallel connection relation of the equivalent resistors to form a circuit model;
Calculating the proportionality coefficient of the through hole resistance value corresponding to each of the inner ring solder ball and the outer ring solder ball in the circuit model when the transmission current of the inner ring solder ball and the outer ring solder ball surrounding the bare chip in the circuit model is the same;
And determining the number of the through holes at the positions of the corresponding solder balls through the proportionality coefficient.
2. The chip design method according to claim 1, wherein the dividing the different locations in the package structure into corresponding circuit grid cells in three-dimensional space comprises:
When the X direction and the Y direction of the packaging structure are the same, dividing circuit grid units in a two-dimensional plane formed by the X direction or the Y direction and the Z direction of the packaging structure;
When the X-direction structure and the Y-direction structure of the packaging structure are different, dividing circuit grid units in two-dimensional planes formed by the X-direction structure, the Y-direction structure and the Z-direction structure respectively;
wherein the Z direction is the thickness direction of the packaging structure, and X, Y and Z are perpendicular to each other.
3. The chip design method according to claim 2, wherein the circuit grid unit includes at least a first grid unit, a second grid unit and a third grid unit, the first grid unit is a grid unit corresponding to a via hole where one inner ring of solder balls of the package structure die is located, the second grid unit is a grid unit corresponding to a via hole where one outer ring of solder balls adjacent to the inner ring of solder balls is located, and the third grid unit is a grid unit between the inner ring of solder balls and the outer ring of solder balls.
4. The chip design method according to claim 3, wherein said determining the series-parallel relationship of the respective equivalent resistances forms the circuit model, comprising:
Determining a first resistor corresponding to the first grid cell, a second resistor corresponding to the second grid cell and a third resistor corresponding to the third grid cell;
The second resistor and the third resistor are connected in series to form a first series branch, and the first series branch and the first resistor are connected in parallel to form the circuit model.
5. The method of claim 4, wherein calculating the scaling factor of the via resistance value of each of the inner ring solder ball and the outer ring solder ball in the circuit model comprises:
Determining a first relation when the resistance of the first series branch and the first resistor are the same;
And calculating the proportionality coefficients of the first resistor and the second resistor according to the first relation.
6. The chip design method according to any one of claims 4 to 5, wherein the circuit grid unit further comprises a fourth grid unit, a fifth grid unit and a sixth grid unit, wherein the fourth grid unit is a grid unit corresponding to a via hole where one inner ring solder ball of the package structure die is located, the fifth grid unit is a grid unit corresponding to a via hole where one outer ring solder ball adjacent to the inner ring solder ball is located, and the sixth grid unit is a grid unit between the inner ring solder ball and the outer ring solder ball;
And connecting lines of the inner ring solder balls corresponding to the first grid unit and the outer ring solder balls corresponding to the second grid unit are positioned in the X direction, and connecting lines of the inner ring solder balls corresponding to the fourth grid unit and the outer ring solder balls corresponding to the fifth grid unit are positioned in the Y direction.
7. The chip design method according to claim 6, wherein the determining the series-parallel relationship of the respective equivalent resistances forms the circuit model, further comprising:
Determining a fourth resistor corresponding to the fourth grid cell, a fifth resistor corresponding to the fifth grid cell and a sixth resistor corresponding to the sixth grid cell;
the fifth resistor and the sixth resistor are connected in series to form a second series branch, the second series branch is connected in parallel with the fourth resistor, and the first series branch, the first resistor, the second series branch and the fourth resistor jointly form the circuit model.
8. The chip design method according to claim 7, wherein the calculating the proportionality coefficient of the via resistance value of each of the inner ring solder ball and the outer ring solder ball in the circuit model further comprises:
determining a second relation when the resistance values of the second serial branch and the fourth resistor are the same;
And calculating the proportionality coefficients of the fourth resistor and the fifth resistor according to the second relation.
9. A chip, characterized in that the chip is manufactured according to the chip design method of any one of claims 1 to 8.
10. A motherboard comprising the chip of claim 9.
11. An electronic device comprising the chip of claim 9.
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| CN102508936A (en) * | 2011-09-22 | 2012-06-20 | 南通大学 | High-frequency equivalent circuit used for via holes of BGA (ball grid array) substrate |
| CN102931166A (en) * | 2011-08-12 | 2013-02-13 | 南亚科技股份有限公司 | Semiconductor package structure with low inductance |
| CN114582824A (en) * | 2020-12-01 | 2022-06-03 | 意法半导体股份有限公司 | Semiconductor device and corresponding method |
| CN115377051A (en) * | 2022-08-25 | 2022-11-22 | 飞腾信息技术有限公司 | Packaging substrate, packaging substrate design method and related equipment |
| CN116008632A (en) * | 2022-12-29 | 2023-04-25 | 篆芯半导体(南京)有限公司 | Method, device, electronic equipment and storage medium for acquiring chip current characteristics |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20230326842A1 (en) * | 2022-04-11 | 2023-10-12 | Xilinx, Inc. | Chip package with integrated current control |
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| CN102931166A (en) * | 2011-08-12 | 2013-02-13 | 南亚科技股份有限公司 | Semiconductor package structure with low inductance |
| CN102508936A (en) * | 2011-09-22 | 2012-06-20 | 南通大学 | High-frequency equivalent circuit used for via holes of BGA (ball grid array) substrate |
| CN114582824A (en) * | 2020-12-01 | 2022-06-03 | 意法半导体股份有限公司 | Semiconductor device and corresponding method |
| CN115377051A (en) * | 2022-08-25 | 2022-11-22 | 飞腾信息技术有限公司 | Packaging substrate, packaging substrate design method and related equipment |
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