CN115377051A

CN115377051A - Packaging substrate, packaging substrate design method and related equipment

Info

Publication number: CN115377051A
Application number: CN202211027501.XA
Authority: CN
Inventors: 卢旭东; 曾维; 周曦; 李晶; 李俊峰
Original assignee: Phytium Technology Co Ltd
Current assignee: Phytium Technology Co Ltd
Priority date: 2022-08-25
Filing date: 2022-08-25
Publication date: 2022-11-22
Also published as: CN115377052A

Abstract

The invention provides a packaging substrate, a packaging substrate design method and related equipment, wherein the packaging substrate comprises a substrate main body, the substrate main body comprises a plurality of conducting layers which are arranged in a stacked mode, the conducting layers positioned on two opposite sides of the substrate main body are respectively provided with a plurality of first bonding pads and a plurality of second bonding pads, each second bonding pad is connected with a welding ball, the first bonding pads are used for being electrically connected with a bare chip, and the second bonding pads are used for being electrically connected with a power supply device.

Description

Packaging substrate, packaging substrate design method and related equipment

Technical Field

The invention relates to the technical field of chips, in particular to a packaging substrate, a packaging substrate design method and related equipment.

Background

With the advent of advanced technologies such as automatic driving and artificial intelligence, the demand of people for computing power of servers has risen exponentially, which requires that a server chip integrates more cores to meet the computing demand of the market. However, with the improvement of the computing performance of the chip, the chip is more prone to have the problem of poor contact such as short circuit of partial solder balls, and the like, and the working performance of the chip is affected.

Disclosure of Invention

In view of the above, the present invention is directed to a package substrate, a method for designing the package substrate, and a related device, so as to solve the problem of poor contact, such as short circuit, of solder balls in a chip portion.

In a first aspect, the present invention discloses a package substrate comprising a substrate body; the substrate main body comprises a plurality of conducting layers which are arranged in a stacked mode and an insulating layer located between every two adjacent conducting layers;

the conducting layers positioned on two opposite sides of the substrate main body are respectively provided with a plurality of first bonding pads and a plurality of second bonding pads, and each second bonding pad is connected with a welding ball; the conducting layers positioned in the middle of the substrate main body comprise a plurality of leads, and the leads positioned on different conducting layers are electrically connected through via holes penetrating through the insulating layers between the conducting layers;

the first bonding pad is used for electrically connecting with a bare chip; the second bonding pad is used for being electrically connected with a power supply device through the solder ball; the power supply means supplies power to the die through a plurality of power supply paths; a power supply path including at least one solder ball, one second pad electrically connected to the one solder ball, a via electrically connecting the one second pad to at least one wire, the at least one wire, a via electrically connecting a plurality of wires of the at least one wire, a via electrically connecting the at least one wire to one first pad, and the one first pad;

in the process that the power supply device supplies power to the bare chip through the plurality of power supply paths, currents flowing through the solder balls corresponding to any two power supply paths are the same in magnitude, so that the problem that the solder balls are burnt due to the fact that part of the currents flowing through the solder balls are too large is avoided, and the problem that the solder balls are poor in contact such as short circuit is further avoided.

Optionally, during the process that the power supply device supplies power to the bare chip through the plurality of power supply paths, impedances corresponding to any two power supply paths are the same, and/or currents flowing through any two power supply paths are the same, so that during the process that the power supply device supplies power to the bare chip through the plurality of power supply paths, currents flowing through solder balls corresponding to any two power supply paths are the same.

Optionally, the package substrate and the power supply device are disposed on a printed circuit board, the power supply device is electrically connected to the package substrate through the printed circuit board, and the power supply device is located on the other side of the package substrate away from the die;

each power supply path comprises a first sub-path, and the first sub-path comprises a solder ball, a second bonding pad, a wire, a via hole and a first bonding pad which are positioned in the packaging substrate; and the impedance of the first sub-path where the solder ball close to the power supply device is located is greater than the impedance of the first sub-path where the solder ball far away from the power supply device is located, so that in the process that the power supply device supplies power to the bare chip through the plurality of power supply paths, the current flowing through the solder balls corresponding to any two power supply paths is the same in magnitude.

Optionally, the package substrate satisfies at least one of the following conditions:

the density of the solder balls in the area where the first sub-path close to the power supply device is located is greater than that of the solder balls in the area where the first sub-path far away from the power supply device is located;

the total area of the wires in the first sub-path close to the power supply device is smaller than the total area of the wires in the first sub-path far away from the power supply device;

the number of the via holes in the first sub-path close to the power supply device is smaller than that of the via holes in the first sub-path far away from the power supply device; so that the current flowing in the solder balls corresponding to any two power supply paths is the same in the process that the power supply device supplies power to the bare chip through the plurality of power supply paths.

Optionally, in a direction from the second pad to the first pad, areas of the plurality of conductive layers sequentially increase, and the plurality of conductive layers overlap each other in a region away from the power supply device and partially overlap each other in a region close to the power supply device, so that a total area of the wires in the first sub-path close to the power supply device is smaller than a total area of the wires in the first sub-path away from the power supply device.

In a second aspect, the present invention discloses a chip comprising a package substrate as described in any of the above and a die electrically connected to the first bonding pad of the package substrate.

In a third aspect, the present invention discloses an integrated circuit system comprising a printed circuit board, a power supply device and the chip, wherein the chip and the power supply device are mounted on the printed circuit board, and the power supply device supplies power to the chip through the printed circuit board.

In a fourth aspect, the invention discloses an electronic device comprising an integrated circuit system as described above.

In a fifth aspect, the present invention discloses a method for designing a package substrate, including that the package substrate includes a substrate main body, the substrate main body includes a plurality of conductive layers arranged in a stacked manner and an insulating layer located between two adjacent conductive layers, the conductive layers located at two opposite sides of the substrate main body respectively have a plurality of first pads and a plurality of second pads, each of the second pads is connected with a solder ball, the first pads are used for electrically connecting with a die, the second pads are used for electrically connecting with a power supply device, the conductive layer located in the middle of the substrate main body includes a plurality of wires, the wires located in different conductive layers are electrically connected through via holes penetrating through the insulating layers between the two conductive layers, the method for designing a package substrate includes:

determining a structure of a plurality of power supply paths through which the power supply device supplies power to the die, one power supply path including at least one solder ball, one second pad electrically connected to the one solder ball, a via electrically connecting the one second pad and at least one wire, the at least one wire, a via electrically connecting a plurality of wires of the at least one wire, a via electrically connecting the at least one wire and one first pad, and the one first pad;

and adjusting at least one structural parameter of the solder balls, the bonding pads, the wires and the via holes in any one power supply path, so that in the process that the power supply device supplies power to the bare chip through the plurality of power supply circuits, the currents flowing in the solder balls corresponding to any two power supply paths are the same in magnitude, the problem that the solder balls are burnt due to the fact that part of the currents flowing in the solder balls are too large is avoided, and the problem that the solder balls are short-circuited and poor in contact is avoided.

Optionally, in a process that the power supply device supplies power to the bare chip through the plurality of power supply paths, impedances corresponding to any two power supply paths are the same, and/or currents flowing through any two power supply paths are the same, so that in a process that the power supply device supplies power to the bare chip through the plurality of power supply paths, currents flowing through solder balls corresponding to any two power supply paths are the same.

Optionally, the package substrate and the power supply device are disposed on a printed circuit board, the power supply device is electrically connected to the package substrate through the printed circuit board, and the power supply device is located on a side of the package substrate away from the die, each of the power supply paths includes a first sub-path, the first sub-path includes a solder ball, a second pad, a wire, a via, and a first pad located in the package substrate, and then the adjusting of the structural parameter of at least one of the solder ball, the pad, the wire, and the via in any one of the power supply paths includes:

and adjusting at least one of the position of the solder ball in any one of the power supply paths, the area of the wire and the number of the via holes, so that the impedance of the first sub-path where the solder ball close to the power supply device is located is greater than the impedance of the first sub-path where the solder ball close to the bare chip is located, and in the process that the power supply device supplies power to the bare chip through the plurality of power supply paths, the current flowing through the solder balls corresponding to any two power supply paths is the same.

Optionally, adjusting the position of the solder ball in any one of the power supply paths comprises: the density of the solder balls in the area where the first sub path close to the power supply device is located is larger than that of the solder balls in the area where the first sub path far away from the power supply device is located;

adjusting the area of the wire in any one of the power supply paths comprises: making a total area of the conductive lines in the first sub-path close to the power supply means smaller than a total area of the conductive lines in the first sub-path far from the power supply means;

adjusting the number of vias in any of the power supply paths comprises: making the number of vias in the first sub-path closer to the power supply device smaller than the number of vias in the first sub-path farther from the power supply device;

so that the current flowing in the solder balls corresponding to any two power supply paths is the same in the process that the power supply device supplies power to the bare chip through the plurality of power supply paths.

Optionally, the making the total area of the wires in the first sub-path where the solder balls close to the power supply device are located smaller than the total area of the wires in the first sub-path where the solder balls close to the die are located includes:

the areas of the conducting layers are sequentially increased in the direction from the second bonding pad to the first bonding pad, the conducting layers are overlapped in the area close to the bare chip, and the conducting layers are partially overlapped in the area close to the power supply device, so that the total area of the conducting wires in the first sub-path close to the power supply device is smaller than the total area of the conducting wires in the first sub-path far away from the power supply device.

Optionally, the determining a plurality of power supply paths comprises:

determining structural information of the package substrate based on design information of the package substrate;

determining the structure of the plurality of power supply paths based on the structure information of the package substrate.

In a sixth aspect, the present invention discloses a computer device, comprising a memory and a processor;

the memory is to store instructions;

the processor is configured to execute the package substrate design method according to the instructions stored in the memory.

In a seventh aspect, the invention discloses a computer-readable storage medium, which is characterized by storing instructions for executing the package substrate design method as described in any one of the above.

The invention provides a packaging substrate, a packaging substrate design method and related equipment, wherein the packaging substrate comprises a substrate main body, the substrate main body comprises a plurality of conducting layers which are arranged in a stacked mode and an insulating layer which is arranged between every two adjacent conducting layers, the conducting layers which are arranged on two opposite sides of the substrate main body are respectively provided with a plurality of first bonding pads and a plurality of second bonding pads, each second bonding pad is connected with a welding ball, the first bonding pad is used for being electrically connected with a bare chip, and the second bonding pad is used for being electrically connected with a power supply device.

Drawings

The above and other objects, features and advantages of the present application will become more apparent by describing in more detail embodiments of the present application with reference to the attached drawings. The accompanying drawings are included to provide a further understanding of the embodiments of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. In the drawings, like reference numbers generally represent like parts or steps.

Fig. 1 is a schematic cross-sectional view of a package substrate according to an embodiment of the invention.

Fig. 2 is a schematic plan view of a first conductive layer according to an embodiment of the present invention.

Fig. 3 is a schematic plan view of a sixth conductive layer according to an embodiment of the disclosure.

Fig. 4 is a schematic plan view of a second conductive layer according to an embodiment of the invention.

Fig. 5 is a schematic cross-sectional structure diagram of a package substrate, a bare chip and a power supply device according to an embodiment of the disclosure.

Fig. 6 is a schematic top view of a package substrate, a die, and a power supply device according to an embodiment of the disclosure.

Fig. 7 is a schematic top view of another package substrate, a die, and a power supply device according to an embodiment of the disclosure.

Fig. 8 is a schematic plan view of a plurality of solder balls according to an embodiment of the present invention.

Fig. 9 is a schematic plan view of another package substrate according to an embodiment of the disclosure.

Fig. 10 is a schematic cross-sectional view of the package substrate shown in fig. 9.

Fig. 11 is a schematic plan view of another package substrate according to an embodiment of the disclosure.

Fig. 12 is a schematic cross-sectional view of another bare chip, a package substrate and a power supply device according to an embodiment of the disclosure.

Fig. 13 is a schematic cross-sectional structure diagram of a chip according to an embodiment of the disclosure.

Fig. 14 is a schematic structural diagram of an integrated circuit system according to an embodiment of the disclosure.

Fig. 15 is a flowchart of a method for designing a package substrate according to an embodiment of the invention.

Fig. 16 is a schematic structural diagram of an electronic device according to an embodiment of the disclosure.

Detailed Description

The technical solutions in the embodiments of the present invention will be described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

With the improvement of the computing performance of the chip, the power consumption of the chip is continuously increased, and the power supply current of the chip is also continuously increased. The inventor researches and discovers that although the solder balls in the chip are uniformly distributed, the current flowing in different solder balls is different, and when the power supply current of the chip is increased, the current flowing in part of the solder balls is easy to be overlarge, so that the part of the solder balls are burnt, and the problem of poor contact such as short circuit and the like of the part of the solder balls is caused.

Therefore, the invention discloses a packaging substrate, which avoids the problem of poor contact such as short circuit of a solder ball and the like due to the fact that the current flowing through the solder ball is the same in the solder balls corresponding to a plurality of power supply paths from a power supply device to a bare chip of the packaging substrate.

As an optional implementation of the disclosure, an embodiment of the present invention discloses a package substrate, which includes a substrate main body, where the substrate main body includes a plurality of conductive layers stacked in a stacked manner, and an insulating layer located between two adjacent conductive layers.

As shown in fig. 1, fig. 1 is a schematic cross-sectional structure diagram of a package substrate according to an embodiment of the disclosure, in which a substrate body includes first to sixth conductive layers L1 to L6 and first to fifth insulating layers R1 to R5, and the first to fifth insulating layers R1 to R5 are respectively located between the first to sixth conductive layers L1 to L6.

It should be noted that, in the embodiment of the present invention, only the substrate main body including six conductive layers is taken as an example for description, and the description is not limited thereto, and in other embodiments, the substrate main body of the package substrate may further include three, four, five, or even more conductive layers, which is not described herein again.

In the embodiment of the invention, the conducting layers positioned on the two opposite sides of the substrate main body are respectively provided with a plurality of first bonding pads and a plurality of second bonding pads, and each second bonding pad is connected with a welding ball. As shown in fig. 1, the first conductive layer L1 and the sixth conductive layer L6 are respectively located on two opposite sides of the substrate body, and the first conductive layer L1 has a plurality of first pads H1, the sixth conductive layer L6 has a plurality of second pads H2, and each of the second pads H2 is connected with a solder ball H3.

As shown in fig. 2, fig. 2 is a schematic plan view of a first conductive layer according to an embodiment of the present invention, and the first pads H1 may be a plurality of square pads arranged in an array. Of course, in other embodiments, the first pads H1 may also be a plurality of circular pads arranged in an array or a plurality of strip pads arranged in parallel, and so on, which are not described herein again.

As shown in fig. 3, fig. 3 is a schematic plan view of a sixth conductive layer according to an embodiment of the present invention, the second pads H2 may be a plurality of square pads arranged in an array, and a central area of each square pad has a solder ball H3. Of course, in other embodiments, the second pads H2 may also be a plurality of circular pads arranged in an array or a plurality of strip pads arranged in parallel, and so on, which are not described herein again.

It is understood that the solder balls H3 in the embodiment of the present invention are made of solder or the like, and a plurality of solder balls H3 arranged in an Array form a Ball Grid Array (BGA), by which a package substrate can be loaded and connected to a printed circuit board.

The first pad H1 and the second pad H2 in the embodiment of the present invention are both power supply pads. The package substrate in the embodiment of the invention not only comprises the power supply bonding pad, but also comprises the grounding bonding pad, the signal bonding pad and the like. In the structure shown in fig. 2, the third pad H4 may be a ground pad and the other pads may be signal pads, and in the structure shown in fig. 3, the fourth pad H5 may be a ground pad and the other pads may be signal pads. Of course, fig. 2 and 3 illustrate only one pad layout, but are not limited thereto.

In the embodiment of the invention, the conducting layer positioned in the middle of the substrate main body comprises a plurality of conducting wires, the conducting wires positioned in different conducting layers are electrically connected through the through holes penetrating through the insulating layers between the conducting wires and the conducting wires, and the bonding pads and the conducting wires are also electrically connected through the through holes penetrating through the insulating layers between the conducting wires and the conducting wires.

As shown in fig. 1, the second to fifth conductive layers L2 to L5 are located in the middle of the substrate main body, and the wires of adjacent two of the second to fifth conductive layers L2 to L5 are electrically connected through a via G penetrating through the insulating layer therebetween, the first pad H1 is electrically connected to the wire of the second conductive layer L2 through a via G penetrating through the first insulating layer R1, and the second pad H2 is electrically connected to the wire of the fifth conductive layer L5 through a via G penetrating through the fifth insulating layer R5.

As shown in fig. 4, fig. 4 is a schematic plan view of a second conductive layer according to an embodiment of the present invention, in which a plurality of conductive lines D are arranged in parallel, and adjacent conductive lines D are insulated by an insulating layer. It is understood that the structures of the third to fifth conductive layers may be the same as or different from the structure of the second conductive layer, for example, the shapes, sizes, and positions of the conductive lines may be different.

In the embodiment of the invention, the first bonding pad H1 is used for being electrically connected with a bare chip (DIE), the second bonding pad H2 is used for being electrically connected with a power supply device through a welding ball H3, and the power supply device supplies power to the bare chip through a plurality of power supply circuits. In fig. 1, only a few power supply paths indicated by arrows are illustrated as an example, and the present invention is not limited to this.

Referring to fig. 1, one power supply path includes at least one solder ball H3, one second pad H2 electrically connected to the one solder ball H3, a via hole electrically connecting the one second pad H2 and at least one wire, a via hole electrically connecting a plurality of wires of the at least one wire, a via hole electrically connecting the at least one wire and one first pad H1, and one first pad H1.

Or, one power supply path at least comprises one solder ball H3, one second pad H2, a plurality of vias, at least one wire and one first pad H1, wherein one solder ball H3 is electrically connected with one second pad H2, one second pad H2 is electrically connected with at least one wire through a via, a plurality of wires in at least one wire are electrically connected through a via, and at least one wire is electrically connected with one first pad H1 through a via.

In some optional examples, one power supply path includes at least one solder ball H3, one second pad H2 electrically connected to one solder ball H3, a via electrically connecting one second pad H2 with a wire in the fifth conductive layer L5, a via electrically connecting a wire in the fifth conductive layer L5 with a wire in the fourth conductive layer L4, a via electrically connecting a wire in the fourth conductive layer L4 with a wire in the third conductive layer L3, a via electrically connecting a wire in the third conductive layer L3 with a wire in the second conductive layer L2, a via electrically connecting a wire in the second conductive layer L2 with one first pad H1, and one first pad H1.

Of course, the present invention is not limited thereto, and in other alternative examples, one second pad H2 may also be electrically connected to one first pad H1 through wires in a part of the second conductive layer L2 to the fifth conductive layer L5, which will not be described herein again. It is understood that the different power supply paths may be identical or different in structure.

In the embodiment of the invention, in the process that the power supply device supplies power to the bare chip through the plurality of power supply paths, the current flowing through the solder balls H3 corresponding to any two power supply paths is the same. Or, in the process that the power supply device supplies power to the bare chip through the plurality of power supply paths, the current flowing through any two solder balls H3 in the plurality of solder balls H3 corresponding to the plurality of power supply paths is the same.

Therefore, the current flowing through the packaging substrate and part of the solder balls H3 of the chip comprising the packaging substrate can be avoided from being overlarge, and further the problem that the part of the solder balls H3 are burnt due to the overlarge current can be avoided, and the problem of poor contact such as short circuit and the like caused by the burning of the part of the solder balls H3 can be avoided.

In some embodiments of the present invention, in a process that the power supply device supplies power to the bare chip through the plurality of power supply paths, impedances corresponding to any two power supply paths are the same, and/or currents flowing through any two power supply paths are the same, so that currents flowing through the solder balls H3 corresponding to any two power supply paths are the same.

It can be understood that, although the power supply voltage or current output by the power supply device to the plurality of power supply paths is the same, the impedance of each power supply path is different, so that the current flowing through each power supply path is different, and the current flowing through the solder ball of each power supply path is different. Based on this, in some alternative examples, the current flowing through the solder ball H3 corresponding to any two power supply paths is the same in magnitude by making the impedance corresponding to any two power supply paths the same.

However, in practical applications, under the influence of factors such as manufacturing process and path dividing manner, the impedances corresponding to any two power supply paths are the same, and it is not necessarily possible to make the currents flowing through the solder balls H3 corresponding to any two power supply paths have the same magnitude. Based on this, in other alternative examples, the current flowing through the solder ball H3 corresponding to any two power supply paths is the same in magnitude by making the current flowing through any two power supply paths the same in magnitude.

Of course, in other alternative examples, the current flowing through the solder ball H3 corresponding to any two power supply paths may also be the same by making the impedance and the current flowing through any two power supply paths respectively the same.

In some embodiments of the present invention, as shown in fig. 5, fig. 5 is a schematic cross-sectional structure diagram of a package substrate, a bare chip, and a power supply device according to an embodiment of the present invention, where the package substrate 10 and the power supply device 30 are both disposed on a printed circuit board 40, the bare chip 20 is disposed on the package substrate 10, the power supply device 30 is located on one side of the package substrate 10, and distances from different solder balls of the package substrate 10 to the power supply device 30 are different.

In some alternative examples, the die 20 is located on one side of the package substrate 10, and the power supply device 30 is located on the other side of the package substrate 10 away from the die 20. As shown in fig. 6, fig. 6 is a schematic top view of a package substrate, a bare chip, and a power supply device according to an embodiment of the present invention, where the bare chip 20 is located on the left side of the package substrate 10, and the power supply device 30 is located on the right side of the package substrate 10 away from the bare chip 20. Of course, the invention is not limited in this regard, and in other embodiments, the die 20 is located on one side of the package substrate 10, and the power supply device 30 is located on the other side of the package substrate 10. As shown in fig. 7, fig. 7 is a schematic top view of another package substrate, a bare chip, and a power supply device according to the embodiment of the present invention, where the bare chip 20 is located on the left side of the package substrate 10, and the power supply device 30 is located on the upper side of the package substrate 10.

In the embodiment of the present invention, structural parameters of solder balls, pads, vias, and wires in the package substrate 10 may be adjusted based on a position relationship between the power supply device 30, the package substrate 10, and the bare chip 20, so that in a process in which the power supply device 30 supplies power to the bare chip 20 through a plurality of power supply paths, impedances corresponding to any two power supply paths are the same, and/or currents flowing through any two power supply paths are the same, so that currents flowing through the solder balls corresponding to any two power supply paths are the same.

In the embodiment of the present invention, as shown in fig. 5, the first bonding pad H1 of the package substrate 10 is electrically connected to the bare chip 20, the second bonding pad H2 of the package substrate 10 is electrically connected to the power supply device 30 through the solder ball H3 and the printed circuit board 40, and the power supply device 30 supplies power to the bare chip 20 through the plurality of power supply paths S. In some alternative examples, each power supply path includes a first sub-path including a solder ball H3, a second pad H2, a wire D, a via G, and a first pad H1 in the package substrate 10, and a second sub-path including a pad, a wire, a via, and the like in the printed circuit board 40.

Since the distances from the different solder balls of the package substrate 10 to the power supply device 30 are different, the impedance of the second sub-path close to the power supply device 30 among the different power supply paths is smaller than the impedance of the second sub-path far from the power supply device 30. Based on this, in some embodiments of the present invention, the impedance of the first sub-path where the solder ball H3 close to the power supply device 30 is located is greater than the impedance of the first sub-path where the solder ball H3 far from the power supply device 30 is located, so that in a process that the power supply device 30 supplies power to the bare chip 20 through a plurality of power supply paths, the impedances corresponding to any two power supply paths are the same, and/or the currents flowing through any two power supply paths are the same, so that the currents flowing through the solder balls corresponding to any two power supply paths are the same.

It can be understood that the impedance of each power supply path is equal to the sum of the impedance of the first sub-path and the impedance of the second sub-path, and therefore, the impedance of the first sub-path where the solder ball H3 close to the power supply device 30 is located can be made larger than the impedance of the first sub-path where the solder ball H3 far from the power supply device 30 is located by adjusting the impedances of the solder ball H3, the second pad H2, the wire D, the via G, and the first pad H1 in the first sub-path.

In the embodiment of the present invention, the plurality of power supply paths may be divided according to the connection relationship between the plurality of first pads H1 and the plurality of second pads H2 on the package substrate. The different power supply paths may include the same wire or different wires. In case the different power supply paths comprise different wires, the impedances and currents of the different power supply paths may be calculated from the impedances of the respective wires of the different power supply paths. In the case where different power supply paths include the same wire, although a plurality of solder balls H3 are all electrically connected to the same wire, each solder ball H3 conducts or transmits current through a partial line segment of the wire closest thereto, and therefore, in some alternative examples, the impedance and current of the plurality of power supply paths may be calculated by dividing the wire into a plurality of line segments and making the plurality of line segments belong to the plurality of power supply paths, respectively.

In some embodiments of the present invention, the package substrate 20 satisfies at least one of a plurality of conditions, such that the current flowing through the solder balls H3 corresponding to any two power supply paths is the same, where the plurality of conditions include: the density of the solder balls H3 in the region where the first sub-path close to the power supply device 30 is located is greater than the density of the solder balls H3 in the region where the first sub-path far from the power supply device 30 is located; the total area of the conductive lines D in the first sub-path close to the power supply device 30 is smaller than the total area of the conductive lines D in the first sub-path far from the power supply device 30; the number of vias G in the first sub-path close to the power supply device 30 is smaller than the number of vias G in the first sub-path far from the power supply device 30.

As shown in fig. 8, fig. 8 is a schematic plan view of a plurality of solder balls, according to an embodiment of the present invention, a pitch of the solder balls H3 in an area Q1 where the first sub-path close to the power supply device 30 is located is smaller than a pitch of the solder balls H3 in an area Q2 where the first sub-path far from the power supply device 30 is located, and a density of the solder balls H3 in the area Q1 where the first sub-path close to the power supply device 30 is located is greater than a density of the solder balls H3 in the area Q2 where the first sub-path far from the power supply device 30 is located.

Since the distances from the different solder balls of the package substrate 10 to the power supply device 30 are different, the current flowing through the area Q1 near the first sub-path of the power supply device 30 is greater than the current flowing through the area Q2 far from the first sub-path of the power supply device 30. Based on this, in some embodiments of the present invention, by making the density of the solder balls H3 in the area Q1 where the first sub-path close to the power supply device 30 is located greater than the density of the solder balls H3 in the area Q2 where the first sub-path far from the power supply device 30 is located, it is possible to make the currents flowing through the solder balls H3 corresponding to any two power supply paths be the same in the process that the power supply device 30 supplies power to the bare die 20 through the plurality of power supply paths.

It should be noted that, in the embodiment of the present invention, the surface of the package substrate with the solder balls H3 is merely divided into two areas, which is not limited to this, and in other embodiments, the surface of the package substrate with the solder balls H3 may be evenly divided into three or more areas, and in a plurality of areas close to the power supply device 30, the density or number of the solder balls H3 is sequentially increased.

In some embodiments of the present invention, the total area of the conductive lines D in the first sub-path where the solder balls H3 close to the power supply device 30 are located can be smaller than the total area of the conductive lines D in the first sub-path where the solder balls H3 close to the die 20 are located by adjusting the length and the width of the conductive lines D in the first sub-path.

Of course, the present invention is not limited thereto, and in other embodiments, the total area of the wires D in the first sub-path where the solder balls H3 close to the power supply device 30 are located may be smaller than the total area of the wires D in the first sub-path where the solder balls H3 close to the die 20 are located by adjusting the area of each conductive layer in the package substrate 10.

As shown in fig. 9 and 10, fig. 9 is a schematic plan view of another package substrate according to an embodiment of the disclosure, and fig. 10 is a schematic cross-sectional view of the package substrate shown in fig. 9, in which areas of the plurality of conductive layers are sequentially increased in a direction from the second pad H2 to the first pad H1. As shown in fig. 9 or 10, the lengths of the first to sixth conductive layers L1 to L6 are sequentially increased so that the areas of the first to sixth conductive layers L1 to L6 are sequentially increased.

Furthermore, the conductive layers are overlapped in the area far away from the power supply device 30, and the conductive layers are partially overlapped in the area close to the power supply device 30, so that the total area of the conductive lines D in the first sub-path where the solder balls H3 close to the power supply device 30 are located is smaller than the total area of the conductive lines D in the first sub-path where the solder balls H3 close to the die 20 are located.

In the structure shown in fig. 8, the package substrate 10 is a regular square substrate, but the present invention is not limited thereto, and in some alternative examples, as shown in fig. 11, fig. 11 is a schematic plane structure of another package substrate disclosed in the embodiment of the present invention, the package substrate 10 may also be a substrate having a bridge region 100, the bridge region 100 is located between the die 20 and the power supply device 30, and the width of the bridge region 100 is smaller than the width of the package substrate 10, so as to reduce the area of the package substrate 10 and reduce the occupied space of the package substrate 10 while extending the length of the conductive layer in the package substrate 10.

In some embodiments of the present invention, as shown in fig. 12, fig. 12 is a schematic cross-sectional structure diagram of another die, a package substrate, and a power supply device disclosed in the embodiments of the present invention, where the number of vias G in a first sub-path where a solder ball H3 close to the power supply device 30 is located is smaller than the number of vias G in a first sub-path where a solder ball H3 far from the power supply device 30 is located, so as to increase impedance of the first sub-path where the solder ball H3 close to the power supply device 30 is located by reducing the number of vias G in the first sub-path where the solder ball H3 close to the power supply device 30 is located, so that impedance of the first sub-path where the solder ball H3 close to the power supply device 30 is located is larger than impedance of the first sub-path where the solder ball H3 close to the die 20 is located.

In the above embodiments of the present invention, only one impedance adjustment manner of the solder ball, the wire and the via is taken as an example for description, however, the present invention is not limited thereto, and in other embodiments, at least two of the impedance of the solder ball, the impedance of the wire and the impedance of the via may also be adjusted at the same time, which is not described herein again.

As an optional implementation of the disclosure, an embodiment of the present invention discloses a chip, which may be a server chip or a processor chip. As shown in fig. 13, fig. 13 is a schematic cross-sectional structure diagram of a chip disclosed in an embodiment of the present invention, the chip includes the package substrate 10 and the die 20 disclosed in any of the above embodiments, wherein the die 20 is packaged on the package substrate 10, and the die 20 is electrically connected to the first pad of the package substrate 10.

As an optional implementation of the disclosure, an embodiment of the present invention discloses an integrated circuit system, as shown in fig. 14, fig. 14 is a schematic structural diagram of the integrated circuit system disclosed in the embodiment of the present invention, the integrated circuit system includes a printed circuit board 40, a power supply device 30 and the above chip, the chip and the power supply device 30 are mounted on the printed circuit board 40, and the power supply device 30 supplies power to the chip through the printed circuit board 40.

As an alternative implementation of the present disclosure, an embodiment of the present invention discloses an electronic device, which includes the integrated circuit system disclosed in the above embodiment. The electronic equipment comprises a smart phone, a tablet computer, a digital camera, a server and the like.

As an optional implementation of the disclosure, an embodiment of the present invention discloses a method for designing a package substrate, as shown in fig. 1, the package substrate includes a substrate main body, where the substrate main body includes a plurality of conductive layers, such as a first conductive layer L1 to a sixth conductive layer L6, stacked in a stacked manner, and an insulating layer, such as a first insulating layer R1 to a fifth insulating layer R5, between two adjacent conductive layers, the conductive layers on two opposite sides of the substrate main body respectively have a plurality of first pads and a plurality of second pads, each of the second pads is connected to a solder ball, for example, the first conductive layer L1 has a plurality of first pads H1, the sixth conductive layer L6 has a plurality of second pads H2, and each of the second pads H2 is connected to a solder ball H3. The first bonding pad H1 is used for electrically connecting with the bare chip, the second bonding pad H2 is used for electrically connecting with the power supply device, the conducting layer positioned in the middle of the substrate main body comprises a plurality of conducting wires, and the conducting wires positioned in different conducting layers are electrically connected through a through hole penetrating through the insulating layer between the conducting wires and the conducting layer.

As shown in fig. 15, fig. 15 is a flowchart of a method for designing a package substrate according to an embodiment of the present invention, where the method for designing a package substrate includes:

s101: determining a plurality of power supply paths, wherein the power supply device supplies power to the bare chip through the plurality of power supply paths, and one power supply path at least comprises a solder ball, a second bonding pad electrically connected with the solder ball, a via hole electrically connected with the second bonding pad and at least one wire, a via hole electrically connected with a plurality of wires in the at least one wire, a via hole electrically connected with the at least one wire and a first bonding pad, and a first bonding pad;

in the embodiment of the present invention, a power supply path between the power supply device and the die may be divided into a plurality of power supply paths according to a structure of the package substrate, where each power supply path at least includes a solder ball, a second pad electrically connected to the solder ball, a via electrically connecting the second pad and at least one wire, a via electrically connecting a plurality of wires in the at least one wire, a via electrically connecting the at least one wire and a first pad, and a first pad.

S102: and adjusting the structural parameters of at least one of the solder balls, the bonding pads, the wires and the via holes in any power supply path, so that the current flowing through the solder balls corresponding to any two power supply paths is the same in the process that the power supply device supplies power to the bare chip through the plurality of power supply circuits.

In the embodiment of the invention, the power supply path between the power supply device and the bare chip is divided into a plurality of power supply paths, and the structural parameters of at least one of the solder balls, the bonding pads, the wires and the through holes in any power supply path are adjusted, so that in the process that the power supply device supplies power to the bare chip through the plurality of power supply paths, the currents flowing through the solder balls corresponding to any two power supply paths are the same, the excessive current flowing through the packaging substrate and part of the solder balls of the chip comprising the packaging substrate is avoided, the burning of part of the solder balls due to the excessive current is avoided, and the problem of poor contact such as short circuit and the like caused by the burning of part of the solder balls is avoided.

In the embodiment of the invention, the packaging substrate can be a packaging substrate in the integrated circuit design process or a packaging substrate after tape-out, so that the structure of the packaging substrate is optimized by redesigning the tape-out packaging substrate. In some alternative examples, the package substrate is a package substrate in an integrated circuit design process, and the determining the plurality of power supply paths includes: determining structural information of the package substrate based on design information of the package substrate; the structure of the plurality of power supply paths is determined based on the structure information of the package substrate.

In some optional examples, a power supply path between the power supply device and the die may be divided into a plurality of power supply paths, for example, an area where a plurality of first pads H1 are located or an area where the die is located may be uniformly divided into a plurality of portions, each portion may include at least one first pad H1, a size of each portion after division may be determined manually, or may be determined according to a certain division policy, and then a via, a wire, a second pad H3, and a solder ball H3 that have an electrical connection relationship with the first pad H1 in each portion are determined, so that each power supply path is finally determined.

Then, the impedance of the pad, the via, the wire, and the solder ball in each power supply path may be calculated based on the structural parameters of the pad, the via, the wire, and the solder ball in the power supply path, such as the length, the width, the impedance per unit area, and the like, by using a numerical analysis method, such as a finite element method, to obtain the impedance of each power supply path. If the impedances corresponding to any two power supply paths are different in the process that the power supply device supplies power to the bare chip through the plurality of power supply paths, the structural parameters of at least one of the solder balls, the bonding pads, the wires and the through holes in any power supply path are adjusted until the impedances corresponding to any two power supply paths are the same.

And then determining whether the current passing through the solder balls corresponding to any two power supply paths is the same in the process that the power supply device supplies power to the bare chip through the plurality of power supply paths, and if the current passing through the solder balls corresponding to any two power supply paths is different, adjusting the structural parameters of at least one of the solder balls, the bonding pads, the wires and the through holes in any power supply path until the current passing through the solder balls corresponding to any two power supply paths is the same.

In some embodiments of the present invention, as shown in fig. 5, the package substrate 10 and the power supply device 30 are disposed on a printed circuit board 40, the power supply device 30 is electrically connected to the package substrate 10 through the printed circuit board 40, and the power supply device 30 is located on a side of the package substrate 10 away from the die 20, each power supply path includes a first sub-path, the first sub-path includes a solder ball, a second pad, a wire, a via, and a first pad located in the package substrate, and then adjusting a structural parameter of at least one of the solder ball, the pad, the wire, and the via in any power supply path includes:

at least one of the position of the solder ball, the area of the wire and the number of the via holes in any power supply path is adjusted so that the impedance of the first sub-path where the solder ball close to the power supply device 30 is located is greater than the impedance of the first sub-path where the solder ball far from the power supply device 30 is located.

As shown in fig. 5, each power supply path includes a first sub-path including a solder ball H3, a second pad H2, a wire D, a via G, and a first pad H1 in the package substrate 10, and a second sub-path including a pad, a wire, a via, and the like in the printed circuit board 40. Since different solder balls of the package substrate 10 have different distances to the power supply device 30, the impedance of the second sub-path close to the power supply device 30 among the different power supply paths is smaller than the impedance of the second sub-path far from the power supply device 30.

Based on this, in some embodiments of the present invention, at least one of the position of the solder ball, the area of the wire, and the number of the via hole in any one of the power supply paths is adjusted, so that the impedance of the first sub-path where the solder ball H3 close to the power supply device 30 is located is greater than the impedance of the first sub-path where the solder ball H3 away from the power supply device 30 is located, so that in a process that the power supply device 30 supplies power to the bare chip 20 through the multiple power supply paths, the impedances corresponding to any two power supply paths are the same, and/or the magnitudes of currents flowing through any two power supply paths are the same, so that the magnitudes of currents flowing through the solder balls corresponding to any two power supply paths are the same.

On the basis, in some embodiments of the present invention, adjusting the position of the solder ball in any power supply path includes: so that the density of the solder balls in the area where the first sub-path close to the power supply device is located is greater than the density of the solder balls in the area where the first sub-path far from the power supply device is located.

As shown in fig. 8, since different solder balls of the package substrate 10 have different distances from the power supply device 30, the current flowing through the area Q1 where the first sub-path close to the power supply device 30 is located is larger than the current flowing through the area Q2 where the first sub-path far from the power supply device 30 is located. Based on this, in some embodiments of the present invention, by making the density of the solder balls H3 in the area Q1 where the first sub-path close to the power supply device 30 is located greater than the density of the solder balls H3 in the area Q2 where the first sub-path far from the power supply device 30 is located, it is possible to make the currents flowing through the solder balls H3 corresponding to any two power supply paths be the same in the process that the power supply device 30 supplies power to the bare die 20 through the plurality of power supply paths.

In some embodiments of the present invention, adjusting the area of the conductive line in any of the power supply paths comprises: so that the total area of the wires in the first sub-path close to the supply means is smaller than the total area of the wires in the first sub-path far from the supply means.

In some alternative examples, the areas of the plurality of conductive layers may be sequentially increased in the direction from the second pad H2 to the first pad H1, as shown in fig. 9 or 10, the lengths of the first to sixth conductive layers L1 to L6 are sequentially increased, so that the areas of the first to sixth conductive layers L1 to L6 are sequentially increased. And, the multiple conductive layers are overlapped in the area far away from the power supply device 30, and the multiple conductive layers are partially overlapped in the area close to the power supply device 30, so that the total area of the conductive wires D in the first sub-path where the solder balls H3 close to the power supply device 30 are located is smaller than the total area of the conductive wires D in the first sub-path where the solder balls H3 close to the bare chip 20 are located.

In some embodiments of the present invention, adjusting the number of vias in any power supply path comprises: so that the number of vias in the first sub-path close to the power supply device is smaller than the number of vias in the first sub-path far from the power supply device.

As shown in fig. 12, the number of the vias G in the first sub-path where the solder ball H3 close to the power supply device 30 is located may be smaller than the number of the vias G in the first sub-path where the solder ball H3 far from the power supply device 30 is located, so as to increase the impedance of the first sub-path where the solder ball H3 close to the power supply device 30 is located by reducing the number of the vias G in the first sub-path where the solder ball H3 close to the power supply device 30 is located, so that the impedance of the first sub-path where the solder ball H3 close to the power supply device 30 is located is larger than the impedance of the first sub-path where the solder ball H3 close to the die 20 is located.

As an optional implementation of the disclosure of the present invention, an embodiment of the present invention discloses a computer device, as shown in fig. 16, fig. 16 is a schematic structural diagram of a computer device disclosed in the embodiment of the present invention, where the computer device includes:

a memory 81 for storing instructions;

the processor 82 is configured to execute the instructions stored in the memory 81 to implement the package substrate design method provided in any of the above embodiments.

In particular, the computer device may also include a bus, a communication interface 83, an input device 84, and an output device 85. The processor 82, the memory 81, the communication interface 83, the input device 84, and the output device 85 are connected to each other via a bus. Wherein:

a bus may include a path that transfers information between components of a computer system.

The processor 82 may be a general-purpose processor, such as a general-purpose Central Processing Unit (CPU), microprocessor, etc., an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of programs in accordance with the inventive arrangements. But may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components. The processor 82 may include a main processor, and may further include a baseband chip, a modem, and the like.

The memory 81 stores a program for executing the technical solution of the present invention, and may also store an operating system and other critical services. In particular, the program may include program code including computer operating instructions. More specifically, memory 81 may include a read-only memory (ROM), other types of static storage devices that may store static information and instructions, a Random Access Memory (RAM), other types of dynamic storage devices that may store information and instructions, a disk storage, a flash, and so forth.

The input device 84 may include a means for receiving user-entered data and information, such as a keyboard, mouse, camera, scanner, light pen, voice input device, touch screen, pedometer or gravity sensor, etc. Output device 85 may include a means for allowing information to be output to a user, such as a display screen, a printer, speakers, etc. Communication interface 83 may include any device that uses a transceiver or the like to communicate with other devices or communication networks, such as an ethernet network, a Radio Access Network (RAN), a Wireless Local Area Network (WLAN), etc.

As an alternative implementation of the disclosure, an embodiment of the present invention discloses a computer-readable storage medium, which is characterized by storing thereon instructions for executing the package substrate design method disclosed in any of the above embodiments.

In the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed in the embodiment corresponds to the method disclosed in the embodiment, so that the description is simple, and the relevant points can be referred to the description of the method part.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A package substrate includes a substrate main body; the substrate main body comprises a plurality of conducting layers which are arranged in a stacked mode and an insulating layer located between every two adjacent conducting layers;

the conducting layers positioned on two opposite sides of the substrate main body are respectively provided with a plurality of first bonding pads and a plurality of second bonding pads, and each second bonding pad is connected with a welding ball; the conducting layer positioned in the middle of the substrate main body comprises a plurality of leads, and the leads positioned on different conducting layers are electrically connected through a through hole penetrating through the insulating layer between the conducting layer and the conducting layer;

in the process that the power supply device supplies power to the bare chip through the plurality of power supply paths, the current flowing in the welding balls corresponding to any two power supply paths is the same in magnitude.

2. The package substrate of claim 1, wherein during the process of supplying power to the die through the plurality of power supply paths by the power supply device, impedances corresponding to any two power supply paths are the same, and/or currents flowing through any two power supply paths are the same.

3. The package substrate of claim 1, wherein the package substrate and the power supply device are disposed on a printed circuit board, the power supply device being electrically connected to the package substrate through the printed circuit board, the power supply device being located on the other side of the package substrate away from the die;

each power supply path comprises a first sub-path, and the first sub-path comprises a solder ball, a second bonding pad, a wire, a via hole and a first bonding pad which are positioned in the packaging substrate; and the impedance of the first sub-path where the solder ball close to the power supply device is positioned is greater than the impedance of the first sub-path where the solder ball far away from the power supply device is positioned.

4. The package substrate of claim 3, wherein the package substrate satisfies at least one of the following conditions:

the number of vias in the first sub-path close to the power supply device is smaller than the number of vias in the first sub-path far from the power supply device.

5. The package substrate according to claim 4, wherein areas of the plurality of conductive layers increase in order in a direction from the second pad to the first pad, and wherein the plurality of conductive layers each overlap in a region away from the power supply device and partially overlap in a region close to the power supply device.

6. A chip comprising the package substrate of any one of claims 1-5 and a die, the die being electrically connected to the first bonding pad of the package substrate.

7. An integrated circuit system comprising a printed circuit board, a power supply device, and the chip of claim 6, the chip and the power supply device being mounted on the printed circuit board, the power supply device supplying power to the chip through the printed circuit board.

8. An electronic device comprising the integrated circuit system of claim 7.

9. A design method of a package substrate is characterized in that the package substrate comprises a substrate main body, the substrate main body comprises a plurality of conducting layers arranged in a stacked mode and an insulating layer located between two adjacent conducting layers, the conducting layers located on two opposite sides of the substrate main body are respectively provided with a plurality of first bonding pads and a plurality of second bonding pads, each second bonding pad is connected with a welding ball, the first bonding pads are used for being electrically connected with a bare chip, the second bonding pads are used for being electrically connected with a power supply device, the conducting layer located in the middle of the substrate main body comprises a plurality of conducting wires, and the conducting wires located in different conducting layers are electrically connected through via holes penetrating through the insulating layer between the first bonding pads and the second bonding pads, the design method of the package substrate comprises the following steps:

and adjusting structural parameters of at least one of a solder ball, a bonding pad, a wire and a via hole in any one of the power supply paths, so that in the process that the power supply device supplies power to the bare chip through the plurality of power supply circuits, the current flowing through the solder balls corresponding to any two power supply paths is the same in magnitude.

10. The method as claimed in claim 9, wherein during the process of supplying power to the die through the plurality of power supply paths by the power supply device, impedances corresponding to any two power supply paths are the same, and/or magnitudes of currents flowing through any two power supply paths are the same.

11. The package substrate design method of claim 10, wherein the package substrate and the power supply device are disposed on a printed circuit board, the power supply device is electrically connected to the package substrate through the printed circuit board, and the power supply device is located on a side of the package substrate away from the die, each of the power supply paths includes a first sub-path, the first sub-path includes a solder ball, a second pad, a wire, a via, and a first pad located in the package substrate, and the adjusting the structural parameter of at least one of the solder ball, the second pad, the wire, and the via in any one of the power supply paths includes:

and adjusting at least one of the position of the solder ball, the area of the wire and the number of the via holes in any one power supply path, so that the impedance of the first sub-path where the solder ball close to the power supply device is positioned is greater than the impedance of the first sub-path where the solder ball far away from the power supply device is positioned.

12. The method of claim 11, wherein adjusting the position of the solder ball in any of the power supply paths comprises: the density of the solder balls in the area where the first sub-path close to the power supply device is located is larger than that of the solder balls in the area where the first sub-path far away from the power supply device is located;

adjusting the number of vias in any of the power supply paths comprises: so that the number of vias in the first sub-path close to the power supply device is smaller than the number of vias in the first sub-path far from the power supply device.

13. The method of claim 12, wherein the making the total area of the wires in the first sub-path where the solder balls near the power supply device are located smaller than the total area of the wires in the first sub-path where the solder balls near the die are located comprises:

such that the areas of the plurality of conductive layers sequentially increase in a direction from the second pad to the first pad, and such that the plurality of conductive layers each overlap in a region near the die and partially overlap in a region near the power supply device.

14. The method of claim 9, wherein the determining the plurality of power supply paths comprises:

15. A computer device comprising a memory and a processor;

the memory is to store instructions;

the processor is configured to execute the package substrate design method of any of claims 9-14 according to the instructions stored in the memory.

16. A computer-readable storage medium having stored thereon instructions for performing the package substrate design method of any of claims 9-14.