CN203310936U - Structure for testing electromigration lifetime of solder joint - Google Patents
Structure for testing electromigration lifetime of solder joint Download PDFInfo
- Publication number
- CN203310936U CN203310936U CN2013203086344U CN201320308634U CN203310936U CN 203310936 U CN203310936 U CN 203310936U CN 2013203086344 U CN2013203086344 U CN 2013203086344U CN 201320308634 U CN201320308634 U CN 201320308634U CN 203310936 U CN203310936 U CN 203310936U
- Authority
- CN
- China
- Prior art keywords
- solder joint
- connecting wiring
- wiring
- test
- wiring layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The utility model relates to a structure for testing the electromigration lifetime of a solder joint, belonging to the technical field of semiconductor packaging. The structure comprises a test substrate (100) and a test chip (200). The test substrate (100) comprises a substrate base (110), a wiring layer I (120) and a solder mask (130). The wiring layer I (120) is arranged on the substrate base (110). The solder mask (130) covers the surface of the wiring layer I (120). The test chip (200) includes a chip body (210), a wiring layer II (220), solder joints (240) and a passivation layer (230). The wiring layer II (220) is arranged on the chip body (210). The solder joints (240) are connected by the wiring layer II (220). The passivation layer (230) covers the surface of the wiring layer II (220). The test chip (200) is electrically connected with the test substrate (100) by the solder joints (240). By using the structure provided by the utility model, the current crowding effect of the solder joints and the thermomigration phenomenon of the test structure are reduced, so that the test result of the electromigration lifetime is accurate.
Description
Technical field
The utility model relates to the test structure of a kind of solder joint electromigration lifetime in Wafer-level Chip Scale Package, belongs to the semiconductor packaging field.
Background technology
To today microminiaturized, the multifunction future development, the IC packaging density constantly increases at electronic product, and the size of packaging interconnection solder joint is more and more less, and the current density that solder joint bears and solder joint working temperature sharply raise, and causes the inner ELECTROMIGRATION PHENOMENON that produces of solder joint.ELECTROMIGRATION PHENOMENON is because the high density electron stream continues to carry out with the solder joint Atom atomic migration phenomenon that inelastic collision causes.The ELECTROMIGRATION PHENOMENON solder joint that can cause interconnecting produces growth and the defects such as dissolving, grain coarsening of projection (Hillocks) and empty (Voids), interface compound, thereby cause the integrality damage of welding spot structure and the degeneration of mechanical property, so that component failure.ELECTROMIGRATION PHENOMENON has become a major challenge of electronic package reliability, is also the large obstacle that electronic product continues to advance.
Especially in recent years, restriction due to package dimension, Power Management Devices in a lot of portable type electronic products is also brought into use Wafer-level Chip Scale Package (WLCSP, Wafer Level Chip Scale Package), in the device of this large electric current, the risk of solder joint electromigration invalidation is larger.
At present in the test structure of solder joint electromigration lifetime, test chip 200 is electrically connected by solder joint and test base 100, as shown in Fig. 1, the tin commonly used due to solder joint is low-melting alloy, test chip 200 is in galvanization, there is current-crowding effect in position, corner in the inflow of solder joint electric current or outflow side, the large 2-3 order of magnitude of current density ratio average current density herein.The uneven distribution of current density will affect the accuracy of solder joint electromigration lifetime test.In addition, after test chip 200 loaded high electric current, thermal value was very large.Material difference due to the solder joint two ends, temperature conductivity and coefficient of heat transfer have very big difference, make interconnection solder joint two ends have thermograde, especially solder joint is when the aluminium wiring with thickness is generally 1 micron left and right is connected, because the resistance of aluminum conductor is larger, thermal value is large under large current condition, can cause test chip 200 to produce larger thermograde to test base.When thermograde reaches certain value, also can cause the thermophoresis effect, finally also can affect the accuracy of electromigration lifetime test.
The utility model content
From the above, the purpose of this utility model is to overcome the deficiency of the test structure of current solder joint electromigration lifetime, provides a kind of and overcome current-crowding effect in solder joint, eliminates the solder joint electromigration lifetime test structure that thermophoresis phenomenon in test structure affects electromigration lifetime test result accuracy.
The purpose of this utility model is achieved in that
A kind of test structure of solder joint electromigration lifetime, comprise test base and test chip, described test base comprises substrate matrix, wiring layer I and solder mask, described wiring layer I is arranged on the substrate matrix, described solder mask covers surface and the gap thereof of wiring layer I, and described test chip comprises chip body wiring layer II, solder joint and passivation layer, and described wiring layer II is arranged on the chip body, described passivation layer covers surface and the gap thereof of wiring layer II
Described wiring layer I comprises connecting wiring A and connecting wiring B, described connecting wiring A and connecting wiring B distribute alternately, the outer end of described connecting wiring A arranges connecting wiring A outer end pad, the inner arranges the inner pad of connecting wiring A, the outer end of described connecting wiring B arranges connecting wiring B outer end pad, the inner arranges the inner pad of connecting wiring B, the inner pad of described connecting wiring A communicates with each other
Described solder mask arranges the solder mask opening in the inner pad of connecting wiring A, the inner pad of connecting wiring B corresponding section, and described connecting wiring A outer end pad and connecting wiring B outer end pad expose solder mask,
Described solder joint comprises that a solder joint I and several evenly are arranged on its solder joint II on every side, and described solder joint is connected by the wiring layer II, and described wiring layer II is that thickness is not less than the copper wiring of 1 micron,
Described test chip is electrically connected to by solder joint with test base, and the inner pad of connecting wiring A is corresponding with the solder joint I, and the inner pad of connecting wiring B is corresponding with the solder joint II.
Further, described wiring layer I radially distributes.
Further, the inner pad of described connecting wiring B extends internally and converges at a bit, and connecting wiring A outer end pad and connecting wiring B outer end pad are positioned at take the inner pad of connecting wiring A on the circle in the center of circle.
Further, described solder mask is rounded.
Further, also comprise metal under salient point, described solder joint is connected with the wiring layer II by metal under salient point.
Further, the thickness of described wiring layer II is not less than 3 microns.
Further, the number of described solder joint II is more than 3.
In this test structure, a plurality of solder joint II are distributed on the circle centered by the solder joint I, in conjunction with thicker copper wiring layer II, current-crowding effect while having alleviated electric current process solder joint and the thermophoresis effect in test structure, thus electromigration lifetime test result more accurately can be obtained.
The beneficial effects of the utility model are:
1
,The utility model is by arranging several conducting solder joint II around a solder joint I to be tested, each solder joint II equates with the distance of solder joint I, while making test, electric current can evenly flow into solder joint to be tested from different directions, thereby weakened the crowding effect of electric current, improved the accuracy of electro-migration testing life test result.
2, between the solder joint of test chip, play the wiring layer II of interconnected effect, adopt the thicker copper of material, its resistance is very little, reduced the thermal value of test chip, reduced the thermograde between test chip and test base, thereby reduced greatly the impact of thermophoresis on test result, helped to improve the accuracy of electro-migration testing life test result.
The accompanying drawing explanation
There is the schematic diagram of current-crowding effect in Fig. 1 in the position, corner of the inflow of solder joint electric current or outflow side for existing test structure;
Fig. 2 is the schematic diagram of test base of the test structure of a kind of solder joint electromigration lifetime of the utility model;
Fig. 3 is the A-A cut-open view of the amplification of Fig. 2;
Fig. 4 is the schematic diagram after Fig. 2 removes solder mask;
Fig. 5 is the schematic diagram of test chip of the test structure of a kind of solder joint electromigration lifetime of the utility model;
Fig. 6 is the B-B cut-open view of the amplification of Fig. 5;
Wherein:
Current crowding zone I
Wiring layer I 120
Connecting wiring A121
Connecting wiring A outer end pad 121a
The inner pad 121b of connecting wiring A
Connecting wiring B122
Connecting wiring B outer end pad 122a
The inner pad 122b of connecting wiring B
Wiring layer II 220
Solder joint I 241
Solder joint II 242
Under salient point, metal 243.
Embodiment
Referring to Fig. 2 to Fig. 6, the test structure of a kind of solder joint electromigration lifetime of the utility model, comprise test base 100 and test chip 200.
Described solder mask 130 covers surface and the gap thereof of wiring layer I 120, and in the inner pad 121b of connecting wiring A, the inner pad 122b of connecting wiring B corresponding section, solder mask opening 131 is set, and in Fig. 3, solder mask 130 is rounded.Connecting wiring A outer end pad 121a and connecting wiring B outer end pad 122a expose solder mask 130, be used to connecting the external testing circuit.
For electric current when testing can evenly flow into solder joint I 241 to be tested from different directions, overcome the current-crowding effect in solder joint, the number of solder joint II 242 is more than three, in Fig. 5, with 242 signals of six solder joint II, solder joint II 242 lays respectively on the orthohexagonal summit centered by solder joint I 241.
When carrying out the test of solder joint electromigration lifetime, test chip 200 back-offs are welded on test base 100, solder joint 240 is connected with each pad by solder mask opening 131, particularly, the inner pad 121b of connecting wiring A is corresponding with solder joint I 241, and the inner pad 122b of connecting wiring B is corresponding with solder joint II 242, and connecting wiring A outer end pad 121a is connected the external testing circuit with connecting wiring B outer end pad 122a, switch on power again, carry out the reading test by solder joint electromigration lifetime testing apparatus.
Claims (7)
1. the test structure of a solder joint electromigration lifetime, comprise test base (100) and test chip (200), described test base (100) comprises substrate matrix (110), wiring layer I (120) and solder mask (130), described wiring layer I (120) is arranged on substrate matrix (110), described solder mask (130) covers surface and the gap thereof of wiring layer I (120), described test chip (200) comprises chip body (210), wiring layer II (220), solder joint (240) and passivation layer (230), described wiring layer II (220) is arranged on chip body (210), described passivation layer (230) covers surface and the gap thereof of wiring layer II (220),
It is characterized in that, described wiring layer I (120) comprises connecting wiring A(121) and connecting wiring B(122), described connecting wiring A(121) and connecting wiring B(122) distribute alternately, described connecting wiring A(121) outer end arranges connecting wiring A outer end pad (121a), the inner arranges the inner pad (121b) of connecting wiring A, described connecting wiring B(122) outer end arranges connecting wiring B outer end pad (122a), the inner arranges the inner pad (122b) of connecting wiring B, the inner pad of described connecting wiring A (121b) communicates with each other
Described solder mask (130) arranges solder mask opening (131) in the inner pad (121b) of connecting wiring A, the inner pad (122b) of connecting wiring B corresponding section, described connecting wiring A outer end pad (121a) and connecting wiring B outer end pad (122a) expose solder mask (130)
Described solder joint (240) comprises that a solder joint I (241) and several evenly are arranged on the solder joint II (242) around it, described solder joint (240) is connected by wiring layer II (220), described wiring layer II (220) is not less than the copper wiring of 1 micron for thickness
Described test chip (200) is electrically connected to by solder joint (240) with test base (100), and the inner pad of connecting wiring A (121b) is corresponding with solder joint I (241), and the inner pad of connecting wiring B (122b) is corresponding with solder joint II (242).
2. the test structure of a kind of solder joint electromigration lifetime according to claim 1, is characterized in that, described wiring layer I (120) radially distributes.
3. the test structure of a kind of solder joint electromigration lifetime according to claim 2, it is characterized in that, the inner pad of described connecting wiring B (122b) extends internally and converges at a bit, and connecting wiring A outer end pad (121a) and connecting wiring B outer end pad (122a) are positioned at take the inner pad of connecting wiring A (121b) on the circle in the center of circle.
4. the test structure of a kind of solder joint electromigration lifetime according to claim 1, is characterized in that, described solder mask (130) is rounded.
5. the test structure of a kind of solder joint electromigration lifetime according to claim 1, is characterized in that, also comprises metal under salient point (243), and described solder joint (240) is connected with wiring layer II (220) by metal under salient point (243).
6. the test structure of a kind of solder joint electromigration lifetime according to claim 1, is characterized in that, the thickness of described wiring layer II (220) is not less than 3 microns.
7. the test structure of a kind of solder joint electromigration lifetime according to claim 1, is characterized in that, the number of described solder joint II (242) is more than 3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013203086344U CN203310936U (en) | 2013-05-30 | 2013-05-30 | Structure for testing electromigration lifetime of solder joint |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013203086344U CN203310936U (en) | 2013-05-30 | 2013-05-30 | Structure for testing electromigration lifetime of solder joint |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203310936U true CN203310936U (en) | 2013-11-27 |
Family
ID=49617137
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2013203086344U Expired - Lifetime CN203310936U (en) | 2013-05-30 | 2013-05-30 | Structure for testing electromigration lifetime of solder joint |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203310936U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105606647A (en) * | 2016-03-23 | 2016-05-25 | 华南理工大学 | Device and method for detecting thermal migration performance of interconnected welding spots |
| CN114152862A (en) * | 2021-11-19 | 2022-03-08 | 北京工业大学 | Test assembly for avoiding thermal influence in electromigration process of linear welding spot and manufacturing method thereof |
-
2013
- 2013-05-30 CN CN2013203086344U patent/CN203310936U/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105606647A (en) * | 2016-03-23 | 2016-05-25 | 华南理工大学 | Device and method for detecting thermal migration performance of interconnected welding spots |
| CN105606647B (en) * | 2016-03-23 | 2018-06-22 | 华南理工大学 | A kind of apparatus and method for detecting interconnection solder joint thermal mobility energy |
| CN114152862A (en) * | 2021-11-19 | 2022-03-08 | 北京工业大学 | Test assembly for avoiding thermal influence in electromigration process of linear welding spot and manufacturing method thereof |
| CN114152862B (en) * | 2021-11-19 | 2024-01-12 | 北京工业大学 | Test assembly for avoiding thermal influence of linear welding spot electromigration process and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11193953B2 (en) | 3D chip testing through micro-C4 interface | |
| US7880310B2 (en) | Direct device attachment on dual-mode wirebond die | |
| US20110244675A1 (en) | Structure and method of forming pillar bumps with controllable shape and size | |
| TWI281840B (en) | Electrically connecting structure of circuit board and method for fabricating same | |
| CN103151337A (en) | Test probing structure | |
| US20120309118A1 (en) | Silicon wafer alignment method used in through-silicon-via interconnection | |
| CN103926430B (en) | A kind of silicon through hole keyset method of testing | |
| TW201243348A (en) | Structure for measuring bump resistance and package substrate comprising the same | |
| CN104810338A (en) | Substrate structure and method for fabricating the same | |
| CN203310936U (en) | Structure for testing electromigration lifetime of solder joint | |
| TWI474021B (en) | Wafer level package resistance monitor scheme | |
| De Vos et al. | High density 20μm pitch CuSn microbump process for high-end 3D applications | |
| US8581343B1 (en) | Electrical connectivity for circuit applications | |
| US20150155258A1 (en) | Method of fabricating a semiconductor structure having conductive bumps with a plurality of metal layers | |
| CN104576434A (en) | Method for testing through holes in silicon | |
| US20190148272A1 (en) | Electrical connectivity for circuit applications | |
| CN207800585U (en) | Chip-packaging structure | |
| CN106771405A (en) | A kind of spherical grid array integrated circuit interface adapter | |
| CN101252107B (en) | Semiconductor package structure and manufacturing method thereof | |
| CN107275306A (en) | Stacking rectifier in encapsulation | |
| TW201822322A (en) | Flip-chip package rectification/protection diode element with multiple chip stacks capable of reducing the height of diode element and extending the number of flip-chips based on voltage resistance requirements | |
| CN106981476B (en) | Semiconductor devices and forming method thereof | |
| TWI541964B (en) | Fabrication method of semiconductor substrate | |
| JP5414219B2 (en) | Insulating test method in wafer level CSP and TEG pattern used therefor | |
| CN103972218A (en) | Integrated passive device fan-out-type wafer-level packaging structure and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20131127 |
|
| CX01 | Expiry of patent term |