CN117715411A - 半导体存储器装置及其制造方法 - Google Patents

半导体存储器装置及其制造方法 Download PDF

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Publication number
CN117715411A
CN117715411A CN202310541788.6A CN202310541788A CN117715411A CN 117715411 A CN117715411 A CN 117715411A CN 202310541788 A CN202310541788 A CN 202310541788A CN 117715411 A CN117715411 A CN 117715411A
Authority
CN
China
Prior art keywords
insulating layer
bonding layer
semiconductor memory
memory device
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310541788.6A
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English (en)
Chinese (zh)
Inventor
金在泽
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
SK Hynix Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SK Hynix Inc filed Critical SK Hynix Inc
Publication of CN117715411A publication Critical patent/CN117715411A/zh
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/50Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
CN202310541788.6A 2022-09-14 2023-05-15 半导体存储器装置及其制造方法 Pending CN117715411A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020220115271A KR20240036792A (ko) 2022-09-14 2022-09-14 반도체 메모리 장치 및 이의 제조 방법
KR10-2022-0115271 2022-09-14

Publications (1)

Publication Number Publication Date
CN117715411A true CN117715411A (zh) 2024-03-15

Family

ID=90155845

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310541788.6A Pending CN117715411A (zh) 2022-09-14 2023-05-15 半导体存储器装置及其制造方法

Country Status (2)

Country Link
KR (1) KR20240036792A (ko)
CN (1) CN117715411A (ko)

Also Published As

Publication number Publication date
KR20240036792A (ko) 2024-03-21

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