CN117713821A - Input common mode level protection circuit applied to ADC lower polar plate sampling - Google Patents
Input common mode level protection circuit applied to ADC lower polar plate sampling Download PDFInfo
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- CN117713821A CN117713821A CN202311759460.8A CN202311759460A CN117713821A CN 117713821 A CN117713821 A CN 117713821A CN 202311759460 A CN202311759460 A CN 202311759460A CN 117713821 A CN117713821 A CN 117713821A
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Abstract
The invention discloses an input common mode level protection circuit applied to ADC lower polar plate sampling, which comprises three groups of switch capacitors, two comparators and corresponding logic circuits, wherein the two comparators comprise a comparator i1 and a comparator i2; the first group of switch capacitors consists of a capacitor C 1P Capacitance C 1N And a switch ss1, a switch ss2, a switch sc1, a switch sc 2; the second group of switch capacitors consists of capacitor C 2P Capacitance C 2P And switch ss3, switch ss4, switch sc3, switch sc 4; the third group of switch capacitors consists of capacitor C 3P Capacitance C 3P And switch ss5, switch ss6, switch sc5, switch sc 6. In the invention, when the set common mode level range is exceeded, the proposed circuit outputs alarm information, and inhibits subsequent ADC conversion after sampling is finished, the sampling capacitor is not turned over, so that the larger input common mode level is not conducted to the capacitorA polar plate.
Description
Technical Field
The invention relates to the technical field of ADC (analog to digital converter), in particular to an input common mode level protection circuit applied to sampling of an ADC lower polar plate.
Background
The sampling of the bottom polar plate of the DAC capacitor array is commonly applied to various ADCs due to high sampling precision, the bottom polar plate can be subjected to capacitor overturning after the sampling is finished, when the common mode level of an input signal deviates greatly from an expected level, the ADC can be caused to reduce the performance of the ADC in the subsequent conversion process, and in some applications involving high and low power supply voltages, the larger common mode voltage change can even cause the risk of device damage.
To sum up, we propose an input common mode level protection circuit applied to ADC bottom plate sampling.
Disclosure of Invention
The invention aims to provide an input common mode level protection circuit applied to ADC lower polar plate sampling, which solves the existing problems.
In order to achieve the above purpose, the present invention provides the following technical solutions:
the input common mode level protection circuit applied to ADC lower polar plate sampling comprises three groups of switch capacitors, two comparators and corresponding logic circuits, wherein the two comparators comprise a comparator i1 and a comparator i2;
the first group of switch capacitors consists of a capacitor C 1P Capacitance C 1N And a switch ss1, a switch ss2, a switch sc1, a switch sc 2;
the second group of switch capacitors consists of capacitor C 2P Capacitance C 2P And switch ss3, switch ss4, switch sc3, switch sc 4;
the third group of switch capacitors consists of capacitor C 3P Capacitance C 3P And switch ss5, switch ss6, switch sc5, switch sc 6;
the logic circuit includes a gate i3, a gate i4, and an inverter i7.
Preferably, the lower plate of the switch capacitor is connected to the reference level V refn Switch ss1 and switch ss2 are connectedInput signal V to ADC ip V (V) in The line between the switch ss1 and the switch ss2 is connected to the positive input of the comparator i1 and the comparator i 2.
Preferably, the lower plate of the switch capacitor is connected to the reference level V refn The switch ss1 and the switch ss2 are connected to the input signal V of the ADC refp V (V) refn The line between the switches ss3, ss4 is connected to the negative terminal input of the comparator i 1.
Preferably, the lower plate of the switch capacitor is connected to the reference level V refn The switch ss1 and the switch ss2 are connected to the input signal V of the ADC refp V (V) refn In which the line between the switches ss5, ss6 is connected to the negative terminal input of the comparator i 2.
Preferably, after the outputs of the two comparators i1 and i2 are respectively connected to the DFF gate i3 and the gate i4, the negative end output of the gate i3 and the positive end output of the gate i4 are connected to the nand gate i5 to output the alarm signal flg_err.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a protection circuit for changing an input common-mode voltage, wherein an ADC (analog-to-digital converter) can normally convert and obtain better performance in a set input common-mode level range; when the sampling voltage exceeds the set common mode level range, the proposed circuit outputs alarm information, and inhibits subsequent ADC conversion after sampling is finished, so that the sampling capacitor cannot be turned over, and the larger input common mode level cannot be conducted to the upper polar plate of the capacitor.
The invention protects the upper polar plate voltage of the ADC by detecting the input common mode level of the ADC and not converting when larger common mode offset occurs, no extra current is introduced into the input signal in the detection stage, and the same capacitor as the sampling capacitor is used, thus the consistency of driving can be ensured, and the detection precision of the common mode level is not high, the switch and the capacitor size in the diagram are much smaller than the sampling capacitor, and the P2 time is much wider than the single conversion time of the normal ADC, and the offset, noise and bandwidth requirements of the comparator are very low, so that the comparator can be realized by small area power consumption.
Drawings
FIG. 1 is a schematic diagram of a common mode level protection circuit according to the present invention;
fig. 2 is a schematic diagram of a conventional ADC sampling switch circuit according to the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments.
As shown in fig. 1, an input common mode level protection circuit applied to ADC bottom plate sampling includes three groups of switch capacitors, two comparators and corresponding logic circuits, wherein the two comparators include a comparator i1 and a comparator i2;
the first group of switch capacitors consists of a capacitor C 1P Capacitance C 1N And a switch ss1, a switch ss2, a switch sc1, a switch sc2, the lower plate of the switch capacitor is connected to the reference level V refn The switch ss1 and the switch ss2 are connected to the input signal V of the ADC ip V (V) in The line between switch ss1 and switch ss2 is connected to the positive inputs of comparator i1 and comparator i2;
the second group of switch capacitors consists of capacitor C 2P Capacitance C 2P And a switch ss3, a switch ss4, a switch sc3, a switch sc4, the lower plate of the switch capacitor is connected to the reference level V refn The switch ss1 and the switch ss2 are connected to the input signal V of the ADC refp V (V) refn A line between the switches ss3, ss4 is connected to the negative terminal input of the comparator i 1;
the third group of switch capacitors consists of capacitor C 3P Capacitance C 3P And a switch ss5, a switch ss6, a switch sc5, a switch sc6, the lower plate of the switch capacitor is connected to the reference level V refn The switch ss1 and the switch ss2 are connected to the input signal V of the ADC refp V (V) refn In (a), the switches ss5, the lines between the switches ss6 are connected to the ratioA negative side input of comparator i2;
the logic circuit includes a gate i3, a gate i4, and an inverter i7.
After the outputs of the two comparators i1 and i2 are respectively connected with the DFF i3/i4, the negative end output of the i3 and the positive end output of the i4 are connected to the nand gate i5 to output the alarm signal flg_err, and meanwhile, the inverter i7 and the and gate i6 are used for performing AND operation with the CK2 to generate a control clock CK2D.
The sampling capacitance portion of the ADC is substantially the same as the conventional sampling capacitance portion except that the transfer flip switch of the bottom plate is changed from CK2 to CK2D.
As shown in fig. 2, fig. 2 shows a conventional bottom plate sampling circuit, in which the bottom plate of the capacitor is connected to differential input signals VIP and VIN during sampling, the common mode level is VICM, the top plate of the capacitor is connected to a set common mode level VTM, when sampling is finished and a conversion stage starts, the bottom plate of the capacitor is connected to a common mode level VCM, the top plate of the capacitor floats to be VTP and VTN, the common mode level is VTOP, the voltage of VTOP is vtm+vcm-VICM at this time can be obtained, when the VICM deviates from a preset value, the voltage dV is directly reflected on the VTOP by-dV, resulting in a larger common mode level deviation of the VTOP, in fig. 2, the bottom plate of the capacitor is a switching timing, CK1 and CK1P are switching control signals in the sampling stage, and the high level of CK2 indicates that the ADC starts conversion.
The specific working flow is as follows:
as shown in fig. 1, in the sampling phase, the sampling capacitor of the ADC works normally in CK1 and CK1P phases, and in fig. 1, the high-level device in CK1 generates 2 clocks P1 and P2, respectively, where P1 is substantially identical to the rising edge of CK1, and the falling edge of P2 is earlier than the falling edge of CK1P, and in the P1 high-level phase: the first group of switch capacitors inputs the signal V ip 、V in Sampling to C 1P ，C 1N A capacitor; the second group of switch capacitors inputs the signal V refp V (V) refn Sampling to C 1P ，C 1N The first group of switch capacitors of the capacitors inputs the signal V refp V (V) refn Sampling to C 1P ，C 1N A capacitor; the comparator is in the reset phase at this time.
At the P2 high phase:c in the first group of switch capacitors 1P ，C 1N The capacitors are short-circuited together, C 1P ，C 1N Capacitance value is equal, thus VC P The voltage value of (2) is the input common mode level VICM of the ADC; c in the second group of switched capacitors 2P ，C 2N The capacitors are short-circuited together, C 2P Capacitance ratio C of (2) 2N Large voltage VC N1 Greater than V refp 、V refn Is denoted as VCM+VTH; c in the third group of switch capacitors 3P ，C 3N The capacitors are short-circuited together, C 3P Capacitance ratio C of (2) 3N Small voltage VC N2 Less than V refp 、V refn Is denoted as VCM-VTH; wherein C is 2P ＝C 3N ，C 2N ＝C 3P The method comprises the steps of carrying out a first treatment on the surface of the VC is realized due to the fast transfer speed of switch charges P ，VC N1 ，VC N2 The level of (2) is stable for a long time after the rising edge of P2, and the remaining time P2 is reserved for pre-amplification by the comparator.
At the falling edge of P2: the two comparators start to latch the comparison result, and the falling edge of CK1P is latched by the DFF and generates FLG_ERR signal, so that when the input common mode level of the input common mode level VICM of the ADC is in the range of [ VCM-VTH, VCM+VTH ], FLG_ERR is output as 0; when the input common mode level of the input common mode level VICM of the ADC is outside the [ VCM-VTH, vcm+vth ] range, the flg_err output is 1. The comparison result of FLG_ERR and CK2 are logically processed to generate CK2D, and CK2D is used for driving the VCM switch of the ADC sampling capacitance lower electrode plate connected to the common mode; when flg_err=0, ck2d=ck2, the sampling capacitor works normally; when flg_err=1 results in ck2d=0, the adc does not perform subsequent conversion, and therefore the sampling capacitance does not flip.
Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (5)
1. The input common mode level protection circuit applied to ADC lower polar plate sampling is characterized by comprising three groups of switch capacitors, two comparators and corresponding logic circuits, wherein the two comparators comprise a comparator i1 and a comparator i2;
the first group of switch capacitors consists of a capacitor C 1P Capacitance C 1N And a switch ss1, a switch ss2, a switch sc1, a switch sc 2;
the second group of switch capacitors consists of capacitor C 2P Capacitance C 2P And switch ss3, switch ss4, switch sc3, switch sc 4;
the third group of switch capacitors consists of capacitor C 3P Capacitance C 3P And switch ss5, switch ss6, switch sc5, switch sc 6;
the logic circuit includes a gate i3, a gate i4, and an inverter i7.
2. An input common mode level protection circuit for ADC bottom plate sampling as recited in claim 1, wherein the bottom plate of the switched capacitor is connected to a reference level V refn The switch ss1 and the switch ss2 are connected to the input signal V of the ADC ip V (V) in The line between the switch ss1 and the switch ss2 is connected to the positive input of the comparator i1 and the comparator i 2.
3. An input common mode level protection circuit for ADC bottom plate sampling as recited in claim 1, wherein the bottom plate of the switched capacitor is connected to a reference level V refn The switch ss1 and the switch ss2 are connected to the input signal V of the ADC refp V (V) refn The line between the switches ss3, ss4 is connected to the negative terminal input of the comparator i 1.
4. An input common mode level protection circuit for ADC bottom plate sampling as recited in claim 1, wherein the bottom plate of the switched capacitor is connected to a reference level V refn The switch ss1 and the switch ss2 are connected to the input signal V of the ADC refp V (V) refn In (a), switch ss5, switch sThe line between s6 is connected to the negative terminal input of comparator i 2.
5. An input common mode level protection circuit applied to ADC bottom plate sampling according to claim 1, wherein the outputs of two comparators i1, i2 are connected to DFF gate i3, gate i4, respectively, and the negative terminal output of gate i3 and the positive terminal output of gate i4 are connected to the output alarm signal flg_err of nand gate i 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311759460.8A CN117713821A (en) | 2023-12-20 | 2023-12-20 | Input common mode level protection circuit applied to ADC lower polar plate sampling |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311759460.8A CN117713821A (en) | 2023-12-20 | 2023-12-20 | Input common mode level protection circuit applied to ADC lower polar plate sampling |
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| CN117713821A true CN117713821A (en) | 2024-03-15 |
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| CN202311759460.8A Pending CN117713821A (en) | 2023-12-20 | 2023-12-20 | Input common mode level protection circuit applied to ADC lower polar plate sampling |
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