CN117712040A - Semiconductor structure and forming method thereof - Google Patents

Abstract

A semiconductor structure and a method of forming the same, comprising: providing a substrate, wherein a grid structure is formed on the substrate, active drain doping layers are formed in the substrates at two sides of the grid structure, a first dielectric layer is formed on the substrate exposed by the grid structure, and the first dielectric layer covers the side wall of the grid structure; forming a source-drain interconnection layer isolation structure penetrating through a first dielectric layer at the side part of the gate structure, wherein the source-drain interconnection layer isolation structure is positioned between adjacent source-drain doping layers along the extending direction of the gate structure and is used for isolating the adjacent source-drain doping layers; and forming a source-drain interconnection layer in the first dielectric layer at the top of the source-drain doping layer, wherein the source-drain interconnection layer is electrically connected with the source-drain doping layer, and the adjacent source-drain doping layers are isolated through a source-drain interconnection layer isolation structure. The invention firstly forms the isolation structure of the source-drain interconnection layer, can better control the position and the size of the isolation structure of the source-drain interconnection layer, and further improves the performance of the semiconductor structure.

Description

Semiconductor structure and forming method thereof

Technical Field

The present disclosure relates to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.

Background

With the rapid development of the semiconductor integrated circuit (integrated circuit, IC) industry, semiconductor technology is continually driven by moore's law towards smaller process nodes, which results in the development of integrated circuits with smaller volumes, higher circuit precision, and higher circuit complexity.

To meet the requirements of interconnect lines with reduced critical dimensions, the interconnection between devices, or between metal lines of different layers, is realized by an interconnect structure. Therefore, before performing the back-end interconnect process, a local interconnect structure of the device, for example, a source-drain interconnect layer electrically connected to the source-drain interconnect layer, that is, a zeroth metal layer (M0), is generally formed.

However, during the development of integrated circuits, the functional density (i.e., the number of interconnect structures per chip) has generally increased while the geometry (i.e., the minimum device size that can be created using process steps) has decreased, which has correspondingly increased the difficulty and complexity of achieving isolation between adjacent source-drain interconnect layers.

Disclosure of Invention

The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, which can better control the position of a source-drain interconnection layer partition so as to improve the performance of the semiconductor structure.

In order to solve the above-mentioned problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein a grid structure is formed on the substrate, source drain doping layers are formed in the substrates at two sides of the grid structure, a first dielectric layer is formed on the substrate exposed out of the grid structure, and the first dielectric layer covers the side wall of the grid structure; forming a source-drain interconnection layer isolation structure penetrating through a first dielectric layer at the side part of the gate structure, wherein the source-drain interconnection layer isolation structure is positioned between adjacent source-drain doping layers along the extending direction of the gate structure and is used for isolating the adjacent source-drain doping layers; and forming a source-drain interconnection layer in the first dielectric layer at the top of the source-drain doping layer, wherein the source-drain interconnection layer is electrically connected with the source-drain doping layer, and adjacent source-drain doping layers are isolated through the source-drain interconnection layer isolation structure.

Correspondingly, the embodiment of the invention also provides a semiconductor structure, which comprises: a substrate; a gate structure on the substrate; the source-drain doping layers are positioned in the substrates at two sides of the grid structure; the first dielectric layer is positioned on the substrate exposed by the grid structure and covers the side wall of the grid structure; the source-drain interconnection layer isolation structure penetrates through the first dielectric layer at the side part of the grid structure, is positioned between adjacent source-drain doping layers along the extending direction of the grid structure and is used for isolating the adjacent source-drain doping layers; the source-drain interconnection layer is positioned in the first dielectric layer at the top of the source-drain doping layer, the source-drain interconnection layer is electrically connected with the source-drain doping layer, and adjacent source-drain doping layers are isolated through the isolation structure of the source-drain interconnection layer.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

the embodiment of the invention provides a method for forming a semiconductor structure, which comprises the steps of forming a source-drain interconnection layer isolation structure penetrating through a first dielectric layer at the side part of a gate structure, and then forming the source-drain interconnection layer isolation structure penetrating through the first dielectric layer at the side part of the gate structure, so that when the source-drain interconnection layer is formed, adjacent source-drain interconnection layers are isolated through a source-drain interconnection layer isolation structure formed in advance, and forming a blocking layer above a region between source-drain doping layers to be isolated in an ion doping mode, and then using the blocking layer as a mask to pattern the first dielectric layer, so as to form an opening exposing the source-drain doping layer.

Drawings

Fig. 1 to 5 are schematic structural views corresponding to steps in a method for forming a semiconductor structure;

FIGS. 6 through 26 are schematic views illustrating the structure of the semiconductor device according to the present invention;

fig. 27 to 29 are schematic structural views of an embodiment of the semiconductor structure of the present invention.

Detailed Description

The performance of a semiconductor structure is still to be improved at present, and the reason why the performance of the semiconductor structure is to be improved is analyzed by combining a forming method of the semiconductor structure.

Fig. 1 to 5 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure.

Referring to fig. 1, a substrate (not shown) is provided, a gate structure (not shown) is formed on the substrate, source/drain doped layers 20 are formed in the substrate at two sides of the gate structure, a first dielectric layer 30 is formed on the substrate exposed by the gate structure, and the first dielectric layer 30 covers the gate structure.

Referring to fig. 2, a dielectric material layer 50 is formed overlying the first dielectric layer 30.

Referring to fig. 3, a part of the dielectric material layer 50 is ion doped, the ion doped dielectric material layer 50 is used as a barrier layer 60, the barrier layer 60 is located above a region between the source and drain doped layers 20 to be isolated, and an etching selection ratio is provided between the barrier layer 60 and the ion undoped dielectric material layer 50.

The location of the barrier layer 60 is the location of the isolation region of the source-drain interconnection layer (i.e., M0).

Referring to fig. 4, the dielectric material layer 50, which is not doped with ions, is removed, leaving the barrier layer 60.

With continued reference to fig. 4, after removing the dielectric material layer 50 that is not doped with ions, the first dielectric layer 30 is patterned with the barrier layer 60 as a mask, so as to form an opening 75 penetrating the first dielectric layer 30, where the opening 75 exposes the source-drain doped layer 20, and the source-drain doped layers 20 to be isolated are isolated by the remaining first dielectric layer 30.

Referring to fig. 5, a source-drain interconnection layer 40 is formed in the opening 75, and the blocking layer 60 is removed during the formation of the source-drain interconnection layer 40.

According to research, in the ion doping process, ion diffusion is easy to occur, so that the implantation dosage greatly affects the size of the blocking area of the source-drain interconnection layer (namely M0), different blocking densities also cause different blocking area deviations, and therefore the positions and the sizes of the blocking areas of the source-drain interconnection layer are difficult to control, and the performance of the semiconductor structure is affected.

In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein a grid structure is formed on the substrate, source drain doping layers are formed in the substrates at two sides of the grid structure, a first dielectric layer is formed on the substrate exposed out of the grid structure, and the first dielectric layer covers the side wall of the grid structure; forming a source-drain interconnection layer isolation structure penetrating through a first dielectric layer at the side part of the gate structure, wherein the source-drain interconnection layer isolation structure is positioned between adjacent source-drain doping layers along the extending direction of the gate structure and is used for isolating the adjacent source-drain doping layers; and forming a source-drain interconnection layer in the first dielectric layer at the top of the source-drain doping layer, wherein the source-drain interconnection layer is electrically connected with the source-drain doping layer, and adjacent source-drain doping layers are isolated through the source-drain interconnection layer isolation structure.

According to the embodiment of the invention, after the source-drain interconnection layer isolation structure penetrating through the first dielectric layer at the side part of the grid structure is formed, the source-drain interconnection layer penetrating through the first dielectric layer at the side part of the grid structure is formed, so that when the source-drain interconnection layer is formed, adjacent source-drain interconnection layers are isolated through the source-drain interconnection layer isolation structure formed in advance, a blocking layer is formed above the area between the source-drain interconnection layers to be isolated in an ion doping mode, the blocking layer is used as a mask to pattern the first dielectric layer to form an opening exposing the source-drain doping layer, and the source-drain interconnection layer isolation structure is formed in the opening and electrically connected with the source-drain doping layer.

In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.

Fig. 6 to 26 are schematic structural views corresponding to each step in an embodiment of the semiconductor forming method according to the present invention.

Referring to fig. 6 to 8, fig. 6 is a top view, fig. 7 is a cross-sectional view of fig. 6 at AA, fig. 8 is a cross-sectional view of fig. 6 at BB, a substrate (not labeled) is provided, a gate structure 120 is formed on the substrate, active drain doped layers 110 are formed in the substrate on both sides of the gate structure 120, a first dielectric layer 130 is formed on the substrate where the gate structure 120 is exposed, and the first dielectric layer 130 covers the sidewalls of the gate structure 120.

The substrate is used for providing a process platform for a subsequent process.

Referring to fig. 7, in this embodiment, the base includes a substrate 100, and the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate may be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

In this embodiment, the substrate is used to form a fin field effect transistor (FinFET), and therefore, the substrate further includes a fin 101 on the substrate 100.

In this embodiment, a shallow trench isolation structure 102 is also formed in the substrate. Specifically, the shallow trench isolation structure 102 is located on the substrate 100 exposed by the fin 101, and covers a portion of the sidewall of the fin 101.

The shallow trench isolation structure 102 is used to realize isolation between adjacent devices.

The material of the shallow trench isolation structure 102 is an insulating material. For example, the material of the shallow trench isolation structure 102 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon oxycarbonitride. As an example, the material of the shallow trench isolation structure 102 is silicon oxide.

Referring to fig. 6 and 7, in this embodiment, the gate structure 120 spans across the fin 101 and covers a portion of the top and a portion of the sidewall of the fin 101.

In this embodiment, the gate structure 120 is a device gate structure. In a specific embodiment, the device gate structure is a metal gate structure.

Specifically, the gate structure 120 includes a gate dielectric layer (not shown), and a gate electrode layer (not shown) covering the gate dielectric layer.

The gate dielectric layer is used for isolating the gate electrode layer and the channel. The gate dielectric layer material comprises HfO ₂ 、ZrO ₂ 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al ₂ O ₃ 、SiO ₂ And La (La) ₂ O ₃ One or more of the following.

The gate electrode layer is used for electrically leading out the gate structure 120. The material of the gate electrode layer includes one or more of TiN, taN, ta, ti, tiAl, W, al, tiSiN and TiAlC.

Referring to fig. 6, the sidewall of the gate structure 120 is further formed with a sidewall 125.

The sidewall 125 is used to protect the sidewall of the device gate structure. The sidewall 125 may have a single-layer structure or a stacked-layer structure, and the material of the sidewall 125 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride oxide, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall 125 is a single-layer structure, and the material of the sidewall 125 is silicon nitride.

Referring to fig. 6 and 8, the source-drain doped layer 110 is specifically located in the fin 101 at two sides of the gate structure 120.

The source-drain doped layer 110 is used as a source or drain region of the transistor being formed. Specifically, the material of the source-drain doped layer 110 may include silicon germanium doped with P-type ions including B, ga or In, and the material of the source-drain doped layer 110 may also include silicon or silicon carbide doped with N-type ions including P, as or Sb.

The first dielectric layer 130 is used to isolate adjacent devices. The material of the first dielectric layer 130 is an insulating material. In this embodiment, the material of the first dielectric layer 130 is silicon oxide. In other embodiments, the material of the first dielectric layer may be an insulating material such as silicon nitride, silicon oxynitride, or the like.

Referring to fig. 9 to 11, fig. 9 is a top view, fig. 10 is a cross-sectional view at AA of fig. 9, and fig. 11 is a cross-sectional view at BB of fig. 9, in this embodiment, the forming method further includes: forming a first stop layer 140 on top of the gate structure 120 and the first dielectric layer 130; a second dielectric layer 150 is formed on top of the first stop layer 140.

In the process of forming the isolation structure of the source-drain interconnection layer of the first dielectric layer 130 penetrating through the side portion of the gate structure 120, the second dielectric layer 150 is patterned with the top of the first stop layer 140 as an etching stop position, and a second initial opening is formed in the second dielectric layer 150.

In the process of forming the gate isolation structure penetrating the gate structure 120 later, the second dielectric layer 150 is patterned with the top of the first stop layer 140 as an etching stop position, and a first initial opening is formed in the second dielectric layer 150.

The material of the first stop layer 140 includes one or more of silicon nitride, silicon carbide, silicon carbonitride oxide, and silicon oxynitride.

In the subsequent process of performing the first planarization on the insulating material and the second dielectric layer 150, the top surface of the second dielectric layer 150 is used to define a final stop position of the first planarization, so as to improve the top surface flatness of the isolation structure of the source-drain interconnection layer and the top surface flatness of the gate isolation structure.

The material of the second dielectric layer 150 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

Specifically, the second dielectric layer 150 and the first stop layer 140 have a larger etching selectivity ratio, so that when the second dielectric layer 150 is etched, the top of the first stop layer 140 can define an etching stop position, and the first stop layer 140 can reduce the probability that the gate structure 120 and the first dielectric layer 130 are damaged during the etching process. Thus, as an example, the material of the second dielectric layer 150 is silicon oxide, and the material of the first stop layer 140 is silicon nitride.

With continued reference to fig. 9 to 11, in this embodiment, the forming method further includes: forming a second stop layer 160 on top of the second dielectric layer 150; a third dielectric layer 170 is formed on top of the second stop layer 160.

In the subsequent process of performing the first planarization on the insulating material and the second dielectric layer 150, the top of the second stop layer 160 is first used as a stop position for the planarization, so as to improve the top surface flatness of the remaining film layer after the first planarization.

After the third dielectric layer 170 is patterned, the remaining third dielectric layer 170 is used as a mask for patterning the second stop layer 160, the second dielectric layer 150, the first stop layer 140 and the first dielectric layer 130 to form a second opening, and is also used as a mask for patterning the second stop layer 160, the second dielectric layer 150, the first stop layer 140 and the gate structure 120.

It should be noted that, the second stop layer 160 and the third dielectric layer 170 are formed on top of the second dielectric layer 150, and in the process of forming the first opening and the second opening, the second dielectric layer 150 is protected by the third dielectric layer 170 and the second stop layer 160, the probability of damage of the second dielectric layer 150 is low, and the flatness of the top surface of the second dielectric layer 150 is high, so that the effect of the subsequent first planarization treatment is improved.

The material of the third dielectric layer 170 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

The material of the second stop layer 160 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, and silicon oxynitride.

Specifically, during the first planarization process, the third dielectric layer 170 and the second stop layer 160 have a larger polishing selectivity. In this embodiment, the material of the third dielectric layer 170 is silicon oxide, and the material of the second stop layer 160 is silicon nitride.

Referring to fig. 12 to 17, fig. 12 is a top view, fig. 13 is a cross-sectional view of fig. 12 at AA, fig. 14 is a cross-sectional view of fig. 12 at BB, fig. 15 is a top view, fig. 16 is a cross-sectional view of fig. 15 at AA, fig. 17 is a cross-sectional view of fig. 15 at BB, a source-drain interconnect layer isolation structure 210 is formed through the first dielectric layer 130 on the side of the gate structure 120, and the source-drain interconnect layer isolation structure 210 is located between adjacent source-drain doped layers 110 and is used for isolating adjacent source-drain doped layers 110 along the extending direction of the gate structure 120.

The source-drain interconnection layer isolation structure 210 is formed before the source-drain interconnection layer to isolate the adjacent source-drain doped layer 110 and the subsequently formed source-drain interconnection layer, so that the adjacent source-drain interconnection layers are isolated by the previously formed source-drain interconnection layer isolation structure 210 when the source-drain interconnection layer is subsequently formed.

The source-drain interconnect layer isolation structure 210 is formed first, which is advantageous for controlling the position accuracy and the dimensional accuracy of the source-drain interconnect layer isolation structure 210, thereby providing the performance of the semiconductor structure.

In addition, compared with the scheme that a blocking layer positioned above the top of a part of source-drain doped layers is formed in an ion doping mode, then a dielectric material layer and a source-drain interconnection layer between the source-drain doped layers are patterned by taking the blocking layer as a mask so as to form an opening exposing a substrate, and a source-drain interconnection layer isolation structure is formed in the opening, the embodiment forms the source-drain interconnection layer isolation structure 210 at a position needing to be isolated first, and the blocking layer is not required to be formed in an ion doping mode, so that the problem of ion diffusion is avoided, the position and the size of the source-drain interconnection layer isolation structure 210 can be better controlled, namely the position precision and the size precision of the source-drain interconnection layer isolation structure 210 are improved, and the performance of a semiconductor structure is further improved.

Referring to fig. 17, in this embodiment, the source-drain interconnection layer isolation structure 210 further penetrates through the second dielectric layer 150 and the first stop layer 140.

Referring to fig. 15 to 17 in combination, the forming method further includes: a gate isolation structure 220 is formed through the gate structure 120, the gate isolation structure 220 being used to divide the gate structure 120 along the extending direction of the gate structure 120.

The gate isolation structures 220 are used to isolate the gate structures 120 along the extending direction of the gate structures 120, so that the gate structures 120 are separated from each other.

In this embodiment, the gate structure 120 is a device gate structure, so that after the device gate structure is formed, the device gate structure is cut, which is beneficial to enlarging a process window of a process for forming the device gate structure. For example, the device gate structure is typically formed in the gate opening by first forming the device gate structure and then cutting the device gate structure, which results in a longer gate opening length, thereby facilitating improved quality of the formation of the gate dielectric layer and the gate electrode layer in the gate opening.

In this embodiment, the gate isolation structure 220 further penetrates the second dielectric layer 150 and the first stop layer 140.

In this embodiment, the drain interconnect isolation structure 210 and the gate isolation structure 220 are formed in the same step, so that the gate isolation structure 220 and the source drain interconnect isolation structure 210 can use the same photomask, which is beneficial to reducing the process cost and simplifying the process steps.

In other embodiments, the drain interconnect isolation structure and the gate isolation structure may be formed in different steps according to actual process requirements.

The respective steps of forming the source-drain interconnection layer isolation structure 210 and the gate isolation structure 220 are described in detail below with reference to the accompanying drawings.

Referring to fig. 14 and 17, in this embodiment, the step of forming the isolation structure 210 of the source-drain interconnection layer includes: forming a second opening (not shown) sequentially penetrating through the second dielectric layer 150, the first stop layer 140 and the first dielectric layer 130 at the side of the gate structure 120, where the second opening is located between adjacent source-drain doped layers 110 along the extending direction of the gate structure 120; source-drain interconnect layer isolation structures 210 are formed in the second openings.

In this embodiment, by patterning the first dielectric layer 130, the first dielectric layer 130 at the position where the source-drain doped layer 110 needs to be separated is removed, and the second opening is formed at the position where the source-drain doped layer 110 needs to be separated, which is beneficial to improving the dimensional accuracy and the position accuracy of the second opening.

Specifically, the step of forming the second opening includes: the third dielectric layer 170, the second stop layer 160, and the second dielectric layer 150 are patterned with the top of the first stop layer 140 as a stop position, and a second initial opening (not shown) exposing the first stop layer 140 is formed in the third dielectric layer 170, the second stop layer 160, and the second dielectric layer 150, and is located above a region between adjacent source and drain doped layers 110.

Referring to fig. 13 and 16, in this embodiment, the step of forming the gate isolation structure 220 includes: forming a first opening (not shown) sequentially penetrating the second dielectric layer 150, the first stop layer 140 and the gate structure 120, wherein the first opening is used for dividing the gate structure 120 along the extending direction of the gate structure; a gate isolation structure 220 is formed in the first opening.

Specifically, the step of forming the first opening includes: the third dielectric layer 170, the second stop layer 160, and the second dielectric layer 150 are patterned with the top of the first stop layer 140 as a stop position, and a first initial opening (not shown) exposing the first stop layer 140 is formed in the third dielectric layer 170, the second stop layer 160, and the second dielectric layer 150, the first initial opening being located above the top of the gate structure 120.

It should be noted that, first, the top of the first stop layer 140 is used as a stop position to form a first initial opening and a second initial opening, and the first stop layer 140 can function as an etching stop layer, so that the depth uniformity of the first initial opening and the second initial opening is improved, and the probability of damaging the gate structure 120 and the first dielectric layer 130 is reduced.

It should be further noted that, in this embodiment, the drain interconnection layer isolation structure 210 and the gate isolation structure 220 are formed in the same step, and accordingly, the first opening and the second opening are formed in the same process.

Specifically, the first initial opening and the second initial opening are formed using one or more photomasks. When the critical dimensions of the first initial opening and the second initial opening are smaller, or the distances between the first initial openings, between the second initial openings, and between the first initial openings and the second initial openings are smaller, it is advantageous to improve the limitation of the critical dimensions or the distances to the photolithography process by using a plurality of photomasks.

The first stop layer 140 is formed on top of the gate structure 120 and the first dielectric layer 130, and after the initial openings are formed in different steps by using the patterned third dielectric layer as a mask, the first stop layer 140 and the gate structure 120 at the bottom of the first initial opening and the first stop layer 140 and the first dielectric layer 130 at the bottom of the second initial opening are removed at the same time, so as to form a first opening and a second opening, and the first stop layer 140 protects the gate structure 120 and the first dielectric layer 130 in the process of forming the first opening and the second opening.

Referring to fig. 12 to 14, fig. 12 is a top view, fig. 13 is a cross-sectional view at AA of fig. 12, fig. 14 is a cross-sectional view at BB of fig. 12, in this embodiment, the step of patterning the third dielectric layer 170, the second stop layer 160, and the second dielectric layer 150 includes: a first mask structure 310 is formed on top of the third dielectric layer 170, and a first mask opening 315 is formed in the first mask structure 310, where the first mask opening 315 is located above the top of the gate structure 120 and above the region between adjacent source-drain doped layers 110, respectively.

Specifically, the first mask structure 310 includes a first planarization layer 311, a first anti-reflection layer 312, and a patterned first photolithography mask layer 313, which are stacked in sequence.

It should be noted that, since the drain interconnect isolation structure 210 and the gate isolation structure 220 are formed in the same step, the second initial opening and the first initial opening are formed in the same process. Accordingly, the first mask opening 315 is also located over the top of the gate structure 120.

With continued reference to fig. 12-14, the third dielectric layer 170, the second stop layer 160, and the second dielectric layer 150 are patterned along the first mask opening 315 using the first mask structure 310 as a mask.

Specifically, the patterned first photoresist mask layer 313 is used as a mask, and the first anti-reflection layer 312, the first planarization layer 311, the third dielectric layer 170, the second stop layer 160, and the second dielectric layer 150 at the bottom of the first mask opening 315 are removed to form a first initial opening and a second initial opening (not shown) exposing the first stop layer 140.

In this embodiment, after the first initial opening and the second initial opening are formed, the first mask structure 310 is removed. After the first initial opening and the second initial opening are formed, the first mask structure 310 is removed first, so that the influence of the thickness of the first mask structure 310 on the subsequent patterning process is avoided, that is, the aspect ratio in the subsequent patterning process is reduced, and the shape quality and the dimensional accuracy of the first opening and the second opening are improved.

Referring to fig. 17, the step of forming the second opening further includes: removing the first stop layer 140 and the first dielectric layer 130 at the bottom of the second initial opening (not shown) by using the patterned third dielectric layer 170 as a mask, so as to form a second opening (not shown) penetrating the first dielectric layer 130 at the side of the gate structure 120; referring to fig. 16, the step of forming the first opening further includes: and removing the first stop layer 140 and the gate structure 120 at the bottom of the first initial opening by using the patterned third dielectric layer 170 as a mask, so as to form a first opening penetrating through the gate structure 120.

In one embodiment, in order to improve the isolation effect of the isolation structure of the drain interconnection layer, in the step of removing the first stop layer 140 and the first dielectric layer 130 at the bottom of the second initial opening, the shallow trench isolation structure 102 and a portion of the thickness of the substrate 100 at the bottom of the second initial opening may also be removed, so that the bottom of the second opening extends into the substrate 100.

Similarly, in order to enhance the isolation effect of the gate isolation structure, in the step of removing the first stop layer 140 and the gate structure 120 at the bottom of the first initial opening, the shallow trench isolation structure 102 and a portion of the thickness of the substrate 100 at the bottom of the first initial opening may also be removed, so that the bottom of the first opening extends into the substrate 100.

Specifically, the process of removing the first stop layer 140, the gate structure 120, and the first dielectric layer 130 at the bottoms of the first and second preliminary openings includes an anisotropic dry etching process. The anisotropic dry etching process has the characteristic of better anisotropic etching, and is beneficial to improving the shape precision and the size precision of the first opening and the second opening.

In this embodiment, the first stop layer 140 and the first dielectric layer 130 are both dielectric materials, and the gate structure 120 is a metal gate structure, so parameters of the anisotropic dry etching process include: the etching gas comprises CxFy, wherein x and y are positive integers; the bias voltage is 500V-1500V; the source power is 50W-300W.

With continued reference to fig. 16, a source-drain interconnect layer isolation structure 210 is formed in the second opening. Referring to fig. 17, a gate isolation structure 220 is formed in the first opening.

In this embodiment, after the insulating material is filled in the first opening and the second opening, a first planarization process is performed on the insulating material and the second dielectric layer 150, the second dielectric layer 150 with a partial thickness or a full thickness is reserved, and the remaining insulating material in the first opening is used as the gate isolation structure 220, and the remaining insulating material in the second opening is used as the source-drain interconnection layer isolation structure 210.

Specifically, the first planarization process includes a chemical mechanical polishing process.

The chemical mechanical polishing process combines the advantages of chemical polishing and mechanical polishing, can obtain a relatively flat surface while ensuring the material removal efficiency, has the characteristics of high surface precision, good integrity, high polishing efficiency and the like, and is beneficial to obtaining good flatness on the surface of the second dielectric layer 105 after the first planarization treatment is performed on the second dielectric layer 150.

Specifically, the material of the source-drain interconnection layer isolation structure 210 is an insulating material, including one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbide, and silicon oxycarbonitride. In this embodiment, the material of the source-drain interconnection layer isolation structure 210 is silicon nitride.

The material of the gate isolation structure 220 is an insulating material including one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, and silicon oxynitride. In this embodiment, the material of the gate isolation structure 220 is silicon nitride.

The higher density of the silicon nitride is correspondingly beneficial to improving the isolation effect of the source-drain interconnection layer isolation structure 210 and the gate isolation structure 220.

Referring to fig. 18 to 26, fig. 18 is a top view, fig. 19 is a cross-sectional view of fig. 18 at AA, fig. 20 is a cross-sectional view of fig. 18 at BB, fig. 21 is a top view, fig. 22 is a cross-sectional view of fig. 21 at AA, fig. 23 is a cross-sectional view of fig. 21 at BB, fig. 24 is a top view, fig. 25 is a cross-sectional view of fig. 24 at AA, fig. 26 is a cross-sectional view of fig. 24 at BB, a source-drain interconnect layer 190 is formed in the first dielectric layer 130 on top of the source-drain interconnect layer 110, the source-drain interconnect layer 190 is electrically connected to the source-drain interconnect layer 110, and adjacent source-drain interconnect layers 110 are isolated by the source-drain interconnect layer isolation 210 structure.

The source-drain interconnection layer 190 is used for connecting with the source-drain doped layer 110, and is used for leading out the electrical property of the source-drain doped layer 110 so as to be electrically connected with the metal layer through a source-drain plug in a subsequent process. The source-drain interconnection layer can be connected with a single source-drain doping layer or a plurality of source-drain doping layers according to actual design requirements, so that the number of source-drain plugs is reduced.

In this embodiment, the material of the source-drain interconnection layer 190 includes cobalt, ruthenium and other materials with lower resistance values.

Referring to fig. 18 to 20, in this embodiment, after forming the isolation structure of the source-drain interconnection layer, the method further includes: a fourth dielectric layer 180 is formed over the second dielectric layer 150, the source drain interconnect layer isolation structure 210, and the gate isolation structure 220.

The fourth dielectric layer 180 is formed above the second dielectric layer 150, the isolation structure 210 of the source-drain interconnection layer, and the isolation structure 220 of the gate electrode, which is favorable for providing enough grinding allowance after the subsequent second planarization treatment, thereby increasing the process window of the second planarization treatment and enabling the second dielectric layer 150 to obtain good flatness.

The material of the fourth dielectric layer 180 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.

In this embodiment, the material of the fourth dielectric layer 180 is silicon oxide. The fourth dielectric layer 180 is made of the same material as the second dielectric layer 150 to improve compatibility with the second dielectric layer 150.

Referring to fig. 21 to 23, in the present embodiment, the first dielectric layer 130, the first stop layer 140, the second dielectric layer 150, and the fourth dielectric layer 180 on top of the source-drain doped layer 110 are removed, and a third opening 115 exposing the source-drain doped layer 110 is formed in the first dielectric layer 130, the first stop layer 140, the second dielectric layer 150, and the fourth dielectric layer 180, and adjacent third openings 115 are isolated by the source-drain interconnection layer isolation structure 210 along the extension direction of the gate structure 120.

Specifically, referring to fig. 18 to 20, before removing the first dielectric layer on top of the source-drain doped layer, the method further includes: a second mask structure 410 is formed above the top of the gate structure 120, the source/drain doped layer 110, the first dielectric layer 130, the first stop layer 140, the second dielectric layer 150, and the fourth dielectric layer 180, a second mask opening 415 extending along the extending direction of the gate structure 120 is formed in the second mask structure 410, the second mask opening 415 is located above the source/drain doped layer 110 on two sides of the gate structure 120, and the source/drain interconnection layer isolation structure 210 on one side of the gate structure 120 is located below the orthographic projection of the same second mask opening 415.

Since the source-drain interconnection layer isolation structures 210 are formed at the positions where the source-drain doping layers 110 need to be isolated, after the first dielectric layer 130 is patterned along the second mask openings 415, the formed third openings 115 are automatically isolated by the source-drain interconnection layer isolation structures 210, so that even if the source-drain interconnection layer isolation structures 210 on one side of the gate structures 120 are located under the orthographic projection of the same second mask openings 415, that is, the second mask openings 415 are in a strip shape, the mutual isolation of the third openings 115 can be realized, and at the same time, the process window of the photolithography process for forming the second mask openings 415 can be increased, and the process window for forming the third openings 115 can be correspondingly increased.

The first dielectric layer 130 is patterned along the second mask opening using the second mask structure 410 as a mask.

In this embodiment, the second mask structure 410 includes a second planarization layer 411, a second anti-reflection layer 412, and a second photo-etching mask layer 413 stacked in sequence, where the second planarization layer 411 covers the fourth dielectric layer 180, and a second mask opening 415 is formed in the second photo-etching mask layer 413.

Specifically, the patterned second photo-etching mask layer 413 is used as a mask, and the second anti-reflection layer 412, the second planarization layer 411, the fourth dielectric layer 180, the second dielectric layer 150, the first stop layer 140 and the first dielectric layer 130 at the bottom of the second mask opening 415 are removed to form a third opening 115 exposing the source-drain doped layer.

In this embodiment, the process of removing the first dielectric layer 140 includes an anisotropic dry etching process, and the anisotropic dry etching process has a better anisotropic etching characteristic, which is beneficial to improving the morphology precision and the dimensional precision of the third opening 115.

The etching ratio of the anisotropic dry etching process to the first dielectric layer 140 and the isolation structure 210 of the source-drain interconnection layer is greater than 5, so that the probability of damage to the isolation structure 210 of the source-drain interconnection layer is reduced in the process of forming the third opening 115, and the isolation effect of the isolation structure 210 of the source-drain interconnection layer on the adjacent source-drain interconnection layer 190 is ensured.

Referring to fig. 21 to 23, after the third opening 115 is formed, the second mask structure 410 is removed.

Referring to fig. 24 to 26, in the present embodiment, a source-drain interconnection layer 190 is formed in the third opening 115.

Specifically, a conductive material layer is filled in the third opening 115; a second planarization process is performed on the conductive material layer and the fourth dielectric layer 180 to expose the second dielectric layer 150 and to make the remaining conductive material layer and the top of the second dielectric layer 150 flush.

The second planarization treatment is performed on the conductive material layer and the fourth dielectric layer 180 to remove the fourth dielectric layer 180 and the conductive material layer higher than the top surface of the second dielectric layer 150, so that the heights of the source-drain interconnection layers 190 meet the process requirements, and the source-drain interconnection layers 190 are separated from each other.

Correspondingly, the invention further provides a semiconductor structure. Fig. 27 to 29 are schematic structural views of an embodiment of the semiconductor structure of the present invention, fig. 27 is a top view, fig. 28 is a cross-sectional view at AA of fig. 27, and fig. 29 is a cross-sectional view at BB of fig. 27.

The semiconductor structure includes: a substrate (not shown); a gate structure 520 on the substrate; the source-drain doped layer 510 is located in the substrate at two sides of the gate structure 520; a first dielectric layer (not shown) on the exposed substrate of the gate structure 520, wherein the first dielectric layer covers the sidewalls of the gate structure 520; a source-drain interconnection layer isolation structure 610 penetrating through the first dielectric layer at the side of the gate structure 520, wherein the source-drain interconnection layer isolation structure 610 is located between adjacent source-drain doped layers 510 along the extending direction of the gate structure 520 and is used for isolating the adjacent source-drain doped layers 510; the source-drain interconnection layer 590 is located in the first dielectric layer on top of the source-drain doped layer 510, the source-drain interconnection layer 590 is electrically connected to the source-drain doped layer 510, and adjacent source-drain doped layers 510 are isolated by the source-drain interconnection layer isolation structure 610.

The substrate is used for providing a process platform for a subsequent process. In this embodiment, the substrate is used to form a fin field effect transistor (FinFET). The base includes a substrate 500, the substrate 500 being a silicon substrate. In other embodiments, the material of the substrate may be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

Referring to fig. 28, in this embodiment, the substrate is used to form a fin field effect transistor (FinFET), and therefore, the substrate further includes a fin 501 on a substrate 500.

In this embodiment, the semiconductor structure further includes: shallow trench isolation structures 502 are located in the substrate. Specifically, the shallow trench isolation structure 502 is located on the substrate 500 exposed by the fin 501, and covers a portion of the sidewall of the fin 501.

The shallow trench isolation structure 502 is used to achieve isolation between adjacent devices.

The material of the shallow trench isolation structure 502 is an insulating material. For example, the material of the shallow trench isolation structure 502 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon oxycarbonitride. As an example, the material of the shallow trench isolation structure 502 is silicon oxide.

Referring to fig. 27 and 28, in this embodiment, the gate structure 520 spans across the fin 501 and covers a portion of the top and a portion of the sidewall of the fin 501.

In this embodiment, the gate structure 520 is a device gate structure. In a specific embodiment, the device gate structure is a metal gate structure.

Specifically, the gate structure 520 includes a gate dielectric layer (not shown), and a gate electrode layer (not shown) covering the gate dielectric layer.

The gate dielectric layer is used for isolating the gate electrode layer and the channel. The gate dielectric layer material comprises HfO ₂ 、ZrO ₂ 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al ₂ O ₃ 、SiO ₂ And La (La) ₂ O ₃ One or more of the following.

The gate electrode layer is used to electrically draw out the gate structure 520. The material of the gate electrode layer includes one or more of TiN, taN, ta, ti, tiAl, W, al, tiSiN and TiAlC.

With continued reference to fig. 27, the semiconductor structure further includes: side walls (not shown) are located on the side walls of the gate structure 520.

The side wall is used for protecting the side wall of the device grid structure. The side wall can be of a single-layer structure or a laminated structure, and the material of the side wall comprises one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride oxide, silicon oxynitride, boron nitride and boron carbonitride. In this embodiment, the side wall is of a single-layer structure, and the material of the side wall is silicon nitride.

Referring to fig. 27 and 29, the source-drain doped layer 510 is specifically located in the fin 501 at two sides of the gate structure 520.

The source-drain doped layer 510 is used as a source or drain region of the transistor being formed. Specifically, the material of the source-drain doped layer 510 may include silicon germanium doped with P-type ions including B, ga or In, and the material of the source-drain doped layer 510 may also include silicon or silicon carbide doped with N-type ions including P, as or Sb.

The first dielectric layer is used for isolating adjacent devices. The first dielectric layer is made of insulating materials. In this embodiment, the material of the first dielectric layer is silicon oxide. In other embodiments, the material of the first dielectric layer may be an insulating material such as silicon nitride, silicon oxynitride, or the like.

The source-drain interconnect layer isolation structure 610 is used for isolating adjacent source-drain doped layers 510 and for isolating the source-drain interconnect layer 590, so that adjacent source-drain interconnect layers 590 are isolated by the source-drain interconnect layer isolation structure 610.

Wherein the source-drain interconnection layer isolation structure 610 is independently formed in the first dielectric layer, so that it is easy to precisely control the position accuracy and the dimensional accuracy of the source-drain interconnection layer isolation structure 610, thereby improving the performance of the semiconductor structure.

The source-drain interconnect layer isolation structure 610 is made of an insulating material including one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbide, and silicon oxycarbonitride. In this embodiment, the material of the isolation structure 610 of the source-drain interconnection layer is silicon nitride, and the density of the silicon nitride is higher, which is correspondingly beneficial to improving the isolation effect of the isolation structure 610 of the source-drain interconnection layer.

In one embodiment, in order to improve the isolation effect of the source-drain interconnection layer isolation structure 610, the source-drain interconnection layer isolation structure 610 further extends through the shallow trench isolation structure 502 and the substrate 500 with a partial thickness, that is, the source-drain interconnection layer isolation structure 610 extends into the substrate 100 with a partial thickness along the normal direction of the top surface of the substrate 500.

The source-drain interconnection layer 590 is used for connecting with the source-drain doped layer 510, and is used for electrically leading out the source-drain doped layer 510 so as to be electrically connected with the metal layer through a source-drain plug in a subsequent process. The source-drain interconnection layer may be connected to a single source-drain doped layer 510 or to multiple source-drain doped layers according to actual design requirements, thereby reducing the number of source-drain plugs.

In this embodiment, the material of the source-drain interconnection layer 590 includes cobalt, ruthenium and other materials with lower resistance values.

Referring to fig. 28, in this embodiment, the structure of the semiconductor further includes: and a gate isolation structure 620 penetrating the gate structure 520, wherein the gate isolation structure 620 is used for dividing the gate structure 520 along the extending direction of the gate structure 520.

The gate isolation structures 620 are used to isolate the gate structures 520 along the extending direction of the gate structures 520, so that the gate structures 520 are separated from each other.

In one embodiment, in order to enhance the isolation effect of the gate isolation structure 620, the gate isolation structure 620 further extends through the shallow trench isolation structure 502 and the substrate 500 with a partial thickness, that is, the gate isolation structure 620 extends into the substrate 100 with a partial thickness along the normal direction of the top surface of the substrate 500.

The material of the gate isolation structure 620 is an insulating material including one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, and silicon oxynitride. In this embodiment, the material of the gate isolation structure 620 is silicon nitride.

In this embodiment, the gate isolation structure 620 and the source-drain interconnection layer isolation structure 610 are made of the same material. In the process of forming the gate isolation structure 620 and the source-drain interconnection layer isolation structure 610, the drain interconnection layer isolation structure 610 and the gate isolation structure 620 are formed in the same step, so that the gate isolation structure 620 and the source-drain interconnection layer isolation structure 610 can use the same photomask, which is beneficial to reducing the process cost and simplifying the process steps.

Referring to fig. 28 and 29, in the present embodiment, the structure of the semiconductor further includes: a first stop layer 540 on top of the gate structure 520 and the first dielectric layer (not shown); a second dielectric layer 550 is located on top of the first stop layer 540.

Accordingly, referring to fig. 28, the gate structure 520 also penetrates the second dielectric layer 550 and the first stop layer 540, and the top of the gate isolation structure 620 is level with the top of the second dielectric layer 550.

Correspondingly, referring to fig. 29, the source-drain interconnection layer isolation structure 610 further penetrates through the second dielectric layer 550 and the first stop layer 540, and the top of the source-drain interconnection layer isolation structure 610 is flush with the top of the second dielectric layer 550; the top of the source drain interconnect layer 590 is flush with the top of the second dielectric layer 550.

The top of the gate isolation structure 620, the source-drain interconnection layer isolation structure 610 and the source-drain interconnection layer 590 are all flush with the top of the second dielectric layer 550, which is beneficial to improving the surface flatness of the semiconductor structure, thereby improving the performance of the semiconductor structure.

During the formation of the semiconductor structure, the source-drain interconnection layer isolation structure 610 is formed in the second opening, and the gate isolation structure 620 is formed in the first opening, so that during the formation of the first opening and the second opening, the top of the first stop layer 140 can be used as an etching stop position to pattern the second dielectric layer 550, which is beneficial to reducing the probability of damaging the film layer at the bottom of the first stop layer 540 while ensuring that the first opening and the second opening can penetrate the second dielectric layer 550 and the first stop layer 540.

The material of the first stop layer 540 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, and silicon oxynitride.

In the process of forming the semiconductor structure, an insulating material is filled in the first opening to form a gate isolation structure 620, an insulating material is filled in the second opening to form a source-drain interconnection layer isolation structure 610, and a first planarization treatment is required to be performed on the insulating material, and the top surface of the second dielectric layer 550 is used for defining a final stop position of the first planarization treatment, so that the top surface flatness of the source-drain interconnection layer isolation structure 610 and the top surface flatness of the gate isolation structure 620 are improved.

The material of the second dielectric layer 550 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

Specifically, the second dielectric layer 550 and the first stop layer 540 have a larger etching selectivity, so that when the second dielectric layer 550 is etched, the top of the first stop layer 540 can define an etching stop position, and the first stop layer 540 can reduce the probability that the gate structure 620 and the first dielectric layer are damaged in the etching process. Thus, as an example, the material of the second dielectric layer 550 is silicon oxide, and the material of the first stop layer 540 is silicon nitride.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (27)

1. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein a grid structure is formed on the substrate, source drain doping layers are formed in the substrates at two sides of the grid structure, a first dielectric layer is formed on the substrate exposed out of the grid structure, and the first dielectric layer covers the side wall of the grid structure;

forming a source-drain interconnection layer isolation structure penetrating through a first dielectric layer at the side part of the gate structure, wherein the source-drain interconnection layer isolation structure is positioned between adjacent source-drain doping layers along the extending direction of the gate structure and is used for isolating the adjacent source-drain doping layers;

and forming a source-drain interconnection layer in the first dielectric layer at the top of the source-drain doping layer, wherein the source-drain interconnection layer is electrically connected with the source-drain doping layer, and adjacent source-drain doping layers are isolated through the source-drain interconnection layer isolation structure.

2. The method of forming a semiconductor structure of claim 1, wherein prior to forming a source-drain interconnect layer in the first dielectric layer on top of the source-drain doped layer, the method further comprises: forming a gate isolation structure penetrating through the gate structure, wherein the gate isolation structure is used for dividing the gate structure along the extending direction of the gate structure;

and forming the source-drain interconnection layer isolation structure and the grid isolation structure in the same step.

3. The method of forming a semiconductor structure of claim 1, further comprising, prior to forming the source-drain interconnect layer isolation structure: forming a first stop layer on top of the gate structure and the first dielectric layer; forming a second dielectric layer on top of the first stop layer;

in the step of forming the source-drain interconnection layer isolation structure, the source-drain interconnection layer isolation structure also penetrates through the second dielectric layer and the first stop layer;

in the step of forming the source-drain interconnection layer in the first dielectric layer on the top of the source-drain doping layer, the source-drain interconnection layer also penetrates through the second dielectric layer and the first stop layer.

4. The method of forming a semiconductor structure of claim 3, further comprising: and forming a gate isolation structure penetrating through the second dielectric layer, the first stop layer and the gate structure, wherein the gate isolation structure is used for dividing the gate structure along the extending direction of the gate structure.

5. The method of forming a semiconductor structure of claim 3, wherein forming the source-drain interconnect layer isolation structure comprises:

forming a second opening penetrating through the second dielectric layer, the first stop layer and the first dielectric layer at the side part of the gate structure in sequence, wherein the second opening is positioned between adjacent source-drain doped layers along the extending direction of the gate structure;

and forming a source-drain interconnection layer isolation structure in the second opening.

6. The method of forming a semiconductor structure of claim 5, further comprising: forming a gate isolation structure penetrating through the second dielectric layer, the first stop layer and the gate structure, wherein the gate isolation structure is used for dividing the gate structure along the extending direction of the gate structure;

the step of forming the gate isolation structure comprises the following steps: forming a first opening penetrating through the second dielectric layer, the first stop layer and the gate structure in sequence, wherein the first opening is used for dividing the gate structure along the extending direction of the gate structure; a gate isolation structure is formed in the first opening.

7. The method of claim 6, wherein the first opening and the second opening are formed in a same process, and wherein the first opening and the second opening are formed using one or more masks;

and forming a grid isolation structure in the first opening in the process of forming a source-drain interconnection layer isolation structure in the second opening.

8. The method of forming a semiconductor structure according to claim 5 or 7, wherein the step of forming a source-drain interconnect layer isolation structure in the second opening comprises: filling insulating materials in the second opening;

and carrying out first planarization treatment on the insulating material and the second dielectric layer, reserving the second dielectric layer with partial thickness or full thickness, enabling the top of the residual insulating material and the top of the second dielectric layer to be flush, and taking the residual insulating material in the second opening as a source-drain interconnection layer isolation structure.

9. The method of forming a semiconductor structure of claim 5 or 7, further comprising, prior to forming the second opening: forming a second stop layer on top of the second dielectric layer; forming a third dielectric layer on top of the second stop layer;

The step of forming the second opening includes: patterning the third dielectric layer, the second stop layer and the second dielectric layer by taking the top of the first stop layer as a stop position, and forming initial openings exposing the first stop layer in the third dielectric layer, the second stop layer and the second dielectric layer, wherein the initial openings comprise second initial openings positioned above the areas between adjacent source and drain doped layers;

and removing the first stop layer and the first dielectric layer at the bottom of the second initial opening by taking the patterned third dielectric layer as a mask, so as to form a second opening penetrating through the first dielectric layer at the side part of the gate structure.

10. The method of forming a semiconductor structure of claim 9, wherein the initial opening further comprises a first initial opening located over a top of the gate structure;

in the step of removing the first stop layer and the first dielectric layer at the bottom of the second initial opening, the first stop layer and the gate structure at the bottom of the first initial opening are also removed, and a first opening penetrating through the gate structure is formed;

the forming method further includes: a gate isolation structure is formed in the first opening.

11. The method of forming a semiconductor structure of claim 10, wherein patterning the third dielectric layer, the second stop layer, and the second dielectric layer comprises: forming a first mask structure on the top of the third dielectric layer, wherein a first mask opening is formed in the first mask structure, and the first mask opening is respectively positioned above the top of the gate structure and above the area between the adjacent source-drain doped layers;

using the first mask structure as a mask, and patterning the third dielectric layer, the second stop layer and the second dielectric layer along the first mask opening;

and removing the first mask structure.

12. The method of forming a semiconductor structure of claim 9, wherein the process of removing the first stop layer and the first dielectric layer at the bottom of the second initial opening comprises an anisotropic dry etching process.

13. The method of forming a semiconductor structure of claim 12, wherein the parameters of the anisotropic dry etching process comprise: the etching gas includes CxFy; the bias voltage is 500V-1500V; the source power is 50W-300W.

14. The method of forming a semiconductor structure of claim 1, wherein forming the source-drain interconnect layer comprises: removing the first dielectric layer at the top of the source-drain doping layer, forming a third opening exposing the source-drain doping layer in the first dielectric layer, and isolating adjacent third openings through the source-drain interconnection layer isolation structure along the extending direction of the gate structure;

And forming a source-drain interconnection layer in the third opening.

15. The method of forming a semiconductor structure of claim 14, wherein removing said first dielectric layer on top of said source drain doped layer comprises an anisotropic dry etch process.

16. The method of claim 15, wherein the anisotropic dry etching process has an etch selectivity of greater than 5 for the first dielectric layer and the source drain interconnect layer isolation structure.

17. The method of forming a semiconductor structure of claim 14, further comprising, prior to forming the source-drain interconnect layer isolation structure: forming a first stop layer on top of the gate structure and the first dielectric layer; forming a second dielectric layer on top of the first stop layer;

in the step of forming a third opening exposing the source-drain doped layer in the first dielectric layer, the third opening also penetrates through the second dielectric layer and the first stop layer;

the step of forming the source-drain interconnection layer in the third opening comprises the following steps: filling a conductive material layer in the third opening; and carrying out second planarization treatment on the conductive material layer to expose the second dielectric layer and enable the rest conductive material layer to be flush with the top of the second dielectric layer.

18. The method of forming a semiconductor structure of claim 17, further comprising, after forming the source-drain interconnect layer isolation structure, before forming the third opening: forming a fourth dielectric layer above the second dielectric layer and the isolation structure of the source-drain interconnection layer;

in the step of forming the third opening, the third opening also penetrates through the fourth dielectric layer at the top of the source-drain doped layer;

and in the step of carrying out second planarization treatment on the conductive material layer, carrying out second planarization treatment on the conductive material layer and the fourth dielectric layer.

19. The method of forming a semiconductor structure of claim 14, further comprising, prior to removing the first dielectric layer on top of the source drain doped layer: forming a second mask structure above the top of the gate structure, the source-drain doped layer and the first dielectric layer, wherein a second mask opening extending along the extending direction of the gate structure is formed in the second mask structure, the second mask opening is positioned above the source-drain doped layers on two sides of the gate structure, and the isolation structure of the source-drain interconnection layer on one side of the gate structure is positioned below the orthographic projection of the same second mask opening;

Using the second mask structure as a mask, and patterning the first dielectric layer along the second mask opening;

and removing the second mask structure.

20. The method of forming a semiconductor structure of claim 1, wherein the source-drain interconnect layer isolation structure material comprises one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbide, and silicon oxycarbonitride.

21. The method of forming a semiconductor structure of claim 1, wherein in the step of providing a substrate, the gate structure is a device gate structure.

22. A semiconductor structure, comprising:

a substrate;

a gate structure on the substrate;

the source-drain doping layers are positioned in the substrates at two sides of the grid structure;

the first dielectric layer is positioned on the substrate exposed by the grid structure and covers the side wall of the grid structure;

the source-drain interconnection layer isolation structure penetrates through the first dielectric layer at the side part of the grid structure, is positioned between adjacent source-drain doping layers along the extending direction of the grid structure and is used for isolating the adjacent source-drain doping layers;

The source-drain interconnection layer is positioned in the first dielectric layer at the top of the source-drain doping layer, the source-drain interconnection layer is electrically connected with the source-drain doping layer, and adjacent source-drain doping layers are isolated through the isolation structure of the source-drain interconnection layer.

23. The semiconductor structure of claim 22, wherein the semiconductor structure further comprises: the grid isolation structure penetrates through the grid structure and is used for dividing the grid structure along the extending direction of the grid structure;

the drain interconnection layer isolation structure and the grid isolation structure are made of the same material.

24. The semiconductor structure of claim 22, further comprising: a first stop layer located on top of the gate structure and the first dielectric layer; a second dielectric layer positioned on top of the first stop layer;

the source-drain interconnection layer isolation structure also penetrates through the second dielectric layer and the first stop layer, and the top of the source-drain interconnection layer isolation structure is flush with the top of the second dielectric layer;

the top of the source-drain interconnection layer is flush with the top of the second dielectric layer.

25. The semiconductor structure of claim 24, wherein the semiconductor structure further comprises: the grid isolation structure penetrates through the second dielectric layer, the first stop layer and the grid structure, is used for dividing the grid structure along the extending direction of the grid structure, and is flush with the top of the second dielectric layer.

26. The semiconductor structure of claim 22, wherein the material of the source-drain interconnect layer isolation structure comprises one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbide, and silicon oxycarbonitride.

27. The semiconductor structure of claim 22, wherein the gate structure is a device gate structure.