CN117711938A

CN117711938A - Isolation groove type terminal IGBT device and manufacturing method thereof

Info

Publication number: CN117711938A
Application number: CN202410161622.6A
Authority: CN
Inventors: 斯海国; 王鹏; 李翔
Original assignee: Shenzhen Tengrui Microelectronics Technology Co ltd
Current assignee: Shenzhen Tengrui Microelectronics Technology Co ltd
Priority date: 2024-02-05
Filing date: 2024-02-05
Publication date: 2024-03-15

Abstract

The invention provides an isolation groove type terminal IGBT device and a manufacturing method thereof. The manufacturing method comprises the steps of preparing a terminal voltage-resistant junction and preparing an active region. The step of preparing the termination voltage junction includes: depositing a first hard mask on a substrate of a first conductivity type; defining a plurality of etching windows by photoetching and etching, and forming a plurality of isolation grooves by groove etching; preparing a sacrificial oxide layer and removing the sacrificial oxide layer; preparing a shielding oxide layer, injecting second conductivity type ions through a plurality of isolation grooves and activating diffusion to form a terminal doping region; and filling an oxide layer in the isolation groove. The implantation depth of the second conductive type ions is ensured through the isolation groove, so that a terminal voltage-resistant junction with a deeper structure is formed, and the terminal voltage-resistant capability is improved. The diffusion length of the terminal doped region can be accurately controlled, the depth can be increased, and meanwhile, the transverse diffusion size of ions can be reduced, so that the horizontal size of the terminal voltage junction is effectively reduced, and the number of cores of wafers is increased.

Description

Isolation groove type terminal IGBT device and manufacturing method thereof

Technical Field

The invention relates to the field of semiconductor devices, in particular to an isolation groove type terminal IGBT device and a manufacturing method thereof.

Background

IGBTs (insulated gate bipolar transistors) have been developed for decades and are widely used in the field of high-power current control, especially in the field of high-voltage (> 600V) high-current control. The two most important characteristics of IGBTs are high reverse withstand voltage and low on-voltage drop, both of which lead to relatively large IGBT chip size area, high withstand voltage results in a wider termination area, lower on-voltage drop results in more conductive channels, and larger size area means higher cost. Therefore, optimizing the size of the IGBT has important significance, and it is difficult to compress the source region conductive path due to the limitation of the low on-voltage drop, but there is an optimization space for optimizing the terminal design and reducing the terminal area. In order to improve the terminal withstand voltage capability, it is necessary to increase the depth of the terminal withstand voltage junction. The depth of the traditional terminal pressure-resistant junction is formed by long-time pushing of the furnace tube after ion injection, and the diffusion of the terminal pressure-resistant structure is diffused along the transverse direction and the longitudinal direction at the same time when the furnace tube is pushed. Therefore, the depth of the terminal pressure-resistant junction is increased, and the horizontal dimension of the terminal pressure-resistant junction is increased, so that the depth of the terminal pressure-resistant junction prepared and formed in the mode is limited by the terminal dimension of a chip in the horizontal direction, the terminal pressure-resistant depth is increased, the horizontal dimension of the terminal is easily oversized, the wafer core yield is low, and the product competitiveness is lacked.

Disclosure of Invention

The invention provides an isolation groove type terminal IGBT device and a manufacturing method thereof, which can improve the terminal voltage endurance capacity and reduce the horizontal size of a terminal.

In one aspect, an embodiment of the present invention provides a method for manufacturing an isolated trench termination IGBT device, including preparing a termination voltage junction and preparing an active region; wherein the step of preparing the termination voltage junction comprises:

depositing a first hard mask on a substrate of a first conductivity type;

defining a plurality of etching windows on the first hard mask by photoetching and etching, and carrying out groove etching on the substrate through the plurality of etching windows to form a plurality of isolation grooves;

preparing a sacrificial oxide layer and removing the sacrificial oxide layer;

preparing a shielding oxide layer, injecting second conductivity type ions through a plurality of isolation grooves and activating diffusion to form a terminal doping region of the second conductivity type;

and filling an oxide layer in the isolation groove, wherein the terminal doping region and the oxide layer filled in the isolation groove form the terminal voltage-resistant junction.

And in the step of defining a plurality of etching windows by photoetching and etching on the first hard mask and carrying out groove etching on the substrate through the plurality of etching windows to form a plurality of isolation grooves, preparing all the isolation grooves through one-time photoetching and etching and one-time groove etching.

In the same terminal voltage-resistant junction, the isolation grooves are divided into a first isolation groove and a second isolation groove, the second isolation grooves are distributed on two sides of the first isolation groove, the depth of the second isolation groove is smaller than that of the first isolation groove, a first terminal doping partition is formed after ions are injected into the first isolation groove, a second terminal doping partition is formed after ions are injected into the second isolation groove, and the bottom edge of the first terminal doping partition is lower than that of the second terminal doping partition.

The step of photoetching and etching on the first hard mask to define a plurality of etching windows and carrying out groove etching on the substrate through the plurality of etching windows to form a plurality of isolation grooves comprises the following steps:

defining a first etching window by photoetching and etching on the first hard mask;

performing groove etching on the substrate through the first etching window to form a primary isolation groove;

defining a plurality of second etching windows on the first hard mask by photoetching and etching;

and carrying out groove etching on the substrate through the first etching window and the second etching window, wherein the first isolation groove is formed after the primary isolation groove is deepened, the second isolation groove is formed at the second etching window, and the groove depth of the first isolation groove is larger than that of the second isolation groove.

The first terminal voltage-resistant junction is formed by the oxide layer filled in the first isolation groove and the first terminal doping partition, the second terminal voltage-resistant junction is formed by the oxide layer filled in the second isolation groove and the second terminal doping partition, and the first terminal voltage-resistant junction and the second terminal voltage-resistant junction are respectively prepared by the method for preparing the terminal voltage-resistant junction.

On the other hand, the invention provides an isolation groove type terminal IGBT device, which comprises a substrate of a first conductive type and a terminal voltage-resistant junction, wherein a plurality of isolation grooves which are distributed at intervals are arranged on the substrate, the substrate at the isolation groove is subjected to ion implantation of a second conductive type to form a terminal doping region of the second conductive type, an oxide layer is filled in the isolation groove, and the terminal doping region and the oxide layer in the isolation groove form the terminal voltage-resistant junction.

Wherein the groove depth of all the isolation grooves is the same.

In the same terminal voltage-resistant junction, the plurality of isolation grooves are divided into a first isolation groove and a second isolation groove, the plurality of second isolation grooves are distributed on two sides of the first isolation groove, the depth of the second isolation groove is smaller than that of the first isolation groove, and the terminal doping region comprises a first terminal doping region and a second terminal doping region; the first terminal doping partition is located at the bottom of the first isolation groove, the second terminal doping partition is located at the bottom of the second isolation groove, and the bottom edge of the first terminal doping partition is lower than the bottom edge of the second terminal doping partition.

The second isolation grooves are even in number and symmetrically distributed on two sides of the first isolation groove.

Wherein, all isolation grooves in the same terminal voltage-resistant junction are distributed at equal intervals.

According to the isolation groove type terminal IGBT device and the manufacturing method thereof, the implantation depth of the second conductive type ions can be ensured through the isolation groove, so that a terminal voltage-resistant junction with a deeper structure is formed, a long-time high-temperature furnace tube pushing method by a traditional deep junction is not needed, the long-time high-temperature furnace tube pushing method is omitted, the diffusion length of a terminal doping region of the second conductive type can be accurately controlled, the depth can be increased, the transverse diffusion size of the ions can be reduced, and the horizontal size of the terminal voltage-resistant junction is effectively reduced; and reduces the occupation of the productivity of the high-temperature furnace tube. By combining the oxide layer with the terminal doping region, terminal electric field lines can be further dispersed, excessive concentration of the electric field lines between the terminal field plates is avoided, and terminal voltage endurance capacity is improved.

Drawings

Fig. 1 is a flowchart of a method of manufacturing an isolated trench termination IGBT device according to a first embodiment of the invention.

Fig. 2 is a flowchart of preparing a termination voltage junction according to a first embodiment of the present invention.

Fig. 3A to 3N are schematic flow diagrams illustrating a method for manufacturing an IGBT device with an isolated trench termination according to a first embodiment of the present invention.

Fig. 4 is a schematic structural diagram of an isolated trench termination IGBT device according to a first embodiment of the invention.

Fig. 5A to fig. 5D are schematic diagrams illustrating a manufacturing process of a termination voltage junction according to a second embodiment of the present invention.

Fig. 6A-6B are schematic diagrams illustrating a manufacturing process of a terminal voltage junction according to a third embodiment of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

In the drawings, like structural elements are denoted by like reference numerals.

Referring to fig. 1, fig. 1 is a flowchart of a method for manufacturing an isolated trench termination IGBT device according to a first embodiment of the invention. Fig. 3A to 3N are schematic flow diagrams illustrating a method for manufacturing an IGBT device with an isolated trench termination according to a first embodiment of the present invention.

The manufacturing method of the isolation trench type terminal IGBT device provided by the first embodiment of the invention comprises the following steps.

Step S100, preparing a terminal voltage-resistant junction. As shown in fig. 2, a flow chart of the preparation of the termination voltage junction according to the present invention is shown, and the steps specifically include the following sub-steps.

In step S110, a first hard mask 120 is deposited on the first conductivity type substrate 100.

In step S120, a plurality of etching windows 129 are defined by photolithography and etching on the first hard mask, and a substrate is trench etched through the plurality of etching windows 129 to form a plurality of isolation trenches 90. As shown in fig. 3A, a schematic structure is provided after forming a plurality of isolation trenches 90.

In this embodiment, all isolation trenches on the terminal voltage-resistant junction are prepared by one photolithography and etching and one trench etching, so that the trench depths of all isolation trenches are the same.

In this step, the size, number and position of the first etching window may be determined according to the size, number and position of the isolation trenches on the terminal voltage junction. Photolithography and etching on the first hard mask means spreading and exposing, etching, photoresist removing and cleaning, etc. the first hard mask.

In this embodiment, the etching windows are four. Correspondingly, the number of the isolation grooves is four. The depth of the isolation trench is 7-9um, and can be determined according to the expected size of the terminal voltage junction.

In step S130, the sacrificial oxide layer is prepared and removed. The groove can be smoothed by sacrificing the oxide layer and removing, and the burr structure on the surface of the gate region is removed.

In step S140, a shielding oxide layer is prepared, and ions of the second conductivity type are implanted through the plurality of isolation trenches and activated to diffuse so as to form the terminal doped region 91 of the second conductivity type. As shown in fig. 3B, a schematic structure is shown after the formation of the termination doped region 91.

And step S150, filling an oxide layer in the isolation groove. This step is specifically as follows.

In step S151, all the residual oxide layer and the first hard mask are removed.

In step S152, an oxide layer is deposited to fill the isolation trench with the oxide layer 92. In this embodiment, the oxide layer is LPTEOS, i.e., the isolation trench is filled with LPTEOS.

And step S153, removing the oxide layer above the upper surface of the substrate to enable the upper surface of the substrate to be flat.

In this step, the oxide layer above the upper surface of the substrate is removed by a CMP (Chemical Mechanical Polishing or Chemical Mechanical Planarization, chemical mechanical polishing) process, thereby completing the filling of the isolation trench.

As shown in fig. 3C, the structure of the terminal voltage-resistant junction 9 after the preparation is completed is schematically shown.

The oxide layer 92 filled in the isolation trench 90 and the terminal doping region 91 of the second conductive type may form a terminal voltage-resistant junction 9. In the invention, the second conductive type ions are injected into the silicon substrate along the isolation groove, so that the depth of the terminal voltage-resistant junction is mainly determined by the depth of the isolation groove, and the depth of the isolation groove can be flexibly set according to the requirement, namely, the depth of the terminal voltage-resistant junction can be flexibly set according to the requirement of voltage resistance. Compared with the traditional method that the depth of the terminal voltage-resistant junction passes through the furnace tube in a long-time pushing mode, the method can ensure the injection depth of the ions of the second conductivity type through the isolation groove, so that the terminal voltage-resistant junction with a deeper structure is formed, the traditional method that the deep junction is pushed by the high-temperature furnace tube for a long time is not needed, the long-time high-temperature furnace tube pushing is omitted, the diffusion length of the terminal doping region of the second conductivity type can be accurately controlled, the depth can be increased, the transverse diffusion size of the ions can be reduced, the horizontal size of the terminal voltage-resistant junction is effectively reduced, and the core number of wafers is increased; and reduces the occupation of the productivity of the high-temperature furnace tube. By combining the oxide layer 92 with the terminal doped region 91, the terminal electric field lines can be further dispersed, so that excessive concentration of the electric field lines between the terminal field plates is avoided, and the terminal voltage endurance is improved.

The termination voltage junction 9 is formed by the above steps.

In step S200, an active region, also called a cell region or an emitter region, is prepared. This step includes the following steps.

In step S210, a field oxide layer is prepared in the termination region. In this step, 12000 angstrom field oxide is thermally oxidized, active lithography and etching are performed, and field oxide 41 is formed on the termination region, thereby defining an Active region, as shown in fig. 3D.

In step S220, a plurality of gate trenches 105 are prepared in the active region, as follows.

Step S221, a second hard mask is deposited, and photoetching and etching are carried out on the second hard mask to define a plurality of gate etching windows.

In step S222, the substrate 100 is subjected to trench etching through the plurality of gate etching windows to form a plurality of gate trenches 105, as shown in fig. 3E.

In step S223, a sacrificial oxide layer is prepared and removed. By sacrificing the oxide layer and removing, the gate trench can be smoothed, and burrs, defects, etc. that may be generated on the surface of the gate trench 105 can be removed.

Through the above steps, a plurality of gate trenches 105 may be prepared and formed, and the second conductive type deep well region may be divided into a plurality of independent regions in the length direction by the plurality of gate trenches 105.

In step S230, as shown in fig. 3F, an oxide layer is prepared to form Gate oxides (Gate oxides) 7 on the inner surfaces of the respective Gate trenches 105. The gate oxide is formed by depositing an oxide layer, in this step, a high-quality gate oxide layer can be formed by furnace tube oxidation, and the thickness and quality of the gate oxide are important factors for determining the value of the turn-on voltage (Vth) and the reliability of HTGB (high temperature gate bias high-temperature gate bias test).

And step S240, filling polysilicon in each gate trench. This step may form a plurality of trench gates 5, the trench gates 5 comprising a companion gate and a control gate. Specifically, the following is described.

In step S241, a layer of polysilicon (Poly) is deposited. Both the termination region and the active region are covered with polysilicon such that the polysilicon fills the gate trench 105 while forming a layer of polysilicon on the oxide surface on the substrate 100.

The gate trench is formed by trench etching and the polysilicon is filled to prepare the accompanying gate and the control gate, so that the depth, the length and other dimensions of the accompanying gate and the control gate can be ensured to meet the expected requirements, each structure of the active region is more compact, the dimension of the trench gate and the interval between the trench gates are reduced, the current density is increased, the dimension of the active region is reduced, and the dimension of the whole device is further reduced. The problem of reduced short circuit capability caused by overlarge current density can be avoided by arranging the accompanying grid.

In step S242, as shown in fig. 3G, the polysilicon is subjected to photolithography and back etching. In this step, the formation of the polysilicon floating structure 30 may be prepared while removing polysilicon from the upper surface of the substrate at the gate trench.

In this embodiment, the polysilicon floating structures 30 include a plurality of terminal polysilicon field plates and gate polysilicon bias connection lines under the gate metal layer, the gate polysilicon bias connection lines being used to apply bias voltages to the gates, the terminal polysilicon field plates being floating terminal conductive structures.

Firstly, depositing an oxide layer, photoetching and etching the oxide layer, reserving the oxide layer corresponding to the terminal polysilicon field plate and the grid polysilicon field bias connection line, then etching the deposited polysilicon, and forming the terminal polysilicon field plate and the grid polysilicon bias connection line after the reserved polysilicon is etched back due to the protection effect of the oxide layer.

When the polysilicon layer is etched, polysilicon on the upper surface of the substrate at the gate groove can be removed, so that no redundant polysilicon remains at the gate groove, and the polysilicon in the gate groove is filled into the gate groove continuously to form the groove gate 5 due to thicker polysilicon in the gate groove. After the back etching of the polysilicon layer is completed, standard cleaning is performed to remove the oxide layer, so that the upper surface of the substrate of the active region is flat, as shown in fig. 3G.

Step S250, preparing a second conductive type deep well region, which is specifically as follows.

And preparing a shielding oxide layer, photoetching and etching, namely gluing, exposing, developing and photoresist removing and cleaning, and forming an injection window of the second conductive type deep well region. Ions of the second conductivity type are implanted through the implantation window and diffused to form the second conductivity type deep well region 8, as shown in fig. 3H.

Specifically, a 500 angstrom screen oxide (screen oxide) is arranged, and P-type ions are implanted and driven with ordinary energy, thereby forming a second conductivity type deep well region 8, as shown in fig. 3H. The field oxide layer is prepared by oxidation, and then P ions are injected and propelled, so that the junction depth of the second conductive deep well region can be ensured, and the damage of the injected ions to the surface of the bare silicon is avoided.

The depth of the second conductive type deep well region is 3um-5um. After the second conductivity type ions are implanted, activation advancement is performed at 1200 degrees for 3-4 hours, thereby forming the second conductivity type deep well region 8. The second conductivity type deep well region 8 is connected to a termination voltage junction 9. After P ion implantation and diffusion promotion, a second conductivity type deep well region may be formed between the plurality of gate trenches and between the gate trench and the termination trench, where the depth of the second conductivity type deep well region is smaller than the depth of the gate trench 105, so that the gate length is greater than the channel length, which is beneficial for normal device opening.

The ion concentration of the second conductive type deep well region is 1.5E13-1.5E14 ions/cm ² 。

In step S260, as shown in fig. 3I, the first conductive type emitting region 6 is prepared. The emitter region is also known as the source region. The depth of the first conductivity type emitter region 6 is less than the depth of the second conductivity type deep well region 8. The first conductivity type emitting region 6 is located between adjacent two gate trenches.

Specifically, a shielding oxide layer is prepared, the shielding oxide layer is subjected to photoetching and photoresist-carrying ion implantation of a first conductive type emission region, and after photoresist removal and cleaning, the first conductive type emission region is activated to form a first conductive type emission region 6.

In this step, the thickness of the shielding oxide layer is 200 angstroms, and the implantation window of the first conductivity type emission region is defined by photolithography, and the implantation window is located between two adjacent gate trenches, so that the first conductivity type emission region is located between two gate trenches. Ions of the first conductivity type, i.e., N-type ions, are implanted band-glue through the implantation window.

And after photoresist removal and cleaning, performing furnace tube pushing activation of the first conductive type emission area.

The ion concentration of the first conductive type emitting region is 5E15-1E16 ions/cm ² 。

In this embodiment, no first conductivity type emitter is provided between two gate trenches adjacent to the terminal voltage junction 9, so that the gate trench nearest to the terminal voltage junction 9 is formed with the accompanying gate 51, and the remaining gate trenches are formed with the control gate 52. With the gate 51, the conductive path can be reduced and the shorting capability of the device can be improved. Of course, in other embodiments, the accompanying gate 51 may not be provided, i.e. the trench gate includes only the control gate 52, and the first conductivity type emitter is provided between two adjacent gate trenches, so that the control gate 52 is formed in all gate trenches. The control gate may control the turning off and on of the device.

In step S270, as shown in fig. 3J, the intermediate insulating layer 40 (Inter Layer Dielectric, ILD for short) is deposited and cured (reflow). The intermediate insulating layer uses an insulating medium, typically LPTEOS (Low Pressure Tetraethyl Orthosilicate, low pressure deposited tetraethoxysilane) or BPSG (Boro-phospho-silicate Glass), as isolation between the emitter and the control gate.

Preferably, the thickness of the intermediate insulating layer 40 is 20000 angstroms.

In step S280, a plurality of contact holes 10 are prepared, and the plurality of contact holes 10 are divided into an emitter contact hole, a gate contact hole and a terminal contact hole by location. The grid contact hole is a contact hole corresponding to the grid metal layer, the terminal contact hole is a contact hole corresponding to the terminal metal layer, and the emitter contact hole is a contact hole corresponding to the emitter metal layer. The emitter contact hole penetrates through the middle of the first conductive type emitter region and extends downwards into the second conductive type deep well region; and implanting ions of the second conductivity type into the emitter contact hole and activating the ions to form a second conductivity type heavily doped region. The method comprises the following steps.

In step S281, the first contact hole is etched.

In this step, the intermediate insulating layer at the contact hole 10 is removed by photolithography and etching, thereby exposing the polysilicon field plate and the first conductive type emitter region at the contact hole region.

In this step, photolithography and etching are performed according to the positions of the contact holes 10, such as the emitter contact hole, the gate contact hole, and the terminal contact hole, to remove the intermediate insulating layer at the positions of the contact holes 10, and to expose the silicon at the contact hole regions. Wherein the emitter contact hole is located in the middle of the first conductivity type emitter region, and the gate contact hole and the terminal contact hole are located at the corresponding polysilicon field plate, as shown in fig. 3K. Here, dry etching can be used, and accuracy is high.

In step S284, silicon etching is performed to form a silicon recess (silicon recess) on the substrate 100 at the contact hole region, as shown in fig. 3L. The silicon recess depth is 4000 angstroms. The depth of the silicon recess is greater than the depth of the first conductivity type emitting region, and the silicon recess is the bottommost end of the contact hole so that the emitter contact hole penetrates the middle of the first conductivity type emitting region to form two first conductivity type emitting regions 6 between the two control gates 52. The depth of the silicon groove is smaller than that of the second conductive type deep well region, so that the lower end of the emitter contact hole extends into the second conductive type deep well region, and the second conductive type heavily doped region is located in the second conductive type deep well region.

In step S285, ions of the second conductivity type are implanted and activated to form a second conductivity type heavily doped region 11 at the bottom of the silicon recess, as shown in fig. 3M.

The emitter contact hole can be prepared and completed through multiple contact hole photoetching, full polishing of silicon nitride and silicon etching, second conductivity type ions can be injected into the bottom of the silicon groove, and the second conductivity type heavily doped region 11 is formed after activation.

In this step, the normal energy injection of the PPLUS (P-type ion doping) and the rapid thermal annealing (RTA for short, rapid Thermal Annealing) are activated in situ, specifically, the RTA at 950 ℃ is used.

Through the above steps, the preparation of the second conductivity type deep well region 8, the gate oxide 7, the first conductivity type emission region 6, and the second conductivity type heavily doped region 11 at the active region can be completed.

Step S300, preparing a metal layer. As shown in fig. 3N, the metal layers include a terminal metal layer 3, a gate metal layer 2, and an emitter metal layer 1. The method specifically comprises the following steps.

Step S310, cleaning process. In this step, a hydrogen fluoride cleaning treatment (HF dip) may be used.

In step S320, a thin film of a composite structure of titanium and titanium nitride is deposited to release the stress of tungsten and to block the diffusion of tungsten, since this thin film is finally left at the bottom of the contact and forms a low-resistance metal silicide.

In step S330, rapid thermal annealing (RTA, rapid Thermal Annealing for short). In this step, RTA at 650℃is used.

Step S340, tungsten (W) deposition and etch back (etch back). Tungsten compounds in gaseous form are easy to control in the reaction and have good hole filling capability, while tungsten has very electromigration resistance and very low resistivity, so the use of tungsten (W) as an inter-layer interconnect metal is becoming more and more widespread. Tungsten is deposited on the surface of the whole device, and the contact hole is formed at the second conductive type heavily doped region, so that the tungsten in the contact hole is thicker, and after the tungsten on the surface of the device is removed by back etching, the tungsten can remain at the second conductive type heavily doped region, thereby realizing better conductivity.

In step S350, a metal layer is deposited. The metal layer is AlCu metal layer to raise electromigration resistance. The thickness of the metal layer is preferably 4um. And photoetching and etching the metal layer to remove redundant metal materials.

In step S360, a passivation layer is deposited, etched, and lithographically etched.

Step S370, annealing. In this step, specifically, annealing is performed by a furnace tube at 400 ℃.

In step S400, a collector is fabricated on the back surface of the substrate 100, as shown in fig. 4. The method specifically comprises the following substeps.

Step S410 performs film lamination on the back surface of the substrate 100.

In step S420, the substrate 100 is thinned to 65um. In this step, the Taiko thinning process may be used for thinning. The Taiko thinning process is an ultrathin thinning process, which does not thin the entire plane of a wafer, i.e., a silicon wafer, but only the middle portion of the wafer, and the edge portion of the wafer having a width of about 2 to 5mm is not thinned, and the edge portion forms a support ring.

In step S430, ions of the first conductivity type, i.e., N-type ion buffer implantation (buffer implant), are implanted to form the heavily doped buffer layer 14 of the first conductivity type.

In step S440, hydrogen high energy ion implantation and boron (boron) backside low energy implantation.

In step S450, the collector 15 of the second conductivity type is formed by laser annealing and backside emitter metal deposition.

The manufacture of the trench type terminal IGBT device can be completed through the steps.

The present invention also provides a second embodiment of a method for manufacturing an isolated trench termination IGBT device, which is a further improvement over the first embodiment described above, except for step S120. In the first embodiment, all isolation grooves on the terminal voltage-resistant junction are prepared through one-time photoetching and etching and one-time groove etching. In this second embodiment, the isolation trench is prepared by two times of photolithography and etching, and two times of trench etching, as follows.

The plurality of etching windows are divided into a first etching window 121 and a plurality of second etching windows 122, and the plurality of second etching windows 122 are distributed at both sides of the first etching window 121. Accordingly, in the same terminal voltage junction, the plurality of isolation trenches are divided into a first isolation trench 901 and a second isolation trench 902, and the second isolation trench 902 is a plurality and is distributed on both sides of the first isolation trench 901.

Step S120 includes the following steps.

In step S121, a first etching window 121 is defined by photolithography and etching on the first hard mask 120.

In step S122, the substrate 100 is subjected to a trench etching through the first etching window 121 to form the preliminary isolation trench 900. As shown in fig. 5A, a schematic structure is provided after the primary isolation trench 900 is formed.

In step S123, a plurality of second etching windows 122 are defined on the first hard mask 120 by photolithography and etching. As shown in fig. 5B, a plurality of second etching windows 122 are distributed on both sides of the first etching window 121.

In step S124, the substrate is etched through the first etching window 121 and the second etching window 122, the first isolation trench 901 is formed after the primary isolation trench is deepened, and the second isolation trench 902 is formed at the second etching window 122, as shown in fig. 5C. The number and positions of the second isolation grooves etched through the second etching windows are consistent with those of the second etching windows, that is, the second isolation grooves 902 are also multiple and distributed on two sides of the first isolation groove 901.

Since the first etching window 121 is subjected to the groove etching twice, the groove depth of the first isolation groove 901 is greater than the groove depth of the second isolation groove 902. The first isolation trenches are located among the plurality of second isolation trenches, after the second conductive ions are implanted and diffused, as shown in fig. 5D, a first terminal doping partition 911 is formed after ions are implanted through the first isolation trenches 901, a second terminal doping partition 912 is formed after ions are implanted through the second isolation trenches 902, and the bottom edge of the first terminal doping partition 911 is lower than the bottom edge of the second terminal doping partition 912, so that the first terminal doping partition 911 located in the middle is deeper, and the deeper middle is utilized to be beneficial to dispersing field intensity; the depth of the second terminal doping region 912 at the second isolation trench 902 is smaller, so that the terminal doping region 91 has a graded structure that gradually deepens from two sides to the middle, and the terminal voltage endurance capability is further improved.

The invention also provides a third embodiment of the manufacturing method of the isolation trench type terminal IGBT device, which has the same structure as the isolation trench type terminal IGBT device manufactured by the second embodiment, and is different in the manufacturing process of the terminal voltage-resistant junction.

As shown in fig. 6A and 6B, in this embodiment, the oxide layer 931 filled in the first isolation trench 901 and the first terminal doped region 911 formed by ion implantation through the first isolation trench together form a first sub-terminal voltage-resistant junction 991, the oxide layer 932 filled in the second isolation trench 902 and the second terminal doped region 912 formed by ion implantation through the second isolation trench 902 form a second sub-terminal voltage-resistant junction 992, and the first sub-terminal voltage-resistant junction 991 and the second sub-terminal voltage-resistant junction 992 are respectively prepared by the preparation method of the terminal voltage-resistant junction in step S100 in the first embodiment.

More specifically, first, as shown in fig. 6A, a first sub-termination voltage-resistant junction 991 is fabricated by the fabrication method of step S100, that is, a hard mask is sequentially deposited, photolithography and etching define etching windows, first isolation trenches 901 are formed by trench etching, first terminal doping regions 911 are formed by ion implantation into the first isolation trenches 901, and an oxide layer 931 is filled into the first isolation trenches 901, thereby fabricating the first sub-termination voltage-resistant junction 991. Then, as shown in fig. 6B, the second sub-termination voltage-resistant junction 992 is fabricated by the fabrication method of step S100, that is, the etching windows are defined by sequentially depositing a hard mask, photolithography, and etching, the second isolation trenches 902 are formed by trench etching, the second terminal doping regions 912 are formed by ion implantation into the second isolation trenches 902, and the oxide layer 932 is filled into the second isolation trenches 902, thereby fabricating the second sub-termination voltage-resistant junction 992. The isolation grooves with different depths and the terminal doping subareas are formed by the preparation method, so that the terminal voltage-resistant junction has a graded structure, and the terminal voltage-resistant capability is improved. Here, the preparation order of the first sub-terminal voltage-resistant junction and the second sub-terminal voltage-resistant junction may be different from each other, or the second sub-terminal voltage-resistant junction may be prepared first, and then the first sub-terminal voltage-resistant junction may be prepared.

The invention also provides a first embodiment of the isolation trench type terminal IGBT device, which is manufactured by the first embodiment of the manufacturing method of the isolation trench type terminal IGBT device. As shown in fig. 3C and fig. 4, the isolated trench type termination IGBT device includes a substrate 100, a plurality of isolated trenches 90 arranged at intervals are provided on the substrate 100, the substrate at the isolated trench is implanted with ions of the second conductivity type to form a termination doped region 91 of the second conductivity type, an oxide layer 92 is filled in the isolated trench 90, and the termination doped region and the oxide layer 92 in the isolated trench form a termination voltage-resistant junction 9.

The plurality of isolation trenches 90 are arranged at equal intervals so that the implantation concentration of the second conductive type ions is more uniform in the region between the isolation trenches 90.

In this embodiment, the groove depths of all the isolation grooves 90 are the same, so that a plurality of isolation grooves can be simultaneously manufactured by one etching, which is convenient for manufacturing and reduces the manufacturing cost.

The present invention also provides a second embodiment of an isolated trench termination IGBT device that may be manufactured from the second embodiment or the third embodiment of the method of manufacturing an isolated trench termination IGBT device described above. The difference between the present embodiment and the first embodiment is that the depths of the plurality of isolation trenches are not identical, and other structures are identical to those of the first embodiment, and will not be described here again.

In this embodiment, as shown in fig. 5D, in the same terminal voltage-resistant junction, the plurality of isolation trenches includes a first isolation trench 901 and a second isolation trench 902, the second isolation trench 902 is plural and distributed on two sides of the first isolation trench 901, the depth of the second isolation trench 902 is smaller than the depth of the first isolation trench 901, and the terminal doping region 91 includes a first terminal doping region 911 and a second terminal doping region 912; the first terminal doping region 911 is located at the bottom of the first isolation trench 901, the second terminal doping region 912 is located at the bottom of the second isolation trench 902, and the bottom side of the first terminal doping region 911 is lower than the bottom side of the second terminal doping region 912. The structure enables the bottom of the terminal pressure-resistant junction to be of a gradual change structure which gradually deepens from two sides to the middle, and the terminal pressure-resistant capability is further improved.

The first isolation trenches 901 and the second isolation trenches 902 are arranged at equal intervals, so that the implantation concentration of the second conductive type ions in the region between the isolation trenches is more uniform. Here, it can be seen from the two embodiments that all the isolation trenches in the same termination voltage junction are preferably arranged at equal intervals.

The number of the second isolation grooves is even, and the second isolation grooves are symmetrically distributed on two sides of the first isolation groove, so that the terminal voltage-resistant junction is of a two-side symmetrical slow-changing structure, and the terminal voltage-resistant capability is improved.

In this embodiment, the number of the first isolation grooves is two, the number of the second isolation grooves is also two, and a gradual change structure can be realized by using a smaller number of isolation grooves, which is beneficial to manufacturing, and the length dimension of the terminal voltage-resistant junction can be reduced.

In summary, although the present invention has been described in terms of the preferred embodiments, the above-mentioned embodiments are not intended to limit the invention, and those skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention, so that the scope of the invention is defined by the appended claims.

Claims

1. The manufacturing method of the isolation groove type terminal IGBT device is characterized by comprising the steps of preparing a terminal voltage-resistant junction and preparing an active region; wherein the step of preparing the termination voltage junction comprises:

depositing a first hard mask on a substrate of a first conductivity type;

preparing a sacrificial oxide layer and removing the sacrificial oxide layer;

2. The method of manufacturing an isolated trench termination IGBT device of claim 1 wherein in the step of defining a plurality of etch windows on the first hard mask by photolithography and etching, and trench etching the substrate through the plurality of etch windows to form a plurality of isolated trenches, all isolated trenches are prepared by one photolithography and etching, one trench etching.

3. The method for manufacturing the Insulated Gate Bipolar Transistor (IGBT) device of claim 1, wherein in the same terminal voltage junction, the plurality of insulated trenches are divided into a first insulated trench and a second insulated trench, the plurality of second insulated trenches are distributed on both sides of the first insulated trench, the depth of the second insulated trench is smaller than the depth of the first insulated trench, a first terminal doping region is formed after ion implantation through the first insulated trench, a second terminal doping region is formed after ion implantation through the second insulated trench, and the bottom edge of the first terminal doping region is lower than the bottom edge of the second terminal doping region.

4. The method of manufacturing an isolated trench termination IGBT device of claim 3 wherein the plurality of etch windows are divided into a first etch window and a second etch window, the steps of lithographically and etching the first hard mask to define a plurality of etch windows, and trench etching the substrate through the plurality of etch windows to form a plurality of isolated trenches comprising:

5. The method for manufacturing an IGBT device according to claim 3, wherein the oxide layer filled in the first isolation trench and the first terminal doping region form a first sub-terminal voltage-resistant junction, the oxide layer filled in the second isolation trench and the second terminal doping region form a second sub-terminal voltage-resistant junction, and the first sub-terminal voltage-resistant junction and the second sub-terminal voltage-resistant junction are respectively manufactured by the method for manufacturing the terminal voltage-resistant junction.

6. The isolation groove type terminal IGBT device is characterized by comprising a substrate of a first conductivity type and a terminal voltage-resistant junction, wherein a plurality of isolation grooves which are distributed at intervals are formed in the substrate, the substrate at the isolation groove is subjected to second conductivity type ion implantation to form a terminal doping region of a second conductivity type, an oxide layer is filled in the isolation groove, and the terminal doping region and the oxide layer in the isolation groove form the terminal voltage-resistant junction.

7. The isolated trench termination IGBT device of claim 6 wherein the trench depth of all of the isolation trenches is the same.

8. The isolated trench termination IGBT device of claim 6 wherein in the same termination voltage junction, the plurality of isolated trenches are divided into a first isolated trench and a second isolated trench, the second isolated trench being a plurality of and being distributed on both sides of the first isolated trench, the second isolated trench having a depth less than a depth of the first isolated trench, the termination doping region comprising a first termination doping region and a second termination doping region; the first terminal doping partition is located at the bottom of the first isolation groove, the second terminal doping partition is located at the bottom of the second isolation groove, and the bottom edge of the first terminal doping partition is lower than the bottom edge of the second terminal doping partition.

9. The isolated trench termination IGBT device of claim 8 wherein the second isolation trenches are an even number and are symmetrically distributed on both sides of the first isolation trench.

10. The isolated trench termination IGBT device of any of claims 6 to 9 wherein all isolation trenches in the same termination voltage junction are equally spaced.