CN117707620A

CN117707620A - Control method for system-on-chip and system-on-chip

Info

Publication number: CN117707620A
Application number: CN202311595106.6A
Authority: CN
Inventors: 林敏�; 董宇; 黄金煌
Original assignee: Beijing Unigroup Tsingteng Microsystems Co Ltd
Current assignee: Beijing Unigroup Tsingteng Microsystems Co Ltd
Priority date: 2023-11-27
Filing date: 2023-11-27
Publication date: 2024-03-15

Abstract

The invention relates to the technical field of chip security, and discloses a control method for a system-in-chip and the system-in-chip, wherein the control method comprises the following steps: determining whether a function in a target program to be executed currently is a changed function; reading original data from a first memory according to an original data address of the function when the function is not the changed function, and executing the function based on the original data; when the function is a modified function, determining a patch configuration corresponding to the function, and determining all patch data addresses of the function based on the patch configuration; the patch data is read from the second memory according to the patch data address, and a function is executed based on the patch data. The patch configuration setting mode reduces the number of patch configurations required by one function, and can meet the function change requirements of more programs by only occupying fewer resources of a chip.

Description

Control method for system-on-chip and system-on-chip

Technical Field

The present disclosure relates to the technical field of chip security, for example, to a control method for a system-in-chip, and a system-in-chip.

Background

A System on a Chip (SOC), also known as a Chip on a Chip, is an integrated circuit with a dedicated target. A system-on-chip will typically include a processor and a Read-Only Memory (ROM) that holds data for functions of the program.

The data stored in the rom cannot be modified, so the system-on-chip may further include a memory supporting reading and writing, and when a function in the program needs to be changed, new data after the change is stored in the memory supporting reading and writing. Executing the function by reading data from the read-only memory for the unaltered function when the processor is running the program; for the modified function, the function is executed by reading new data from the memory supporting the reading and writing.

In the related art, in order for a processor to accurately read new data of a modified function, a Patch (Patch) configuration is required for original data and new data of the modified function, and address mapping between data can be performed by the Patch configuration. However, one function typically has a plurality of data, and the related art needs to set patch configurations for respective data of the same function, which requires the use of a large number of patch configurations. Thus, if the number of patch configurations is limited, the number of functions allowed to be changed in the program is also limited; if a larger number of patch configurations are allowed, this in turn results in the patch configurations taking up excessive resources. The related art sets the patch configuration mode, and can not meet the function change requirement of more programs under the condition of occupying less resources of the chip.

It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview, and is intended to neither identify key/critical elements nor delineate the scope of such embodiments, but is intended as a prelude to the more detailed description that follows.

The embodiment of the disclosure provides a control method for a system-in-chip and the system-in-chip, and the method for setting patch configuration can meet the function change requirement of more programs by only occupying fewer resources of the chip.

According to a first aspect of the present disclosure, there is provided a control method for a system-on-chip, comprising:

determining whether a function in a target program to be executed currently is a changed function;

reading original data from a first memory according to an original data address of the function when the function is not the changed function, and executing the function based on the original data;

when the function is a modified function, determining a patch configuration corresponding to the function, and determining all patch data addresses of the function based on the patch configuration;

The patch data is read from the second memory according to the patch data address, and a function is executed based on the patch data.

In some embodiments, determining whether the function in the target program currently to be executed is a modified function includes: and sending a data request of the original data address of the function in the target program to be executed currently to the bus arbitration module, so that the bus arbitration module determines whether the function is a changed function or not based on the original data address and a first register, wherein the first register is used for storing the original data address of each changed function.

In some embodiments, the bus arbitration module is to determine whether the function is a modified function based on a first original data address of the first function and a first register to store the first original data address of each modified function.

In some embodiments, determining a patch configuration corresponding to the function, and determining all patch data addresses of the function based on the patch configuration includes: reading a jump program in the second memory; and determining one patch configuration corresponding to the function by executing the jump procedure, and determining all patch data addresses of the function based on the patch configuration.

In some embodiments, reading the jump program in the second memory includes: reading a target address stored in a second register, wherein the target address is an address of a jump program stored in a second memory; and reading the jump program from the second memory according to the target address.

In some embodiments, before determining a patch configuration corresponding to the function by executing the jump procedure, and determining all patch data addresses of the function based on the patch configuration, the method includes: jumping out the flow of the target program; after reading patch data from the second memory in accordance with the patch data address and executing the function based on the patch data, the method includes: the process of the target program is skipped.

In some embodiments, determining a patch configuration corresponding to the function, and determining all patch data addresses of the function based on the patch configuration includes: querying a patch number corresponding to the function in a third register, wherein the third register is used for indicating the patch number which is hit currently, and the patch number which is hit currently is the patch number corresponding to the function; and determining all patch data addresses of the function based on the patch numbers corresponding to the function.

In some embodiments, the patch data address includes a replaced PC pointer, the control method further comprising: based on the replaced PC pointer, the function to be executed next by the processor is determined.

According to a third aspect of the present disclosure, there is provided a system-on-chip comprising a processor, a bus arbitration module, a first memory, and a second memory; the processor, the first memory and the second memory are respectively in communication connection with the bus arbitration module; the processor is configured to perform the control method for the system-on-chip provided in the first aspect of the present disclosure.

In some embodiments, the bus arbitration module is configured to determine whether the function is a modified function based on an original data address of the function currently being executed by the processor, the original data address being included in a data request sent by the processor, and a first register for storing the original data address of each modified function.

The control method for the system-on-chip and the system-on-chip provided by the embodiment of the disclosure can realize the following technical effects:

the embodiment of the disclosure stores patch data containing all data required for implementing the modified function in a second memory for the modified function required to be modified for the original data, and sets patch configuration in units of functions, so that all patch data stored in the second memory of each modified function shares one patch configuration. Each original data address of a function and the corresponding patch data address can be mapped through one patch configuration. The patch configuration setting mode reduces the number of patch configurations required by one function, all patch data addresses of the changed function can be determined through one patch configuration, and the function change requirement of more programs can be met only by occupying fewer resources of a chip.

The foregoing general description and the following description are exemplary and explanatory only and are not intended to limit the present disclosure.

Drawings

One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which like reference numerals refer to similar elements, and in which:

FIG. 1 is a schematic diagram of a system-on-chip provided by an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a second memory provided by an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a control method for a system-on-chip provided by an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of another control method for a system-on-chip provided by an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of another control method for a system-on-chip provided by an embodiment of the present disclosure;

FIG. 6 is a schematic diagram of another control method for a system-on-chip provided by an embodiment of the present disclosure;

fig. 7 is a schematic diagram of an application scenario for a system-on-chip provided in an embodiment of the present disclosure;

fig. 8 is a schematic diagram of another control method for a system-on-chip provided in an embodiment of the disclosure.

Detailed Description

So that the manner in which the features and techniques of the disclosed embodiments can be understood in more detail, a more particular description of the embodiments of the disclosure, briefly summarized below, may be had by reference to the appended drawings, which are not intended to be limiting of the embodiments of the disclosure. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may still be practiced without these details. In other instances, well-known structures and devices may be shown simplified in order to simplify the drawing.

The terms first, second and the like in the description and in the claims of the embodiments of the disclosure and in the above-described figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe embodiments of the present disclosure. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion.

The term "plurality" means two or more, unless otherwise indicated.

In the embodiment of the present disclosure, the character "/" indicates that the front and rear objects are an or relationship. For example, A/B represents: a or B.

The term "and/or" is an associative relationship that describes an object, meaning that there may be three relationships. For example, a and/or B, represent: a or B, or, A and B.

The term "corresponding" may refer to an association or binding relationship, and the correspondence between a and B refers to an association or binding relationship between a and B.

A System on a Chip (SOC), also known as a Chip on a Chip, is an integrated circuit with a dedicated target. A system on a chip will typically include a processor and read only memory. The rom has a faster access speed, so that data (e.g., main program code) of a program is stored in the rom, so as to improve the operation efficiency of the processor. The data stored in the ROM needs to be written into the ROM by a mask mode during the chip manufacture. After chip streaming, the data stored in the rom cannot be modified. Therefore, the system-in-chip also comprises a memory supporting read-write, and when the functions in the program need to be changed, new changed data is stored in the memory supporting read-write. Executing the function by reading data from the read-only memory for the unaltered function when the processor is running the program; for the modified function, the function is executed by reading new data from the memory supporting the reading and writing.

In the related art, in order for a processor to accurately read new data of a modified function, a Patch (Patch) configuration is required for original data and new data of the modified function, and address mapping between data can be performed by the Patch configuration. During execution of the program by the processor, if the function to be executed is a modified function, a bus arbitration module in the system on chip maps the address of the original data of the modified function to the address of the new data based on the patch configuration so that the process can read the new data from the address of the new data.

However, one function typically has a plurality of data, and related art needs to set patch configurations for respective data of the same function, that is, changing one function may require setting a plurality of patch configurations, so changing a plurality of functions requires using a large number of patch configurations. Therefore, if the number of patch configurations is limited, the number of functions allowed to be changed in the program is also limited, so that the function changing requirements of more programs cannot be met, and the current chip development requirements are difficult to adapt; allowing a greater number of patch configurations can result in excessive resources being consumed by the patch configurations, and excessive patch configurations can also significantly increase the path length of the processor accessing memory, affecting the system dominant frequency. Therefore, the related art sets the patch configuration mode, and can not meet the function change requirement of more programs under the condition of occupying less resources of the chip.

The disclosed embodiment provides a system-on-chip, and referring to fig. 1, the system-on-chip includes a processor 101, a bus arbitration module 102, a first memory 103 and a second memory 104, where the processor 101, the first memory 103 and the second memory 104 are respectively communicatively connected to the bus arbitration module 102. Specifically, the processor 101, the first memory 103, and the second memory 104 are respectively communicatively connected to the bus arbitration module 102 via buses, and the type of the bus arbitration module 102 may depend on the type of the bus protocol.

The Bus protocol may be an AHB (Advanced High-performance Bus) protocol and the Bus arbitration module 102 is an AHB_MST2SLV module. The ahb_mst2SLV module is a module in an ARM (Advanced RISC Machine, advanced reduced instruction set machine) embedded processor architecture, and involves data transfer between an AHB (Advanced High-performance Bus), a Master, and a Slave device. Specifically, the ahb_mst2SLV module represents a module that a Master device transmits data to a Slave device.

The bus protocol may also be an AXI4 (Advanced Extensible Interface, version 4, advanced extensible interface) protocol, and the bus arbitration module 102 is an arbiter (arbiter) in the AXI4 protocol.

In some embodiments, the first memory 103 may be a read-only memory, which is a solid-state semiconductor memory that can only read data stored in advance. The first memory 103 stores original data of the target program, and the processor 101 may read the original data through the bus arbitration module 102 to execute the target program.

The object includes one or more functions, each function having corresponding data. The data of the respective functions of the target program are preferentially stored in the first memory 103. For ease of understanding and description, the presently disclosed embodiments define data of respective functions of the target program stored in the first memory 103 as raw data. It is understood that, in the case where the first memory 103 is a read only memory, the original data of the first memory 103 storing the target program cannot be changed.

In the process of modifying the target program, at least part of the original data of at least part of the functions in the target program needs to be modified. In particular, the modification of the target program may be achieved by providing new data to replace the original data of the function. For ease of understanding and description, the disclosed embodiments define a function with new data for replacing original data as a modified function.

In the disclosed embodiment, the second memory 104 is used to store patch data of a modified function, where the patch data contains all the data needed to implement the execution of the modified function. In some cases, all of the original data of the changed function needs to be changed, each of the original data of the function corresponds to new data, and the patch data of the function includes new data corresponding to each of the original data of the function. In some cases, the original data of the part of the function that has been changed needs to be changed, the original data of the function that needs to be changed corresponds to new data, the original data that does not need to be changed does not have corresponding new data, and the patch data of the function includes the original data that does not need to be changed, and the new data corresponding to each original data that needs to be changed.

In the embodiment of the present disclosure, the second memory 104 is a memory supporting reading and writing. For example, the second Memory 104 may be a Flash Memory (Flash Memory). Flash memory is a form of electronically erasable programmable read-only memory that allows memory to be erased or written multiple times during operation. As shown in fig. 2, the second memory 104 is provided with a patch data area, and patch data of the function is stored in the patch data area of the second memory 104.

When it is determined by the bus arbitration module 102 that the function currently to be executed by the processor 101 is not a modified function during execution of the target program, the original data may be read from the first memory 103, and the function may be executed based on the original data. When the processor 101 determines that the function to be currently executed by the processor 101 is a modified function through the bus arbitration module 102, the patch data may be read from the second memory 104, and the function may be executed based on the patch data.

In some embodiments, bus arbitration module 102 is configured to determine whether a function is a modified function based on an original data address of the function currently being executed by processor 101, which is included in a data request sent by processor 101, and a first register for storing the original data address of each modified function.

In some embodiments, the system on chip further includes other memory in addition to the first memory 103 and the second memory 104. For example, the system on chip further comprises a third memory 105, which third memory 105 may be a RAM (Random Access Memory ).

In some embodiments, the second memory 104 is provided with a patch configuration area, which may store information related to patch configuration. For example, the patch configuration area may store registers that may be used to determine whether the function is a modified function, the address of patch data, and the like.

In some embodiments, the second memory 104 is provided with a jump program area, which may store a jump program, and the processor 101 may determine the address of the patch data by executing the jump program.

In some embodiments, the second memory 104 is provided with a user data area, which may store user data.

In connection with the system-on-chip shown in fig. 1, an embodiment of the present disclosure provides a control method for a system-on-chip, as shown in fig. 3, including:

s301, determining whether a function in a target program to be currently executed is a changed function.

The object program comprises one or more functions, and the processor executes each function according to set logic in the process of executing the object program. For each function of the target program, the processor needs to determine, by the bus arbitration module, whether the function is a modified function before the function is to be executed.

The object program includes one or more functions, each function having corresponding data, raw data of the respective function being stored in the first memory. Some functions may require modification of their original data, thus requiring configuration of new data to modify the original data of the function, and the disclosed embodiments define functions that require configuration of new data to replace the original data as modified functions. The modified function corresponds to the patch data, which is stored in the second memory, containing new data for replacing the original data of the function that needs to be modified.

In some embodiments, a function has multiple raw data. For the changed function, when each original data of the function needs to be changed, the patch data of the function comprises new data corresponding to each original data; when part of original data of the function needs to be changed, patch data of the function comprises original data which does not need to be changed and new data corresponding to the original data which needs to be changed.

S302, when the function is not changed, the processor reads the original data from the first memory according to the original data address of the function, and executes the function based on the original data.

In the disclosed embodiment, the original data address represents an address of original data of the function in the first memory. In the case where the function includes a plurality of original data, each of the original data of the function corresponds to one original data address. When the function is not a modified function, it is indicated that the original data of the function does not need to be modified. In this case, the processor may execute the function directly based on the raw data. Specifically, the processor may send the original data address to the bus arbitration module, and the bus arbitration module may obtain each original data from the first memory based on the original data address, and the processor receives each original data returned by the bus arbitration module.

After the current function is executed, if it is determined that the target program is not completed, execution of S301 may be restarted for the next function in the target program. After the current function is executed, if it is determined that the target program has been completed, the flow may be ended.

S303, when the function is a changed function, the processor determines a patch configuration corresponding to the function, and determines all patch data addresses of the function based on the patch configuration.

In the embodiment of the present disclosure, the patch data address represents an address of patch data of the function in the second memory. In the case where the function includes a plurality of patch data, each patch data corresponds to one patch data address. When the function is a modified function, it is indicated that the original data of the function needs to be modified. In this case, the processor needs to execute a function based on the patch data.

Embodiments of the present disclosure configure one patch configuration per modified function in units of functions. Each original data address of the function corresponds to a patch data address, and a patch configuration of the function may be used to map the respective original data address with the corresponding patch data address. Thus, all patch data addresses for the function can be determined based on one patch configuration.

S304, the processor reads the patch data from the second memory according to the patch data address, and executes the function based on the patch data.

After determining all patch data addresses of the function, the processor may send the patch data addresses to the bus arbitration module, and the bus arbitration module may obtain each patch data from the second memory based on the patch data addresses, where the processor receives each patch data returned by the bus arbitration module.

According to the control method for the system-in-chip, as for the changed function of which the original data needs to be changed, patch data containing all data needed for implementing execution of the changed function is stored in the second memory, and patch configuration is set in function units, so that all patch data of each changed function stored in the second memory share one patch configuration. Each original data address of a function and the corresponding patch data address can be mapped through one patch configuration. The patch configuration setting mode reduces the number of patch configurations required by one function, all patch data addresses of the changed function can be determined through one patch configuration, and the function change requirement of more programs can be met only by occupying fewer resources of a chip.

In some embodiments, the bus arbitration module determining whether a function in the target program currently to be executed is a modified function includes: and sending a data request of the original data address of the function in the target program to be executed currently to the bus arbitration module, so that the bus arbitration module determines whether the function is a changed function or not based on the original data address and a first register, wherein the first register is used for storing the original data address of each changed function.

The embodiment of the disclosure provides another control method for a system-on-chip, as shown in fig. 4, the control method for the system-on-chip includes:

s401, the processor sends a data request of an original data address of a function in a target program to be currently executed to the bus arbitration module.

S402, the bus arbitration module determines whether the function is a modified function based on the original data address and the first register.

Embodiments of the present disclosure preconfigure a first register for storing the original data address of each modified function. The bus arbitration module may parse the original data address of the function from the data request and determine whether the original data address of the function can be matched in the first stored original data address. If the original data address of the function is not matched in the first mailed stored original data address, determining that the function is not a modified function; if the original data address of the function is matched in the first mailed original data address, it is determined that the function is a modified function.

In some embodiments, the first register is for storing a first original data address of each modified function. The bus arbitration module is used for determining whether the function is a changed function based on the first original data address of the first function and the first register. Because the first register only needs to store the first original data address of each changed function, the data storage capacity of the first register can be reduced, the occupation of the first register to the memory is further reduced, and the storage resource is saved.

The function includes a plurality of original data, each corresponding to one original data address, so that one function needs to correspond to a plurality of original data addresses. In the embodiment of the disclosure, the original data address corresponding to the original data to be read for the first of the functions is the first original address. The bus arbitration module can analyze the original data address of the function from the data request, determine the first original data address, and determine whether the first original data address of the function can be matched with the first original data address stored in the first register. If the first original data address of the function is not matched in the first original data address stored in the first register, determining that the function is not a modified function; if the first original data address of the function is matched in the first stored first original data address, the function is determined to be a modified function.

TABLE 1

Bits	Function name	Attributes of	First original data address
				31:0	Function X	RW	ADDRESSX

Table 1 shows a schematic diagram of the first register, function X representing the xth function of the target program, address X representing the first original data address of the xth function.

S403, when the function is not the changed function, the processor reads the original data from the first memory according to the original data address of the function, and executes the function based on the original data.

S404, when the function is a changed function, the processor determines a patch configuration corresponding to the function, and determines all patch data addresses of the function based on the patch configuration.

S405, the processor reads the patch data from the second memory according to the patch data address, and executes a function based on the patch data.

The embodiment of the disclosure configures the jump program and stores the jump program in the second memory, so that the processor realizes the process of determining the patch data address by executing the jump program, and the function of determining the patch data address of the processor is additionally added on the basis of the original function of the target program.

The embodiment of the disclosure provides another control method for a system-on-chip, as shown in fig. 5, the control method for the system-on-chip includes:

s501, the processor determines whether the function in the target program to be currently executed is a modified function.

S502, when the function is not changed, the processor reads the original data from the first memory according to the original data address of the function, and executes the function based on the original data.

S503, when the function is changed, the processor reads the jump program in the second memory.

In step 503, the bus arbitration module may acquire the jump program in the second memory, and the processor reads the jump program in the second memory through the bus arbitration module.

S504, the processor determines a patch configuration corresponding to the function by executing the jump procedure, and determines all patch data addresses of the function based on the patch configuration.

S505, the processor reads patch data from the second memory according to the patch data address, and executes a function based on the patch data.

In some embodiments, the target address is an address of a jump program stored in the second memory, where the target address may be stored. Reading the jump program in the second memory, comprising: and reading the target address stored in the second register, and reading the jump program from the second memory according to the target address. In an embodiment of the disclosure, the processor may send the target address to a bus arbitration module, the bus arbitration module obtains the jump program in the second memory based on the target address, and the processor reads the jump program through the bus arbitration module.

In some embodiments, the target address is a first address of a jump program stored in the second memory, which may be stored in the second memory. Reading the jump program in the second memory, comprising: the first address of the jump program stored in the second register is read, and the jump program is read from the second memory starting from the first address. In the embodiment of the disclosure, the processor may send the first address to the bus arbitration module, and the bus arbitration module sequentially acquires each data of the jump program in the second memory based on the first address, and the processor reads the jump program through the bus arbitration module.

The second register only needs to store the first address of the jump program, which can reduce the data storage capacity of the second register, further reduce the occupation of the second register to the memory and save the storage resource.

TABLE 2

Bits	Name of the name	Attributes of	Jump program head address
				31:0	Jump program	RW	SOURCE ADDRESS

Table 2 shows a schematic diagram of the second register, SOURCE ADDRESS in table 2 representing the first ADDRESS of the degree of jump.

In some embodiments, the processor jumps out of the process of the target program before determining a patch configuration corresponding to the function by executing the jump program and determining all patch data addresses of the function based on the patch configuration. After reading the patch data from the second memory according to the patch data address and executing the function based on the patch data, the processor jumps back to the flow of the target program.

The embodiment of the disclosure sets the steps of jumping out and jumping back to the target program, and executes the jumping program under the condition of jumping out of the target program, so that the target program and the jumping program can be separately executed by a processor, and program execution errors are avoided.

In some embodiments, determining a patch configuration corresponding to the function, and determining all patch data addresses of the function based on the patch configuration includes: inquiring patch numbers corresponding to the functions in a third register; and determining all patch data addresses of the function based on the patch numbers corresponding to the function. The third register is used for indicating the currently hit patch number, and the currently hit patch number is the patch number corresponding to the function.

The embodiment of the disclosure provides another control method for a system-on-chip, as shown in fig. 6, the control method for the system-on-chip includes:

s601, the processor determines whether the function in the target program to be currently executed is a modified function.

S602, when the function is not changed, the processor reads the original data from the first memory according to the original data address of the function, and executes the function based on the original data.

S603, when the function is changed, the processor queries a patch number corresponding to the function in a third register.

TABLE 3 Table 3

Table 3 shows a schematic diagram of a third register, which is a hardware circuit-based register, that can indicate the hit status of the patch number of each patch configuration. The third register is used for indicating the currently hit patch number, and the currently hit patch number is the patch number corresponding to the function. The processor determines the hit patch number queried in the third register as the patch number corresponding to the function.

S604, the processor determines all patch data addresses of the function based on the patch numbers corresponding to the function.

The patch configuration of the embodiment of the present disclosure may include a mapping relationship of the patch number and the patch data address of the patch data of the corresponding function. The processor may determine all patch data addresses for the function based on the mapping relationship and the determined patch number.

S605, the processor reads the patch data from the second memory according to the patch data address, and executes a function based on the patch data.

In some embodiments, the patch configuration may include a mapping of the patch number to a first patch data address of patch data of the corresponding function. The processor may determine a first patch data address of the function based on the mapping relationship and the determined patch number. Each patch data is read one by one from the second memory starting from the first patch data address, and a function is executed based on the patch data.

Optionally, an index table may be set in the embodiments of the present disclosure, where the mapping relationship between the patch number and the first patch data address of the patch data of the corresponding function is represented by the index table.

TABLE 4 Table 4

Patch number	First patch data address
		PAHCH1	ADDRESS1
PAHCH2	ADDRESS2
		PAHCH3	ADDRESS3
---	---
		PAHCH64	ADDRESS64

Table 4 shows an index table provided by an embodiment of the present disclosure, in table 4, PAHCH1 to PAHCH64 are the 64 patch numbers, and ADDRESS1 to ADDRESS64 are the first patch data addresses of the 64 functions.

In connection with the system-on-chip shown in fig. 1, an embodiment of the present disclosure provides an application scenario for the system-on-chip, as shown in fig. 7, in which a function to be currently executed by a processor is a function 2 of a target program, the application scenario includes the following steps:

s701, the processor sends a data request for an original data address containing function 2 to the bus arbitration module, which determines whether the function is a modified function based on the original data address and the first register.

After S701, when the function is not a modified function, S702 is performed; when the function is a changed function, S703 is executed. Wherein when the function is a modified function, it indicates that the second memory stores data of a new function 2, and the data of the new function 2 is patch data of the function 2.

The bus arbitration module may obtain each original data from the first memory based on the original data address, and the processor receives each original data returned by the bus arbitration module and performs a function based on the original data.

S703, the processor queries the patch numbers corresponding to the functions in the third register by executing the jump procedure, and determines all patch data addresses of the functions based on the patch numbers corresponding to the functions.

The processor reads the patch data from the second memory according to the patch data address and executes a function based on the patch data S704.

S705 is performed after S704, where in S705 function 3 is taken as the function to be currently performed by the processor, and the specific content of S705 is the same as S701.

In some embodiments, the patch data address includes a replaced PC pointer. The control method for the system-on-chip provided by the embodiment of the disclosure further comprises the following steps: based on the replaced PC pointer, the function to be executed next by the processor is determined.

The PC pointer in the embodiment of the present disclosure refers to a Program Counter (Program Counter) pointer. The embodiment of the disclosure can take the PC pointer as patch data, and can change the execution sequence of the functions in the target program by modifying the PC pointer so as to realize modification of the target program.

The embodiment of the disclosure provides another control method for a system-on-chip, as shown in fig. 8, the control method for the system-on-chip includes:

s801, the processor determines whether a function in the target program to be currently executed is a modified function.

S802, when the function is not changed, the processor reads the original data from the first memory according to the original data address of the function, and executes the function based on the original data.

S803, when the function is a changed function, the processor determines a patch configuration corresponding to the function, and determines all patch data addresses of the function based on the patch configuration.

S804, the processor reads the patch data from the second memory according to the patch data address, and executes the function based on the patch data.

S805, the processor determines a function to be executed next by the processor based on the replaced PC pointer.

The disclosed embodiments also provide a fourth register, where each bit code in the fourth register represents an enable bit of a patch configuration, and when the enable bit of a patch configuration is 1, it represents that the patch configuration is enabled.

TABLE 5

Bits	Name of the name	Attributes of	Function of
				31:2	PATCH31:2_EN	RW	PATCH31:2PATCHSRCADDR31:2ENABLE
1	PATCH1_EN	RW	PATCH1 PATCHSRCADDR1 ENABLE
				0	PATCH0_EN	RW	PATCH0 PATCHSRCADDR0 ENABLE

Table 5 is a schematic diagram of a fourth register provided by an embodiment of the present disclosure, in table 5, patch0_en and patch1_en represent names of respective PATCH position ENABLE bits, and PATCH0PATCHSRCADDR0 ENABLE and PATCH1 PATCHSRCADDR1 ENABLE represent addresses of respective PATCH position ENABLE bits.

The disclosed embodiments provide a computer-readable storage medium storing computer-executable instructions configured to perform the above-described control method for a system-on-chip.

Embodiments of the present disclosure may be embodied in a software product stored on a storage medium, including one or more instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of a method according to embodiments of the present disclosure. While the aforementioned storage medium may be a non-transitory storage medium, such as: a usb disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk or an optical disk, or other various media capable of storing program codes.

The above description and the drawings illustrate embodiments of the disclosure sufficiently to enable those skilled in the art to practice them. Other embodiments may involve structural, logical, electrical, process, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in, or substituted for, those of others. Moreover, the terminology used in the present disclosure is for the purpose of describing embodiments only and is not intended to limit the claims. As used in the description of the embodiments and the claims, the singular forms "a," "an," and "the" (the) are intended to include the plural forms as well, unless the context clearly indicates otherwise. Similarly, the term "and/or" as used in this disclosure is meant to encompass any and all possible combinations of one or more of the associated listed. Furthermore, when used in this disclosure, the terms "comprises," "comprising," and/or variations thereof, mean the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Without further limitation, an element defined by the phrase "comprising one …" does not exclude the presence of other like elements in a process, method or apparatus comprising such elements. In this context, each embodiment may be described with emphasis on the differences from the other embodiments, and the same similar parts between the various embodiments may be referred to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method sections disclosed in the embodiments, the description of the method sections may be referred to for relevance.

Those of skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. The skilled artisan may use different methods for each particular application to achieve the described functionality, but such implementation should not be considered to be beyond the scope of the embodiments of the present disclosure. It will be clearly understood by those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, which are not repeated herein.

In the embodiments disclosed herein, the disclosed methods, articles of manufacture (including but not limited to devices, apparatuses, etc.) may be practiced in other ways. For example, the apparatus embodiments described above are merely illustrative, and for example, the division of the units may be merely a logical function division, and there may be additional divisions when actually implemented, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. In addition, the coupling or direct coupling or communication connection shown or discussed with each other may be through some interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form. The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to implement the present embodiment. In addition, each functional unit in the embodiments of the present disclosure may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. In the description corresponding to the flowcharts and block diagrams in the figures, operations or steps corresponding to different blocks may also occur in different orders than that disclosed in the description, and sometimes no specific order exists between different operations or steps. For example, two consecutive operations or steps may actually be performed substantially in parallel, they may sometimes be performed in reverse order, which may be dependent on the functions involved. Each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

Claims

1. A control method for a system-on-chip, comprising:

reading original data from a first memory according to an original data address of the function when the function is determined not to be a changed function, and executing the function based on the original data;

when the function is determined to be a changed function, determining a patch configuration corresponding to the function, and determining all patch data addresses of the function based on the patch configuration, wherein each original data address of the function corresponds to one patch data address;

and reading patch data from the second memory according to the patch data address, and executing the function based on the patch data.

2. The control method according to claim 1, wherein the determining whether the function in the target program to be currently executed is a modified function includes:

and sending a data request of an original data address of a function in a target program to be executed currently to a bus arbitration module, so that the bus arbitration module determines whether the function is a changed function or not based on the original data address and a first register, wherein the first register is used for storing the original data address of each changed function.

3. The control method of claim 2, wherein the bus arbitration module is configured to determine whether the function is a modified function based on a first of the original data addresses of a first of the functions and a first register, wherein the first register is configured to store a first of the original data addresses of each of the modified functions.

4. A control method according to claims 1 to 3, wherein said determining a patch configuration corresponding to said function and determining all patch data addresses of said function based on said patch configuration comprises:

reading a jump program in the second memory;

and determining one patch configuration corresponding to the function by executing the jump program, and determining all patch data addresses of the function based on the patch configuration.

5. The control method according to claim 4, characterized in that the reading of the jump program in the second memory includes:

reading a target address stored in a second register, wherein the target address is an address of a jump program stored in the second memory;

and reading the jump program from the second memory according to the target address.

6. The control method according to claim 4, characterized by, before said determining one patch configuration corresponding to said function by executing said jump program, and determining all patch data addresses of said function based on said patch configuration, comprising: jumping out the flow of the target program;

after said reading patch data from the second memory in accordance with said patch data address and performing said function based on said patch data, comprising: and jumping back to the flow of the target program.

7. A control method according to claims 1 to 3, wherein said determining a patch configuration corresponding to said function and determining all patch data addresses of said function based on said patch configuration comprises:

inquiring a patch number corresponding to the function in a third register, wherein the third register is used for indicating a currently hit patch number, and the currently hit patch number is the patch number corresponding to the function;

and determining all patch data addresses of the function based on the patch numbers corresponding to the function.

8. A control method according to claims 1 to 3, wherein the patch data address includes a replaced PC pointer, the control method further comprising: and determining a function to be executed next by the processor based on the replaced PC pointer.

9. The system-on-chip is characterized by comprising a processor, a bus arbitration module, a first memory and a second memory; the processor, the first memory and the second memory are respectively in communication connection with the bus arbitration module;

the processor is configured to perform the control method for a system-on-chip as claimed in any one of claims 1 to 8.

10. The system-on-chip of claim 9, the bus arbitration module configured to determine whether the function is a modified function based on an original data address of a function currently to be executed by the processor and a first register for storing original data addresses of respective modified functions, the original data address being included in a data request sent by the processor.