CN116049030A

CN116049030A - Method and device for data access, electronic equipment and storage medium

Info

Publication number: CN116049030A
Application number: CN202211593342.XA
Authority: CN
Inventors: 黄钧
Original assignee: Beijing Ziguang Xinneng Technology Co Ltd
Current assignee: Beijing Ziguang Xinneng Technology Co Ltd
Priority date: 2022-12-13
Filing date: 2022-12-13
Publication date: 2023-05-02

Abstract

The application relates to the technical field of flash memory control, and discloses a method for data access, which comprises the following steps: acquiring a mapping address to be accessed of a chip, a mapping space initial address of the chip, a physical initial address of a flash memory, an index value of an expected mapping partition and a mapping space capacity of the chip; determining whether the index range is qualified according to the index value of the expected mapping partition; and under the condition that the index range is qualified, calculating according to a first preset algorithm by using the to-be-accessed mapping address, the mapping space starting address, the physical starting address, the index value of the expected mapping partition and the mapping space capacity to obtain the target physical address of the flash memory. Thus, all physical addresses in the flash memory can be accessed by dynamically changing the mapping relation between the mapping address to be accessed and the target physical address. In the on-chip execution mode of the serial flash memory controller, the space utilization rate of the flash memory is conveniently improved. The application also discloses a device, electronic equipment and storage medium for data access.

Description

Method and device for data access, electronic equipment and storage medium

Technical Field

The present invention relates to the field of flash memory control technologies, and for example, to a method and apparatus for data access, an electronic device, and a storage medium.

Background

Currently, there is a general need for communication between a chip and a flash memory. Based on the transmission characteristics of QSPI (Quad SPI), communication between the chip and the flash memory is more and more widely carried out through QSPI. For example: chinese patent document publication No. CN112463651a discloses: in computer technology, it is often necessary to communicate with flash memory. In flash memory access, a serial peripheral interface (Serial Peripheral Interface, SPI) is typically used to communicate with the flash memory. However, since the SPI is a single line, the transmission speed of data is slow when flash access is performed through the SPI. The inventor finds that QSPI is an extension of SPI interface, is more widely applied than SPI, and on the basis of SPI protocol, QSPI functions are enhanced, a queue transmission mechanism is increased, and a queue serial peripheral interface protocol is deduced. Meanwhile, as the application of QSPI increases, the application of QSPI Flash (Quad SPI Flash) is also becoming wider and wider. For example: chinese patent document publication No. CN115248790a discloses: because of the small number of pins, QSPI Flash (Quad SPI Flash) has the advantages of simple operation, large storage space and low cost. The method is widely applied to SoC (System on Chip) chips and embedded systems. One application is software code storage, where a CPU or other processor may read instructions directly from Flash and run, called on-chip execution, in english, called eXecute In Place, XIP for short. The second application is data storage, storing fixed initialization data or software code (code needs to be copied to SRAM before it can run).

Serial Flash controllers typically support XIP (execution in place) mode so that a CPU (central processing unit ) or other processor can read and run instructions directly from a QSPI Flash (serial Flash). In the related art, the system on chip memory space is divided into a fixed space with continuous addresses as a QSPI mapping space. After the chip design streams, the QSPI mapping space divided for the user is fixed. The capacity of the QSPI mapping space and the mapping space address range of the QSPI mapping space cannot be modified, and a user cannot adjust the conversion relationship between the mapping space address and the physical address of the QSPI Flash. However, the chip designer cannot always predict how large the QSPI Flash is required to be used by many users in the design stage, so that the capacity of the QSPI mapping space divided by the users is not matched with the capacity of the QSPI Flash used by the actual users. Since the mapped spatial address is typically fixed for only one physical address. Thus, with the serial flash controller in XIP mode, the user can only access the physical address range that corresponds to the mapped spatial address range fixed, and cannot access physical addresses outside the fixed corresponding physical address range. Fig. 1 is a schematic diagram of a first mapping relationship, as shown in fig. 1, a QSPI mapping space 2 is provided on a system memory space 1 of the chip, where the QSPI mapping space 2 corresponds to a mapping region on a QSPI Flash3, that is, only the mapping region on the QSPI Flash3 can be accessed through a serial Flash controller, but an excess part beyond the mapping region in the QSPI Flash3 cannot be accessed.

In the process of implementing the embodiments of the present disclosure, it is found that at least the following problems exist in the related art: in the on-chip execution mode of the serial flash controller, the space utilization of the flash memory is low.

Disclosure of Invention

The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview, and is intended to neither identify key/critical elements nor delineate the scope of such embodiments, but is intended as a prelude to the more detailed description that follows.

The embodiment of the disclosure provides a method and a device for data access, electronic equipment and a storage medium, so that the space utilization rate of a flash memory is conveniently improved in an on-chip execution mode of a serial flash memory controller.

In some embodiments, the method for data access is applied to a serial flash controller, which is in an on-chip execution mode; the method for data access comprises the following steps: acquiring a mapping address to be accessed of a chip, a mapping space initial address of the chip, a physical initial address of a flash memory, an index value of an expected mapping partition and a mapping space capacity of the chip; determining whether the index range is qualified according to the index value of the expected mapping partition; and under the condition that the index range is qualified, calculating according to a first preset algorithm by using the mapping address to be accessed, the mapping space starting address, the physical starting address, the index value of the expected mapping partition and the mapping space capacity to obtain the target physical address of the flash memory.

In some embodiments, determining whether the index range is acceptable based on the desired mapped partition index value comprises: acquiring the expected flash memory capacity; calculating according to a second preset algorithm by utilizing the expected flash memory capacity and the mapping space capacity to obtain a maximum index value; and comparing the maximum index value with the index value of the expected mapping partition, and determining whether the index range is qualified according to a comparison result.

In some embodiments, determining whether the index range is acceptable based on the comparison result includes: determining that the index range is qualified under the condition that the index value of the expected mapping partition is smaller than the maximum index value; and/or determining whether the mapping address to be accessed is in a preset space mapping address range or not under the condition that the index value of the desired mapping partition is equal to the maximum index value; and determining that the index range is qualified when the mapping address to be accessed is in the space mapping address range.

In some embodiments, after obtaining the target physical address of the flash memory, the method further includes: and reading the data stored by the target physical address of the flash memory.

In some embodiments, the means for data access is applied to a serial flash controller, the serial flash controller being in an on-chip execution mode; the apparatus for data access includes: the system comprises an acquisition module, a memory module and a memory module, wherein the acquisition module is configured to acquire a mapping address to be accessed of a chip, a mapping space starting address of the chip, a physical starting address of a flash memory, an index value of an expected mapping partition and a mapping space capacity of the chip; a determining module configured to determine whether an index range is qualified according to the desired mapping partition index value; the calculation module is configured to calculate, according to a first preset algorithm, the target physical address of the flash memory by using the address to be accessed, the mapping space starting address, the physical starting address, the index value of the expected mapping partition and the mapping space capacity under the condition that the index range is qualified.

In some embodiments, the determining module is configured to determine whether the index range is eligible based on the desired mapped partition index value in the following manner: acquiring the expected flash memory capacity; calculating according to a second preset algorithm by utilizing the expected flash memory capacity and the mapping space capacity to obtain a maximum index value; and comparing the maximum index value with the index value of the expected mapping partition, and determining whether the index range is qualified according to a comparison result.

In some embodiments, the determining module is configured to determine whether the index range is acceptable based on the comparison result in the following manner: determining that the index range is qualified under the condition that the index value of the expected mapping partition is smaller than the maximum index value; and/or determining whether the mapping address to be accessed is in a preset space mapping address range or not under the condition that the index value of the desired mapping partition is equal to the maximum index value; and determining that the index range is qualified when the mapping address to be accessed is in the space mapping address range.

In some embodiments, the apparatus for data access further comprises: and the reading module is configured to read the data stored by the target physical address of the flash memory after the target physical address of the flash memory is obtained.

In some embodiments, the electronic device comprises a processor and a memory storing program instructions, the processor being configured to perform the above-described method for data access when executing the program instructions.

In some embodiments, the storage medium stores program instructions that, when executed, perform the method for data access described above.

The method and device for data access, the electronic device and the storage medium provided by the embodiment of the disclosure can realize the following technical effects: the method comprises the steps of obtaining a mapping address to be accessed of a chip, a mapping space starting address of the chip, a physical starting address of a flash memory, an expected mapping partition index value and a mapping space capacity of the chip. And determining whether the index range is qualified according to the index value of the expected mapping partition. And under the condition that the index range is qualified, calculating according to a first preset algorithm by using the to-be-accessed mapping address, the mapping space starting address, the physical starting address, the index value of the expected mapping partition and the mapping space capacity to obtain the target physical address of the flash memory. In this way, under the on-chip execution mode of the serial flash controller, all physical addresses in the flash memory can be accessed by dynamically changing the mapping relation between the mapping address to be accessed and the target physical address. Therefore, in the on-chip execution mode of the serial flash memory controller, the space utilization rate of the flash memory is conveniently improved.

The foregoing general description and the following description are exemplary and explanatory only and are not restrictive of the application.

Drawings

One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which like reference numerals refer to similar elements, and in which:

fig. 1 is a schematic diagram of a first mapping relationship provided in an embodiment of the present disclosure;

FIG. 2 is a schematic diagram illustrating signaling of a serial flash controller according to an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a mapping address translation module according to an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a method for data access provided by an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a second mapping relationship provided by an embodiment of the present disclosure;

FIG. 6 is a schematic diagram of an apparatus for data access provided by an embodiment of the present disclosure;

fig. 7 is a schematic diagram of an electronic device according to an embodiment of the disclosure.

Reference numerals:

1: memory space of the chip system; 2: QSPI mapping space; 3: QSPI Flash;4: a serial flash memory controller; 5: XIP port; 6: a command port; 7: a set of status/control registers; 8: a data and control signal module; 9: mapping an address conversion module; 10: SPI controller.

Detailed Description

So that the manner in which the features and techniques of the disclosed embodiments can be understood in more detail, a more particular description of the embodiments of the disclosure, briefly summarized below, may be had by reference to the appended drawings, which are not intended to be limiting of the embodiments of the disclosure. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may still be practiced without these details. In other instances, well-known structures and devices may be shown simplified in order to simplify the drawing.

The terms first, second and the like in the description and in the claims of the embodiments of the disclosure and in the above-described figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe embodiments of the present disclosure. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion.

The term "plurality" means two or more, unless otherwise indicated.

In the embodiment of the present disclosure, the character "/" indicates that the front and rear objects are an or relationship. For example, A/B represents: a or B.

The term "and/or" is an associative relationship that describes an object, meaning that there may be three relationships. For example, a and/or B, represent: a or B, or, A and B.

The term "corresponding" may refer to an association or binding relationship, and the correspondence between a and B refers to an association or binding relationship between a and B.

In some embodiments, the serial flash controller of the present application, for example: a QSPI controller. The Flash memory is QSPI Flash (serial Flash memory).

In some embodiments, FIG. 2 is a signaling diagram of a serial flash controller. As shown in connection with fig. 2, the serial flash controller 4 includes: map address translation module 9, command port 6, status/control register set 7, data and control signal module 8, SPI controller 10, and XIP port 5. Wherein the command port 6 comprises a set of status/control registers 7.SPI controller 10 accesses QSPI Flash3 via a serial bus. In the case where the serial flash controller is in command mode, the command mode read data is read through the command port or the command mode write data is written through the command port. In command mode, the user configures the set of status/control registers through the command port. The command port obtains parameters of the state/control register set after user configuration, and then transmits state/control register signals with the SPI controller according to the parameters of the state/control register set, so that the SPI (Serial Peripheral Interface ) controller can read/write/erase data in the external expansion QSPI Flash through a serial bus. The data in the Flash of the Flash-out QPI is generally read/written/erased based on the internal physical address of the Flash of the QPI, which ranges from (FlsAddrStart, flsAddrEnd). Wherein FlsAddrStart is the physical start address and FlsAddrEnd is the physical end address. Typically, flsaddrstart=0. The internal physical address of the QSPI Flash is independent of the memory space of the chip system, and the internal physical address are not mutually interfered. Before the serial flash controller executes the on-chip execution mode, it is generally necessary to configure on-chip execution mode command parameters in the command mode before switching the operation mode of the serial flash controller to the on-chip execution mode. Under the condition that the serial Flash memory controller is in an on-chip execution mode, a mapping address conversion module of the serial Flash memory controller obtains a mapping address to be accessed (Memaddr) in a read command of the CPU, and converts the mapping address to be accessed into a target physical address (FlsAddr) of the QSPI Flash. Wherein FlsAddrStart.ltoreq.FlsAddr.ltoreq.FlsAddrEnd. The map address translation module then sends the target physical address to the set of status/control registers of the command port. At the same time, the status/control register set of the command port also receives the on-chip execution mode command parameters. The command port obtains the parameters of the state/control register set and transmits data receiving and transmitting signals with the data and control signal module. Meanwhile, the command port receives the status signal sent by the data and control signal module. The data and control signal module sends control signals and sending data to the SPI controller, and the SPI controller reads the data of the target physical address FlsAddr through the serial bus and sends the data to the data and control signal module, so that the data and control signal module receives the data. The SPI controller also sends the data to the XIP port in the form of a data burst. The on-chip execution mode read data is read out through the XIP port.

In some embodiments, because the user can only access the physical address range that corresponds to the mapped spatial address range fixed while the serial flash controller is in XIP mode, physical addresses outside of the fixed corresponding physical address range cannot be accessed. Physical addresses outside the fixed corresponding physical address range of the mapping space address range are only accessible through command mode. Therefore, in the case where the serial flash controller is in the XIP mode, there is a case where the space utilization of the serial flash is low. By improving the mapping address conversion module, the space utilization rate of the flash memory is conveniently improved in an on-chip execution mode of the serial flash memory controller. The serial flash memory controller comprises a mapping address conversion module, wherein the mapping address conversion module is used for converting a mapping address to be accessed of the chip into a target physical address of the flash memory. Fig. 3 is a schematic diagram of the structure and signals of the mapping address conversion module. As shown in connection with fig. 3, the mapping address conversion module 9 includes: the memory system comprises a mapping address conversion calculation unit, a serial flash capacity register (FLSZ), a serial flash partition index value register (FPI), a memory mapping area highest address register (MADDR), a serial flash physical partition number register (FPN) and a serial flash partition status register (FPS). And inputting the mapping addresses to be accessed in the read commands of the serial flash capacity register, the serial flash partition index value register and the CPU into a mapping address conversion calculation unit for calculation, and respectively writing data into the memory mapping area highest address register, the serial flash physical partition number register and the serial flash partition state register by the mapping address conversion calculation unit according to calculation results. And simultaneously, converting the mapping address to be accessed into a target physical address, and sending the target physical address to the command port. The command port also receives on-chip execution mode command parameters. The serial flash capacity register is used for storing the expected flash capacity input by a user; the serial flash memory partition index value register is used for storing the expected mapping partition index value input by a user; the highest address register of the memory mapping area is used for storing the high address of the access address range of the XIP mapping area; serial flash physical partition number register: for storing a maximum index value; serial flash partition status register: for setting an alarm. The user can read the value of the highest address register of the memory mapping area to judge whether the CPU accesses the illegal area. The maximum index value and the high address of the access address range of the XIP map partition are both calculated by the map address conversion calculation unit. Whether the serial flash partition status register is set for alarm is also determined by the calculation of the mapping address conversion calculation unit.

In some embodiments, before the serial Flash controller uses the XIP mode to access the QSPI Flash, the user is required to configure the serial Flash capacity register and then to configure the serial Flash partition index value register to access the target map area. The target mapping area is the mapping area that the user desires to access. And switching the working mode of the serial flash controller to an XIP mode, initiating access to the mapping address of the target physical address to be accessed through the CPU, transmitting the mapping address to be accessed to the mapping address conversion calculation unit for address conversion, and storing the related state or calculated value into a memory mapping area highest address register, a serial flash physical partition number register and a serial flash partition state register. And then, the calculated output is matched with the command parameters of the execution mode in the chip, the data of the target physical address is read through the command port, and the data is transmitted to the CPU through the XIP port.

Referring to fig. 4, an embodiment of the present disclosure provides a method for data access, applied to a serial flash controller, where the serial flash controller is in an on-chip execution mode; the method for data access comprises the following steps:

in step S401, the serial flash controller obtains the mapping address to be accessed of the chip, the mapping space starting address of the chip, the physical starting address of the flash, the index value of the desired mapping partition, and the mapping space capacity of the chip.

In step S402, the serial flash controller determines whether the index range is qualified according to the desired mapping partition index value.

Step S403, under the condition that the index range is qualified, the serial flash memory controller calculates by utilizing the mapping address to be accessed, the mapping space starting address, the physical starting address, the index value of the expected mapping partition and the mapping space capacity according to a first preset algorithm, and obtains the target physical address of the flash memory.

By adopting the method for data access provided by the embodiment of the disclosure, the mapping address to be accessed of the chip, the mapping space starting address of the chip, the physical starting address of the flash memory, the index value of the expected mapping partition and the mapping space capacity of the chip are obtained. And determining whether the index range is qualified according to the index value of the expected mapping partition. And under the condition that the index range is qualified, calculating according to a first preset algorithm by using the to-be-accessed mapping address, the mapping space starting address, the physical starting address, the index value of the expected mapping partition and the mapping space capacity to obtain the target physical address of the flash memory. In this way, in the on-chip execution mode of the serial flash controller, all internal physical addresses in the flash memory can be accessed by dynamically changing the mapping relationship between the mapping address to be accessed and the target physical address. Therefore, in the on-chip execution mode of the serial flash memory controller, the space utilization rate of the flash memory is conveniently improved.

In some embodiments, the desired mapped partition index value is obtained from a serial flash partition index value register.

Further, the mapping space capacity of the chip is obtained by: xipmemsz=memaddrend-memaddrstart+1 is calculated to obtain the mapped spatial capacity. Wherein XIPMEMSZ is the mapped space capacity. (MemAddrStart, memAddrEnd) represents the address range of the QSPI mapping space. MemAddrStart is the mapping space start address of the QSPI mapping space. Memaddrdend is the mapping space end address of the QSPI mapping space.

Further, according to a first preset algorithm, calculating by using the mapping address to be accessed, the mapping space starting address, the physical starting address, the index value of the expected mapping partition and the mapping space capacity, to obtain a target physical address of the flash memory, including: flsAddr= (Memaddr-MemaddrStart) + (FlsAddrStart+FPI×XIPMEMSZ) is calculated to obtain the target physical address. Wherein FlsAddr is the target physical address; memAddr is the mapped address to be accessed; memAddrStart is the mapped space starting address; flsAddrStart is the physical starting address; FPI is a desired mapping partition index value; XIPMEMSZ is the mapped spatial capacity. In this way, by obtaining the index value of the desired mapping partition, the address to be accessed can be mapped to the mapping area corresponding to the index value of the desired mapping partition in the XIP mode of the serial flash controller. For example: in the case of fpi=1, the mapping address to be accessed can be mapped to the first mapping area by the above formula. Fig. 5 is a schematic diagram of a second mapping relationship, and in combination with fig. 5, a QSPI mapping space 2 is disposed on a system on chip memory space 1. By changing the desired mapping partition index value, the mapping space address of the QSPI mapping space 2 can be mapped to the first mapping region, the second mapping region, the third mapping region, or the like of the QSPI Flash 3. Because of the conventional address mapping method, only the mapping address to be accessed can be fixedly mapped to the zeroth mapping area, but the first mapping area, the second mapping area or the third mapping area of the high address segment cannot be accessed. Thus, by the address translation scheme of the present application, the access space of the serial flash controller to the flash memory in XIP mode can be improved.

Optionally, determining whether the index range is acceptable according to the desired mapping partition index value includes: acquiring the expected flash memory capacity; calculating according to a second preset algorithm by using the expected flash memory capacity and the mapping space capacity to obtain a maximum index value; comparing the maximum index value with the index value of the expected mapping partition, and determining whether the index range is qualified according to the comparison result. Therefore, by comparing the maximum index value with the expected mapping partition index value, whether the expected mapping partition index value configured by the user is wrong or not can be rapidly judged, so that the user is conveniently reminded of correctly configuring the expected mapping partition index value, and the internal physical address of the flash memory cannot be accessed.

In some embodiments, the desired flash capacity is obtained from a serial flash capacity register.

Further, according to a second preset algorithm, calculating by using the expected flash memory capacity and the mapping space capacity to obtain a maximum index value, including: by calculation of

The maximum index value is obtained. Wherein FPImax is the maximum index value, and FLSZ is the expected flash memory capacity; XIPMEMSZ is the mapped spatial capacity. Wherein (1)>

To round up operator, "=" is equal, "=" is division, "+" is addition, "-" is subtraction, "×" is multiplication.

Further, determining whether the index range is qualified according to the comparison result includes: determining that the index range is qualified under the condition that the index value of the expected mapping partition is smaller than the maximum index value; and/or determining whether the mapping address to be accessed is in a preset space mapping address range or not under the condition that the index value of the expected mapping partition is equal to the maximum index value; and determining that the index range is qualified when the mapping address to be accessed is in the space mapping address range. Wherein, the preset space mapping address range is (MemAddrStart, memAddrStart + (FLSZ mod XIPMEMSZ) -1), and mod represents the remainder operation. Thus, the index range may be qualified if 0.ltoreq.FPI.ltoreq.FPImax. Thus, in the event that the mapping partition index value is desired to be less than the maximum index value, the physical address of the flash memory must be accessible. Therefore, in the case where the mapping partition index value is expected to be smaller than the maximum index value, the index range is determined to be qualified. In the case where it is desired that the mapping partition index value is equal to the maximum index value, the capacity of the QSPI Flash may not be an integer multiple of the capacity of the mapping space. Therefore, the mapping area corresponding to the maximum index value includes the inaccessible excess area. It is necessary to further determine whether the mapped address to be accessed is within the spatial mapped address range, so as to ensure correct access to the flash memory. Referring to fig. 5, a QSPI mapping space 2 is provided on a system on chip memory space 1. Assume that the maximum index value is three. In the case where it is desired that the mapping partition index value is also three, the mapping space address of the QSPI mapping space 2 is mapped to the third mapping region of the QSPI Flash3, but there may be an out-of-range region in the third mapping region.

Optionally, determining whether the index range is qualified according to the comparison result further includes: and under the condition that the index range is determined to be unqualified, error information is displayed to a user.

In some embodiments, the error information is presented to the user by setting the error report through the status register FPS. Thus, since the FPN is configured to

At this time, the CPU may access the out-of-range area. When the out-of-range area is accessed, the status register FPS sets an error. The method can remind the user to change the configuration parameters in time so as to normally access the physical space address of the flash memory.

Optionally, after determining whether the index range is qualified according to the comparison result, the method further includes: obtaining the highest addresses of mapping areas which are respectively accessible by the mapping areas in an XIP mode; and storing the highest address of the mapping area which is accessible by each mapping area in a highest address register of the memory mapping area.

Further, the highest address of the mapping zone accessible to the mapping zone in XIP mode is obtained by: by calculation of

The highest address of the mapping zone that is accessible by the mapping zone in XIP mode is obtained. Wherein MADDR (FPI) is the highest address of the mapping area whose mapping area is FPI.

Optionally, after obtaining the target physical address of the flash memory, the method further includes: and reading the data stored by the target physical address of the flash memory. Thus, the data stored in the target physical address of the flash memory is read, the accessed data is conveniently transmitted back to the CPU, and the CPU is accessed to the flash memory.

Optionally, before obtaining the mapping address to be accessed of the chip, the mapping space starting address of the chip, the physical starting address of the flash memory, the index value of the desired mapping partition, and the mapping space capacity of the chip, the method further includes: and switching the serial flash memory controller into a command mode, and respectively storing different applications or configuration files in each mapping partition of the flash memory in response to an input instruction of a user. In this way, different applications or configuration files are stored in different mapping areas, and because physical isolation exists between the mapping areas, the applications or configuration files stored in the different mapping areas cannot be mutually accessed, and the safety of the applications or configuration files is ensured. Meanwhile, by matching with the method for data access, the application or configuration file of each mapping area can be accessed respectively. And the security of each application or configuration file can be ensured while each application or configuration file is normally accessed.

In some embodiments, the data stored by the target physical address is a user program that the user downloads to the target physical address via command mode. And storing the user program in the plug-in QSPI Flash, and switching to directly execute codes corresponding to the user program stored in the plug-in QSPI Flash in an XIP mode. To facilitate application upgrades, the capacity of QSPI Flash is chosen to be twice the capacity of the QSPI mapping space, i.e., xipmemsz=2×flsz. Under the condition that the user program is stored in the zeroth mapping area, the expected mapping area index value of the serial flash area index value register is configured to be 0, so that the mapping space of the chip system memory is mapped to the zeroth mapping area, and the CPU can directly execute codes in the zeroth mapping area. In the case of an application upgrade, the user downloads the new version of the application to the first mapping zone via the command mode. After the downloading is completed, configuring the index value of the expected mapping partition of the serial flash partition index value register to be 1, and mapping the memory mapping space of the chip system to the first mapping area. In this way, the mapping space of the system memory of the chip can be mapped to the first mapping area, and the CPU accesses the mapping space of the system memory at the moment, so that the CPU is a new application program in the accessed first mapping area. When the application program is updated next time, the user only needs to download the new version of the application program into the zeroth mapping area and configure the serial flash partition index value register to finish the updating of the application program. By means of the method, the application program is updated, the application program of the new version and the application program of the old version exist in the address range of the QSPI mapping space, and because different mapping areas are mutually and physically isolated, in the XIP mode, the inactive mapping area cannot be damaged, and the integrity of the application program of the old version can be protected. Under the condition that the application program of the new version is accidentally destroyed, the application program can be immediately switched to the application program of the old version, thereby maintaining the stable operation of the application program.

In some embodiments, if the capacity of QSPI Flash is selected to be N times the capacity of the QSPI mapping space, i.e., xipmemsz=n×flsz. The user can store different applications or configuration files in different mapping areas according to different requirements, and the applications or configuration files stored in the different mapping areas cannot be accessed mutually due to physical isolation between the mapping areas, so that the safety of each application or configuration file is ensured.

Referring to FIG. 6, an embodiment of the present disclosure provides an apparatus 12 for data access for use with a serial flash controller in an on-chip execution mode; the apparatus for data access includes: an acquisition module 13, a determination module 14 and a calculation module 15. The system comprises an acquisition module, a memory module and a memory module, wherein the acquisition module is configured to acquire a mapping address to be accessed of a chip, a mapping space starting address of the chip, a physical starting address of a flash memory, an index value of an expected mapping partition and a mapping space capacity of the chip; a determining module configured to determine whether the index range is acceptable according to the desired mapping partition index value; the calculation module is configured to calculate by using the mapping address to be accessed, the mapping space starting address, the physical starting address, the expected mapping partition index value and the mapping space capacity according to a first preset algorithm under the condition that the index range is qualified, and obtain the target physical address of the flash memory.

By adopting the device for data access provided by the embodiment of the disclosure, the to-be-accessed mapping address of the chip, the mapping space starting address of the chip, the physical starting address of the flash memory, the expected mapping partition index value and the mapping space capacity of the chip are obtained through the obtaining module. The determining module determines whether the index range is qualified according to the index value of the desired mapping partition. And the calculation module calculates by utilizing the mapping address to be accessed, the mapping space starting address, the physical starting address, the index value of the expected mapping partition and the mapping space capacity according to a first preset algorithm under the condition that the index range is qualified, and obtains the target physical address of the flash memory. In this way, in the on-chip execution mode of the serial flash controller, all internal physical addresses in the flash memory can be accessed by dynamically changing the mapping relationship between the mapping address to be accessed and the target physical address. Therefore, in the on-chip execution mode of the serial flash memory controller, the space utilization rate of the flash memory is conveniently improved.

Optionally, the determining module is configured to determine whether the index range is acceptable according to the desired mapping partition index value in the following manner: acquiring the expected flash memory capacity; calculating according to a second preset algorithm by using the expected flash memory capacity and the mapping space capacity to obtain a maximum index value; comparing the maximum index value with the index value of the expected mapping partition, and determining whether the index range is qualified according to the comparison result.

Further, the determining module is configured to determine whether the index range is acceptable according to the comparison result in the following manner: determining that the index range is qualified under the condition that the index value of the expected mapping partition is smaller than the maximum index value; and/or determining whether the mapping address to be accessed is in a preset space mapping address range or not under the condition that the index value of the expected mapping partition is equal to the maximum index value; and determining that the index range is qualified when the mapping address to be accessed is in the space mapping address range.

Optionally, the apparatus for data access further comprises: and the reading module is configured to read the data stored by the target physical address of the flash memory after the target physical address of the flash memory is obtained.

As shown in connection with fig. 7, an embodiment of the present disclosure provides an electronic device 11 including a processor (processor) 17 and a memory (memory) 18. Optionally, the apparatus may further comprise a communication interface (Communication Interface) 19 and a bus 20. The processor 17, the communication interface 19 and the memory 18 may communicate with each other via a bus 20. The communication interface 19 may be used for information transfer. The processor 17 may call logic instructions in the memory 18 to perform the method for data access of the above-described embodiments.

By adopting the electronic equipment provided by the embodiment of the disclosure, the mapping address to be accessed of the chip, the mapping space starting address of the chip, the physical starting address of the flash memory, the index value of the expected mapping partition and the mapping space capacity of the chip are obtained. And determining whether the index range is qualified according to the index value of the expected mapping partition. And under the condition that the index range is qualified, calculating according to a first preset algorithm by using the to-be-accessed mapping address, the mapping space starting address, the physical starting address, the index value of the expected mapping partition and the mapping space capacity to obtain the target physical address of the flash memory. In this way, in the on-chip execution mode of the serial flash controller, all internal physical addresses in the flash memory can be accessed by dynamically changing the mapping relationship between the mapping address to be accessed and the target physical address. Therefore, in the on-chip execution mode of the serial flash memory controller, the space utilization rate of the flash memory is conveniently improved.

Further, the logic instructions in the memory 18 described above may be implemented in the form of software functional units and stored in a computer readable storage medium when sold or used as a stand alone product.

The memory 18 is a computer readable storage medium that can be used to store a software program, a computer executable program, such as program instructions/modules corresponding to the methods in the embodiments of the present disclosure. The processor 17 executes the functional applications and data processing by running the program instructions/modules stored in the memory 18, i.e. implements the method for data access in the above-described embodiments.

The memory 18 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, at least one application program required for a function; the storage data area may store data created according to the use of the terminal device, etc. In addition, the memory 18 may include high-speed random access memory, and may also include nonvolatile memory.

Embodiments of the present disclosure provide a computer-readable storage medium storing computer-executable instructions configured to perform the above-described method for data access.

The disclosed embodiments provide a computer program product comprising a computer program stored on a computer readable storage medium, the computer program comprising program instructions which, when executed by a computer, cause the computer to perform the above-described method for data access.

The computer readable storage medium may be a transitory computer readable storage medium or a non-transitory computer readable storage medium.

Embodiments of the present disclosure may be embodied in a software product stored on a storage medium, including one or more instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of a method according to embodiments of the present disclosure. And the aforementioned storage medium may be a non-transitory storage medium including: a plurality of media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or a transitory storage medium.

The above description and the drawings illustrate embodiments of the disclosure sufficiently to enable those skilled in the art to practice them. Other embodiments may involve structural, logical, electrical, process, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in, or substituted for, those of others. Moreover, the terminology used in the present application is for the purpose of describing embodiments only and is not intended to limit the claims. As used in the description of the embodiments and the claims, the singular forms "a," "an," and "the" (the) are intended to include the plural forms as well, unless the context clearly indicates otherwise. Similarly, the term "and/or" as used in this application is meant to encompass any and all possible combinations of one or more of the associated listed. Furthermore, when used in this application, the terms "comprises," "comprising," and/or "includes," and variations thereof, mean that the stated features, integers, steps, operations, elements, and/or components are present, but that the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof is not precluded. Without further limitation, an element defined by the phrase "comprising one …" does not exclude the presence of other like elements in a process, method or apparatus comprising such elements. In this context, each embodiment may be described with emphasis on the differences from the other embodiments, and the same similar parts between the various embodiments may be referred to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method sections disclosed in the embodiments, the description of the method sections may be referred to for relevance.

Those of skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. The skilled artisan may use different methods for each particular application to achieve the described functionality, but such implementation should not be considered to be beyond the scope of the embodiments of the present disclosure. It will be clearly understood by those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, which are not repeated herein.

In the embodiments disclosed herein, the disclosed methods, articles of manufacture (including but not limited to devices, apparatuses, etc.) may be practiced in other ways. For example, the apparatus embodiments described above are merely illustrative, and for example, the division of the units may be merely a logical function division, and there may be additional divisions when actually implemented, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. In addition, the coupling or direct coupling or communication connection shown or discussed with each other may be through some interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form. The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to implement the present embodiment. In addition, each functional unit in the embodiments of the present disclosure may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. In the description corresponding to the flowcharts and block diagrams in the figures, operations or steps corresponding to different blocks may also occur in different orders than that disclosed in the description, and sometimes no specific order exists between different operations or steps. For example, two consecutive operations or steps may actually be performed substantially in parallel, they may sometimes be performed in reverse order, which may be dependent on the functions involved. Each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

Claims

1. A method for data access, characterized by being applied to a serial flash memory controller, the serial flash memory controller being in an on-chip execution mode; the method for data access comprises the following steps:

acquiring a mapping address to be accessed of a chip, a mapping space initial address of the chip, a physical initial address of a flash memory, an index value of an expected mapping partition and a mapping space capacity of the chip;

determining whether the index range is qualified according to the index value of the expected mapping partition;

and under the condition that the index range is qualified, calculating according to a first preset algorithm by using the mapping address to be accessed, the mapping space starting address, the physical starting address, the index value of the expected mapping partition and the mapping space capacity to obtain the target physical address of the flash memory.

2. The method of claim 1, wherein determining whether an index range is acceptable based on the desired mapped partition index value comprises:

acquiring the expected flash memory capacity;

calculating according to a second preset algorithm by utilizing the expected flash memory capacity and the mapping space capacity to obtain a maximum index value;

and comparing the maximum index value with the index value of the expected mapping partition, and determining whether the index range is qualified according to a comparison result.

3. The method of claim 2, wherein determining whether the index range is acceptable based on the comparison result comprises:

determining that the index range is qualified under the condition that the index value of the expected mapping partition is smaller than the maximum index value; and/or the number of the groups of groups,

determining whether the mapping address to be accessed is in a preset space mapping address range or not under the condition that the index value of the expected mapping partition is equal to the maximum index value; and determining that the index range is qualified when the mapping address to be accessed is in the space mapping address range.

4. A method according to any one of claims 1 to 3, further comprising, after obtaining the target physical address of the flash memory:

and reading the data stored by the target physical address of the flash memory.

5. An apparatus for data access, characterized by being applied to a serial flash memory controller, said serial flash memory controller being in an on-chip execution mode; the apparatus for data access includes:

the system comprises an acquisition module, a memory module and a memory module, wherein the acquisition module is configured to acquire a mapping address to be accessed of a chip, a mapping space starting address of the chip, a physical starting address of a flash memory, an index value of an expected mapping partition and a mapping space capacity of the chip;

A determining module configured to determine whether an index range is qualified according to the desired mapping partition index value;

the calculation module is configured to calculate, according to a first preset algorithm, the target physical address of the flash memory by using the address to be accessed, the mapping space starting address, the physical starting address, the index value of the expected mapping partition and the mapping space capacity under the condition that the index range is qualified.

6. The apparatus of claim 5, wherein the determining module is configured to determine whether an index range is acceptable based on the desired mapped partition index value by:

acquiring the expected flash memory capacity;

7. The apparatus of claim 6, wherein the determining module is configured to determine whether the index range is acceptable based on the comparison result in the following manner:

8. The apparatus according to any of claims 5 to 7, wherein the apparatus for data access further comprises:

and the reading module is configured to read the data stored by the target physical address of the flash memory after the target physical address of the flash memory is obtained.

9. An electronic device comprising a processor and a memory storing program instructions, wherein the processor is configured to perform the method for data access of any of claims 1 to 4 when executing the program instructions.

10. A storage medium storing program instructions which, when executed, perform the method for data access of any one of claims 1 to 4.