CN117690786A - Semiconductor structure, scribe line structure and forming method thereof - Google Patents

Semiconductor structure, scribe line structure and forming method thereof Download PDF

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Publication number
CN117690786A
CN117690786A CN202211029656.7A CN202211029656A CN117690786A CN 117690786 A CN117690786 A CN 117690786A CN 202211029656 A CN202211029656 A CN 202211029656A CN 117690786 A CN117690786 A CN 117690786A
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China
Prior art keywords
trimmed
hard mask
layer
mask layer
substrate
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CN202211029656.7A
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Chinese (zh)
Inventor
张雁红
杨鹏
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to CN202211029656.7A priority Critical patent/CN117690786A/en
Priority to PCT/CN2023/110796 priority patent/WO2024041339A1/en
Publication of CN117690786A publication Critical patent/CN117690786A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Abstract

The invention provides a semiconductor structure, a dicing channel structure and a forming method thereof. The method for forming the cutting channel structure comprises the following steps: forming a stacking layer on a substrate, defining a plurality of areas to be trimmed, and covering at least one pattern to be trimmed in each area to be trimmed; and etching the stacked layers and trimming the pattern to be trimmed on the basis of the area to be trimmed. Namely, the invention can realize trimming of the graph to be trimmed by forming the stacked layers and defining the area to be trimmed, reduce the step height caused by trimming of the graph to be trimmed, reduce the load effect, reduce the defects and further improve the yield of products.

Description

Semiconductor structure, scribe line structure and forming method thereof
Technical Field
The present disclosure relates to semiconductor technology, and more particularly, to a semiconductor structure, a scribe line structure, and a method of forming the same.
Background
With the continuous reduction of the size of the dynamic random access memory (Dynamic Random Access Memory, DRAM), the problem of the loading effect of the scribe line area becomes more and more obvious, and especially, the damage of the mark pattern is easily caused at the place of the large trench, and the peeling of the defect into the chip is easily caused, which results in the reduction of the yield.
Therefore, it is desirable to provide a semiconductor structure, a scribe line structure and a method for forming the same to solve the problem of loading effect in the scribe line region.
Disclosure of Invention
The invention aims to provide a semiconductor structure, a dicing channel structure and a forming method thereof, so as to solve the problem of the loading effect of the dicing channel area.
To achieve the above and other related objects, the present invention provides a method for forming a scribe line structure, comprising the steps of:
providing a substrate, defining a cutting channel region on the substrate, and forming a plurality of patterns to be trimmed on the substrate of the cutting channel region;
forming a stacked layer on the substrate, and defining a plurality of areas to be trimmed on the stacked layer, wherein each area to be trimmed covers at least one pattern to be trimmed;
etching the stacked layer of the area to be trimmed to form a patterned stacked layer;
and trimming the pattern to be trimmed by taking the patterned stacked layer as a mask to obtain a trimmed pattern.
Optionally, in the method for forming a scribe line structure, the step of defining a plurality of areas to be trimmed on the stacked layers includes:
forming a photoresist layer on the stacked layers;
the photoresist layer is exposed and developed to define a plurality of areas to be trimmed.
Optionally, in the method for forming a scribe line structure, each of the areas to be trimmed covers one of the patterns to be trimmed, so as to trim each of the patterns to be trimmed.
Optionally, in the method for forming a scribe line structure, a horizontal distance between a side edge of the to-be-trimmed region and a side edge of the same side of the to-be-trimmed pattern covered by the to-be-trimmed region is 30nm to 50nm.
Optionally, in the method for forming a scribe line structure, the stacked layer includes a first hard mask layer, a second hard mask layer, a third hard mask layer, a fourth hard mask layer, and a fifth hard mask layer sequentially from bottom to top.
Optionally, in the method for forming a scribe line structure, the material of the first hard mask layer includes at least one of amorphous carbon, an amorphous carbon layer, and a diamond-like carbon coating; and/or
The material of the second hard mask layer comprises SiON and/or SiCN; and/or
The material of the third hard mask layer comprises silicon oxide; and/or
The fourth hard mask layer is made of SOH; and/or
The fifth hard mask layer is made of SiON and/or SiCN.
Optionally, in the method for forming a scribe line structure, the stacked layer further includes a bottom anti-reflection layer, and the bottom anti-reflection layer is located on the fifth hard mask layer.
Optionally, in the method for forming a scribe line structure, the material of the bottom anti-reflective layer includes at least one of SiON, silicon oxide, and tetraethyl orthosilicate.
Optionally, in the method for forming a scribe line structure, the forming process of the fourth hard mask layer includes a spin coating process, and the forming processes of the first hard mask layer, the second hard mask layer, the third hard mask layer, and the fifth hard mask layer each independently include one of CVD, ALD, and PVD.
Optionally, in the method for forming a scribe line structure, a plurality of chip regions are further defined on the substrate, and the scribe line regions are located between adjacent chip regions.
Optionally, in the method for forming a scribe line structure, in the step of forming a stacked layer on the substrate, the stacked layer further covers the substrate corresponding to each of the chip regions.
Optionally, in the method for forming a scribe line structure, the step of trimming the pattern to be trimmed using the patterned stacked layer as a mask includes: and etching the substrate by taking the patterned stacked layer as a mask so as to form a plurality of groove structures on the substrate at the corresponding positions of the pattern to be trimmed.
To achieve the above and other related objects, the present invention also provides a dicing street structure comprising:
a plurality of trimmed patterns positioned in scribe line areas on the substrate;
and the groove structures are positioned on the trimmed patterns, and each groove structure at least covers one trimmed pattern.
Optionally, in the scribe line structure, each of the groove structures covers one of the trimmed patterns, and a horizontal distance between a side edge of the groove structure and a side edge of the same side of the trimmed pattern covered by the groove structure is 30nm to 50nm.
To achieve the above and other related objects, the present invention also provides a semiconductor structure comprising:
a substrate on which a plurality of chip regions and scribe line regions between adjacent chip regions are defined;
the dicing street structure described above, wherein the dicing street structure is located in the dicing street region on the substrate.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
the method comprises the steps of forming a stacked layer on a substrate, defining a plurality of areas to be trimmed, covering at least one pattern to be trimmed in each area to be trimmed, and trimming the pattern to be trimmed on the substrate after etching the stacked layer in the area to be trimmed. Compared with the prior art that a plurality of patterns to be trimmed are integrally trimmed, the trimming of the patterns to be trimmed can be regulated and controlled by reducing the area to be trimmed, for example, trimming of a single pattern to be trimmed can be realized, the etching depth of the substrate can be reduced, the step height caused by etching the substrate is reduced, the load effect can be reduced, the defects are reduced, and the yield of products is improved.
Drawings
FIG. 1 is a schematic view showing a structure in which a trimming area covers a pattern to be trimmed arranged in one direction;
FIG. 2 is a schematic view showing a structure in which a trimming area covers a pattern to be trimmed arranged in another direction;
FIG. 3 is a schematic view of the structure of a scribe line area before trimming the pattern to be trimmed;
FIG. 4 is a schematic view of the structure of the scribe line area after trimming the pattern to be trimmed;
FIG. 5 is a flowchart of a method for forming a scribe line structure according to an embodiment of the invention;
FIG. 6 is a schematic view of stacked layers of scribe line regions according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of the structure of stacked layers of a chip area according to an embodiment of the invention;
FIG. 8 is a schematic diagram of a product structure after the scribe line region performs step S2 in the method for manufacturing a scribe line structure according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of a product structure after the scribe line region performs step S4 in the method for manufacturing a scribe line structure according to an embodiment of the present invention;
FIG. 10 is a schematic diagram of a chip area after trimming according to an embodiment of the present invention;
FIG. 11 is a schematic view of a structure of a to-be-trimmed region covering a to-be-trimmed pattern arranged along one direction according to an embodiment of the invention;
FIG. 12 is a schematic view showing a structure in which a region to be trimmed covers a pattern to be trimmed arranged in another direction according to an embodiment of the invention;
in fig. 1 to 4:
011-a dielectric layer, 012-an oxide layer, 013-a graph to be trimmed and 02-a trimming area;
fig. 5 to 12:
101-dielectric layer, 102-oxide layer, 103-pattern to be trimmed, 20-stacked layer, 201-first hard mask layer, 202-second hard mask layer, 203-third hard mask layer, 204-fourth hard mask layer, 205-fifth hard mask layer, 301-photoresist layer pattern unit, 40-region to be trimmed.
Detailed Description
The semiconductor structure, the scribe line structure and the method of forming the same according to the present invention are described in further detail below with reference to the accompanying drawings and specific examples. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
After patterning, the semiconductor structure is subjected to trimming, which mainly includes trimming of critical dimensions and trimming of excess patterns. In the process of the dynamic random access memory, the patterns of the chip area are mainly trimmed for critical dimensions, and the patterns of the scribe line area are mainly used for alignment marks, so that a plurality of patterns unrelated to the mark patterns (i.e., patterns to be trimmed) need to be trimmed. The pattern of the scribe line area is more, and the scribe line area can be oriented in any direction according to the process design. For example, fig. 1 shows a plurality of to-be-trimmed patterns 013 arranged in a first direction, and fig. 2 shows a plurality of to-be-trimmed patterns 013 arranged in a second direction, the first direction being different from the second direction, and further, the first direction being perpendicular to the second direction. In the prior art, when the to-be-trimmed graphics 013 are trimmed, the adjacent to-be-trimmed graphics 013 are trimmed together as a whole. That is, the existing process of forming the scribe line structure is to directly trim after forming the pattern to be trimmed 013, and not form a stacked layer, so that the etching range cannot be well controlled in the prior art, the pattern to be trimmed 013 in the whole area is generally etched together, that is, a plurality of patterns to be trimmed 013 are trimmed together, trimming of the pattern to be trimmed 013 cannot be regulated and controlled, each pattern to be trimmed 013 cannot be trimmed independently, and the whole pattern to be trimmed 013 is covered by the final trimming area 02.
Referring to fig. 3, a schematic diagram of the structure of the scribe line area before trimming the pattern to be trimmed 013 is shown, and fig. 4, a schematic diagram of the structure of the scribe line area after trimming the pattern to be trimmed 013 is shown. Referring to fig. 3 and 4, the conventional method for forming the scribe line structure is as follows: forming a trench in a dielectric layer 011 of the substrate; forming an oxide layer 012 covering the dielectric layer 011 and filling the trench, wherein the trench filled with the oxide layer 012 is used as a pattern of a scribe line region, and determining which patterns in the scribe line region belong to the pattern to be trimmed 013 according to a known alignment mark pattern; after determining the pattern to be trimmed 013, trimming the pattern to be trimmed 013 directly to obtain a trimmed structure, see fig. 4. And the overall to-be-trimmed pattern 013 is trimmed together, the formed opening is relatively large, the step height after etching is relatively large, the overall load effect problem is relatively obvious, particularly, the damage of important patterns (such as mark patterns) on the periphery of the to-be-trimmed pattern can be easily caused at the place of a large groove, and the situation that defects are peeled off to the inside of a chip easily occurs, so that the yield is reduced.
Therefore, it is necessary to provide a method for forming a scribe line structure to reduce the step height after etching, thereby reducing the loading effect, reducing the probability of occurrence of flaking defects, and improving the yield of the product.
Referring to fig. 5, the present invention provides a method for forming a scribe line structure, comprising the following steps:
step S1: providing a substrate, defining a cutting channel region on the substrate, and forming a plurality of patterns to be trimmed on the substrate of the cutting channel region;
step S2: forming a stacked layer on the substrate, and defining a plurality of areas to be trimmed on the stacked layer, wherein each area to be trimmed covers at least one pattern to be trimmed;
step S3: etching the stacked layer of the area to be trimmed to form a patterned stacked layer;
step S4: and trimming the pattern to be trimmed by taking the patterned stacked layer as a mask to obtain a trimmed pattern.
Referring to fig. 6 and 7, step S1 is performed to provide a substrate. The substrate may include a base on which a structural layer is formed. The substrate may comprise a single material, multiple layers of different materials, one or more structural layers with regions of different materials or different structural patterns, etc. These materials may include semiconductors, insulators, conductors, or combinations thereof. The substrate shown in fig. 6 and 7 may include a base (not shown), a dielectric layer 101, a trench formed in the dielectric layer 101, and an oxide layer 102 covering the dielectric layer 101 and filling the trench, and the oxide layer 102 is preferably silicon oxide, but is not limited thereto. Alternatively, the substrate may be formed by sequentially disposing the above-described multi-layer structure on a base by a thin film deposition process such as CVD (Chemical Vapor Deposition ), PVD (Physical Vapor Deposition, physical vapor deposition), ALD (Atomic Layer Deposition ), or any combination thereof.
The substrate may define a plurality of chip regions and a plurality of scribe line regions between adjacent ones of the chip regions. The trenches filled with oxide layer 102 on the substrate act as a pattern of scribe line regions and chip regions. The pattern of the scribe line region and the chip region may be various, for example, but not limited to, a buried word line. Since the pattern of the scribe line region only needs to be able to ensure that the subsequent mark alignment is achieved, the scribe line region only needs to retain a small amount of pattern, i.e., the pattern of a portion of the scribe line region needs to be trimmed. The embodiment can determine the pattern 103 to be trimmed in the cutting path area according to the designed mark pattern. Referring to fig. 6, a pattern 103 to be trimmed is shown for the scribe line area.
In this embodiment, the trimming is performed on the pattern to be trimmed 103, and simultaneously, other patterns (for example, a mark pattern) of the scribe line region and the pattern of the chip region may be trimmed, for example, the trimming is performed on the critical dimension of the pattern of the chip region while trimming the pattern to be trimmed 103, so that the final critical dimension of the pattern of the chip region is closer to the target value.
With continued reference to fig. 6, step S2 is performed to form a stacked layer 20 on the substrate, and define a plurality of regions to be trimmed 40 on the stacked layer 20.
During the formation of the stack 20, the stack 20 may cover the channel region and the substrate of the chip region at the same time.
The stacked layer 20 includes, in order from bottom to top, a first hard mask layer 201, a second hard mask layer 202, a third hard mask layer 203, a fourth hard mask layer 204, and a fifth hard mask layer 205. I.e., a first hard mask layer 201, a second hard mask layer 202, a third hard mask layer 203, a fourth hard mask layer 204, and a fifth hard mask layer 205 are formed on the substrate of each of the channel region and the chip region, see fig. 6. The thicknesses of the first hard mask layer 201, the second hard mask layer 202, the third hard mask layer 203, the fourth hard mask layer 204, and the fifth hard mask layer 205 may be set according to actual requirements.
The step of forming the stacked layer 20 on the substrate specifically includes: the first hard mask layer 201, the second hard mask layer 202, the third hard mask layer 203, the fourth hard mask layer 204, and the fifth hard mask layer 205 are sequentially formed on the substrate.
With continued reference to fig. 6, a first hard mask layer 201 is formed over the oxide layer 102 of the substrate. The material of the first hard mask layer 201 is preferably at least one of amorphous carbon, amorphous Carbon (ACL) and diamond-like carbon (DLC), but not limited thereto, and for example, the material of the first hard mask layer 201 may be SOH (spin on hardmask; hard mask upper rotator). The material of the first hard mask layer 201 is preferably amorphous carbon, which has the advantage of being easier to etch than the second hard mask layer 202 to the fifth hard mask layer 205, and can be more easily provided as a thicker layer, thus enabling the formation of a transfer pattern having higher characteristics.
After forming the first hard mask layer 201, the second hard mask layer 202 is formed on the first hard mask layer 201. The material of the second hard mask layer 202 is preferably silicon oxynitride (SiON) and/or SiCN, but is not limited thereto.
After forming the second hard mask layer 202, the third hard mask layer 203 is formed on the second hard mask layer 202. The material of the third hard mask layer 203 is preferably silicon oxide, but is not limited thereto.
After forming the third hard mask layer 203, the fourth hard mask layer 204 is formed on the third hard mask layer 203. The material of the fourth hard mask layer 204 is preferably SOH (spin on hardmask; spin on hard mask), but is not limited thereto. The fourth hard mask layer 204 may be formed by a spin coating process, but is not limited thereto. The SOH may include a silicon hard mask material, a carbon hard mask material, an organic hard mask material, and the like.
After forming the fourth hard mask layer 204, the fifth hard mask layer 205 is formed on the fourth hard mask layer 204. The fifth hard mask layer 205 is preferably made of SiON and/or SiCN, but is not limited thereto.
In the present embodiment, the forming processes of the first hard mask layer 201, the second hard mask layer 202, the third hard mask layer 203, and the fifth hard mask layer 205 each independently include one of CVD, ALD, and PVD, but are not limited thereto. The CVD may be PECVD (Plasma Enhanced Chemical Vapor Deposition ), HDPCVD (High Density Plasma Chemical Vapor Deposition, high density plasma chemical vapor deposition) or MOCVD (Metal Organic Chemical Vapor DePosition ), but is not limited thereto. For example, amorphous carbon is deposited on the oxide layer 102 of the substrate using a CVD process to form the first hard mask layer 201; then depositing silicon oxynitride on the first hard mask layer 201 using a CVD process to form a second hard mask layer 202; next, depositing silicon oxide on the second hard mask layer 202 by using a CVD process to form a third hard mask layer 203; spin-coating SOH on the third hard mask layer 203 using a spin-coating process to form the fourth hard mask layer 204; finally, a CVD process is used to deposit silicon oxynitride on the fourth hard mask layer 204 to form a fifth hard mask layer 205.
The stacked layer 20 may further include a bottom anti-reflective layer (BARC) (not shown) on the fifth hard mask layer 205. The bottom anti-reflection layer may be formed by CVD (e.g., PECVD, HDPCVD or MOCVD), ALD or PVD, etc. The bottom anti-reflection layer may be made of one or more of SiON, silicon oxide or tetraethyl orthosilicate, but is not limited thereto. SiON is deposited on the fifth hard mask layer 205, for example, using a CVD process, to form the bottom antireflective layer.
The bottom anti-reflection layer is made of an anti-reflection material capable of effectively eliminating light reflection to form standing waves, the bottom anti-reflection layer is added between the photoresist layer and the substrate, the exposure energy range (EL) and the focal length (DOF) can be increased, the influence on the uniformity of CD (critical dimension) caused by the difference of the geometric structures of the substrate is reduced, meanwhile, the pattern notch caused by scattering of reflected light caused by sharp edges of the substrate is reduced, the swing curve effect caused by different thicknesses of the photoresist caused by the configuration of the substrate is relieved, and therefore, a better photoetching pattern can be obtained under smaller line width.
The method for forming the stacked layer 20 may further include, before forming the third hard mask layer 203: a seventh hard mask layer and an eighth hard mask layer (not shown) are sequentially formed on the second hard mask layer 202, and the seventh hard mask layer are sequentially etched to form openings. After forming the opening, a forming process of the third hard mask layer 203 is performed. The seventh hard mask layer and the eighth hard mask layer of the scribe line region are etched completely, and only a portion of the seventh hard mask layer and the eighth hard mask layer of the chip region is left, and the seventh hard mask layer is made of the same material as the fourth hard mask layer 204, and the eighth hard mask layer is made of the same material as the fifth hard mask layer 205, as shown in fig. 7.
Referring to fig. 8, after the stacked layers 20 are formed, a step of defining a plurality of regions to be trimmed 40 is performed. The defining of the plurality of areas to be trimmed 40 may include:
step S24: forming a photoresist layer on the stacked layer 20;
step S25: the photoresist layer is exposed and developed to define the plurality of regions to be trimmed 40.
In step S24, after the bottom anti-reflection layer is formed, a photoresist layer is spin-coated on the bottom anti-reflection layer. The photoresist layer covers not only the stack layer 20 of the scribe line region but also the stack layer 20 of the chip region.
The photoresist layer may be made of a material including a negative photoresist and a positive photoresist, for example, the photoresist layer may be made of a phenol-formaldehyde polymer. The illumination may alter the chemical structure of the photoresist layer and the exposed portions of the photoresist layer or the unexposed portions of the photoresist layer may be removed by a chemical solvent.
In step S25, the photoresist layer is exposed and developed to form a patterned photoresist layer. And exposing and developing the photoresist layer may form a plurality of openings on the photoresist layer, and a photoresist layer pattern unit 301 between the openings. The opening exposes a part of the area of the stacked layer 20, the to-be-trimmed area 40 is an area corresponding to a part of the opening, specifically, an opening corresponding to the to-be-trimmed pattern 103, and the openings at other positions are used for trimming critical dimensions and other trimming of other patterns (such as a mark pattern) of the scribe line area and patterns of the chip area.
In this embodiment, each of the to-be-trimmed areas 40 covers at least one of the to-be-trimmed patterns 103, that is, each of the to-be-trimmed areas 40 may cover one of the to-be-trimmed patterns 103, or may cover a plurality of the to-be-trimmed patterns 103 at the same time. Preferably, each of the to-be-trimmed areas 40 covers one of the to-be-trimmed patterns 103. Since the smaller the area covered by each of the regions 40 to be trimmed is, the smaller the opening formed in the photoresist layer is, and the smaller the opening of the groove structure formed by finally etching the substrate is, the less etching gas is accumulated in the groove structure, and further the lower the step height after etching is, the smaller the loading effect is, the defects are reduced, and the higher the yield of the product is, it is preferable that each of the regions 40 to be trimmed covers one of the patterns 103 to be trimmed. The cross-sectional area of each to-be-trimmed region 40 perpendicular to the growth direction of the stacked layer 20 is larger than the cross-sectional area of the corresponding to-be-trimmed pattern 103 perpendicular to the growth direction of the stacked layer 20, so as to achieve that the to-be-trimmed region 40 completely covers the corresponding to-be-trimmed pattern 103. In this embodiment, the horizontal distance between the side edge of the to-be-trimmed region 40 and the side edge of the same side of the to-be-trimmed pattern 103 covered by the to-be-trimmed region 40 is preferably 30nm to 50nm, specifically, the to-be-trimmed region 40 and all the to-be-trimmed patterns 103 covered by the to-be-trimmed region 40 may be projected on the same horizontal plane, and on the horizontal plane, the distance between the side edge of the to-be-trimmed region 40 and the side edge of the same side of the to-be-trimmed patterns 103 covered by the to-be-trimmed region 40 is preferably 30nm to 50nm. For example, when each of the to-be-trimmed regions 40 covers one of the to-be-trimmed patterns 103, a horizontal distance between a side of each of the to-be-trimmed regions 40 and a same side of the covered to-be-trimmed pattern 103 is 40nm.
Step S3 is performed to etch the stacked layer 20 of the to-be-trimmed region 40 to form a patterned stacked layer. As an example, the fifth hard mask layer 205, the fourth hard mask layer 204, the third hard mask layer 203, the second hard mask layer 202, and the first hard mask layer 201 may be sequentially etched using, but not limited to, a dry etching process. When the bottom anti-reflection layer is formed on the fifth hard mask layer 205, dry etching is required to etch the bottom anti-reflection layer first, and then the fifth hard mask layer 205, the fourth hard mask layer 204, the third hard mask layer 203, the second hard mask layer 202 and the first hard mask layer 201 are etched in sequence. The etching gas of the dry etching can be Cl 2 、BCl 3 Etc., but is not limited thereto. It should be noted that during the etching process, the patterned photoresist layer is partially removed by the etching plasma, but some of the patterned photoresist layer remains to protect the stacked layer 20 under the photoresist pattern 301 and over the substrate from being etched. The remaining stacked layers 20 under the photoresist pattern unit 301 constitute the stacked layer pattern unit.
At the same time of etching the stacked layer 20 on the substrate of the scribe line region, the stacked layer 20 on the substrate of the chip region is also etched, and the photoresist pattern unit 301 on the stacked layer 20 of the chip region may be designed according to the process requirements. That is, when the bottom anti-reflection layer, the fifth hard mask layer 205, the fourth hard mask layer 204, the third hard mask layer 203, the second hard mask layer 202 and the first hard mask layer 201 of the scribe line region are sequentially etched, the bottom anti-reflection layer, the fifth hard mask layer 205, the fourth hard mask layer 204, the third hard mask layer 203, the second hard mask layer 202 and the first hard mask layer 201 of the chip region are also sequentially etched simultaneously. For example, the bottom reflective layer of the die area is etched simultaneously when the bottom reflective layer of the scribe line area is etched.
After etching the stacked layers 20 of the to-be-trimmed region 40, the method for forming the scribe line structure further includes: and removing the patterned photoresist layer. In other embodiments, the removal process of the patterned photoresist layer may also be disposed after the trimming step of each of the to-be-trimmed patterns 103.
The method for removing the patterned photoresist layer is preferably an ashing process, but is not limited thereto. Currently, the ashing process is performed using a plasma gas containing oxygen radicals or oxygen ions to remove the photoresist layer, and the ashing process is generally performed by heating at a low pressure and introducing the plasma gas into the reaction chamber. Since the ashing rate of the ashing process is proportional to the temperature, the ashing process is generally performed at a high temperature, and the ashing temperature is generally 80 to 300 ℃. The ashing process removes the remaining photoresist layer in the die area, i.e., the patterned photoresist layer, as well as the remaining photoresist layer in the scribe line area, i.e., the ashing process removes all of the remaining photoresist layer.
Referring to fig. 9, step S4 is performed to trim the pattern to be trimmed 103 using the patterned stacked layer as a mask. Namely, the patterned stacked layer is used as a mask to etch the substrate, and a plurality of groove structures are formed on the substrate at the corresponding positions of the to-be-trimmed regions 40, so as to trim the to-be-trimmed patterns 103. In this embodiment, each groove structure may trim a plurality of the to-be-trimmed patterns 103, or may trim only one of the to-be-trimmed patterns 103. Preferably, each groove structure clips only one of the patterns to be trimmed 103. Because the groove structures correspond to the to-be-trimmed areas 40, the smaller the area covered by each to-be-trimmed area 40 is, the smaller the opening of the corresponding formed groove structure is, the less etching gas is accumulated in the groove structure, the lower the step height after etching is, the smaller the loading effect is, the defects are reduced, and the higher the yield of the product is.
While trimming the pattern to be trimmed 103, the etching gas etches the substrate at other positions of the scribe line region and the substrate of the chip region to trim other patterns (e.g., mark patterns) of the scribe line region and critical dimensions of the pattern of the chip region, etc. For example, referring to fig. 10, a plurality of grooves are formed on the substrate of the scribe line region, and a plurality of grooves are formed on the substrate of the chip region. And the stopping condition for etching the substrate, namely the condition for stopping introducing etching gas is as follows: and stopping the introduction of etching gas when the depth of the groove in the chip area reaches a target value, wherein the target value can be designed according to the process requirement.
In step S4, the etching gas may be Cl 2 、BCl 3 Etc., but is not limited thereto. In the etching process, the oxide layer 102 and the dielectric layer 101 on the substrate are partially removed under the action of the etching plasma, so as to implement trimming of the pattern to be trimmed 103, trimming of the mark pattern and the chip area pattern, and the like.
Referring to fig. 11 and 12, since each of the to-be-trimmed regions 40 covers at least one of the to-be-trimmed patterns 103, and the finally formed groove structure corresponds to the to-be-trimmed region 40, the width of the groove structure is greater than the width of all of the to-be-trimmed patterns 103 covered by the groove structure. For example, when each of the to-be-trimmed areas 40 covers one of the to-be-trimmed patterns 103, the width of the groove structure is larger than the width of one of the to-be-trimmed patterns 103 covered by the groove structure.
In the etching process, each of the areas to be trimmed 40 may trim one of the graphics to be trimmed 103 or a plurality of the graphics to be trimmed 103, and in this embodiment, trimming adjustment of the graphics to be trimmed 103 may be achieved by adjusting the size of the area to be trimmed 40. Compared with the prior art that a plurality of patterns to be trimmed are trimmed integrally, the width of the groove structure of the cutting channel area in the embodiment can be adjusted, that is, the opening size of the groove structure can be adjusted, and only one pattern 103 to be trimmed can be trimmed by one groove structure, so that the opening of the groove structure in the embodiment can be reduced, etching gas can be less, and accumulation can be less. And stopping introducing etching gas when the groove formed by etching the chip area reaches the target value, wherein the time for stopping etching is shorter because less etching gas is accumulated in the groove structure of the cutting channel area, so that the final step height is reduced, and the load effect is also reduced. Particularly in the position of large grooves, the effect is more pronounced, and grooves generally larger than 1 μm can be considered large grooves. The step height may refer to the depth of the groove structure. The trimming of the pattern to be trimmed can be adjusted by reducing the area to be trimmed, namely reducing the size of the opening of the stacked layers, for example, trimming of a single pattern to be trimmed is realized, the etching depth of the substrate can be reduced, the step height caused by etching the substrate can be reduced, the load effect, particularly the load effect of a large groove can be reduced, meanwhile, the occurrence of defects can be reduced, and the yield of products can be improved. Meanwhile, the load effect of the cutting path area is reduced, so that the damage of the marking pattern of the cutting path area can be avoided, the substantial influence in the chip can be avoided, and the failure of the chip can be avoided.
Therefore, the method for forming the cutting channel structure can obviously reduce the step height under the condition that the internal chip is not affected, and the overall load effect is reduced, especially the load effect at the position of the large groove is greatly reduced, so that the overall health condition of the cutting channel area is obviously improved.
The method for forming the scribe line structure of the present invention is applicable to a Dynamic Random Access Memory (DRAM) process, and other Memory processes are also applicable, such as a Static Random Access Memory (SRAM) process. Therefore, the invention can improve the loading effect of the cutting channel area in the manufacturing process of the dynamic random access memory and the like, and improve the product yield.
In addition, the invention also provides a cutting channel structure formed by the method for forming the cutting channel structure. The dicing street structure comprises: a plurality of trimmed patterns positioned in scribe line areas on the substrate; and the groove structures are positioned on the trimmed patterns, and each groove structure at least covers one trimmed pattern. Namely, by forming a stacked layer 20 on a substrate, defining a plurality of areas to be trimmed 40, and each area to be trimmed 40 covers at least one pattern to be trimmed 103; etching the stacked layer 20 of the to-be-trimmed region 40; and finally trimming the pattern 103 to be trimmed on the substrate to form the trimmed pattern. The trimming of the pattern to be trimmed 103 on the substrate is specifically: and etching the substrate by taking the etched stacked layer 20 as a mask, so as to form a plurality of groove structures on the substrate at the corresponding positions of the pattern 103 to be trimmed. Preferably, each groove structure covers one of the trimmed patterns, and the horizontal distance between the side edge of the groove structure and the same side edge of the trimmed pattern covered by the groove structure is preferably 30 nm-50 nm. The trimming adjustment of one or more graphics to be trimmed 103 can be realized through the opening size adjustment of the groove structure, that is, one groove structure trims only one graphics to be trimmed 103 or one groove structure trims a plurality of graphics to be trimmed 103; the height of the step caused by etching the substrate can be reduced by adjusting the size of the opening of the groove structure, the load effect, particularly the load effect of the large groove, can be reduced, meanwhile, the occurrence of defects can be reduced, and the yield of products can be improved.
The scanning result of the scanning electron microscope in this embodiment can find that the surface of the scribe line structure formed by the method for forming the scribe line structure is smooth and free of contaminant particles, while the surface of the scribe line structure formed by the prior art is rough and may have particulate contaminants. The API inspection result shows that the cutting channel structure formed by the cutting channel structure forming method has no falling defect, and the cutting channel formed by the prior art has falling defect. Therefore, the loading effect of the cutting channel structure formed by the method for forming the cutting channel structure is relatively low, defects are relatively few, and the product yield is relatively high.
In addition, the invention also provides a semiconductor structure, which comprises
A substrate on which a plurality of chip regions and scribe line regions between the chip regions are defined;
a scribe line structure located within the scribe line region on the substrate.
The substrate may include a base on which a structural layer is formed. The substrate may comprise a single material, multiple layers of different materials, one or more structural layers with regions of different materials or different structural patterns, etc. These materials may include semiconductors, insulators, conductors, or combinations thereof.
The dicing street structure is prepared by adopting the method for forming the dicing street structure, specifically, a stacked layer 20 is formed on a substrate, a plurality of areas to be trimmed 40 are defined, and each area to be trimmed 40 covers at least one pattern 103 to be trimmed; etching the stacked layer 20 of the to-be-trimmed region 40; finally, trimming the pattern 103 to be trimmed on the substrate. The scribe line structure formed by the method has lower loading effect and fewer defects, so that the yield of the semiconductor structure comprising the scribe line structure is higher and fewer defects are generated.
In addition, it will be understood that while the invention has been described in terms of preferred embodiments, the above embodiments are not intended to limit the invention. Many possible variations and modifications of the disclosed technology can be made by anyone skilled in the art without departing from the scope of the technology, or the technology can be modified to be equivalent. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention still fall within the scope of the technical solution of the present invention.
Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component to another component, these terms are used in this specification for convenience only, such as in terms of the orientation of the examples depicted in the drawings. It will be appreciated that if the device is turned upside down, the components recited as "up" will become "down". When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.
As used herein, the term "layer" refers to a portion of material that includes regions having a thickness. The layer may extend over the entire superstructure or substructure, or may have a range less than the substructure or superstructure. Furthermore, the layer may be a region of uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure or between any pair of horizontal planes at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along a tapered surface.
It is also to be understood that this invention is not limited to the particular methodology, compounds, materials, manufacturing techniques, uses, and applications described herein, as such may vary. It should also be understood that the terminology described herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a step" means a reference to one or more steps, and may include sub-steps. All conjunctions used should be understood in the broadest sense. Thus, the word "or" should be understood as having the definition of a logical "or" rather than a logical exclusive or "unless the context clearly indicates the contrary. Structures described herein will be understood to also refer to the functional equivalents of such structures. Language that may be construed as approximate should be construed unless the context clearly indicates the contrary.

Claims (15)

1. A method of forming a scribe line structure, comprising the steps of:
providing a substrate, defining a cutting channel region on the substrate, and forming a plurality of patterns to be trimmed on the substrate of the cutting channel region;
forming a stacked layer on the substrate, and defining a plurality of areas to be trimmed on the stacked layer, wherein each area to be trimmed covers at least one pattern to be trimmed;
etching the stacked layer of the area to be trimmed to form a patterned stacked layer;
and trimming the pattern to be trimmed by taking the patterned stacked layer as a mask to obtain a trimmed pattern.
2. The method of forming a scribe line structure according to claim 1, wherein the step of defining a plurality of areas to be trimmed on the stacked layers comprises:
forming a photoresist layer on the stacked layers;
the photoresist layer is exposed and developed to define a plurality of areas to be trimmed.
3. The method of claim 2, wherein each of the areas to be trimmed covers one of the patterns to be trimmed to effect trimming of each of the patterns to be trimmed.
4. The method of claim 3, wherein a horizontal distance between a side of the repair area and a same side of the repair pattern covered by the repair area is 30nm to 50nm.
5. The method of claim 1-4, wherein the stacked layer comprises a first hard mask layer, a second hard mask layer, a third hard mask layer, a fourth hard mask layer, and a fifth hard mask layer in order from bottom to top.
6. The method of claim 5, wherein the first hard mask layer comprises at least one of amorphous carbon, and diamond-like carbon; and/or
The material of the second hard mask layer comprises SiON and/or SiCN; and/or
The material of the third hard mask layer comprises silicon oxide; and/or
The fourth hard mask layer is made of SOH; and/or
The fifth hard mask layer is made of SiON and/or SiCN.
7. The method of claim 5, wherein the stacked layer further comprises a bottom anti-reflective layer, the bottom anti-reflective layer being on the fifth hard mask layer.
8. The method of claim 7, wherein the bottom anti-reflective coating comprises at least one of SiON, silicon oxide and ethyl orthosilicate.
9. The method of claim 5, wherein the fourth hard mask layer forming process comprises a spin-on process, and the first hard mask layer, the second hard mask layer, the third hard mask layer, and the fifth hard mask layer forming process each independently comprise one of CVD, ALD, and PVD.
10. The method of claim 1-4, further comprising defining a plurality of die regions on the substrate, the die regions being located between adjacent die regions.
11. The method of claim 10, wherein in the step of forming a stacked layer on the substrate, the stacked layer further covers the substrate corresponding to each of the chip regions.
12. The method of forming a scribe line structure according to any one of claims 1 to 4, wherein the trimming the pattern to be trimmed using the patterned stacked layer as a mask comprises: and etching the substrate by taking the patterned stacked layer as a mask so as to form a plurality of groove structures on the substrate at the corresponding positions of the pattern to be trimmed.
13. A dicing street structure, characterized by comprising:
a plurality of trimmed patterns positioned in scribe line areas on the substrate;
and the groove structures are positioned on the trimmed patterns, and each groove structure at least covers one trimmed pattern.
14. The street structure of claim 13, wherein each of the groove structures covers one of the post-trim patterns, and the horizontal distance between the side of the groove structure and the same side of the post-trim pattern covered by the groove structure is 30nm to 50nm.
15. A semiconductor structure, comprising:
a substrate on which a plurality of chip regions and scribe line regions between adjacent chip regions are defined;
the dicing street structure of claim 13 or 14, located within the dicing street region on the substrate.
CN202211029656.7A 2022-08-25 2022-08-25 Semiconductor structure, scribe line structure and forming method thereof Pending CN117690786A (en)

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