WO2024041339A1

WO2024041339A1 - Semiconductor structure, and scribe line structure and method for forming same

Info

Publication number: WO2024041339A1
Application number: PCT/CN2023/110796
Authority: WO
Inventors: 张雁红; 杨鹏
Original assignee: 长鑫存储技术有限公司
Priority date: 2022-08-25
Filing date: 2023-08-02
Publication date: 2024-02-29
Also published as: CN117690786A

Abstract

Disclosed are a semiconductor structure, and a scribe line structure and a method for forming same. The method for forming a scribe line structure comprises: forming a stack layer on a substrate, and defining a plurality of areas to be trimmed, wherein each area to be trimmed at least covers one pattern to be trimmed; and on the basis of the areas to be trimmed, etching the stack layer and trimming the patterns to be trimmed.

Description

Semiconductor structure, scribe line structure and formation method thereof

This disclosure is based on a Chinese patent application with the application number 202211029656.7, the filing date being August 25, 2022, and the application title being "Semiconductor Structure, Cutting Street Structure and Formation Method", and claims the priority of the Chinese patent application, which The entire contents of the Chinese patent application are hereby incorporated by reference into this disclosure.

Technical field

The present disclosure relates to, but is not limited to, a semiconductor structure, a scribe line structure and a method of forming the same.

Background technique

As the size of Dynamic Random Access Memory (DRAM) continues to shrink, the load effect problem in the dicing area has become more and more obvious, especially in large grooves, which can easily cause damage to the mark pattern, and it is easy to Defects may peel off into the chip, resulting in lower yield.

Therefore, it is necessary to provide a semiconductor structure, a scribe line structure and a forming method thereof to solve the problem of the load effect in the scribe line area.

Contents of the invention

The following is an overview of the subject matter described in detail in this disclosure. This summary is not intended to limit the scope of the claims.

The present disclosure provides a semiconductor structure, a scribe line structure and a method of forming the same.

According to some embodiments, a first aspect of the present disclosure provides a method for forming a kerf structure, including the following steps:

A substrate is provided, and a scribe line area is defined on the substrate, and a plurality of graphics to be trimmed are formed on the substrate in the scribe line area;

Forming a stacked layer on the substrate, and defining a plurality of areas to be trimmed on the stacked layer, each of the areas to be trimmed covers at least one of the graphics to be trimmed;

Etching the stacked layer of the area to be trimmed to form a patterned stacked layer;

Using the patterned stacked layer as a mask, the pattern to be trimmed is trimmed to obtain a trimmed pattern.

According to some embodiments, a second aspect of the present disclosure provides a kerf structure, including:

A plurality of trimmed graphics located within the scribe lane area on the substrate;

A plurality of groove structures are located on the trimmed graphics, and each groove structure covers at least one of the trimmed graphics.

According to some embodiments, a third aspect of the present disclosure provides a semiconductor structure including:

A substrate, on which a plurality of chip areas and a dicing track area located between adjacent chip areas are defined;

The scribe line structure described above is located in the scribe line area on the substrate.

In the semiconductor structure, scribe line structure and formation method provided by the present disclosure, stacked layers are formed on the substrate, and multiple areas to be trimmed are defined, and each of the areas to be trimmed covers at least one of the patterns to be trimmed. , after etching the stacked layers of the area to be trimmed, trimming the pattern to be trimmed on the substrate. In this way, by reducing the area to be trimmed, not only can the trimming of the pattern to be trimmed be controlled, for example, the trimming of a single pattern to be trimmed can be realized, but the etching depth of the substrate can also be reduced, and the steps caused by etching the substrate can be reduced. height, thereby reducing load effects, reducing defects and improving product yield.

Description of drawings

Figure 1 is a schematic structural diagram of a pruning area covering a graphic to be pruned arranged along one direction;

Figure 2 is a schematic structural diagram of a trimming area covering a graphic to be trimmed arranged in another direction;

Figure 3 is a schematic structural diagram of a cutting area area before the graphics to be trimmed is trimmed;

Figure 4 is a schematic structural diagram of a cutting area area after trimming the graphics to be trimmed;

Figure 5 is a flow chart of a method for forming a cutting track structure according to an embodiment of the present disclosure;

Figure 6 is a schematic structural diagram of the stacked layers in the dicing lane area according to an embodiment of the present disclosure;

Figure 7 is a schematic structural diagram of stacked layers in the chip area according to an embodiment of the present disclosure;

Figure 8 is a schematic diagram of the product structure after step S2 is performed in the cutting track area in the method for preparing a cutting track structure according to an embodiment of the present disclosure;

Figure 9 is a schematic diagram of the product structure after step S4 is performed in the cutting track area in the method for preparing a cutting track structure according to an embodiment of the present disclosure;

Figure 10 is a schematic structural diagram of the chip area after trimming according to an embodiment of the present disclosure;

Figure 11 is a schematic structural diagram of an area to be trimmed covering a figure to be trimmed arranged in one direction according to an embodiment of the present disclosure;

Figure 12 is a schematic structural diagram of an area to be trimmed covering a figure to be trimmed arranged in another direction according to an embodiment of the present disclosure;

Reference signs:

In Figures 1 to 4:
011-dielectric layer, 012-oxide layer, 013-pattern to be trimmed, 02-trimming area;

In Figure 5 to Figure 12:
10-Substrate, 101-Dielectric layer, 102-Oxide layer, 103-Pattern to be trimmed, 104-Pattern after trimming, 20-Stacked layer, 201-First hard mask layer, 202-Second hard mask layer, 203-The third hard mask layer, 204-The fourth hard mask layer, 205-The fifth hard mask layer, 206-Bottom anti-reflective layer, 30-Photoresist layer, 301-Photoresist layer graphics unit, 40 - area to be trimmed, 50 - groove structure.

Detailed ways

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative efforts fall within the scope of protection of the present disclosure. It should be noted that, as long as there is no conflict, the embodiments and features in the embodiments can be arbitrarily combined with each other.

The semiconductor structure needs to be trimmed after the pattern is formed. The trimming mainly includes trimming of critical dimensions and trimming of redundant patterns. In the manufacturing process of dynamic random access memory, the graphics in the chip area are mainly used for trimming critical dimensions, while the graphics in the scribe area are mainly used for alignment marks. Therefore, many graphics unrelated to the mark graphics need to be trimmed (that is, graphics to be trimmed). There are many types of graphics to be trimmed in the cutting area, and the graphics to be trimmed can be set in any direction according to the process design. For example, Figure 1 shows a plurality of graphics to be trimmed 013 arranged along a first direction, and Figure 2 shows a plurality of graphics to be trimmed 013 arranged along a second direction. The first direction is different from the second direction. Further, The first direction is perpendicular to the second direction. At present, the commonly used method is: when trimming the figure 013 to be trimmed, the adjacent figures 013 to be trimmed will be trimmed together. That is, after the figure 013 to be trimmed is formed, the figure 013 to be trimmed is directly trimmed to form a cutting track structure, and Stacked layers are not formed, so the etching range cannot be well controlled. Specifically, the graphics 013 to be trimmed in the entire area are generally etched together, that is, multiple graphics 013 to be trimmed will be trimmed together as a whole, and the trimming of the graphics to be trimmed 013 cannot be controlled, nor can each of the graphics to be trimmed 013 be trimmed. Graphic 013 is trimmed separately, and the final trimming area 02 will cover the entire graphic 013 to be trimmed.

Referring to FIG. 3 , a schematic structural diagram of the graphics 013 to be trimmed in the cutting lane area is shown before trimming. FIG. 4 shows a schematic structural diagram of the graphics 013 to be trimmed in the cutting lane area after trimming. Referring to Figures 3 and 4, the existing method of forming a scribe line structure is as follows: forming a trench in the dielectric layer 011 of the substrate; forming a covering dielectric layer 011 and The oxide layer 012 filling the trench, the trench filled with the oxide layer 012 serves as the pattern of the scribe line area, and based on the known alignment mark pattern, it can be determined which graphics in the scribe line area belong to the pattern to be trimmed 013; after determining the pattern to be trimmed After graph 013, directly prune graph 013 to be pruned to obtain the pruned structure, see Figure 4. After the pattern 013 to be trimmed is trimmed as a whole, the opening formed is relatively large, which will cause the step height after etching to be relatively large, and the overall load effect problem is more obvious, especially in large trenches, which will easily cause Important graphics (such as marking graphics) around the trimmed pattern 013 are damaged, and defects are prone to peeling off into the chip, thus reducing the product yield.

Therefore, it is necessary to provide a method for forming a cutting track structure to reduce the step height after etching, thereby reducing the load effect, reducing the possibility of peeling defects, and improving the product yield.

Referring to Figures 5, 6, 7, 8 and 9, embodiments of the present disclosure provide a method for forming a kerf structure, including the following steps:

Step S1: Provide a substrate 10, and define a scribe line area on the substrate 10, and a plurality of graphics to be trimmed 103 are formed on the substrate 10 in the scribe line area;

Step S2: Form a stacked layer 20 on the substrate 10, and define a plurality of areas 40 to be trimmed on the stacked layer 20, and each area 40 to be trimmed covers at least one pattern 103 to be trimmed;

Step S3: Etch the stacked layer 20 of the area to be trimmed 40 to form a patterned stacked layer 20;

Step S4: Using the patterned stacked layer 20 as a mask, trim the to-be-trimmed pattern 103 to obtain the trimmed pattern 104.

Referring to FIG. 6 and FIG. 7 , step S1 is performed to provide a substrate 10 . Substrate 10 may include a substrate with a structural layer formed thereon. Substrate 10 may include a single material, multiple layers of different materials, one or more structural layers with regions of different materials or different structural patterns, etc. These materials may include semiconductors, insulators, conductors, or combinations thereof. For example, the substrate 10 in FIGS. 6 and 7 may include a substrate, a dielectric layer 101, a trench formed in the dielectric layer 101, and an oxide layer 102 covering the dielectric layer 101 and filling the trench. The oxide layer 102 is preferably silicon oxide, but Not limited to this. As an option, the substrate can be sequentially deposited on the substrate through a thin film deposition process such as CVD (Chemical Vapor Deposition), PVD (Physical Vapor Deposition), ALD (Atomic Layer Deposition) or any combination thereof. The above-mentioned multi-layer structure is disposed on the substrate 10 to form the substrate 10 .

The substrate 10 may define a plurality of chip areas and a plurality of scribe line areas, and the scribe line areas are located between adjacent chip areas. The trenches filled with the oxide layer 102 on the substrate 10 serve as patterns for the scribe line area and the chip area. There are many types of patterns in the scribe line area and the chip area, for example, they can be buried word lines, but are not limited thereto. Since the graphics in the cutting lane area only need to be able to ensure subsequent mark alignment, only a small amount of graphics in the cutting lane area needs to be retained, that is, part of the graphics in the cutting lane area needs to be trimmed. In this embodiment, the graphics to be trimmed 103 in the cutting lane area can be determined based on the designed mark graphics. Referring to FIG. 6 , a to-be-trimmed graphic 103 whose cutting lane area needs to be trimmed is shown.

In this embodiment, while trimming the graphics 103 to be trimmed, other graphics (such as mark graphics) in the dicing lane area and graphics in the chip area can also be trimmed. For example, while trimming the graphics 103 to be trimmed, the chip area can also be trimmed. The critical dimensions of the graphics are trimmed so that the final critical dimensions of the graphics in the chip area are closer to the target value.

Continuing to refer to FIGS. 6 and 8 , step S2 is performed to form a stacked layer 20 on the substrate 10 , and define a plurality of areas 40 to be trimmed on the stacked layer 20 .

In the process of forming the stacked layer 20, the stacked layer 20 will cover the substrate 10 in the channel area and the chip area at the same time.

The stacked layer 20 includes a first hard mask layer 201, a second hard mask layer 202, a third hard mask layer 203, a fourth hard mask layer 204 and a fifth hard mask layer 205 from bottom to top. That is, a first hard mask layer 201, a second hard mask layer 202, a third hard mask layer 203, a fourth hard mask layer 204 and a third hard mask layer 204 are formed on the substrate 10 in each channel area and chip area. Five hard mask layers 205, see Figure 6 . The thicknesses of the first hard mask layer 201, the second hard mask layer 202, the third hard mask layer 203, the fourth hard mask layer 204 and the fifth hard mask layer 205 can be set according to actual requirements.

The step of forming the stacked layer 20 on the substrate 10 includes: sequentially forming a first hard mask layer 201 on the substrate 10, The second hard mask layer 202 , the third hard mask layer 203 , the fourth hard mask layer 204 and the fifth hard mask layer 205 .

Continuing to refer to FIG. 6 , a first hard mask layer 201 is formed on the oxide layer 102 of the substrate 10 . The material of the first hard mask layer 201 is at least one of amorphous carbon, amorphous carbon layer (ACL) and diamond-like coating (DLC), but is not limited thereto. For example, the material of the first hard mask layer 201 It can also be SOH (spin on hardmask; spin on hard mask). As an example, the first hard mask layer 201 is made of amorphous carbon. Compared with the materials of the second hard mask layer 202 to the fifth hard mask layer 205 , amorphous carbon has the advantage of being easier to etch, and can Easier to provide as thicker layers, thus enabling the formation of transfer patterns with higher characteristics.

After the first hard mask layer 201 is formed, a second hard mask layer 202 is formed on the first hard mask layer 201 . The material of the second hard mask layer 202 is silicon oxynitride (SiON) and/or SiCN, but is not limited thereto.

After the second hard mask layer 202 is formed, a third hard mask layer 203 is formed on the second hard mask layer 202 . The material of the third hard mask layer 203 is silicon oxide, but is not limited thereto.

After the third hard mask layer 203 is formed, a fourth hard mask layer 204 is formed on the third hard mask layer 203 . The material of the fourth hardmask layer 204 is SOH (spin on hardmask; spin on hardmask), but is not limited to this. The fourth hard mask layer 204 may be formed by a spin coating process, but is not limited thereto. SOH can include silicon hard mask materials, carbon hard mask materials, organic hard mask materials, etc.

After the fourth hard mask layer 204 is formed, a fifth hard mask layer 205 is formed on the fourth hard mask layer 204 . The material of the fifth hard mask layer 205 is SiON and/or SiCN, but is not limited thereto.

In this embodiment, the formation processes of the first hard mask layer 201 , the second hard mask layer 202 , the third hard mask layer 203 and the fifth hard mask layer 205 each independently include CVD, ALD and PVD. of, but not limited to. CVD can be PECVD (Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition method), HDPCVD (High Density Plasma Chemical Vapor Deposition, high density plasma chemical vapor deposition) or MOCVD (Metal Organic Chemical Vapor DePosition, metal organic compounds) chemical vapor deposition), but is not limited to this. For example, a CVD process is used to deposit amorphous carbon on the oxide layer 102 of the substrate 10 to form the first hard mask layer 201; and then a CVD process is used to deposit silicon oxynitride on the first hard mask layer 201 to form a third hard mask layer 201. Second hard mask layer 202; then use a CVD process to deposit silicon oxide on the second hard mask layer 202 to form a third hard mask layer 203; then use a spin coating process to spin on the third hard mask layer 203 SOH is applied to form the fourth hard mask layer 204; finally, a CVD process is used to deposit silicon oxynitride on the fourth hard mask layer 204 to form the fifth hard mask layer 205.

Continuing to refer to FIG. 6 , the stacked layer 20 may also include a bottom anti-reflective coating 206 (Bottom Anti-Reflective Coating, BARC) located on the fifth hard mask layer 205 . The formation process of the bottom anti-reflective layer 206 may be CVD (such as PECVD, HDPCVD or MOCVD), ALD or PVD, etc. The material of the bottom anti-reflective layer 206 may be one or more of SiON, silicon oxide, or tetraethyl orthosilicate, but is not limited thereto. For example, a CVD process is used to deposit SiON on the fifth hard mask layer 205 to form the bottom anti-reflective layer 206 .

The bottom anti-reflective layer 206 uses an anti-reflective material that can effectively eliminate light reflection to form standing waves. Therefore, the design solution of adding the bottom anti-reflective layer 206 between the photoresist layer 30 and the substrate 10 can increase exposure. The energy range (EL) and focal length (DOF) reduce the impact of differences in the geometric structure of the substrate 10 on the uniformity of the CD (critical dimension), and at the same time reduce the pattern gaps caused by the scattering of reflected light caused by the sharp edges of the substrate 10 , alleviating the swing curve effect caused by the different thicknesses of the photoresist layer 30 due to the configuration of the substrate 10 , thereby enabling better photolithography patterns to be obtained with smaller line widths.

In this embodiment, before forming the third hard mask layer 203, the method of forming the stacked layer 20 may further include: sequentially forming a seventh hard mask layer and an eighth hard mask layer on the second hard mask layer 202, and The eighth hard mask layer and the seventh hard mask layer are sequentially etched to form openings. After the openings are formed, a formation process of the third hard mask layer 203 is performed. The seventh hard mask layer and the eighth hard mask layer in the scribe area are completely etched, leaving only part of the seventh hard mask layer and the eighth hard mask layer in the chip area, and the seventh hard mask layer The material of is the same as the material of the fourth hard mask layer 204 , and the material of the eighth hard mask layer is the same as the material of the fifth hard mask layer 205 , as shown in FIG. 7 .

Referring to FIG. 8 , after the stacked layer 20 is formed, a step of defining a plurality of areas 40 to be trimmed is performed. The steps of defining multiple areas 40 to be trimmed may include:

Form a photoresist layer 30 on the stacked layer 20;

After the photoresist layer 30 is formed on the stacked layer 20 , the photoresist layer 30 is exposed and developed to define a plurality of areas 40 to be trimmed.

After defining multiple areas 40 to be trimmed based on the above method, after forming the bottom anti-reflective layer 206, the photoresist layer 30 is spin-coated on the bottom anti-reflective layer 206. The photoresist layer 30 not only covers the stacked layer 20 in the scribe line area, but also covers the stacked layer 20 in the chip area.

The material of the photoresist layer 30 may include a negative photoresist layer 30 and a positive photoresist layer 30. For example, the material of the photoresist layer 30 may be a phenol-formaldehyde polymer. Illumination can change the chemical structure of the photoresist layer 30, and the exposed portions of the photoresist layer 30 or the unexposed portions of the photoresist layer 30 can be removed using chemical solvents.

In the process of exposing and developing the photoresist layer 30 to form the patterned photoresist layer 30, the photoresist layer 30 can be exposed and developed to form a plurality of openings on the photoresist layer 30, and the photoresist located between the openings. Layer graphics unit 301. The opening exposes a partial area of the stacked layer 20. The area 40 to be trimmed is the area corresponding to the partial opening. The partial opening is specifically the opening corresponding to the pattern 103 to be trimmed, while the openings in other positions are used for other patterns in the cutting lane area. (such as marking graphics) and graphics in the chip area for critical dimension trimming and other trimming.

In this embodiment, referring to Figures 8 and 9, each area to be trimmed 40 covers at least one figure to be trimmed 103, that is, each area to be trimmed 40 can cover one figure to be trimmed 103, or can cover multiple to be trimmed at the same time. Graphics 103. As an example, each area to be trimmed 40 covers a pattern 103 to be trimmed. In this way, the smaller the area covered by each area 40 to be trimmed, the smaller the opening formed on the photoresist layer 30 will be, and the substrate will eventually be etched. The opening of the groove structure 50 formed by 10 will be smaller, so the etching gas accumulated in the groove structure 50 will be less, and the step height after etching will be lower, and the load effect will be smaller. Defects will also be reduced and product yields will be higher.

The cross-sectional area of each area to be trimmed 40 perpendicular to the growth direction of the stacked layer 20 is larger than the cross-sectional area of the corresponding pattern 103 perpendicular to the growth direction of the stacked layer 20 , so that the area to be trimmed 40 completely covers the corresponding Graphics to be pruned 103. As an example, the horizontal distance between the side of the area to be trimmed 40 and the same side of the graphics 103 to be trimmed covered by the area to be trimmed 40 is 30 nm to 50 nm. Specifically, the area to be trimmed 40 and all the graphics to be trimmed 103 covered by the area to be trimmed 40 can be projected on the same horizontal plane, and on this horizontal plane, the sides of the area to be trimmed 40 and the areas covered by the area to be trimmed 40 are The distance between the same side edges of the pattern 103 to be trimmed is 30nm to 50nm. This design makes it easier to control the boundaries of the pattern 103 to be trimmed, and the height of the final groove structure is relatively neat, which is beneficial to reducing the load effect and thus improving the Product yield. For example, when each area to be trimmed 40 covers a figure to be trimmed 103, the horizontal distance between the side of each area to be trimmed 40 and the side of the same side of the covered figure to be trimmed 103 is 40 nm.

Step S3 is performed to etch the stack layer 20 of the region 40 to be trimmed to form a patterned stack 20 . As an example, a dry etching process may be used, but is not limited to, to etch the fifth hard mask layer 205, the fourth hard mask layer 204, the third hard mask layer 203, the second hard mask layer 202 and the third hard mask layer 202 in sequence. A hard mask layer 201. When the bottom anti-reflective layer 206 is formed on the fifth hard mask layer 205, dry etching can be used to etch the bottom anti-reflective layer 206 first, and then etch the fifth hard mask layer 205 and the fourth hard mask layer in sequence. layer 204, third hard mask layer 203, second hard mask layer 202 and first hard mask layer 201. The etching gas for dry etching can be Cl2, BCl3, etc., but is not limited to this. It should be noted that during the etching process, the patterned photoresist layer 30 will be partially removed by the etching plasma, but a certain amount of the patterned photoresist layer 30 will still remain. To protect the stacked layer 20 located below the photoresist layer pattern unit 301 from being removed by etching, wherein the stacked layer 20 located below the photoresist layer pattern unit 301 is also located above the substrate 10 . The remaining stacked layer 20 located below the photoresist layer pattern unit 301 constitutes a stacked layer pattern unit.

While the stacked layer 20 on the substrate 10 in the scribe area is etched, the stacked layer 20 on the substrate 10 in the chip area will also be etched, and the photoresist layer on the stacked layer 20 in the chip area will also be etched. The graphics unit 301 can be designed according to process requirements. As an example, the reflective layer 204, the fourth hard mask layer 204, When the second hard mask layer 202 and the first hard mask layer 201 are used, the reflective layer 204, the fifth hard mask layer 205, the fourth hard mask layer 204, the third hard mask layer 203, and the second hard mask layer 201 in the chip area The hard mask layer 202 and the first hard mask layer 201 are also sequentially and simultaneously etched. For example, when the reflective layer 204 in the scribe area is etched, the reflective layer 204 in the chip area is simultaneously etched.

After etching the stacked layer 20 in the region 40 to be trimmed, the method of forming the scribe line structure further includes: removing the patterned photoresist layer 30 . In other embodiments, the removal process of the patterned photoresist layer 30 may also be provided after the step of trimming each pattern 103 to be trimmed.

The removal method of the patterned photoresist layer 30 is preferably an ashing process, but is not limited thereto. The currently commonly used ashing process is to use plasma gas containing oxygen radicals or oxygen ions to remove the photoresist layer 30; the ashing process is generally heated under low pressure and the plasma gas is introduced into the reaction chamber. Since the ashing rate of the ashing process is proportional to the temperature, the ashing process is generally carried out at high temperatures. The commonly used ashing temperature is 80°C to 300°C. While the ashing process removes the remaining photoresist layer 30 in the scribe line area (i.e., the patterned photoresist layer 30), it will also remove the remaining photoresist layer 30 in the chip area. That is, the ashing process will remove all remaining photoresist layers 30 in the chip area. photoresist layer 30.

Referring to Figure 8 and Figure 9, step S4 is performed to trim the pattern 103 to be trimmed using the patterned stacked layer 20 as a mask, that is, using the patterned stacked layer 20 as a mask to etch the substrate 10, in the area to be trimmed. A plurality of groove structures 50 are formed on the substrate 10 at corresponding positions 40 to trim the pattern 103 to be trimmed. In this embodiment, each groove structure 50 can trim multiple figures 103 to be trimmed, or only one figure 103 to be trimmed. As an example, each groove structure 50 only trims one figure 103 to be trimmed. Since the groove structure 50 corresponds to the area to be trimmed 40 , the smaller the area covered by each area to be trimmed 40 , the smaller the opening of the corresponding groove structure 50 will be. There will be less etching gas, so the step height after etching will be lower, the load effect will be smaller, defects will be reduced, and the product yield will be higher.

While trimming the pattern 103 to be trimmed, the etching gas will also etch the substrate 10 in other positions in the scribe line area and the substrate 10 in the chip area to trim other patterns (such as mark patterns) in the scribe line area and the chip area. Key dimensions of graphics, etc. For example, referring to FIG. 10 , while multiple groove structures 50 are formed on the substrate 10 in the scribe area, multiple grooves are also formed on the substrate 10 in the chip area. The stop condition for etching the substrate 10, that is, the condition for stopping the flow of etching gas is: the groove depth in the chip area reaches a target value, and the target value can be designed according to process requirements.

In step S4, the etching gas may be Cl2, BCl3, etc., but is not limited thereto. It should be noted that during the etching process, the oxide layer 102 and the dielectric layer 101 on the substrate 10 will be partially removed under the action of etching plasma to trim the pattern 103 to be trimmed and mark the pattern and chip. Trimming of regional graphics, etc.

Referring to Figures 10, 11 and 12, since each to-be-trimmed area 40 covers at least one to-be-trimmed figure 103, and the finally formed groove structure 50 corresponds to the to-be-trimmed area 40, the width of the groove structure 50 is larger than the width of the groove structure 50. The groove structure 50 covers the entire width of the graphics 103 to be trimmed. As an example, when each to-be-trimmed area 40 covers one to-be-trimmed figure 103 , the width of the groove structure 50 is greater than the width of the one to-be-trimmed figure 103 covered by the groove structure 50 .

During the etching process, each area 40 to be trimmed will trim one figure 103 or multiple figures 103 to be trimmed. In this embodiment, the trimming adjustment of the figures 103 to be trimmed can be realized by adjusting the size of the area 40 to be trimmed. Compared with the common method in which multiple graphics to be trimmed are trimmed as a whole, the width of the groove structure 50 in the cutting lane area in this embodiment can be adjusted, that is, the opening size of the groove structure 50 can be adjusted to realize a groove structure. 50 only trims one pattern 103 to be trimmed, so the opening of the groove structure 50 in this embodiment will be reduced, less etching gas will enter, and less accumulation will occur. When the groove formed by etching in the chip area reaches the target value, the etching gas is stopped flowing. Since the etching gas accumulated in the groove structure 50 of the dicing track area in this embodiment is small, the etching stop time is short, so The final step height will be reduced, and the load effect will also be reduced, especially at the location of large trenches, the effect is more obvious. Generally, trenches larger than 1 μm can be considered large trenches, and the step height can refer to the depth of the groove structure 50 .

This embodiment can adjust the trimming of the pattern to be trimmed by reducing the area to be trimmed, that is, reducing the opening size of the stacked layer. For example, trimming a single pattern to be trimmed can reduce the etching depth of the substrate 10, thereby reducing the etching depth of the substrate 10. The step height caused by etching the substrate 10 reduces the load effect, especially the load effect of large trenches, and at the same time can reduce the occurrence of defects and improve the product yield. At the same time, since the load effect in the scribe line area is reduced, damage to the marking pattern in the scribe line area can be avoided, and substantial impact on the chip can be avoided, thereby avoiding chip failure.

Therefore, the formation method of the scribe line structure in the embodiment of the present disclosure can significantly reduce the step height and reduce the overall load effect without affecting the internal chip. In particular, the load effect at the large trench position will be extremely large. This will result in a significant improvement in the overall health of the cutting lane area.

The formation method of the scribe line structure in the embodiment of the present disclosure is suitable for dynamic random access memory processes, and is also applicable to other memory processes, such as static random access memory (Static Random-Access Memory, SRAM) processes. Therefore, embodiments of the present disclosure can improve the load effect of the dicing lane area in processes such as dynamic random access memory and improve product yield.

In addition, embodiments of the present disclosure also provide a dicing track structure formed by using the forming method of the dicing track structure in the above embodiment. Referring to FIG. 9 , the cutting track structure includes: a plurality of trimmed patterns 104 and a plurality of groove structures 50 . A plurality of trimmed patterns 104 are located in the scribe lane area on the substrate 10; a plurality of groove structures 50 are located on the trimmed patterns 104, and each groove structure 50 covers at least one trimmed pattern 104. Specifically, referring to FIG. 8 , a stacked layer 20 is formed on the substrate 10 and a plurality of areas 40 to be trimmed are defined, and each area 40 to be trimmed covers at least one graphic 103 to be trimmed; and then the stacking of the areas 40 to be trimmed is performed The layer 20 is etched; after the stacked layer 20 in the region 40 to be trimmed is etched, the pattern 103 to be trimmed on the substrate 10 is trimmed to form a trimmed pattern 104. Trimming the pattern 103 to be trimmed on the substrate 10 specifically includes: using the etched stack layer 20 as a mask, etching the substrate 10 to form multiple layers on the substrate 10 at positions corresponding to the pattern 103 to be trimmed. A groove structure 50. As an example, each groove structure 50 covers a trimmed pattern, and the horizontal distance between the side of the groove structure 50 and the side on the same side of the trimmed pattern 104 covered by the groove structure 50 is preferably 30 nm~ 50nm.

In this embodiment, the trimming adjustment of one or more figures 103 to be trimmed can be realized by adjusting the opening size of the groove structure 50 , that is, one groove structure 50 trims only one figure 103 to be trimmed, or one groove structure 50 trims multiple figures 103 to be trimmed. The pattern 103 to be trimmed; and by adjusting the opening size of the groove structure 50, it can not only reduce the step height caused by etching the substrate 10, reduce the load effect, especially the load effect of large trenches, but also reduce the occurrence of defects and improve Product yield.

In this embodiment, it can be found from the scanning electron microscope scanning results that the surface of the kerf structure formed by the above-mentioned kerf structure formation method is smooth and free of contaminant particles, while the surface of the kerf structure formed by the common method is rough and contains particles. contaminants. The API inspection results show that the cutting track structure formed by the above-mentioned cutting track structure forming method does not have the defect of falling off, but the cutting track formed by the common method has the defect of falling off. Therefore, the kerf structure formed by the above-mentioned kerf structure formation method has a lower load effect, fewer defects, and a higher product yield.

In addition, embodiments of the present disclosure also provide a semiconductor structure. Refer to FIGS. 9 and 10 . The semiconductor structure includes a substrate 10 and a dicing track structure. A plurality of chip areas and scribe line areas located between the chip areas are defined on the substrate 10; the scribe line structure is located in the scribe line area on the substrate 10.

Substrate 10 may include a substrate with a structural layer formed thereon. Substrate 10 may include a single material, multiple layers of different materials, one or more structural layers with regions of different materials or different structural patterns, etc. These materials may include semiconductors, insulators, conductors, or combinations thereof.

Referring to Figures 6, 7 and 8, the scribe line structure is prepared using the above-mentioned formation method of the scribe line structure, specifically by forming a stacked layer 20 on the substrate 10 and defining a plurality of areas 40 to be trimmed, and Each area to be trimmed 40 covers at least one pattern to be trimmed 103; then the stacked layer 20 of the area to be trimmed 40 is etched; after the stacked layer 20 of the area to be trimmed 40 is etched, the pattern to be trimmed on the substrate 10 is 103 is formed by pruning. The load effect of the scribe line structure formed by the above method is relatively low and there are relatively few defects. Therefore, the yield rate of the semiconductor structure including the scribe line structure is relatively high and there are relatively few defects.

In addition, it can be understood that although the embodiments of the present disclosure are disclosed above, the above-mentioned embodiments are not intended to limit the present disclosure. Disclosed Embodiments. For any person familiar with the art, without departing from the scope of the technical solutions of the disclosed embodiments, they can use the technical content disclosed above to make many possible changes and modifications to the technical solutions of the disclosed embodiments, or modify them to be equivalent. Varied equivalent embodiments. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the embodiments of the present disclosure that do not deviate from the technical solutions of the embodiments of the present disclosure still fall within the scope of protection of the technical solutions of the embodiments of the present disclosure. Inside.

Although relative terms, such as "upper" and "lower" are used in this specification to describe the relative relationship of one component to another component, these terms are used in this specification only for convenience, such as according to the figures. Example orientation. It will be understood that if the device is turned upside down, components described as "on" would then appear as "on" components. When a structure is "on" another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" placed on the other structure, or that the structure is "indirectly" placed on the other structure through another structure. on other structures.

As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer may extend over the entire superstructure or substructure, or may have an extent less than the substructure or superstructure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure or between any pair of horizontal planes at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along tapered surfaces.

Furthermore, it should also be understood that the disclosed embodiments are not limited to the specific methods, compounds, materials, manufacturing techniques, uses and applications described herein, as they may vary. It should also be understood that the terminology described herein is used only to describe particular embodiments and is not intended to limit the scope of the disclosed embodiments. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates a contrary meaning. Thus, for example, a reference to "a step" means a reference to one or more steps, and may include secondary steps. All conjunctions used should be understood in their broadest sense. Accordingly, the word "or" should be understood to have the definition of a logical "or" and not a logical "exclusive-or" unless the context clearly indicates the contrary. Structures described herein will be understood to also recite functional equivalents of that structure. Language that may be construed as approximate should be construed as such unless the context clearly indicates a contrary meaning.

Industrial applicability

In the semiconductor structure, scribe line structure and formation method provided by the present disclosure, by reducing the area to be trimmed, not only can the trimming of the pattern to be trimmed be controlled, for example, the trimming of a single pattern to be trimmed can be realized, but also the engraving of the substrate can be reduced. The etching depth can reduce the step height caused by etching the substrate, thereby reducing the load effect, reducing defects and improving product yield.

Claims

A method for forming a cutting track structure includes the following steps:

A substrate (10) is provided, and a scribe line area is defined on the substrate (10), and a plurality of graphics to be trimmed (103) are formed on the substrate (10) in the scribe line area;

A stacked layer (20) is formed on the substrate (10), and a plurality of areas (40) to be trimmed are defined on the stacked layer (20), and each of the areas (40) to be trimmed covers at least one The graphics to be trimmed (103);

Etching the stacked layer (20) of the region (40) to be trimmed to form a patterned stacked layer (20);

Using the patterned stacked layer (20) as a mask, the pattern to be trimmed (103) is trimmed to obtain a trimmed pattern (104).
The method of forming a scribe line structure as claimed in claim 1, wherein the step of defining a plurality of areas (40) to be trimmed on the stacked layer (20) includes:

Form a photoresist layer (30) on the stacked layer (20);

The photoresist layer (30) is exposed and developed to define the plurality of areas to be trimmed (40).
The method of forming a cutting track structure according to claim 1 or 2, wherein each of the to-be-trimmed areas (40) covers one of the to-be-trimmed graphics (103), so as to realize each of the to-be-trimmed graphics (103). 103) pruning.
The method of forming a cutting track structure according to any one of claims 1 to 3, wherein the sides of the area to be trimmed (40) and the graphics to be trimmed (103) covered by the area to be trimmed (40) The horizontal distance between the sides on the same side is 30nm~50nm.
The method of forming a scribe line structure according to any one of claims 1 to 4, wherein the stacked layer (20) includes a first hard mask layer (201), a second hard mask layer (201) from bottom to top. 202), the third hard mask layer (203), the fourth hard mask layer (204) and the fifth hard mask layer (205).
The method of forming a scribe line structure according to claim 5, wherein the material of the first hard mask layer (201) includes at least one of amorphous carbon, an amorphous carbon layer and a diamond-like coating; and /or

The material of the second hard mask layer (202) includes SiON and/or SiCN; and/or

The third hard mask layer (203) is made of silicon oxide; and/or

The material of the fourth hard mask layer (204) includes SOH; and/or

The fifth hard mask layer (205) is made of SiON and/or SiCN.
The method of forming a scribe line structure according to claim 5 or 6, wherein the stacked layer (20) further includes a bottom anti-reflective layer (206), the bottom anti-reflective layer (206) is located on the fifth hard on the mask layer (205).
The method of forming a scribe line structure according to claim 7, wherein the material of the bottom anti-reflective layer (206) includes at least one of SiON, silicon oxide and ethyl orthosilicate.
The method of forming a scribe line structure according to any one of claims 5 to 8, wherein the formation process of the fourth hard mask layer (204) includes a spin coating process, and the first hard mask layer (204) 201), the formation processes of the second hard mask layer (202), the third hard mask layer (203) and the fifth hard mask layer (205) each independently include CVD, ALD and PVD one of them.
The method of forming a scribe line structure according to any one of claims 1 to 9, wherein a plurality of chip areas are also defined on the substrate (10), and the scribe line areas are located in adjacent chip areas. between.
The method of forming a scribe line structure according to claim 10, wherein in the step of forming a stacked layer (20) on the substrate (10), the stacked layer (20) also covers each of the on the substrate (10) corresponding to the chip area.
The method of forming a scribe line structure according to any one of claims 1 to 11, wherein the patterned stacked layer (20) is used as a mask to trim the pattern (103) to be trimmed. The steps include: using the patterned stacked layer (20) as a mask, etching the substrate (10) to form a plurality of layers on the substrate (10) corresponding to the pattern (103) to be trimmed. Groove structure (50).
A cutting track structure, wherein the cutting track structure includes:

A plurality of trimmed graphics (104) located in the scribe lane area on the substrate (10);

A plurality of groove structures (50) are located on the trimmed pattern (104), and each groove structure (50) covers at least one of the trimmed pattern (104).
The cutting channel structure according to claim 13, wherein each of the groove structures (50) covers one of the trimmed patterns (104), and the side edges of the groove structures (50) are in contact with the groove. The horizontal distance between the same sides of the trimmed pattern (104) covered by the structure (50) is 30 nm to 50 nm.
A semiconductor structure, the semiconductor structure includes:

A substrate (10), on which a plurality of chip areas and a dicing track area located between adjacent chip areas are defined;

The scribe line structure according to claim 13 or 14, the scribe line structure is located in the scribe line area on the substrate (10).