CN117255554A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, which relate to the technical field of semiconductors, and are used for eliminating the high level difference formed by the heights of a cell area and a peripheral area due to the capacitor, improving the process defect and further improving the product yield while controlling the process cost. The semiconductor device includes: a substrate, a capacitor pattern, and an etch stop pattern. The substrate has a peripheral region, a cell region, and a partition region between the peripheral region and the cell region. The capacitor pattern is formed on the substrate. The capacitor pattern is located in the cell region. An etch stop pattern is formed on the substrate. The etching barrier pattern is located in the partition area. The upper surfaces of the etch stop pattern and the capacitor pattern are flush with the upper surface of the substrate. The lower surface of the etch stop pattern is at least flush with the lower surface of the capacitor pattern. The manufacturing method of the semiconductor device is used for manufacturing the semiconductor device.

Description

Semiconductor device and manufacturing method thereof

Technical Field

The present invention relates to the field of semiconductor technology, and in particular, to a semiconductor device and a method for manufacturing the same.

Background

In the semiconductor manufacturing process, as the size of a semiconductor device is gradually reduced, the structure inside the device is more and more complex. In an actual capacitor manufacturing process, since the capacitor is disposed in the memory cell region, a high level difference generated between the peripheral circuit region (also referred to as a peripheral region) and the memory cell region (also referred to as a cell region) due to the height of the capacitor needs to be removed in order to perform a subsequent patterning process.

The typical method of removing the high level difference is to deposit a dielectric layer above the height of the capacitor on the substrate after the capacitor is formed, and then planarize the dielectric layer to eliminate the high level difference in the peripheral circuit region and the memory cell region. However, in this process, the added deposition process and planarization process are additionally costly and may create defects such as: scratches, pits, erosion, particles, etc., thereby affecting the yield of the semiconductor device.

Disclosure of Invention

The invention aims to provide a semiconductor device and a manufacturing method thereof, which are used for controlling the process cost, eliminating the high level difference formed by the height of a capacitor in a cell area and a peripheral area, improving the process defect and further improving the product yield.

In order to achieve the above object, the present invention provides a semiconductor device including:

a substrate; the substrate is provided with a peripheral area, a unit area and a partition area positioned between the peripheral area and the unit area;

a capacitor pattern formed on the substrate, the capacitor pattern being located in the cell region;

an etching barrier pattern formed on the substrate, the etching barrier pattern being located in the partition region, upper surfaces of the etching barrier pattern and the capacitor pattern being flush with the upper surface of the substrate; the lower surface of the etch stop pattern is at least flush with the lower surface of the capacitor pattern.

Compared with the prior art, in the semiconductor device provided by the invention, the etching barrier pattern is formed on the substrate positioned in the isolation region, and the lower surface of the etching barrier pattern is at least flush with the lower surface of the capacitor pattern. That is, the etch stop pattern extends into the substrate to a depth greater than or equal to the depth of the capacitor pattern extending into the substrate. In addition, the etching barrier pattern has a good barrier effect. Based on this, an etching barrier pattern may be formed on the substrate in advance in manufacturing the semiconductor device to avoid corrosion of the corresponding structure located in the peripheral region by subsequent wet etching. Meanwhile, the upper surfaces of the etching barrier pattern and the capacitor pattern are flush with the upper surface of the substrate, so that the upper surfaces of the whole peripheral area, the partition area and the unit area are flattened, and a semiconductor device without high level difference is formed. Therefore, in the manufacturing process of the semiconductor device provided by the invention, a dielectric layer is not required to be formed above a substrate by adopting an additional deposition process, and the dielectric layer is flattened by adopting a flattening process, so that defects such as scratch, pit, erosion and particle generated by high-level difference can be avoided, and the adverse effect of a final product is ensured.

The invention also provides a manufacturing method of the semiconductor device, which comprises the following steps:

providing a substrate; the substrate is provided with a unit area, a peripheral area and a partition area positioned between the unit area and the peripheral area;

forming a capacitor pattern and an etch stop pattern on a substrate; the capacitor pattern is located in the cell region; the etching barrier pattern is positioned in the isolation area, and the upper surfaces of the etching barrier pattern and the capacitor pattern are flush with the upper surface of the substrate; the lower surface of the etch stop pattern is at least flush with the lower surface of the capacitor pattern.

Compared with the prior art, the beneficial effects of the manufacturing method of the semiconductor device provided by the invention are the same as those of the semiconductor device provided by the technical scheme, and the description is omitted here.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and do not constitute a limitation on the invention. In the drawings:

FIG. 1 is a schematic diagram of a process flow of a prior art method for fabricating a semiconductor device;

FIG. 2 is a schematic diagram of a process flow of a semiconductor device according to the prior art;

FIG. 3 is a schematic view of a structure of a substrate according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a structure after forming a first pattern hole structure and a second pattern hole structure according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a structure after forming a capacitor pattern and an etch stop pattern according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a structure after forming a mask layer according to an embodiment of the present invention;

FIG. 7 is a schematic view of a structure of the embodiment of the invention after exposing the molding material layer;

FIG. 8 is a schematic view of the structure after forming the molding layer and the support layer according to an embodiment of the present invention;

reference numerals:

100 is a substrate, 101 is a peripheral region, 102 is a cell region, 103 is a partition region,

104, 1041, 1042 is a first conductive layer,

105, 1051, 1052 is a second pattern hole structure, 1052 is an etch stop layer,

200 is a layer of molding material, 201 is a layer of bottom molding material, 202 is a layer of intermediate molding material,

210, 211, bottom, 212,

300 is a layer of support material, 301 is a layer of intermediate support material, 302 is a layer of top support material,

310 is the support layer, 311 is the intermediate support layer, 312 is the top support layer,

400 is an amorphous carbon layer, 500 is an anti-reflective layer, and 610 is a mask layer.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is only exemplary and is not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure.

Various structural schematic diagrams according to embodiments of the present disclosure are shown in the drawings. The figures are not drawn to scale, wherein certain details are exaggerated for clarity of presentation and may have been omitted. The shapes of the various regions, layers and relative sizes, positional relationships between them shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.

In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. In addition, if one layer/element is located "on" another layer/element in one orientation, that layer/element may be located "under" the other layer/element when the orientation is turned. In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise. The meaning of "a number" is one or more than one unless specifically defined otherwise.

In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.

Fig. 1 and 2 are schematic views showing a process of forming and discharging a lower electrode included in a capacitor in the related art. As shown in fig. 1, the surface of the substrate 100 is formed with two stacked layers of a molding material layer 200 and a supporting material layer 300 alternately stacked. Portions of the two stacked layers located within the unit region 102 are etched to form an electrode hole pattern (i.e., a first pattern hole structure 1041). Next, a lower electrode (i.e., the first conductive layer 1042) is formed on the inner wall of the hole comprised by the electrode hole pattern. Then, a mask layer 610 is formed on the unit region 102, and the area of the mask layer 610 covering the unit region 102 is the area where the subsequently formed top support layer 312 is located. Under the masking action of the masking layer 610, the top support material layer 302 is etched to remove portions of the top support material layer 302 exposed outside the masking layer 610 to expose the molding material layer 200 below the top support material layer 302. After removing the molding material layer 200, the lower electrode surrounded by the molding material layer 200 may be released.

As can be seen from the above-described process of forming and releasing the lower electrode, after removing the portion of the top support material layer 302 exposed outside the mask layer 610, not only the portion of the molding material layer 200 located at the partial cell region 102 but also the portion of the molding material layer 200 located at the peripheral region 101 are exposed. Based on this, as shown in fig. 2, in the process of etching the molding material layer 200 to release the lower electrode, not only the portion of the molding material layer 200 located at the outer periphery of the lower electrode of the cell region 102 but also the portion of the molding material layer 200 located at the peripheral region 101 are removed, so that a high level difference is generated between the peripheral region 101 and the cell region 102. In order to eliminate the high level difference between the peripheral region 101 and the cell region 102, the prior art generally deposits a dielectric layer higher than the capacitor height on the substrate 100 after the capacitor is formed, and then planarizes the dielectric layer, thereby eliminating the high level difference between the peripheral region 101 and the cell region 102. However, in this process, the added deposition process and planarization process add additional expense and may create drawbacks such as: scratches, pits, erosion, particles, etc., thereby affecting the yield of the semiconductor device.

In order to solve the technical problems, embodiments of the present invention provide a semiconductor device and a method for manufacturing the same. In the semiconductor device provided by the embodiment of the invention, the etching barrier pattern is formed on the part of the substrate located in the isolation region, the upper surface of the etching barrier pattern is flush with the upper surface of the substrate, and the lower surface of the etching barrier pattern is at least flush with the lower surface of the capacitor pattern. Based on this, in manufacturing the semiconductor device, an etching barrier pattern may be formed on the substrate in advance to avoid the influence of the subsequent etching process on the peripheral region. Therefore, a dielectric layer is formed above the substrate without adopting a deposition process and a planarization process additionally when the semiconductor device is manufactured, so that defects such as scratch, pit, erosion, particles and the like caused by high-level differences can be avoided, and the product yield is improved.

As shown in fig. 8, the semiconductor device provided by the embodiment of the present invention includes a substrate 100, a capacitor pattern 104, and an etch stop pattern 105.

Specifically, as shown in fig. 8, the substrate 100 has a peripheral region 101, a cell region 102, and a partition region 103 located between the peripheral region 101 and the cell region 102. Wherein the peripheral region 101 is mainly a peripheral circuit region of the semiconductor device, and is formed in a region around the cell region 102. The cell region 102 is mainly a region where a memory cell is located in a semiconductor device. For example: for DRAM (dynamic random access memory), the memory cell includes a transistor and a capacitor. At this time, the memory cell includes a transistor and a capacitor in the cell region 102. And the partition 103 is an area where the peripheral region 101 and the cell region 102 interface.

The substrate 100 may be a substrate on which no film layer is formed, or may be a substrate on which some film layers are formed. The substrate on which any film layer is not formed may be a silicon substrate, a germanium substrate, a silicon-on-insulator substrate, or the like, which is not exemplified herein.

In one example, as shown in fig. 8, the substrate 100 may have the mold layers 210 and the support layers 310 alternately stacked. The number of layers of the mold layer 210 and the support layer 310 may be set according to practical situations. For example: the number of the molding layers 210 may be two, and the two molding layers 210 include a bottom molding layer 211 and an intermediate molding layer 212 positioned above the bottom molding layer 211. The number of the support layers 310 may be two, and the two support layers 310 include: an intermediate support layer 311, and a top support layer 312 located above the intermediate support layer 311. In addition, the molding layer 210 is located in the peripheral region 101. The top support layer 312 is located at a part of the cell region 102 and the peripheral region 101, and the middle support layer 311 is located at the peripheral region 101 and the cell region 102. The material of the molding layer 210 may be an oxide containing a substrate material. The material of the supporting layer 310 may be nitride containing substrate material. For example, when the substrate 100 is a silicon substrate, the material of the molding layer 210 may be SiO ₂ . The material of the support layer 310 may be SiN.

As shown in fig. 8, the above-mentioned capacitor pattern 104 is formed on the substrate 100, and the capacitor pattern 104 is located in the cell region 102. It should be appreciated that the number of the capacitor patterns 104 may be plural. The plurality of capacitor patterns 104 may be arranged in a matrix-matched manner at a portion of the substrate 100 located at the cell region 102.

In one example, as shown in fig. 8, the capacitor pattern 104 may include a first pattern hole structure 1041, and a first conductive layer 1042 covering an inner wall of the first pattern hole structure 1041. The first pattern hole structure 1041 may be a cylindrical first pattern hole structure. The material of the first conductive layer 1042 may be a conductive material such as TiN, taN, WN.

As shown in fig. 8, the above-described etch stop pattern 105 is formed on the substrate 100, and the etch stop pattern 105 is located in the partition 103. The upper surfaces of the etch stop pattern 105 and the capacitor pattern 104 are flush with the upper surface of the substrate 100. The lower surface of the etch stop pattern 105 is at least flush with the lower surface of the capacitor pattern 104. It should be appreciated that when the lower surface of the etch stop pattern 105 is at least flush with the lower surface of the capacitor pattern 104, the etch stop pattern 105 extends into the substrate 100 to a depth greater than or equal to the depth of the capacitor pattern 104 extending into the substrate 100. Specifically, the specific structure of the etching stopper pattern 105 and the depth of the etching stopper pattern 105 extending into the substrate 100 may be set according to practical situations, so long as the corresponding structure located in the peripheral area 101 can be protected from damage during the subsequent etching process of the structure in the cell area 102.

In practical application, in view of the fact that the peripheral area is located around the unit area, the etching blocking pattern can be reasonably patterned, namely, the etching blocking pattern is reasonably patterned according to the shape and layout of the peripheral area and the structure and shape of the capacitor pattern located in the unit area, so that the etching blocking pattern can be distributed more uniformly on the portion of the substrate located in the partition area through a simple process. The etching barrier pattern may be a linear etching barrier pattern, or may be a wavy etching barrier pattern or an arc etching barrier pattern.

In the manufacture of a semiconductor device, an etching barrier pattern may be formed on a substrate in advance to avoid subsequent wet etching from corroding a molding material layer (a film layer for forming the foregoing molding layer) located in the peripheral region. Meanwhile, the upper surfaces of the etching barrier pattern and the capacitor pattern are flush with the upper surface of the substrate, so that the upper surfaces of the whole peripheral area, the partition area and the unit area are flattened, and a semiconductor device without high level difference is formed. Therefore, in the manufacturing process of the semiconductor device provided by the embodiment of the invention, a dielectric layer is not required to be formed above a substrate by adopting an additional deposition process, and the dielectric layer is flattened by adopting a flattening process, so that defects such as scratch, pit, erosion and particle generated by high-level difference can be avoided, and the adverse effect of a final product is ensured.

In one possible implementation, as shown in fig. 8, the etching stop pattern 105 includes a second pattern hole structure 1051, and an etching stop layer 1052 covering an inner wall of the second pattern hole structure 1051.

Specifically, the specific specification and shape of the above-described second pattern hole structure may be determined according to the relative positional relationship between the cell region and the peripheral region. For example: when the peripheral region is formed only at one side of the cell region, the second pattern hole structure may be a linear second pattern hole structure opened in the partition region and dividing the cell region and the peripheral region. Also for example: the second pattern hole structure may be a circular second pattern hole structure when the peripheral region surrounds the periphery of the cell region.

For the above-mentioned etching barrier layer, the material of the etching barrier layer needs to have a certain etching selectivity ratio with the material of the molding layer and the supporting layer, respectively. Illustratively, the material of the etch stop layer may be one or more of TiN, taN, WN, but is not limited thereto.

In practical application, the capacitor pattern can be formed on the part of the substrate located in the unit area and the etching barrier pattern can be formed on the part of the substrate located in the partition area, so that more steps of processes can be saved to simultaneously achieve the purposes of forming the etching barrier pattern and forming the capacitor pattern. In this case, the material of the etching stopper layer included in the etching stopper pattern is the same as the material of the first conductive layer included in the capacitor pattern. Of course, after or before the etching barrier pattern is formed, the capacitor pattern may be formed on the portion of the substrate located in the cell region, and both methods may achieve the purpose, or may avoid adverse effects on different structures when the same process is performed, but the process of separate operations may increase the process steps, thereby increasing the cost of the product.

In one possible implementation, the semiconductor device further includes a dielectric layer and a second conductive layer. The dielectric layer is disposed on the etch stop layer and the first conductive layer. The second conductive layer is located on the dielectric layer.

Specifically, after the molding layer is formed, a dielectric layer and a second conductive layer may be sequentially formed on the first conductive layer, so that a complete capacitor pattern may be formed. The first conductive layer in the capacitor pattern is a lower electrode, and the second conductive layer in the capacitor pattern is an upper electrode. When the complete capacitor pattern is formed, the dielectric layer and the second conductive layer can be formed in the second pattern hole structure at the same time, so that the inner space of the second pattern hole structure is filled, and the upper surfaces of the peripheral area, the partition area and the unit area are ensured to be level, thereby facilitating the follow-up process.

For the dielectric layer, the material contained in the dielectric layer is an insulating material. The insulating material may be silicon oxide or a high K (dielectric constant) material. For the second conductive layer, the material contained in the second conductive layer may be doped polysilicon, silicon germanium, metal or metal nitride.

Fig. 3 to 8 are schematic views illustrating states of respective steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. As shown in fig. 3 to 8, the method for manufacturing the semiconductor device includes:

as shown in fig. 3, a substrate 100 is provided. The substrate 100 has a peripheral region 101, a partition region 103, and the partition region 103 located between the peripheral region 101 and the cell region 102. The material and structure of the substrate 100 are described above with reference to the substrate 100 and are not described in detail herein.

Illustratively, as shown in fig. 3, molding material layers 200 and supporting material layers 300 are alternately stacked on a substrate 100. The number and material of the molding material layer 200 may be set with reference to the number and material of the molding layer 210 described above. The number and material of the support material layer 300 may be set with reference to the number and material of the support layer 310 described above, and will not be described in detail herein.

For example: as shown in fig. 3, the number of the molding material layers 200 may be two, and the two molding material layers 200 include a bottom molding material layer 201 and an intermediate molding material layer 202. The number of the support material layers 300 may be two, and the two support material layers 300 include a middle support material layer 301 and a top support material layer 302.

In the actual application process, the bottom molding material layer 201, the middle supporting material layer 301, the middle molding material layer 202 and the top supporting material layer 302 may be sequentially formed on the substrate 100 by deposition, and at this time, the portions of the substrate 100 located in the peripheral region 101, the cell region 102 and the partition region 103 each have the alternately laminated molding material layers 200 and supporting material layers 300 as shown in fig. 3.

As shown in fig. 4, a first pattern hole structure 1041 is formed in a portion of the substrate 100 located in the cell region 102, and a second pattern hole structure 1051 is formed in a portion of the substrate 100 located in the partition region 103.

For example, as shown in fig. 4, the portions of the substrate 100 located in the cell region 102 and the partition region 103 may be etched using photolithography and etching processes, and the second pattern hole structure 1051 may be formed in the partition region 103 while the first pattern hole structure 1041 is formed in the cell region 102. The shapes, specifications, and distributions of the first pattern hole structures 1041 and the second pattern hole structures 1051 may be referred to as above, and will not be described herein.

Alternatively, the above manner may be adopted, where the portion of the etching substrate located in the partition region forms the second pattern hole structure before or after the portion of the etching substrate located in the cell region forms the first pattern hole structure. Specifically, the order of formation of the first pattern hole structure and the second pattern hole structure may be set according to actual conditions, and is not particularly limited herein.

As shown in fig. 5, a capacitor pattern 104 is formed at a portion of the substrate 100 located in the cell region 102, and an etch stop pattern 105 is formed at a portion of the substrate 100 located in the partition region 103. The upper surfaces of the etch stop pattern 105 and the capacitor pattern 104 are flush with the upper surface of the substrate 100. The lower surface of the etch stop pattern 105 is at least flush with the lower surface of the capacitor pattern 104.

For example, a conductive material layer covering the substrate 100, the inner wall of the first pattern hole structure 1041, and the inner wall of the second pattern hole structure 1051 may be formed using a chemical vapor deposition or the like. And planarizing the conductive material layer to remove portions of the conductive material layer that are on the surface of the substrate 100. Accordingly, as shown in fig. 5, a portion of the conductive material layer located on the inner wall of the first pattern hole structure 1041 forms a first conductive layer 1042. The capacitor pattern 104 includes a first pattern hole structure 1041 and a first conductive layer 1042. The portion of the conductive material layer located on the inner wall of the second pattern hole structure 1051 forms an etch stop layer 1052, and the etch stop pattern 105 includes the second pattern hole structure 1051 and the etch stop layer 1052. As can be seen from the above, the capacitor pattern 104 and the etch stop pattern 105 may be formed on the substrate 100 at the same time using the same process. In this way, more steps of the process may be saved to achieve both the purpose of forming the etch stop pattern 105 and the purpose of forming the capacitor pattern 104.

It should be noted that the above process may be adopted, where the portion of the substrate located in the cell area is etched to form a first pattern hole structure, and the inner wall of the first pattern hole structure is covered to form a first conductive layer, so as to obtain the capacitor pattern. Then, the etching barrier pattern is formed on the portion of the substrate located in the partition area in the mode. Alternatively, the above process may be used to form the etching barrier pattern on the portion of the substrate located in the isolation region, and then form the capacitor pattern on the portion of the substrate located in the cell region. Both methods achieve the objective and avoid the adverse effects on different structures when the same process is performed, but the separate operation of the process increases the number of process steps and thus the cost.

As shown in fig. 6, a mask layer 610 is formed on the upper surface of the substrate 100.

For example, as shown in fig. 6, an amorphous carbon layer 400 may be formed on the upper surface of the substrate 100. In addition, an anti-reflection layer 500 may be further formed on the amorphous carbon layer 400 to reduce light reflected by the substrate 100 toward the photoresist layer during subsequent exposure of the photoresist layer, thereby improving the accuracy of the photoresist pattern formed through the photoresist layer. Next, a photoresist layer is formed on the anti-reflection layer 500, and the photoresist layer is exposed to a laser or a specific light, at this time, as shown in fig. 6, a photoresist pattern protecting at least the peripheral region 101 and a portion of the cell region 102 is obtained. An etching process may then be used to etch the anti-reflective layer 500 and the amorphous carbon layer 400 from top to bottom under the mask of the photoresist pattern, resulting in the mask layer 610.

The anti-reflection layer may be made of silicon oxynitride, silicon nitride, silicon oxide, or the like. The thicknesses of the amorphous carbon layer, the anti-reflection layer and the photoresist layer may be set according to actual conditions, and are not particularly limited herein.

It should be noted that, under the condition that the thickness of the photoresist layer is smaller, the amorphous carbon layer can be used as an etching mask to improve the effect of subsequent etching. Therefore, the amorphous carbon layer may not be formed when the thickness of the photoresist layer is appropriate. In addition, the photoresist pattern obtained after exposing the photoresist layer may cover only the peripheral region and a portion of the cell region. Or after the etching barrier pattern is formed, if a part of the supporting material layer and the molding material layer remain between the side wall of the second pattern hole structure and the peripheral area, the photoresist pattern is not only covered on the peripheral area and a part of the unit area, but also needs to be covered on the partition area in order to ensure that the supporting material layer and the molding material layer in the peripheral area are not affected in the subsequent etching process. The photoresist pattern covers the unit area, and the area where the part of the subsequently formed top support layer is located in the unit area.

As shown in fig. 7, a support layer 310 is formed on the substrate 100.

For example, as shown in fig. 7, when two support material layers 300 are formed on the substrate 100, an etching process or a liquid phase laser ablation (Laser ablation in liquids, LAL) may be used to remove at least a portion of the top support material layer 302 located in the cell region 102 under the mask of the mask layer 610, so that the remaining support material layers 300 form the support layer 310. The portion of the middle support layer 311 and the top support layer 312 located in the cell region 102 may support the capacitor pattern 104, so as to ensure that the capacitor pattern 104 does not fall down. And, an intermediate support layer 311 on the substrate 100, and a top support layer 312 at least in the peripheral region 101 are used to support the etch stop pattern 105.

As shown in fig. 8, a molding layer 210 is formed on the substrate 100.

Illustratively, as shown in fig. 8, under the mask of the mask layer 610, an etching process or a liquid phase laser ablation technique (Laser ablation in liquids, abbreviated as LAL) may be used to completely remove the portion of the molding material layer 200 located in the cell region 102, so that at least the molding material layer 200 located in the peripheral region 101 forms the molding layer 210. And the supporting layer 310 located at the peripheral region 101 and the molding layer 210 located at the peripheral region 101 are laminated with each other, ensuring a certain height for eliminating the high level difference of the peripheral region 101 and the cell region 102.

Note that, as shown in fig. 7 and 8, under the mask of the mask layer 610, by removing the portion of the top support material layer 302 located in the partial cell region 102 and removing the portion of the mold material layer 200 located in the cell region 102, the alternately stacked mold material layers 200 and support material layers 300 of the portion of the substrate 100 located in the peripheral region 101 are maintained, so that the upper surface of the peripheral region 101, the upper surface of the partition region 103 having the etching stopper pattern 105, and the upper surface of the cell region 102 having the capacitor pattern 104 are flush, thereby eliminating a step difference formed between the peripheral region 101 and the cell region 102 due to the height of the capacitor pattern 104. Therefore, the manufacturing method of the semiconductor device provided by the embodiment of the invention does not need to adopt a deposition process to form a dielectric layer above the substrate 100, and adopts a planarization process to planarize the dielectric layer, so that defects such as scratch, pit, erosion, particle and the like caused by high-level differences can be avoided, thereby ensuring that the final product has adverse effects and improving the product yield.

As one possible implementation, after the molding layer is formed, a dielectric layer and an upper electrode may be sequentially formed on the first conductive layer. The first conductive layer, the portion of the dielectric layer on the first conductive layer, and the portion of the second conductive layer on the first conductive layer form a complete capacitor pattern. At this time, the first conductive layer in the capacitor pattern is a lower electrode. The second conductive layer in the capacitor pattern is an upper electrode. In particular, the dielectric layer may be located not only on the inner surface of the first conductive layer but also on the outer surface of the first conductive layer.

In practical application, when a film layer is deposited on the first conductive layer to form a complete capacitor pattern, a corresponding film layer can be deposited in the second pattern hole structure at the same time, so that the process can be greatly simplified on one hand, and the inner space of the second pattern hole structure is filled on the other hand, so that the upper surfaces of the peripheral region, the partition region and the unit region are flush. For example, while depositing a film layer within the first pattern hole structure to form a capacitor pattern, deposition may be correspondingly performed within the second pattern hole structure. At this time, a dielectric layer and a second conductive layer may be sequentially formed in the second pattern hole structure in a thin film deposition manner. The dielectric layer is located on the etching barrier layer, and the second conductive layer is located on the dielectric layer, that is, the dielectric layer is located between the etching barrier layer and the second conductive layer.

In the above description, technical details of patterning, etching, and the like of each layer are not described in detail. Those skilled in the art will appreciate that layers, regions, etc. of the desired shape may be formed by a variety of techniques. In addition, to form the same structure, those skilled in the art can also devise methods that are not exactly the same as those described above. In addition, although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination.

The embodiments of the present disclosure are described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the disclosure, and such alternatives and modifications are intended to fall within the scope of the disclosure.

Claims (10)

1. A semiconductor device, comprising:

a substrate; the substrate is provided with a peripheral area, a unit area and a partition area positioned between the peripheral area and the unit area;

a capacitor pattern formed on the substrate, the capacitor pattern being located in the cell region;

an etch stop pattern formed on the substrate, the etch stop pattern being located in the isolation region, upper surfaces of the etch stop pattern and the capacitor pattern being flush with an upper surface of the substrate; the lower surface of the etch stop pattern is at least flush with the lower surface of the capacitor pattern.

2. The semiconductor device according to claim 1, wherein the capacitor pattern includes a first pattern hole structure in the cell region, and a first conductive layer covering an inner wall of the first pattern hole structure;

the etching barrier pattern comprises a second pattern hole structure positioned in the partition area and an etching barrier layer covering the inner wall of the second pattern hole structure; the upper surface of the etching barrier layer is flush with the upper surface of the first conductive layer.

3. The semiconductor device according to claim 2, wherein a material of the etching stopper layer is the same as a material of the first conductive layer; and/or the number of the groups of groups,

the semiconductor device further includes a dielectric layer and a second conductive layer, the dielectric layer being on the etch stop layer and the first conductive layer, the second conductive layer being on the dielectric layer.

4. A semiconductor device according to any one of claims 1 to 3, wherein the substrate has alternately laminated mold layers and support layers; the molding layer is located at the peripheral region, and the supporting layer is located at the peripheral region and the unit region.

5. The semiconductor device according to claim 4, wherein the number of support layers is two;

the two layers of the supporting layer comprise: a middle support layer, and a top support layer positioned above the middle support layer; the top support layer is located in the peripheral region and a portion of the cell region, and the middle support layer is located in the peripheral region and the cell region.

6. A method of manufacturing a semiconductor device, comprising:

providing a substrate; the substrate has a cell region, a peripheral region, and a partition region between the cell region and the peripheral region;

forming a capacitor pattern and an etch stop pattern on the substrate; the capacitor pattern is located in the cell region; the etching barrier pattern is positioned in the isolation area, and the upper surfaces of the etching barrier pattern and the capacitor pattern are flush with the upper surface of the substrate; the lower surface of the etch stop pattern is at least flush with the lower surface of the capacitor pattern.

7. The method for manufacturing a semiconductor device according to claim 6, wherein forming the capacitor pattern on the substrate comprises:

etching the part of the substrate located in the unit area to form a first pattern hole structure;

forming a first conductive layer on the inner wall of the first pattern hole structure; the capacitor pattern includes the first pattern hole structure and the first conductive layer; and/or the number of the groups of groups,

forming the etching barrier pattern on the substrate, comprising:

etching the part of the substrate, which is positioned in the partition area, to form a second pattern hole structure;

forming an etching barrier layer on the inner wall of the second pattern hole structure; the etching barrier pattern comprises the second pattern hole structure and the etching barrier layer.

8. The method for manufacturing a semiconductor device according to claim 7, wherein the substrate includes a molding material layer and a supporting material layer which are alternately stacked;

after the capacitor pattern and the etching barrier pattern are formed on the substrate, the method for manufacturing the semiconductor device further comprises the following steps:

forming a mask layer on the upper surface of the substrate;

and removing a part of the molding material layer located in the unit area under the mask of the mask layer, so that a part of the molding material layer located in the peripheral area forms a molding layer.

9. The method for manufacturing a semiconductor device according to claim 8, wherein the number of support material layers is two; the two layers of the support material include: a middle support material layer and a top support material layer;

after forming the mask layer on the upper surface of the substrate, before removing the part of the molding material layer located in the cell region under the mask of the mask layer, the method for manufacturing the semiconductor device further comprises:

and removing part of the top support material layer positioned on the part of the unit area under the mask of the mask layer, so that the top support material layer forms a top support layer, and the middle support material layer forms the middle support layer.

10. The method of manufacturing a semiconductor device according to claim 8, wherein forming a mask layer on an upper surface of the substrate comprises:

forming an anti-reflection layer on the upper surface of the substrate;

forming a photoresist layer on the anti-reflection layer;

exposing the photoresist layer to obtain a photoresist pattern for protecting at least the peripheral area and part of the unit area; the mask layer comprises the photoresist pattern; and/or the number of the groups of groups,

the method for manufacturing the semiconductor device further comprises the steps of, after removing the part of the molding material layer located in the unit area under the mask of the mask layer:

forming a dielectric layer on the etching barrier layer and the first conductive layer;

a second conductive layer is formed over the dielectric layer.