CN116546877B

CN116546877B - Method for preparing semiconductor structure

Info

Publication number: CN116546877B
Application number: CN202310832116.0A
Authority: CN
Inventors: 文兴成
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2023-07-07
Filing date: 2023-07-07
Publication date: 2023-12-05
Anticipated expiration: 2043-07-07
Also published as: CN116546877A

Abstract

The disclosure provides a preparation method of a semiconductor structure, and relates to the technical field of semiconductors. The method comprises the following steps: providing a wafer, wherein the wafer comprises a substrate and a laminated layer formed on the substrate, and the laminated layer comprises a sacrificial layer and a supporting layer; forming a capacitor etching protection layer on the laminated layer, wherein the capacitor etching protection layer comprises a first photoresist region and a second photoresist region, the first photoresist region covers a non-capacitor region of the wafer, and the second photoresist region covers an edge region of the wafer; forming a capacitor hole penetrating through the laminated layer in a region which is not covered by the capacitor etching protective layer; forming a lower electrode in the capacitor hole; and removing the sacrificial layer. The present disclosure improves the problems of capacitor collapse and spalling and reduces manufacturing costs.

Description

Method for preparing semiconductor structure

Technical Field

The disclosure relates to the field of semiconductor technology, and in particular, to a method for manufacturing a semiconductor structure.

Background

With the evolution of semiconductor processes, devices are continuously improved in miniaturization and integration. In order to increase the storage density, the aspect ratio of the capacitor is continuously increased, so that the three-dimensional space can be fully utilized, the area of the capacitor is increased, and the storage capacitor is improved.

However, with the increase of the aspect ratio of the capacitor, the capacitor structure is easy to incline or bend, even collapse or peel (peeling) during the process, which results in wafer contamination, and seriously affects the electrical property of the semiconductor, and reduces the yield of the product.

Disclosure of Invention

The present disclosure provides a method of fabricating a semiconductor structure to address, at least to some extent, the problem of capacitor collapse and spalling.

According to one aspect of the present disclosure, there is provided a method of manufacturing a semiconductor structure, comprising: providing a wafer, wherein the wafer comprises a substrate and a laminated layer formed on the substrate, and the laminated layer comprises a sacrificial layer and a supporting layer; forming a capacitor etching protection layer on the laminated layer, wherein the capacitor etching protection layer comprises a first photoresist region and a second photoresist region, the first photoresist region covers a non-capacitor region of the wafer, and the second photoresist region covers an edge region of the wafer; forming a capacitor hole penetrating through the laminated layer in a region which is not covered by the capacitor etching protective layer; forming a lower electrode in the capacitor hole; and removing the sacrificial layer.

Optionally, the forming a capacitive etching protection layer on the stack layer includes: coating a negative photoresist material on the stack; exposing the negative photoresist material by using a photomask defining the pattern of the non-capacitance area, and exposing the negative photoresist material of the edge area by a wafer edge exposure process; and developing the negative photoresist material to retain the negative photoresist material covering the non-capacitance region and the negative photoresist material covering the edge region, thereby forming the first photoresist region and the second photoresist region respectively.

Optionally, the forming a capacitor hole penetrating through the stack layer in a region not covered by the capacitor etching protection layer includes: forming a capacitor hole photoresist layer in a region of the stack layer which is not covered by the capacitor etching protective layer, wherein the missing part of the capacitor hole photoresist layer defines the pattern of the capacitor hole; and etching the lamination by taking the capacitor etching protection layer and the capacitor hole photoresist layer as masks to form the capacitor hole, and removing the capacitor etching protection layer and the capacitor hole photoresist layer.

Optionally, a mask layer is further formed on the stack layer, and the capacitor etching protection layer and the capacitor hole photoresist layer are located on the mask layer; and etching the laminated layer by using the capacitor etching protection layer and the capacitor hole photoresist layer as masks to form the capacitor hole, and removing the capacitor etching protection layer and the capacitor hole photoresist layer, wherein the method comprises the following steps: etching the mask layer by taking the capacitor etching protection layer and the capacitor hole photoresist layer as masks; removing the capacitor etching protective layer and the capacitor hole photoresist layer; and etching the laminated layer by taking the mask layer as a mask to form the capacitor hole.

Optionally, the material of the capacitor etching protection layer is the same as that of the capacitor hole photoresist layer.

Optionally, the removing the sacrificial layer includes: and carrying out wet etching on the sacrificial layer along the opening in the supporting layer so as to remove the sacrificial layer.

Optionally, the projections of the capacitor holes on the substrate plane are arranged in a hexagonal shape, and each opening is located between three adjacent capacitor holes.

Optionally, after removing the sacrificial layer, forming a sacrificial layer space at a position of the sacrificial layer; the method further comprises the steps of: a dielectric is formed on the lower electrode and on an inner wall of the sacrificial layer space, and an upper electrode is formed to cover the dielectric.

Optionally, the edge region of the wafer includes an incomplete die area of the wafer, and the non-capacitive area is located within the complete die area of the wafer.

Optionally, the non-capacitive region includes one or more of: peripheral area, edge area of die, spacing area between different dies.

The technical scheme of the present disclosure has the following beneficial effects:

on the one hand, the problem that the capacitor structure is inclined, bent, even collapsed and peeled off due to insufficient etching of the capacitor holes at the edge is avoided by avoiding forming the capacitor holes and the capacitors at the edge area of the wafer, the defect number can be reduced, the problem of wafer pollution is improved, and the electrical property of the semiconductor and the yield of the product are improved. On the other hand, the scheme realizes the improvement of the capacitor collapse problem of the edge area under the condition of not increasing the photoetching times, and is beneficial to reducing the manufacturing cost and improving the production efficiency.

Drawings

Fig. 1A shows a defect schematic of a wafer edge region.

Fig. 1B shows a schematic diagram of insufficient capacitor hole depth.

Fig. 1C shows a schematic diagram of the collapse and spalling of a capacitive structure.

Fig. 2 is a flowchart showing a method of manufacturing a semiconductor structure in the present exemplary embodiment.

Fig. 3 shows a schematic diagram of a complete grain region and a non-complete grain region.

Fig. 4 shows a schematic view of a wafer structure provided in the present exemplary embodiment.

Fig. 5 shows a schematic diagram of forming a capacitive etching protection layer in the present exemplary embodiment.

Fig. 6 shows a flowchart of forming a capacitive etch protection layer in the present exemplary embodiment.

Fig. 7A shows a schematic top view of a capacitive etching protection layer in this exemplary embodiment.

Fig. 7B shows a schematic top view of another capacitive etch protection layer in this exemplary embodiment.

Fig. 7C shows a partial enlarged view in fig. 7B.

Fig. 8 shows a flowchart of forming a capacitor hole in the present exemplary embodiment.

Fig. 9 is a schematic diagram showing formation of a capacitor hole photoresist layer in the present exemplary embodiment.

Fig. 10 shows a schematic diagram of forming a capacitor hole in the present exemplary embodiment.

Fig. 11 is a schematic diagram showing removal of the capacitor etch resist and the capacitor hole photoresist layer in the present exemplary embodiment.

Fig. 12 shows a flowchart of forming a capacitor hole in the present exemplary embodiment.

Fig. 13 shows a schematic diagram of forming a capacitor hole photoresist layer in the presence of a mask layer in the present exemplary embodiment.

Fig. 14 shows a schematic diagram of an etching mask layer in the present exemplary embodiment.

Fig. 15 shows a schematic diagram of forming a capacitor hole and a lower electrode in the present exemplary embodiment.

Fig. 16 shows a schematic diagram of removal of the sacrificial layer in the present exemplary embodiment.

Fig. 17 shows a schematic diagram of the capacitor holes and openings in the present exemplary embodiment.

Fig. 18 shows a schematic diagram of forming dielectrics and upper electrodes in the present exemplary embodiment.

Fig. 19 shows a wafer defect comparison chart of the related art and the present exemplary embodiment.

The reference numerals are as follows:

101: a substrate; 102: a sacrificial layer; 102': sacrificial layer space; 103: a support layer; 104: an isolation structure; 105: a capacitor connection part; 1051: a contact window; 1052: a conductive layer; 106: etching the protective layer by using a capacitor; 1061: a first photoresist region; 1062: a second photoresist region; 107: a capacitor hole; 108: a lower electrode: 109: dielectric medium: 110: an upper electrode; 111: a capacitor hole photoresist layer; 112: a mask layer; 113: an opening.

Detailed Description

Exemplary embodiments of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings.

The drawings are schematic illustrations of the present disclosure and are not necessarily drawn to scale. The technical solution of the present disclosure may be embodied in various forms and should not be construed as being limited to the examples set forth herein. The described features, structures, or characteristics of the disclosure may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough description of embodiments of the present disclosure. However, it will be understood by those skilled in the art that one or more specific details may be omitted, or other methods, components, structures, etc. may be used instead of one or more specific details in implementing the aspects of the present disclosure.

In a semiconductor device such as a DRAM (Dynamic Random Access Memory ), a capacitor is one of core devices. High aspect ratio capacitors can provide a larger capacitor area to increase storage capacitor size and storage density, but their dimensions in the depth direction are large, requiring the surrounding structures to provide a strong support. In semiconductor processing, capacitive collapse and spalling may occur.

The inventors have found that the collapse and peeling of the capacitor occur more in the edge region of the wafer, and that the defects (dots) generated by the peeling of the capacitor are concentrated more near the edge of the wafer as shown in fig. 1A. This is due to: when the capacitor hole is etched, the problem of insufficient etching capability exists in the edge area of the wafer, and the capacitor hole is difficult to etch to a desired depth, so that the depth and the shape of the capacitor hole are abnormal. As shown in fig. 1B, the rightmost capacitor hole is at the edge region of the wafer, and has a depth less than the normal capacitor hole due to under etching. Therefore, after partial or all capacitor structures (such as the lower electrode of the capacitor) are formed in the capacitor holes and the film layers on two sides of the capacitor are etched, the support of the surrounding residual structures on the capacitor is insufficient, and the capacitor is easy to collapse and peel. As shown in fig. 1C, after forming a lower electrode in the capacitor hole and etching the sacrificial layers on both sides, a supporting layer is left on both sides, and a dielectric layer is present at the bottom of the capacitor, so that the bottom and both sides can support the columnar structure of the capacitor under normal conditions. However, if the depth of the capacitor (or capacitor hole) is insufficient, the dielectric layer at the bottom cannot provide support, and the effect of the support layers at both sides may be weakened, so that the capacitor structure is easily collapsed and peeled off. Fig. 1C shows that the rightmost capacitor structure collapses, creating a spalling-type defect.

In some related art schemes, photoresist is applied to the wafer edge by adding one photolithography to make these areas free of capacitance, so as to improve the situation of capacitance collapse and peeling. However, this solution increases the number of times of photolithography, resulting in an increase in manufacturing cost and a decrease in production efficiency.

In view of one or more of the above problems, exemplary embodiments of the present disclosure provide a method of manufacturing a semiconductor structure capable of solving the problems of capacitor collapse and peeling. Fig. 2 shows an exemplary flow of the method, which may include the following steps S210 to S250:

step S210, providing a wafer, the wafer including a substrate 101 and a stack formed on the substrate 101, the stack including a sacrificial layer 102 and a support layer 103;

step S220, forming a capacitor etching protection layer 106 on the stack, wherein the capacitor etching protection layer 106 includes a first photoresist region 1061 and a second photoresist region 1062, the first photoresist region 1061 covers a non-capacitor region of the wafer, and the second photoresist region 1062 covers an edge region of the wafer;

step S230, forming a capacitor hole 107 penetrating the stack in a region not covered by the capacitor etching protection layer 106;

step S240, forming the lower electrode 108 in the capacitor hole 107;

in step S250, the sacrificial layer 102 is removed.

Based on the above method, on one hand, the problem that the capacitor structure is inclined, bent, even collapsed and peeled off due to insufficient etching of the capacitor hole 107 at the edge is avoided by avoiding forming the capacitor hole 107 and the capacitor at the edge region of the wafer, the defect number can be reduced, the problem of wafer pollution is improved, and the electrical property of the semiconductor and the yield of the product are improved. On the other hand, the scheme realizes the improvement of the capacitor collapse problem of the edge area under the condition of not increasing the photoetching times, and is beneficial to reducing the manufacturing cost and improving the production efficiency.

Each step in fig. 2 is specifically described below with reference to fig. 3 to 10.

Referring to fig. 2, in step S210, a wafer is provided, the wafer including a substrate 101 and a stack formed on the substrate 101, the stack including a sacrificial layer 102 and a support layer 103.

The wafer may include edge regions and non-edge regions. The present disclosure does not limit the size of the edge region. For example, the above-mentioned area with insufficient etching capability may be defined as an edge area, and the size of the edge area may be set empirically, for example, a circular area may be formed according to the center of the wafer and 95% of the radius of the wafer (or other empirically determined ratio), the circular area is defined as a non-edge area, and a wafer area other than the circular area is defined as an edge area.

In one embodiment, the edge region of the wafer may include an incomplete die area of the wafer. In semiconductor manufacturing, semiconductor devices are manufactured in wafer units, and after the manufacture of the semiconductor devices is completed, the wafer is cut into individual dies (die), each of which can be individually used as a chip (e.g., a memory chip). Referring to fig. 3, the die is rectangular or square, and the wafer is circular, so that the die in the edge region of the wafer is an incomplete die, the region where the incomplete die is located is referred to as an incomplete die region, and correspondingly, the die in the middle portion of the wafer is a complete die, and the region where the incomplete die is located is referred to as a complete die region. Incomplete die is usually an ineffective die, and the incomplete die area of the wafer is used as an edge area, so that the capacitor holes 107 and the capacitors are not formed in the incomplete die area in the subsequent steps, and the product yield is not affected.

The substrate 101 is typically located at the bottom of the wafer, providing a base for forming semiconductor devices. The substrate 101 may be formed of silicon (e.g., monocrystalline silicon, polycrystalline silicon, amorphous silicon), germanium, silicon-germanium compounds, group iii-v compounds (e.g., gallium arsenide), and the like. The substrate 101 may have an epitaxial layer or may be a silicon-on-insulator substrate (i.e., SOI substrate). The present disclosure is not limited to the specific structure in the substrate 101. For example, referring to fig. 4, the substrate 101 may have an isolation structure 104 formed therein, such as a shallow trench isolation, for separating different active regions, which may include a source region, a drain region, and a channel region.

With continued reference to fig. 4, a stack is formed on the substrate 101, the stack including the sacrificial layer 102 and the support layer 103 disposed in an overlapping manner, however, the stack may include only one sacrificial layer 102 and one support layer 103. The number of the sacrificial layer 102 and the support layer 103 is not limited in the present disclosure, and the number of the two may be equal to form an overlapped structure, for example, fig. 4 shows a case where the number of the sacrificial layer 102 and the support layer 103 is 2. It should be appreciated that the greater the number of support layers 103, the greater the subsequent support for the capacitor, but the more complex the corresponding fabrication process. In addition, the thickness of the sacrificial layer 102 and the supporting layer 103 is not limited in the present disclosure, and the thickness of the sacrificial layer 102 may be greater than the thickness of the supporting layer 103, so that sufficient space is reserved for the dielectric of the capacitor when the capacitor is formed subsequently, which is beneficial to improving the capacitor. In one embodiment, sacrificial layer 102 may be a material that is susceptible to wet chemical reactions, such as silicon oxide, and support layer 103 may be a chemically relatively stable insulating material, such as silicon carbonitride.

In one embodiment, the substrate 101 may further have a capacitor connection portion 105 formed thereon for connecting the active region in the substrate 101 to a location in the stack where a capacitor is to be formed, such that the capacitor connection portion 105 is capable of connecting the active region to the capacitor after the capacitor is formed. The capacitive connection 105 may include a contact 1051 and a conductive layer 1052, the bottom of the contact 1051 being in contact with the source or drain region in the active region and the top being in contact with the conductive layer 1052, although other layers for improving the contact may be provided between the contact 1051 and the conductive layer 1052. A Landing Pad (LP) may be formed on top of the conductive layer 1052, and after a capacitor is subsequently formed, the lower electrode of the capacitor may contact the Landing Pad and thus be connected to the active region through the capacitor connection 105. Both the contact 1051 and the conductive layer 1052 are made of conductive materials, for example, the contact 1051 may be made of polysilicon (or doped polysilicon), and the conductive layer 1052 may be made of metal or alloy. Bit lines, isolation layers (for isolating the contact 1051 from the bit lines), and the like may be formed between the contact 1051, and dielectric layers, and the like may be formed between the conductive layers 1052, which are not specifically shown in the figure.

With continued reference to fig. 2 and 5, in step S220, a capacitive etch protection layer 106 is formed on the stack, the capacitive etch protection layer 106 including a first photoresist region 1061 and a second photoresist region 1062, the first photoresist region 1061 covering a non-capacitive region of the wafer and the second photoresist region 1062 covering an edge region of the wafer.

For semiconductor devices, not all regions are used to form capacitance, non-capacitive regions refer to regions where capacitance is not required to be formed, as may include, but are not limited to, one or more of the following: peripheral Area (peripheral Area), edge Area of die, spacing Area between different dies (e.g. scribe line Area, etc.). In addition, it is also undesirable to form a capacitor in the edge region of the wafer, because the edge region has a problem of insufficient etching capability of the capacitor hole, as described above, and capacitor collapse and peeling are liable to occur.

In one embodiment, the edge region of the wafer includes an incomplete die area of the wafer. Thus, incomplete die areas may be disregarded when determining the non-capacitive areas. Specifically, the non-capacitive region may be located within a full die region of the wafer, such as may include a peripheral region of the full die, an edge region of the full die, and a spacing region between different full dies.

Referring to fig. 5, a capacitor etching protection layer 106 is formed on the stack, where the capacitor etching protection layer 106 includes a first photoresist region 1061 and a second photoresist region 1062, and the first photoresist region and the second photoresist region are used to cover the two regions where no capacitor is formed, i.e. a non-capacitor region and an edge region, respectively.

In the present exemplary embodiment, the capacitive etch protection layer 106 may be formed by a single photolithography process. For example, a mask covering the non-capacitance region and the edge region may be prepared in advance, and the capacitance etching protection layer 106 including the first photoresist region 1061 and the second photoresist region 1062 may be formed by exposure and development.

In one embodiment, referring to fig. 6, the formation of the capacitor etching protection layer on the stack may include the following steps S610 to S630:

step S610, coating negative photoresist material on the lamination;

step S620, exposing the negative photoresist material by using a photomask defining the pattern of the non-capacitance area, and exposing the negative photoresist material of the edge area by the wafer edge exposure process;

in step S630, the negative photoresist is developed to leave the negative photoresist covering the non-capacitor region and the negative photoresist covering the edge region, thereby forming a first photoresist region 1061 and a second photoresist region 1062, respectively.

The light-transmitting region of the mask defining the pattern of the non-capacitive region may be the pattern of the non-capacitive region for matching with the negative photoresist material. The negative photoresist is exposed to light using the mask, and the negative photoresist covering the non-capacitance region is irradiated and remains in the development process.

Wafer edge exposure (Wafer Edge Exposure, WEE) is one process that some litho machines are currently capable of providing. In a conventional photolithography process, wafer edge exposure is used to remove excess photoresist material from the wafer edge. In the present exemplary embodiment, wafer edge exposure is used to achieve a completely opposite effect from conventional processes, i.e., not to remove the photoresist, but to retain the photoresist. Specifically, the negative photoresist material of the wafer edge area is exposed through the wafer edge exposure process, and the negative photoresist material is remained in the developing process.

In step S620, the negative photoresist may be exposed by a photomask, and then the negative photoresist in the edge region may be exposed by a wafer edge exposure process, or the negative photoresist in the edge region may be exposed by a wafer edge exposure process, and then the negative photoresist may be exposed by a photomask.

After exposure, a development process is performed, and the exposed negative photoresist remains, including a negative photoresist covering the non-capacitive areas, which forms a first photoresist region 1061, and a negative photoresist covering the edge areas, which forms a second photoresist region 1062. Thus, no special mask is required for forming the second photoresist region 1062, and the cost of the mask is saved.

In one embodiment, in step S620, the negative photoresist material of the incomplete die area may be exposed by a wafer edge exposure process to form a second photoresist area 1062 covering the incomplete die area after development.

In the method of fig. 6, the wafer edge exposure function of the existing lithography machine is utilized and the use of negative photoresist is combined, so that the formation of the second photoresist region 1062 in the edge region of the wafer is realized, and the complete capacitor etching protection layer 106 is formed through one lithography process in combination with the process of forming the first photoresist region 1061, thereby reducing the lithography times, realizing the process based on conventional equipment and a photomask without greatly modifying the original process, and effectively reducing the manufacturing cost.

Fig. 7A and 7B illustrate top views of the capacitive etch protection layer 106, where the capacitive etch protection layer 106 includes a first photoresist region 1061 and a second photoresist region 1062, the first photoresist region 1061 covering a non-capacitive region in a full die region, and the second photoresist region 1062 covering a non-full die region located in a wafer edge region. Fig. 7A shows that the non-capacitive areas may be peripheral areas in each complete die. Fig. 7B illustrates that the non-capacitance region may be a scribe line region of each complete die edge, fig. 7C is a partial enlarged view of the incomplete die region and scribe line region of fig. 7B, the first photoresist region 1061 may cover the scribe line region, and the second photoresist region 1062 may completely cover the incomplete die region.

With continued reference to fig. 2, in step S230, a capacitor hole 107 is formed through the stack in the area not covered by the capacitor etch protection layer 106.

Therein, the capacitor hole 107 may be formed by a photolithography and etching process. Due to the existence of the capacitor etching protection layer 106, the process of forming the capacitor hole 107 does not affect the non-capacitor area and the incomplete grain area covered by the capacitor etching protection layer 106, i.e. the capacitor hole 107 is not formed in these areas, and the capacitor is not formed in these areas later.

In one embodiment, referring to fig. 8, the formation of the capacitor hole 107 penetrating the stack in the region not covered by the capacitor etching protection layer 106 may include the following steps S810 and S820:

step S810, forming a capacitor hole photoresist layer 111 on the region of the stack not covered by the capacitor etching protection layer 106, wherein the missing part of the capacitor hole photoresist layer 111 defines the pattern of the capacitor hole 107;

in step S820, the capacitor etching protection layer 106 and the capacitor hole photoresist layer 111 are used as masks to etch the stack layer, thereby forming the capacitor hole 107, and the capacitor etching protection layer 106 and the capacitor hole photoresist layer 111 are removed.

Referring to fig. 9, a capacitor hole photoresist layer 111 may be formed on the stack in areas not covered by the capacitor etch protection layer 106. Illustratively, a material of the capacitor hole photoresist layer 111 may be coated on the stack, which may be the same as or different from the material of the capacitor etch protection layer 106. Then, the material of the capacitor hole photoresist layer 111 is exposed to light by using a photomask defining the pattern of the capacitor hole 107, and then developed, and the remaining material forms the capacitor hole photoresist layer 111. If the material of the photoresist layer 111 with capacitor holes is positive photoresist, in the mask defining the pattern of the capacitor holes 107, the region corresponding to the capacitor holes 107 in the non-edge region, the non-capacitor region and the region corresponding to the edge region may be all set as light-transmitting regions, the remaining regions are light-shielding regions, and only the negative photoresist at the position of the light-shielding regions remains during exposure and development. If the material of the capacitor hole photoresist layer 111 is a negative photoresist material (the negative photoresist material may be the same as or different from that of the capacitor etching protection layer 106), in the mask defining the pattern of the capacitor hole 107, the area except for the capacitor hole 107 in the capacitor area other than the edge area may be set as a light-transmitting area, and the rest areas (including the area of the capacitor hole 107 in the capacitor area, the non-capacitor area and the edge area) are all light-shielding areas, so that only the negative photoresist material at the position of the light-transmitting area remains during exposure and development. The capacitor hole photoresist layer 111 thus formed, wherein the missing portions define the pattern of the capacitor holes 107.

Referring to fig. 10, the capacitor etching protection layer 106 and the capacitor hole photoresist layer 111 are used as masks to etch the stack, that is, the stack in the area where the missing portion of the capacitor hole photoresist layer 111 is located is etched, and the capacitor hole 107 penetrating through the stack is formed by controlling the etching time and other process parameters to etch to the bottom of the sacrificial layer 102 or using the conductive layer 1052 as an etching stop layer. Referring to fig. 11, after the etching of the capacitor hole 107 is completed, the capacitor etch protection layer 106 and the capacitor hole photoresist layer 111 may be removed.

In the method of fig. 8, the formation of the capacitor hole 107 in the area not covered by the capacitor etching protection layer 106, i.e. the area covered by the capacitor etching protection layer 106 does not form the capacitor hole 107 and the subsequent capacitor, so as to effectively improve the problem of collapse and peeling of the fringe capacitor.

In one embodiment, the materials of the capacitor etching protection layer 106 and the capacitor hole photoresist layer 111 may be the same, so that both may be removed simultaneously through one process (such as etching, cleaning, chemical mechanical polishing, etc.), which further simplifies the process flow and reduces the manufacturing cost. For example, the capacitor etch protection layer 106 and the capacitor hole photoresist layer 111 may be wet etched using the same chemistry to remove.

In one embodiment, a mask layer 112 may also be formed on the stack, and both the capacitor etch protection layer 106 and the capacitor hole photoresist layer 111 may be located on the mask layer 112. Referring to fig. 12, the above-mentioned etching and laminating with the capacitor etching protection layer 106 and the capacitor hole photoresist layer 111 as masks to form the capacitor hole 107, and removing the capacitor etching protection layer 106 and the capacitor hole photoresist layer 111 may include the following steps S1210 to S1230:

step S1210, etching the mask layer 112 by using the capacitor etching protection layer 106 and the capacitor hole photoresist layer 111 as masks;

step S1220, removing the capacitor etching protection layer 106 and the capacitor hole photoresist layer 111;

in step S1230, the stack is etched using the mask layer 112 as a mask to form the capacitor hole 107.

The structure and positional relationship of the mask layer 112, the capacitor etching protection layer 106 and the capacitor hole photoresist layer 111 can be shown with reference to fig. 13. The formation of the mask layer 112 may be preceded by a formation process of the capacitive etch protection layer 106 and followed by a formation process of the stack. Referring to fig. 14, the mask layer 112 is etched by using the capacitor etching protection layer 106 and the capacitor hole photoresist layer 111 as masks, so that the mask layer 112 covers the edge region and the non-capacitor region of the wafer, and has the pattern of the capacitor hole 107 in the capacitor region, and then the capacitor etching protection layer 106 and the capacitor hole photoresist layer 111 can be removed, for example, by wet etching or the like.

Further, the mask layer 112 is used as a mask to etch the stack layer to form the capacitor hole 107, and compared with the capacitor etching protection layer 106 and the capacitor hole photoresist layer 111 which are used as the mask capacitor hole 107, the mask layer 112 is used to make the etching process of the capacitor hole 107 more controllable. Mask layer 112 may then be removed to form the structure shown in fig. 11 described above.

With continued reference to fig. 2, in step S240, the lower electrode 108 is formed in the capacitor hole 107.

The bottom electrode 108 refers to the bottom electrode of the capacitor, which may be made of a conductive material, such as any one or a combination of more of TiN, ru, taN, WN, pt, ir. The lower electrode 108 may be formed by a Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD) process or the like.

In one embodiment, referring to fig. 15, the bottom electrode 108 may be attached to the inner wall (including the sidewall and the bottom) of the capacitor hole 107, and the thickness thereof may be 20-100 nm, which is not limited in this disclosure. The bottom of the lower electrode 108 may contact the conductive layer 1052 such that the conductive layer 1052 is in communication with the capacitance. Illustratively, a layer of conductive material of the lower electrode 108 may be conformally deposited over the surface of the entire structure, and then the conductive material on the surface of the support layer 103 is removed using chemical mechanical polishing, with the remaining conductive material forming the lower electrode 108. The lower electrode 108 is only located on the inner wall of the capacitor hole 107, not completely filling the capacitor hole 107, so that the capacitor hole 107 is also left with space for filling the dielectric 109 and the upper electrode 110 in a subsequent step.

In one embodiment, the bottom electrode 108 may also completely fill the capacitor hole 107. Illustratively, the conductive material of the bottom electrode 108 may be deposited to completely fill the capacitor hole 107 and cover the surface of the support layer 103, and then the conductive material on the surface of the support layer 103 is removed by chemical mechanical polishing, and the remaining conductive material completely fills the conductive material of the capacitor hole 107 to form a columnar bottom electrode 108.

With continued reference to fig. 2, in step S250, the sacrificial layer 102 is removed.

Wherein the sacrificial layer 102 is removed, a space is left for the dielectric 109 of the capacitor. As described above, removal of the sacrificial layer 102 results in reduced support on both sides of the lower electrode 108, and collapse and peeling are likely to occur if insufficient-depth capacitance is present in the edge region of the wafer. In the present exemplary embodiment, the capacitor hole 107 and the capacitor (the capacitor structure at this time mainly includes the lower electrode 108) are formed only in the capacitor region in the non-edge region, and collapse and peeling occur rarely due to insufficient depth of the capacitor, thereby improving the problem of the collapse and peeling of the capacitor.

In one embodiment, the removing the sacrificial layer 102 may include the following steps:

the sacrificial layer 102 is wet etched along the openings 113 in the support layer 103 to remove the sacrificial layer 102.

As shown with reference to fig. 16, openings 113 may be located in the support layer 103, through the support layer 103. Due to the presence of the opening 113, the wet etching chemistry may be allowed to enter the sacrificial layer 102 from the opening 113 and react sufficiently with the sacrificial layer 102 to complete the wet etching.

The timing of forming the opening 113 is not limited in the present disclosure. For example, the opening 113 may be formed by etching or the like after the support layer 103 is formed, or the opening 113 may be filled with the material of the sacrificial layer 102 after the opening 113 is formed, so that the opening 113 can be easily restored when the sacrificial layer 102 is wet-etched. After the formation of the lower electrode 108, the opening 113 may be formed by etching or the like. If multiple support layers 103 are present, openings 113 may be formed in each support layer 103.

In one embodiment, the capacitive apertures 107 are arranged in a hexagonal pattern in projection onto the substrate plane, with each opening 113 being located between three adjacent capacitive apertures 107. Referring to fig. 17, a top view of a projected capacitive hole 107 and opening 113 on a substrate plane, which may be a plane formed by a word line direction and a bit line direction in a semiconductor device. The projections of the capacitor holes 107 may form a hexagonal arrangement, and 6 adjacent capacitor holes 107 around each capacitor hole 107 form a regular hexagon, so that the density of the capacitor holes 107 can be increased. Each opening 113 is located between three adjacent capacitive apertures 107, fig. 17 shows that the opening 113 may be in contact with its adjacent capacitive aperture 107, i.e. there is an intersection of the projections of the opening 113 and the capacitive aperture 107. Of course, the opening 113 may not contact the capacitor hole 107 adjacent thereto. By arranging the openings 113, each opening 113 opens the sacrificial layer 102 area between the three capacitor holes 107, which is beneficial to improving the wet etching efficiency.

It should be appreciated that fig. 15 and 16 illustrate a structure of the lower electrode 108, and the lower electrode 108 is a thin layer attached to the inner wall of the capacitor hole 107, which may form a double-sided capacitor in a subsequent process, and the lower electrode 108 lacks support on both sides after the sacrificial layer 102 is removed. In another structure, if the capacitor hole 107 is completely filled when the bottom electrode 108 is formed, the bottom electrode 108 is formed in a pillar shape, which can form a single-sided pillar capacitor in a subsequent process, and after the sacrificial layer 102 is removed, the bottom electrode 108 is also free from support on both sides. It can be seen that, both the bottom electrode 108 of the thin layer structure and the bottom electrode 108 of the columnar structure are not supported sufficiently, and if there is insufficient depth, the bottom electrode 108 is not sufficiently fixed, so that collapse and peeling of the bottom electrode 108 are very likely to occur. In the present exemplary embodiment, due to the existence of the capacitor etching protection layer 106, the capacitor hole 107, the lower electrode 108 and the subsequent capacitor structure are not formed in the edge region and the non-capacitor region of the wafer, and the situation that the depth of the edge capacitor structure is insufficient is not existed, so that the problems of capacitor collapse and peeling can be improved.

In one embodiment, as shown in fig. 16 described above, after the sacrificial layer 102 is removed, a sacrificial layer space 102' is formed at the location of the sacrificial layer 102. The method for preparing the semiconductor structure can further comprise the following steps:

a dielectric 109 is formed on the lower electrode 108 and on the inner wall of the sacrificial layer space 102', and an upper electrode 110 is formed to cover the dielectric 109.

Wherein the dielectric 109 may be conformally formed on the surface of the lower electrode 108, the surface of the support layer 103. Dielectric 109 may employ one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, high-k materials. The upper electrode 110 may be formed on the surface of the dielectric 109, may also fill the sacrificial layer space 102', and covers the upper surface of the support layer 103. The upper electrode 110 may be formed by a chemical vapor deposition, atomic layer deposition, electrochemical plating, or the like. The upper electrode 110 may be made of a conductive material, such as any one or more of TiN, ru, taN, WN, pt, ir, which may or may not be the same material as the lower electrode 108. Dielectric 109 may separate lower electrode 108 from upper electrode 110 such that lower electrode 108, dielectric 109, upper electrode 110 form a capacitance. In the present exemplary embodiment, the capacitor is formed in the non-edge region, and the non-edge region does not have a problem of insufficient etching capability, so that the capacitor has a low probability of having insufficient depth and abnormal shape, and is not easy to collapse and peel. Thereby ensuring the electrical property of the semiconductor and the yield of the product.

In one embodiment, fig. 18 shows the structure after forming dielectric 109 and upper electrode 110 on the basis of fig. 16. The dielectric 109 may be attached to the inner wall of the lower electrode 108 to form a thin layer structure within the capacitor hole 107, and attached to the outer wall of the capacitor hole 107 and the surface of the support layer 103 to form a thin layer structure within the sacrificial layer space 102'. Dielectric 109 may also be located on the upper surface of lower electrode 108 to isolate lower electrode 108 from upper electrode 110 above. The upper electrode 110 fills the remaining space within the capacitor hole 107 and the remaining space within the sacrificial layer space 102' and extends over the support layer 103 and the dielectric 109. The lower electrode 108, dielectric 109, and upper electrode 110 form a double-sided capacitance.

In another embodiment, the bottom electrode 108 completely fills the capacitor hole 107, and is a bottom electrode 108 with a columnar structure. Dielectric 109 may be attached to the sidewalls of lower electrode 108 to form a thin layer structure within sacrificial layer space 102' and may also cover the upper surface of lower electrode 108 to isolate lower electrode 108 from upper electrode 110 above. The upper electrode 110 fills the remaining space within the sacrificial layer space 102' and extends over the support layer 103 and the dielectric 109. The lower electrode 108, dielectric 109, and upper electrode 110 form a single-sided columnar capacitor.

The double-sided capacitor or the single-sided columnar capacitor is not formed in the edge area of the wafer, so that the depth is enough, and the capacitor is not easy to collapse and peel.

Fig. 19 shows a wafer defect comparison of the related art with the present exemplary embodiment. The defects in the figure are defects detected after the sacrificial layer 102 is removed, and are mainly defects generated by capacitor peeling. The left side is a defect in the wafer prepared by the related art, the number of which is 9558, and the right side is a defect in the wafer prepared by the present exemplary embodiment, the number of which is 9024. One photolithography is added in the related art, the present exemplary embodiment does not add photolithography, and the cost of the present exemplary embodiment is reduced much compared to the present exemplary embodiment, while the difference of defects in the wafer is not large or even small. It can be seen that the present exemplary embodiment achieves effective control of defects generated by capacitor peeling in a wafer with reduced cost.

It is to be understood that the present disclosure is not limited to the precise arrangements and instrumentalities shown in the drawings, and that various modifications and changes may be effected without departing from the scope thereof. This application is intended to cover any variations, uses, or adaptations of the solution following the general principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. The contents of the specification are to be considered as exemplary only, with the scope and spirit of the disclosure being indicated by the appended claims.

Claims

1. A method of fabricating a semiconductor structure, comprising:

providing a wafer, wherein the wafer comprises a substrate and a laminated layer formed on the substrate, and the laminated layer comprises a sacrificial layer and a supporting layer;

forming a capacitor etching protection layer on the laminated layer through a one-time photoetching process, wherein the capacitor etching protection layer comprises a first photoresist region and a second photoresist region, the first photoresist region covers a non-capacitor region of the wafer, and the second photoresist region covers an edge region of the wafer;

forming a capacitor hole penetrating through the laminated layer in a region which is not covered by the capacitor etching protective layer;

forming a lower electrode in the capacitor hole;

removing the sacrificial layer;

the forming a capacitor etching protection layer on the laminated layer through a photoetching process comprises the following steps:

coating a negative photoresist material on the stack;

exposing the negative photoresist material by using a photomask defining the pattern of the non-capacitance area, and exposing the negative photoresist material of the edge area by a wafer edge exposure process;

and developing the negative photoresist material to retain the negative photoresist material covering the non-capacitance region and the negative photoresist material covering the edge region, thereby forming the first photoresist region and the second photoresist region respectively.

2. The method of claim 1, wherein forming a capacitor hole through the stack in a region not covered by the capacitor etch protection layer comprises:

forming a capacitor hole photoresist layer in a region of the stack layer which is not covered by the capacitor etching protective layer, wherein the missing part of the capacitor hole photoresist layer defines the pattern of the capacitor hole;

and etching the lamination by taking the capacitor etching protection layer and the capacitor hole photoresist layer as masks to form the capacitor hole, and removing the capacitor etching protection layer and the capacitor hole photoresist layer.

3. The method of claim 2, wherein the stack further has a mask layer formed thereon, the capacitive etch resist layer and the capacitive aperture photoresist layer being located on the mask layer; and etching the laminated layer by using the capacitor etching protection layer and the capacitor hole photoresist layer as masks to form the capacitor hole, and removing the capacitor etching protection layer and the capacitor hole photoresist layer, wherein the method comprises the following steps:

etching the mask layer by taking the capacitor etching protection layer and the capacitor hole photoresist layer as masks;

removing the capacitor etching protective layer and the capacitor hole photoresist layer;

and etching the laminated layer by taking the mask layer as a mask to form the capacitor hole.

4. The method of claim 2, wherein the material of the capacitive etch protection layer and the capacitive aperture photoresist layer are the same.

5. The method of claim 1, wherein the removing the sacrificial layer comprises:

and carrying out wet etching on the sacrificial layer along the opening in the supporting layer so as to remove the sacrificial layer.

6. The method of claim 5, wherein projections of the capacitive apertures on the plane of the substrate are arranged in a hexagonal pattern, each of the openings being located between three adjacent capacitive apertures.

7. The method of claim 1, wherein after removing the sacrificial layer, forming a sacrificial layer space at a location of the sacrificial layer; the method further comprises the steps of:

a dielectric is formed on the lower electrode and on an inner wall of the sacrificial layer space, and an upper electrode is formed to cover the dielectric.

8. The method of any of claims 1 to 7, wherein the edge region of the wafer comprises an incomplete die area of the wafer, the non-capacitive area being located within the complete die area of the wafer.

9. The method of any one of claims 1 to 7, wherein the non-capacitive region comprises one or more of: peripheral area, edge area of die, spacing area between different dies.