CN117674826A - Double-loop charge pump phase-locked loop and stability improving method thereof - Google Patents
Double-loop charge pump phase-locked loop and stability improving method thereof Download PDFInfo
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- CN117674826A CN117674826A CN202311361486.7A CN202311361486A CN117674826A CN 117674826 A CN117674826 A CN 117674826A CN 202311361486 A CN202311361486 A CN 202311361486A CN 117674826 A CN117674826 A CN 117674826A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L5/00—Automatic control of voltage, current, or power
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention provides a double loop charge pump phase-locked loop and a stability improving method thereof, wherein the phase-locked loop comprises: the phase frequency detector compares the phases and frequencies of an input signal and a frequency division signal to control the working state of the charge pump, controls the filtering voltage of the loop filter according to the charging current or discharging current of the charge pump, detects the filtering voltage through the detection module to obtain a control signal, controls the working state of the loop control switch and the voltage control module according to the control signal, adjusts the fine tuning voltage and the coarse tuning voltage, and adjusts the oscillation signal and the frequency division signal; when the charging current or the discharging current is abnormal, the loop control switch is turned off through the control signal to cut off the double loop charge pump phase-locked loop, so that the stability of the double loop charge pump phase-locked loop is improved.
Description
Technical Field
The invention relates to the technical field of microelectronics, in particular to a double-loop charge pump phase-locked loop and a stability improving method thereof.
Background
The clock of a high-speed analog-to-digital converter is usually implemented by a phase-locked loop, and the performance of the phase-locked loop directly affects the performance of the analog-to-digital converter. Compared with a single loop phase-locked loop, the double loop phase-locked loop has higher frequency range, lower phase noise and better linearity. The feedback voltage of the conventional dual-loop charge pump phase-locked loop comprises a fine tuning voltage and a coarse tuning voltage, because the fine tuning loop has large bandwidth, high adjusting speed and the coarse tuning loop has small bandwidth and low adjusting speed. During the regulation, the fine tuning voltage is quickly pulled up to the supply voltage or pulled down to the ground voltage until the voltage controlled oscillator in the dual loop phase locked loop is regulated by the coarse tuning voltage to fall within the frequency range in which the fine tuning voltage is tunable, and the fine tuning voltage is gradually restored to the reference voltage. In the process of pulling up the fine tuning voltage to the power supply voltage or pulling down the fine tuning voltage to the ground voltage, charge and discharge current of a charge pump in the double-loop phase-locked loop is reduced, loop bandwidth of the phase-locked loop is reduced, and phase margin is reduced, so that stability of the double-loop phase-locked loop in a working state is poor.
Therefore, how to design a dual-loop charge pump pll to improve the stability of the pll is a technical problem to be solved.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, the present invention provides a dual-loop charge pump phase-locked loop and a method for improving stability thereof, so as to solve the above-mentioned technical problems.
In one aspect, the present application provides a dual loop charge pump phase locked loop comprising:
the frequency and phase discriminator compares the frequency and the phase of the input signal and the frequency division signal to obtain a pull-up control signal and a pull-down control signal;
the charge pump is connected with the phase frequency detector, and the pull-up control signal and the pull-down control signal control the working state of the charge pump, so that the charge pump outputs charging current to a rear stage or the rear stage inputs discharging current to the charge pump;
the loop filter is connected with the charge pump and used for carrying out current-voltage conversion on the charging current or the discharging current to obtain a filtering voltage;
the detection module is connected with the loop filter and used for detecting the filtering voltage to obtain a first control signal, a second control signal and a third control signal;
the loop control switch, the input end connects the loop filter, the control end connects the third control signal, the output end outputs the fine tuning voltage;
the voltage control module is connected with the detection module in a control way, the output end of the voltage control module is connected with the output end of the loop control switch, and the fine tuning voltage is clamped and controlled according to the first control signal, the second control signal and the third control signal;
the integrator is connected with the output end of the loop control switch and used for integrating the difference value between the fine tuning voltage and the reference voltage to obtain a coarse tuning voltage;
the voltage-controlled oscillator is connected with the output end of the loop control switch, the voltage control module and the integrator, and generates and outputs an oscillation signal according to the fine tuning voltage and the coarse tuning voltage;
the frequency divider is connected with the voltage-controlled oscillator and the phase frequency detector and used for dividing the frequency of the oscillating signal to obtain the frequency-divided signal;
when the charging current or the discharging current is abnormal, the loop control switch is turned off through the third control signal, and the double loop charge pump phase-locked loop is cut off, so that oscillation of the double loop charge pump phase-locked loop is avoided.
Optionally, the detection module includes a first comparator, a second comparator and an and gate, where an output end of the first comparator is connected to a first input end of the and gate, an output end of the second comparator is connected to a second input end of the and gate, a non-inverting input end of the first comparator is connected to a preset high voltage threshold, an inverting input end of the first comparator is connected to a non-inverting input end of the second comparator, and a non-inverting input end of the second comparator is connected to a preset low voltage threshold, where a non-inverting input end of the second comparator is connected to the filter voltage, an output end of the first comparator outputs the first control signal, an output end of the second comparator outputs the second control signal, and an output end of the and gate outputs the third control signal.
Optionally, the first comparator includes a first resistor, a second resistor and a first operational amplifier, where a first end of the first resistor is connected to a non-inverting input end of the first operational amplifier, the second resistor is connected in series between the non-inverting input end of the first operational amplifier and an output end of the first operational amplifier, a second end of the first resistor is connected to the preset high voltage threshold, an inverting input end of the first operational amplifier is connected to the filtering voltage, and an output end of the first operational amplifier outputs the first control signal.
Optionally, the second comparator includes a third resistor, a fourth resistor, a second operational amplifier and an inverter, where a first end of the third resistor is connected to the in-phase input end of the second operational amplifier, the fourth resistor is connected in series between the in-phase input end of the second operational amplifier and the output end of the second operational amplifier, and an output end of the second operational amplifier is connected to the input end of the inverter, where a second end of the third resistor is connected to the preset low voltage threshold, an inverting input end of the second operational amplifier is connected to the filtering voltage, and an output end of the inverter outputs the second control signal.
Optionally, the charge pump includes a PMOS tube, a first switch, a second switch and an NMOS tube, where a source of the PMOS tube is connected to a power supply voltage, a gate of the PMOS tube is connected to a first bias voltage, a drain of the PMOS tube is connected to a drain of the NMOS tube after passing through the first switch and the second switch that are sequentially connected in series, a gate of the NMOS tube is connected to a second bias voltage, and a source of the NMOS tube is grounded, where a control end of the first switch is connected to the pull-up control signal, a control end of the second switch is connected to the pull-down control signal, and a common end of the first switch and the second switch outputs the charging current or inputs the discharging current.
Optionally, the voltage control module includes a third switch, a fourth switch and a fifth switch, where a first end of the third switch is connected to the power supply voltage, a second end of the third switch is connected to the ground after passing through the fourth switch in series, a first end of the fifth switch is connected to the second end of the third switch, a second end of the fifth switch is connected to the fine tuning voltage, a control end of the third switch is connected to the first control signal, a control end of the fourth switch is connected to the second control signal, and a control end of the fifth switch is connected to the third control signal.
Optionally, the integrator includes a third operational amplifier and a first capacitor, an output end of the third operational amplifier is connected to a first end of the first capacitor, a second end of the first capacitor is grounded, a non-inverting input end of the third operational amplifier is connected to the fine tuning voltage, an inverting input end of the third operational amplifier is connected to the reference voltage, and an output end of the third operational amplifier outputs the coarse tuning voltage.
In a second aspect, the present application provides a method for improving stability of a dual-loop charge pump phase-locked loop, where the method is applied to the dual-loop charge pump phase-locked loop as described above, and includes:
when the charging current or the discharging current is normal, the loop control switch is conducted through the third control signal, and the double loop charge pump phase-locked loop is conducted, so that the double loop charge pump phase-locked loop works normally;
when the charging current or the discharging current is abnormal, the loop control switch is disconnected through the third control signal, the double loop charge pump phase-locked loop is cut off, so that oscillation of the fine tuning branch is avoided, and stability of the double loop charge pump phase-locked loop is improved.
Optionally, when the charging current or the discharging current is normal, turning on the loop control switch by the third control signal, including: when the charging current or the discharging current is normal, the filtering voltage is smaller than the preset high voltage threshold value and the filtering voltage is larger than the preset low voltage threshold value, the first control signal and the second control signal are high level, the third control signal is determined to be high level, and the third control signal of high level closes the loop control switch; wherein the preset high voltage threshold is greater than the preset low voltage threshold.
Optionally, when the charging current or the discharging current is abnormal, opening the loop control switch by the third control signal includes: when the charging current is abnormal, the filtering voltage is larger than the preset high voltage threshold, the first control signal is in a low level, the second control signal is in a high level, the third control signal is determined to be in a low level, and the third control signal turns off the loop control switch; when the discharging current is abnormal, the filtering voltage is smaller than the preset low voltage threshold, the first control signal is in a high level, the second control signal is in a low level, the third control signal is determined to be in a low level, and the control signal turns off the loop control switch.
The invention provides a double loop charge pump phase-locked loop and a stability improving method thereof, wherein the phase-locked loop comprises: the frequency and phase discriminator compares the frequency and the phase of the input signal and the frequency division signal to obtain a pull-up control signal and a pull-down control signal; the charge pump is connected with the phase frequency detector, and the pull-up control signal and the pull-down control signal control the working state of the charge pump, so that the charge pump outputs charging current to the rear stage or the rear stage inputs discharging current to the charge pump; the loop filter is connected with the charge pump and used for carrying out current-voltage conversion on the charging current or the discharging current to obtain a filtering voltage; the detection module is connected with the loop filter and used for detecting the filtering voltage to obtain a first control signal, a second control signal and a third control signal; the loop control switch, the input end connects the loop filter, the control end connects the third control signal, the output end outputs the fine tuning voltage; the voltage control module is connected with the detection module in a control way, the output end of the voltage control module is connected with the fine tuning voltage, the fine tuning voltage is controlled according to the control signal output by the detection module, the integrator is connected with the loop control switch, and the difference value between the fine tuning voltage and the reference voltage is integrated to obtain the coarse tuning voltage; the voltage-controlled oscillator is connected with the loop control switch, the voltage control module and the integrator, and generates and outputs an oscillation signal according to the fine tuning voltage and the coarse tuning voltage; the frequency divider is connected with the voltage-controlled oscillator and the frequency and phase discriminator and used for dividing the frequency of the oscillating signal to obtain a frequency-divided signal; when the charging current or the discharging current is abnormal, the loop control switch is turned off through the control signal, and the dual-loop charge pump phase-locked loop is cut off, so that the oscillation of the dual-loop charge pump phase-locked loop is avoided. According to the method and the device, the working state of the charge pump is controlled according to the input signal and the frequency division signal, the size of the filtering voltage is controlled through the working state of the charge pump, when the output current or the input current of the charge pump is abnormal, the detection module turns off the loop control switch according to the filtering voltage, and the double-loop charge pump phase-locked loop is cut off, so that the stability of the double-loop charge pump phase-locked loop is improved.
Drawings
FIG. 1 is a schematic diagram of a conventional dual loop charge pump phase locked loop in an exemplary embodiment of the present application;
FIG. 2 is a block diagram of a dual loop charge pump phase locked loop in an exemplary embodiment of the present application;
FIG. 3 is a specific circuit diagram of a dual loop charge pump phase locked loop in an exemplary embodiment of the present application;
FIG. 4 is a specific circuit diagram of a detection module in an exemplary embodiment of the present application;
fig. 5 is a voltage transmission characteristic diagram of a detection module in an exemplary embodiment of the present invention.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.
It should be noted that the illustrations provided in the following embodiments merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
In the following description, numerous details are set forth in order to provide a more thorough explanation of embodiments of the present invention, it will be apparent, however, to one skilled in the art that embodiments of the present invention may be practiced without these specific details, in other embodiments, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the embodiments of the present invention.
The clock of a high-speed analog-to-digital converter is usually implemented by a phase-locked loop, and the performance of the phase-locked loop directly affects the performance of the analog-to-digital converter. Compared with a single loop phase-locked loop, the double loop phase-locked loop has higher frequency range, lower phase noise and better linearity.
Referring to fig. 1, fig. 1 is a schematic view of a display deviceA schematic diagram of a conventional dual loop charge pump phase locked loop in an exemplary embodiment of the present application. As shown in fig. 1, the conventional dual loop charge pump phase locked loop circuit includes a phase frequency detector, a charge pump, a loop filter, a voltage controlled oscillator (LC VCO), a frequency divider, and an integrator. The phase-locked loop includes two analog negative feedback loops: a coarse tuning loop formed by the integrator and the voltage controlled oscillator and a fine tuning loop formed by the loop filter and the voltage controlled oscillator. The coarse tuning loop may apply a coarse tuning voltage V coarse To the voltage-controlled oscillator, the fine tuning loop may apply a fine tuning voltage V fine To a voltage controlled oscillator.
During the locking process of the double-loop charge pump phase-locked loop, the fine tuning loop is the same as the conventional single-loop phase-locked loop, and the fine tuning voltage V is applied fine To the voltage-controlled oscillator, thereby providing low tuning gain, while the coarse tuning loop can widen the frequency range of the phase-locked loop, and solve the contradiction between the low tuning gain and the wide frequency range of the single loop phase-locked loop. The integrator in the coarse tuning loop will fine tune the voltage V fine With reference voltage V ref The difference of (VDD/2) is integrated to output coarse tuning voltage V coarse To a voltage-controlled oscillator so that the phase-locked loop fine tunes the voltage V at the final lock fine Stabilized at VDD/2, both the charge pump and the voltage controlled oscillator have optimal performance. Because the fine tuning loop has large bandwidth, the adjusting speed is high, and the coarse tuning loop has small bandwidth and the adjusting speed is low. In the adjusting process, the fine tuning voltage is quickly pulled up to the power supply voltage VDD or pulled down to the ground voltage GND until the voltage-controlled oscillator in the dual-loop phase-locked loop is adjusted by the coarse tuning voltage to fall within the frequency range of the fine tuning voltage tuning, and the fine tuning voltage is gradually restored to the reference voltage V ref . In the process that the fine tuning voltage is pulled up to the power supply voltage VDD or pulled down to the ground voltage GND, the charging current or discharging current of a charge pump in the double-loop phase-locked loop is reduced, the loop bandwidth of the phase-locked loop is reduced, the phase margin is reduced, and the stability of the double-loop phase-locked loop in a working state is poor.
In order to solve the problems, the output filtering voltage of the loop filter is subjected to logic conversion to obtain a control signal, the working states of the fine tuning branch and the coarse tuning branch are controlled according to the control signal, and when the current of the charge pump becomes smaller, the control signal breaks the fine tuning loop and the coarse tuning loop, so that the stability of the circuit is improved.
Referring to fig. 2, fig. 2 is a block diagram of a dual loop charge pump phase locked loop in an exemplary embodiment of the present application.
As shown in fig. 2, the present application provides a dual loop charge pump phase locked loop, including:
phase frequency detector, comparing input signals F ref And frequency-divided signal F div Obtaining a pull-UP control signal UP and a pull-down control signal DOWM;
the charge pump is connected with the phase frequency detector, and the pull-UP control signal UP and the pull-down control signal DOWM control the working state of the charge pump, so that the charge pump outputs charging current to the rear stage or the rear stage inputs discharging current to the charge pump;
the loop filter is connected with the charge pump and used for carrying out current-voltage conversion on the charging current or the discharging current to obtain a filtering voltage V lpf ；
The detection module is connected with the loop filter and is used for filtering the voltage V lpf Detecting to obtain a first control signal, a second control signal and a third control signal;
a loop control switch with input end connected to the loop filter, control end connected to the third control signal, and output end for outputting fine tuning voltage V fine ；
The voltage control module is controlled by the detection module, the output end of the voltage control module is connected with the output end of the loop control switch, and the fine tuning voltage V is controlled according to the first control signal, the second control signal and the third control signal fine Clamping control is performed;
an integrator connected to the loop control switch for fine tuning the voltage V fine Integrating the difference with the reference voltage to obtain a coarse tuning voltage V coarse ；
Voltage-controlled oscillator, loop control switch, voltage control module and integrator, according to fine tuning voltage V fine Coarse tuning voltage V coarse Generating and outputting an oscillation signal F out ；
Frequency divider connected to voltage-controlled oscillator and phase frequency detector for oscillating signal F out Frequency division is carried out to obtain a frequency division signal F div ；
When the charging current or the discharging current is abnormal, the loop control switch is turned off through the third control signal, and the dual-loop charge pump phase-locked loop is cut off, so that oscillation of the dual-loop charge pump phase-locked loop is avoided.
It should be emphasized that, as shown in fig. 2, the loop filter, the loop switch and the voltage controlled oscillator constitute a fine tuning loop, and the integrator and the voltage controlled oscillator constitute a coarse tuning loop.
Referring to fig. 3, fig. 3 is a specific circuit diagram of a dual loop charge pump phase locked loop according to an exemplary embodiment of the present application.
In detail, as shown in fig. 3, the detection module includes a first comparator COMP1, a second comparator COMP2, AND an AND gate AND, the output of the first comparator COMP1 is connected to a first input of the AND gate AND, the output of the second comparator COMP2 is connected to a second input of the AND gate AND, AND the non-inverting input of the first comparator is connected to a preset high voltage threshold V H The inverting input of the first comparator COMP1 is connected with the non-inverting input of the second comparator COMP2, and the inverting input of the second comparator COMP2 is connected with a preset low voltage threshold V L Wherein the non-inverting input of the second comparator COMP2 is connected with the filtered voltage V lpf The output terminal of the first comparator COMP1 outputs the first control signal SW1, the output terminal of the second comparator COMP2 outputs the second control signal SW2, AND the output terminal of the AND gate AND outputs the third control signal SW3.
It should be noted that, in the first comparator COMP1 and the second comparator COMP2 of the detection module, when the voltage V is filtered lpf At a preset high voltage threshold V H Or preset low voltage threshold V L When slight change occurs on the left and right sides, the output voltages of the first comparator COMP1 and the second comparator COMP2 jump, so that the control signal is changed; from this, it can be seen that the interference resistance of the first comparator COMP1 and the second comparator COMP2 is relatively poor, and the ratio needs to be increasedResistance of the comparator.
Referring to fig. 4, fig. 4 is a specific circuit diagram of a detection module according to an exemplary embodiment of the present application, and in order to improve the resistance of the comparators, the specific structures of the first comparator COMP1 and the second comparator COMP2 are shown in fig. 4.
In more detail, as shown in FIG. 4, the first comparator COMP1 includes a first resistor R 1 A second resistor R 2 And a first operational amplifier AMP1, a first resistor R 1 A second resistor R connected in series between the non-inverting input terminal of the first operational amplifier AMP1 and the output terminal of the first operational amplifier AMP1 2 Wherein the first resistor R 1 Is preset with a high voltage threshold V H The inverting input of the first operational amplifier AMP1 is connected with the filter voltage V lpf The output terminal of the first operational amplifier AMP1 outputs a first control signal SW1.
It should be noted that the first comparator COMP1 includes two threshold voltages, respectively the filtered voltage V lpf A first threshold voltage V for generating a jump of the first control signal SW1 during the small-scale process HH Filtered voltage V lpf A second threshold voltage V for making the first control signal SW1 generate jump from the big to the small HL . First threshold voltage V HH And a second threshold voltage V HL The expression of (2) is shown in (1):
wherein V is HH At a first threshold voltage, R 1 R is the first resistance 2 Is a second resistor, VDD is a power supply voltage, V H For presetting a high voltage threshold, V HL Is the second threshold voltage.
In more detail, as shown in FIG. 4, the second comparator COMP2 packetIncludes a third resistor R 3 Fourth resistor R 4 A second operational amplifier AMP2, a NOT gate INV, a third resistor R 3 A fourth resistor R connected in series between the non-inverting input terminal of the second operational amplifier AMP2 and the output terminal of the second operational amplifier AMP2 4 The output end of the second operational amplifier AMP2 is connected with the input end of the NOT gate INV, wherein the third resistor R 3 Is preset with a low voltage threshold V L The inverting input of the second operational amplifier AMP2 is connected with the filter voltage V lpf An output terminal of the not gate INV outputs the second control signal SW2.
Similarly, the second comparator COMP2 includes two threshold voltages, respectively the filtered voltage V lpf A third threshold voltage V for making the second control signal SW2 generate a jump in the process of small-scale LH Filtered voltage V lpf A fourth threshold voltage V for making the second control signal SW2 generate jump from the big to the small LL . Third threshold voltage V LH And a fourth threshold voltage V LL The expression of (2) is shown as (3) and (4):
wherein V is LH At a third threshold voltage, R 3 R is a third resistance 4 A fourth resistor, VDD is the power supply voltage, V L For presetting a low voltage threshold, V LL Is the fourth threshold voltage.
In detail, as shown in FIG. 3, the charge pump includes a PMOS transistor Q1, a first switch K 1 Second switch K 2 And an NMOS transistor Q2, the source electrode of the PMOS transistor Q1 is connected with the power supply voltage VDD, and the grid electrode of the PMOS transistor Q1 is connected with the first bias voltage V p The drain electrode of the PMOS tube Q1 is sequentially connected in series with a first switch K 1 Second switch K 2 The drain electrode of the NMOS tube Q2 is connected at the back, and the grid electrode of the NMOS tube Q2Connected with a second bias voltage V N The source electrode of the NMOS tube Q2 is grounded, wherein the first switch K 1 Control terminal of (a) pulls UP control signal UP, second switch K 2 A control terminal of the pull-DOWN control signal DOWN, a first switch K 1 And a second switch K 2 To output a charging current or to input a discharging current.
In detail, as shown in fig. 3, the voltage control module includes a third switch K 3 Fourth switch K 4 Fifth switch K 5 Third switch K 3 A third switch K connected to the first terminal of the power supply voltage VDD 3 A fourth switch K connected in series with the second end of the switch 4 Rear ground, fifth switch K 5 Is connected with the third switch K 3 A fifth switch K 5 Is connected with the second end of the fine tuning voltage V fine Wherein the third switch K 3 A fourth switch K connected to the first control signal SW1 4 A fifth switch K connected to the second control signal SW2 5 Is connected to the third control signal SW3.
In detail, as shown in fig. 3, the integrator includes a third operational amplifier AMP3 and a first capacitor C 1 The output end of the third operational amplifier AMP3 is connected with the first capacitor C 1 A first capacitor C 1 Wherein the non-inverting input of the third operational amplifier AMP3 is connected to the fine tuning voltage V fine The inverting input of the third operational amplifier AMP3 is connected with the reference voltage V ref The output terminal of the third operational amplifier AMP3 outputs the coarse tuning voltage V coarse 。
In detail, as shown in fig. 3, the loop filter includes a fifth resistor R 5 A second capacitor C 2 Third capacitor C 3 Fifth resistor R 5 Is connected in series with a second capacitor C 2 Rear ground, third capacitor C 3 A first terminal of the fifth resistor R 5 A third capacitor C 3 Wherein the fifth resistor R is grounded 5 A third capacitor C 3 Is output by the first end of the filter voltage V lpf 。
Referring to fig. 2-4, the specific working principle of the dual loop charge pump pll is as follows:
when inputting signal F ref Greater than the frequency-divided signal F div The pull-UP control signal UP is high and the pull-DOWN control signal DOWN is low, and in the charge pump, the first switch K 1 Closing a second switch K 2 Off, a first bias voltage V P The PMOS tube Q1 is controlled to be conducted, the charge pump charges the loop filter through the power supply voltage VDD, and the filtering voltage V lpf Is increased; at this time, if the filter voltage V lpf ≤VDD-V dsat1 (overdrive voltage of the PMOS tube Q1), the PMOS tube Q1 works in a saturation region, and the charge pump charging current is kept unchanged; if the filter voltage V lpf >VDD-V dsat1 (overdrive voltage of PMOS transistor Q1), the PMOS transistor Q1 works in the linear region, along with the filtered voltage V lpf And the charge pump charging current decreases.
When inputting signal F ref Less than the frequency-divided signal F div The pull-UP control signal UP is low and the pull-DOWN control signal DOWN is high, and in the charge pump, the first switch K 1 Open, second switch K 2 Closing, second bias voltage V N The NMOS tube Q2 is controlled to be conducted, the loop filter discharges the charge pump, and the voltage V is filtered lpf Is decreased; at this time, if the filter voltage V lpf ≥V dsat2 (overdrive voltage of NMOS transistor Q2), NMOS transistor Q2 works in saturation region, charge pump discharge current remains unchanged; if the filter voltage V lpf <V dsat2 (overdrive voltage of NMOS transistor Q2), NMOS transistor Q2 operates in the linear region, with V lpf And the charge pump discharge current decreases.
It can be seen that the anomalies of the charge current and the discharge current can be detected by filtering the voltage V lpf Overdrive voltage V of power supply VDD and PMOS tube Q1 dsat1 Overdrive voltage V of NMOS transistor Q2 dsat2 The method is shown. Preset high voltage threshold V of detection module H For judging whether the PMOS tube Q1 is in the saturation region, therefore, a high voltage threshold V is preset H The requirements are as follows: v (V) H ≤VDD-V dsat1 If V lpf ≤V H The PMOS tube Q1 works in a saturation region; if V lpf >V H The PMOS transistor Q1 operates in the linear region. Preset low voltage threshold V of detection module L For judging whether the NMOS transistor Q2 is in the saturation region, therefore, a low voltage threshold V is preset L The requirements are as follows: v (V) L≥ V dsat2 If V lpf ≥V L The NMOS transistor Q2 operates in the saturation region; if V lpf <V L The NMOS transistor Q2 operates in the linear region.
In the embodiment provided in the application, the power supply voltage is set to be 1V, and the overdrive voltage V of the PMOS transistor Q1 dsat1 Overdrive voltage V with NMOS transistor Q2 dsat2 Setting 150mV, presetting a high voltage threshold V H Can be set to 850mV, and preset a low voltage threshold V L Can be set to 150mV.
By filtering the voltage V lpf And preset high voltage threshold V H Control the level of the first control signal SW1, if V lpf <V H The first comparator COMP1 outputs the first control signal SW1 to be high level; if V lpf ≥V H The first comparator COMP1 outputs the first control signal SW1 to a low level; by filtering the voltage V lpf And a preset low voltage threshold V L Control the level of the second control signal SW2, if V lpf ＜V L The second comparator COMP2 outputs the second control signal SW2 to a low level; if V lpf ≥V L The second comparator COMP2 outputs the second control signal SW2 to a high level. Thus, when V L ≤V lpf <V H When the charge pump charge current or discharge current is normal, the first control signal SW1 is at a high level, the second control signal SW2 is at a high level, the third control signal SW3 is at a high level, and the first control signal SW1 at a high level controls the third switch K 3 The second control signal SW2 of high level controls the fourth switch K to be turned off 4 The third control signal SW3 of high level controls the loop control switch S to open and controls the fifth switch K 5 Disconnecting, and normally operating the double-loop charge pump phase-locked loop; when V is lpf <V L <V H When the charge pump discharge current is reduced, the first controlThe control signal SW1 is high, the second control signal SW2 is low, the third control signal SW3 is low, and the first control signal SW1 of high level controls the third switch K 3 The second control signal SW2 of the low level controls the fourth switch K to be turned off 4 The third control signal SW3 of low level controls the loop control switch S to be opened and controls the fifth switch K to be closed 5 The double-loop charge pump phase-locked loop is closed, the negative feedback of the phase-locked loop is cut off, and the stability of the double-loop charge pump phase-locked loop is improved; at this time, the loop control switch is turned off, the voltage control module is grounded, and the voltage V is finely tuned fine =gnd, coarse tuning voltage V output by integrator coarse Decrease, oscillate signal F out And frequency-divided signal F div Decrease until the frequency-divided signal F div < input Signal F ref The pull-UP control signal UP is high and the pull-DOWN control signal DOWN is low, and in the charge pump, the first switch K 1 Closing a second switch K 2 The PMOS tube Q1 is disconnected, the charge pump charges the loop filter through the power supply voltage VDD, and the filter voltage V lpf The voltage value of (2) rises to the filter voltage V lpf Is greater than a preset low voltage threshold V L The third control signal SW3 of high level controls the loop control switch S to close and open the fifth switch K 5 The dual loop charge pump phase locked loop returns to normal. When V is lpf ≥V H >V L When the charge pump charge current decreases, the first control signal SW1 is low, the second control signal SW2 is high, the third control signal SW is low, and the first control signal SW1 of low controls the third switch K 3 The second control signal SW2 of high level controls the fourth switch K 4 The third control signal SW3 of low level controls the loop control switch S to be turned off and controls the fifth switch K to be turned on 5 The double-loop charge pump phase-locked loop is closed, the negative feedback of the phase-locked loop is cut off, and the stability of the double-loop charge pump phase-locked loop is improved; at this time, the voltage control module is connected to the power supply voltage to fine tune the voltage V due to the disconnection of the loop control switch fine =vdd, coarse tuning voltage V output by integrator coarse Rise, oscillate signal F out And frequency-divided signal F div Rising to a frequency-divided signal F div > input signal F ref The pull-UP control signal UP is low and the pull-DOWN control signal DOWN is high, and in the charge pump, the first switch K 1 Open, second switch K 2 Closing, conducting NMOS tube Q2, discharging charge pump by loop filter, filtering voltage V lpf The voltage value of (2) is reduced to the filter voltage V lpf Less than a preset high voltage threshold V H The third control signal SW3 of high level controls the loop control switch S to close and open the fifth switch K 5 The dual loop charge pump phase locked loop returns to normal.
Referring to fig. 5, fig. 5 is a voltage transmission characteristic diagram of the detection module according to an exemplary embodiment of the invention. As shown in FIG. 5, when V LH <V lpf <V HL When the first comparator COMP1 AND the first comparator COMP2 output the first control signal SW1 AND the second control signal SW2 both at the high level, AND the AND gate AND outputs the third control signal SW3 at the high level; when V is lpf From V LH ～V HL The voltage between them increases to V HH At this time, the first control signal SW1 outputted from the first comparator COMP1 becomes a low level, the second control signal SW2 remains a high level, and the third control signal SW3 becomes a low level; when V is lpf From greater than V HH Reduced to V HL At this time, the first control signal SW1 becomes a high level, the second control signal SW2 remains a high level, and therefore the third control signal SW3 becomes a high level; when V is lpf From V LH ～V HL The voltage between them is reduced to V LL When the second control signal SW2 output from the second comparator COMP2 goes low, the first control signal SW1 remains high, and the third control signal SW3 goes low; when V is lpf From less than V LL Is increased to V LH When the second control signal SW2 goes high, the first control signal SW1 remains high, and the third control signal SW3 goes high. In particular V HH 、V HL 、V LH 、V LL Can be set to 850mV, 800mV, 200mV and 150mV respectively.
The application also provides a method for improving the stability of the double-loop charge pump phase-locked loop,the method is applied to the double loop charge pump phase-locked loop as described above, and comprises the following steps: when the charging current or the discharging current is normal, the loop control switch is conducted through the third control signal, and the double-loop charge pump phase-locked loop is conducted, so that the double-loop charge pump phase-locked loop works normally; when the charging current or the discharging current is abnormal, the loop control switch is disconnected through the third control signal, and the double-loop charge pump phase-locked loop is cut off, so that the oscillation of the fine tuning branch is avoided, and the stability of the double-loop charge pump phase-locked loop is improved. When the charging current or the discharging current is normal, the filter voltage is at V L ≤V lpf <V H The third control signal is high level, the loop control switch is closed, the double loop charge pump phase-locked loop works normally, when the charging current or discharging current is abnormal, the filtering voltage is in V lpf <V L <V H Or V lpf ≥V H >V L The third control signal is low level, the loop control switch is opened, and the double loop charge pump phase-locked loop is cut off.
In detail, when the charging current or the discharging current is normal, the loop control switch is turned on by the third control signal, including: when the charging current or the discharging current is normal, the filtering voltage is smaller than a preset high voltage threshold value and larger than a preset low voltage threshold value, the first control signal and the second control signal are in a high level, the third control signal is determined to be in a high level, and the third control signal in the high level closes a loop control switch; wherein the preset high voltage threshold is greater than the preset low voltage threshold.
In detail, when the charge current or the discharge current is abnormal, opening the loop control switch by the third control signal includes: when the charging current is abnormal, the filtering voltage is larger than a preset high voltage threshold, the first control signal is low level, the second control signal is high level, the third control signal is low level, and the control signal turns off the loop control switch; when the discharging current is abnormal, the filtering voltage is smaller than a preset low voltage threshold, the first control signal is at a high level, the second control signal is at a low level, the third control signal is determined to be at a low level, and the control signal turns off the loop control switch.
The invention provides a double loop charge pump phase-locked loop and a stability improving method thereof, wherein the phase-locked loop comprises: the frequency and phase discriminator compares the frequency and the phase of the input signal and the frequency division signal to obtain a pull-up control signal and a pull-down control signal; the charge pump is connected with the phase frequency detector, and the pull-up control signal and the pull-down control signal control the working state of the charge pump, so that the charge pump outputs charging current to the rear stage or the rear stage inputs discharging current to the charge pump; the loop filter is connected with the charge pump and used for carrying out current-voltage conversion on the charging current or the discharging current to obtain a filtering voltage; the detection module is connected with the loop filter and used for detecting the filtering voltage to obtain a first control signal, a second control signal and a third control signal; the loop control switch, the input end connects the loop filter, the control end connects the third control signal, the output end outputs the fine tuning voltage; the voltage control module is connected with the detection module in a control way, the output end of the voltage control module is connected with the fine tuning voltage, the fine tuning voltage is controlled according to the control signal output by the detection module, the integrator is connected with the loop control switch, and the difference value between the fine tuning voltage and the reference voltage is integrated to obtain the coarse tuning voltage; the voltage-controlled oscillator is connected with the loop control switch, the voltage control module and the integrator, and generates and outputs an oscillation signal according to the fine tuning voltage and the coarse tuning voltage; the frequency divider is connected with the voltage-controlled oscillator and the frequency and phase discriminator and used for dividing the frequency of the oscillating signal to obtain a frequency-divided signal; when the charging current or the discharging current is abnormal, the loop control switch is turned off through the control signal, and the dual-loop charge pump phase-locked loop is cut off, so that the oscillation of the dual-loop charge pump phase-locked loop is avoided. According to the method and the device, the working state of the charge pump is controlled according to the input signal and the frequency division signal, the size of the filtering voltage is controlled through the working state of the charge pump, when the output current or the input current of the charge pump is abnormal, the detection module turns off the loop control switch according to the filtering voltage, and the double-loop charge pump phase-locked loop is cut off, so that the stability of the double-loop charge pump phase-locked loop is improved.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. It is therefore intended that all equivalent modifications and changes made by those skilled in the art without departing from the spirit and technical spirit of the present invention shall be covered by the appended claims.
Claims (10)
1. A dual loop charge pump phase locked loop comprising:
the frequency and phase discriminator compares the frequency and the phase of the input signal and the frequency division signal to obtain a pull-up control signal and a pull-down control signal;
the charge pump is connected with the phase frequency detector, and the pull-up control signal and the pull-down control signal control the working state of the charge pump, so that the charge pump outputs charging current to a rear stage or the rear stage inputs discharging current to the charge pump;
the loop filter is connected with the charge pump and used for carrying out current-voltage conversion on the charging current or the discharging current to obtain a filtering voltage;
the detection module is connected with the loop filter and used for detecting the filtering voltage to obtain a first control signal, a second control signal and a third control signal;
the loop control switch, the input end connects the loop filter, the control end connects the third control signal, the output end outputs the fine tuning voltage;
the voltage control module is connected with the detection module in a control way, the output end of the voltage control module is connected with the output end of the loop control switch, and the fine tuning voltage is clamped and controlled according to the first control signal, the second control signal and the third control signal;
the integrator is connected with the output end of the loop control switch and used for integrating the difference value between the fine tuning voltage and the reference voltage to obtain a coarse tuning voltage;
the voltage-controlled oscillator is connected with the output end of the loop control switch, the voltage control module and the integrator, and generates and outputs an oscillation signal according to the fine tuning voltage and the coarse tuning voltage;
the frequency divider is connected with the voltage-controlled oscillator and the phase frequency detector and used for dividing the frequency of the oscillating signal to obtain the frequency-divided signal;
when the charging current or the discharging current is abnormal, the loop control switch is turned off through the third control signal, and the double loop charge pump phase-locked loop is cut off, so that oscillation of the double loop charge pump phase-locked loop is avoided.
2. The dual loop charge pump phase locked loop of claim 1, wherein the detection module comprises a first comparator, a second comparator and an and gate, wherein an output terminal of the first comparator is connected with a first input terminal of the and gate, an output terminal of the second comparator is connected with a second input terminal of the and gate, a non-inverting input terminal of the first comparator is connected with a preset high voltage threshold, a non-inverting input terminal of the first comparator is connected with a non-inverting input terminal of the second comparator, a non-inverting input terminal of the second comparator is connected with a preset low voltage threshold, wherein a non-inverting input terminal of the second comparator is connected with the filter voltage, an output terminal of the first comparator outputs the first control signal, an output terminal of the second comparator outputs the second control signal, and an output terminal of the and gate outputs the third control signal.
3. The dual loop charge pump phase locked loop of claim 2 wherein said first comparator comprises a first resistor, a second resistor and a first operational amplifier, a first end of said first resistor is connected to a non-inverting input of said first operational amplifier, said second resistor is connected in series between said non-inverting input of said first operational amplifier and an output of said first operational amplifier, wherein a second end of said first resistor is connected to said predetermined high voltage threshold, an inverting input of said first operational amplifier is connected to said filtered voltage, and an output of said first operational amplifier outputs said first control signal.
4. The dual loop charge pump phase locked loop of claim 2 wherein said second comparator comprises a third resistor, a fourth resistor, a second operational amplifier and a not gate, a first end of said third resistor is connected to a non-inverting input of said second operational amplifier, a non-inverting input of said second operational amplifier is connected in series with said fourth resistor, an output of said second operational amplifier is connected to an input of said not gate, a second end of said third resistor is connected to said predetermined low voltage threshold, an inverting input of said second operational amplifier is connected to said filtered voltage, and an output of said not gate outputs said second control signal.
5. The dual loop charge pump phase locked loop of claim 1, wherein the charge pump comprises a PMOS transistor, a first switch, a second switch, and an NMOS transistor, a source of the PMOS transistor is connected to a power supply voltage, a gate of the PMOS transistor is connected to a first bias voltage, a drain of the PMOS transistor is connected to a drain of the NMOS transistor after passing through the first switch and the second switch, which are sequentially connected in series, a gate of the NMOS transistor is connected to a second bias voltage, and a source of the NMOS transistor is grounded, wherein a control terminal of the first switch is connected to the pull-up control signal, a control terminal of the second switch is connected to the pull-down control signal, and a common terminal of the first switch and the second switch outputs the charge current or inputs the discharge current.
6. The dual loop charge pump phase locked loop of claim 5 wherein said voltage control module comprises a third switch, a fourth switch and a fifth switch, a first end of said third switch being connected to said supply voltage, a second end of said third switch being connected in series with said fourth switch and being connected to ground, a first end of said fifth switch being connected to said second end of said third switch, a second end of said fifth switch being connected to said fine tuning voltage, wherein a control of said third switch is connected to said first control signal, a control of said fourth switch is connected to said second control signal, and a control of said fifth switch is connected to said third control signal.
7. The dual loop charge pump phase locked loop of claim 5 wherein the integrator comprises a third operational amplifier and a first capacitor, an output of the third operational amplifier is connected to a first terminal of the first capacitor, a second terminal of the first capacitor is grounded, wherein a non-inverting input of the third operational amplifier is connected to the fine tuning voltage, an inverting input of the third operational amplifier is connected to the reference voltage, and an output of the third operational amplifier outputs the coarse tuning voltage.
8. A method for improving stability of a dual-loop charge pump phase-locked loop, applied to the dual-loop charge pump phase-locked loop as claimed in claims 1-7, comprising:
when the charging current or the discharging current is normal, the loop control switch is conducted through the third control signal, and the double loop charge pump phase-locked loop is conducted, so that the double loop charge pump phase-locked loop works normally;
when the charging current or the discharging current is abnormal, the loop control switch is disconnected through the third control signal, the double loop charge pump phase-locked loop is cut off, so that oscillation of the fine tuning branch is avoided, and stability of the double loop charge pump phase-locked loop is improved.
9. The method of claim 8, wherein turning on the loop control switch via the third control signal when the charge current or the discharge current is normal, comprises:
when the charging current or the discharging current is normal, the filtering voltage is smaller than the preset high voltage threshold value and the filtering voltage is larger than the preset low voltage threshold value, the first control signal and the second control signal are high level, the third control signal is determined to be high level, and the third control signal of high level closes the loop control switch;
wherein the preset high voltage threshold is greater than the preset low voltage threshold.
10. The method of claim 9, wherein opening the loop control switch via the third control signal when the charge current or the discharge current is abnormal, comprises:
when the charging current is abnormal, the filtering voltage is larger than the preset high voltage threshold, the first control signal is in a low level, the second control signal is in a high level, the third control signal is determined to be in a low level, and the control signal turns off the loop control switch;
when the discharging current is abnormal, the filtering voltage is smaller than the preset low voltage threshold, the first control signal is in a high level, the second control signal is in a low level, the third control signal is determined to be in a low level, and the control signal turns off the loop control switch.
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