CN117674588A - Power management system and unit - Google Patents
Power management system and unit Download PDFInfo
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- CN117674588A CN117674588A CN202211639694.4A CN202211639694A CN117674588A CN 117674588 A CN117674588 A CN 117674588A CN 202211639694 A CN202211639694 A CN 202211639694A CN 117674588 A CN117674588 A CN 117674588A
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- power
- power management
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/073—Charge pumps of the Schenkel-type
- H02M3/077—Charge pumps of the Schenkel-type with parallel connected charge pump stages
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/36—Means for starting or stopping converters
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Direct Current Feeding And Distribution (AREA)
Abstract
The application discloses a power management system and a unit, wherein the power management system comprises a power management unit and a resistor-capacitor time sequence circuit. The power management unit is a microprocessor unit including a non-sequential logic circuit for receiving a power on/off signal and generating and outputting a power control signal according to the power on/off signal. The resistor-capacitor timing circuit is electrically connected with the non-timing logic circuit and is used for generating a plurality of on/off signals to the plurality of voltage adjustment units according to a specific timing sequence according to the power supply control signal so as to turn on/off the plurality of voltage adjustment units according to the specific timing sequence, wherein the plurality of voltage adjustment units are used for respectively generating a plurality of power supply voltages to the power supply management unit according to the input voltage, and the non-timing logic circuit receives the normally-on power supply voltage.
Description
Technical Field
The invention relates to a power management technology, in particular to a power management system and a power management unit which can be realized by directly using a micro-processing unit to match a plurality of voltage adjustment units and a resistor-capacitor time sequence circuit without using an external power management chip or an external single chip microcomputer.
Background
Conventional micro processing unit (Micro Processing Unit, MPU) systems can use a matched external power management chip to implement power management, but this can limit the cost and supply status of the micro processing unit system to the selling price and supply status of the external power management chip. In addition, the conventional micro-processing unit system can also use an external single-chip microcomputer and be matched with a plurality of groups of voltage adjusting units to realize power management, but the method needs to be matched with a program to control the voltage adjusting units, so that the complexity and the cost of the system of the micro-processing unit system are increased. On the other hand, no matter an external single chip or an external power management chip is used, the problem of extra power consumption exists.
Disclosure of Invention
The invention provides a power management system, which comprises a power management unit and a resistor-capacitor time sequence circuit. The power management unit is a microprocessor unit including a non-sequential logic circuit for receiving a power on/off signal and generating and outputting a power control signal according to the power on/off signal. The resistor-capacitor timing circuit is electrically connected with the non-timing logic circuit and is used for generating a plurality of on/off signals to the plurality of voltage adjustment units according to a specific timing sequence according to the power supply control signal so as to turn on/off the plurality of voltage adjustment units according to the specific timing sequence, wherein the plurality of voltage adjustment units are used for respectively generating a plurality of power supply voltages to the power supply management unit according to the input voltage, and the non-timing logic circuit receives the normally-on power supply voltage.
The invention provides a power management unit, which is a micro-processing unit and is used for receiving a plurality of power voltages output by a plurality of voltage adjusting units in a power management system and comprises a central processing unit, a non-sequential logic circuit, a controller and a state register. The non-sequential logic circuit receives a normally-open supply voltage. The controller is electrically connected with the central processing unit and the non-sequential logic circuit and is used for receiving the normally-open power supply voltage. The state register is electrically connected with the controller and the time sequence logic circuit and is used for receiving the normally open power supply voltage and receiving and storing the state information of the power supply management system. The controller is controlled by the central processing unit and is used for acquiring the state information temporarily stored in the state register. The controller generates a status signal to the non-sequential logic circuit according to the status information. The non-sequential logic circuit generates and outputs a power control signal and state information according to the state signal and the power on/off signal, wherein the power control signal is used for enabling the resistance capacitance sequential circuit to generate a plurality of on/off signals to the plurality of voltage adjusting units according to a specific time sequence, so that the plurality of voltage adjusting units are turned on/off according to the specific time sequence.
In summary, the power management system and unit of the present invention can be implemented by directly using the microprocessor unit in combination with a plurality of voltage adjustment units and resistor-capacitor timing circuits without using an external power management chip or an external single chip. In general, the power management system and unit of the present invention have the advantages of lower cost, lower system complexity, higher reliability, lower power consumption, etc.
For a further understanding of the technology, means, and effects of the present invention, reference should be made to the following detailed description and accompanying drawings so that the objects, features, and concepts of the invention may be fully and specifically understood. However, the following detailed description and drawings are merely for purposes of reference and illustration of implementations of the invention and are not intended to limit the invention.
Drawings
The accompanying drawings are included to provide a further understanding of the invention to those skilled in the art, and are incorporated into and constitute a part of this specification. The accompanying drawings illustrate exemplary embodiments of the invention and, together with the description, serve to explain the principles of the invention.
FIG. 1 is a block diagram of a power management system according to an embodiment of the invention.
FIG. 2 is a block diagram of a power management unit implemented as a microprocessor unit according to an embodiment of the present invention.
FIG. 3 is a schematic diagram of a resistor-capacitor timing circuit according to an embodiment of the invention.
The symbols indicated in the drawings are described as follows:
1: a power management system;
100: a resistor-capacitor timing circuit;
1002 to 1012: a resistor-capacitor charging and discharging unit;
102. 104, 106: a DC-DC converter;
108. 110, 112: a low dropout voltage regulator;
118: a battery; 114. 116: a diode;
120: a power management unit; 122: a non-sequential logic circuit;
124: a controller;
126: a status register;
128: an uninterruptible power region;
130: a central processing unit;
push_b: a power on/off unit;
GND: a ground voltage; TR: a power on/off signal;
VIN: an input voltage; CTPW: a power control signal;
VDD1 to VDD3, AVDD1 to AVDD3: a power supply voltage;
r1: a resistor;
c1: a capacitor;
p1, N1, P2, N2: and a transistor.
Detailed Description
Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. In addition, the practice of the exemplary embodiments is only one implementation of the design concepts of the invention, and none of the examples below is intended to limit the invention.
In view of the technical problems of high system complexity, high cost and extra power consumption in the prior art, the invention aims to provide a power management system and a power management unit which can be realized by directly using a micro-processing unit to be matched with a plurality of voltage adjustment units and a resistor-capacitor time sequence circuit without using an external power management chip or an external singlechip. Further, the microprocessor unit is used as a power management unit and is provided with a non-time sequence logic circuit, and the non-time sequence logic circuit is used for generating a power control signal according to a power on/off signal. The resistor-capacitor timing circuit is used for receiving the power control signal and generating a plurality of on/off signals to the plurality of voltage adjusting units so that the plurality of voltage adjusting units can provide or stop providing a plurality of power voltages to the power management unit according to a specific timing sequence.
Briefly, the power management system of the present invention eliminates the use of an external power management chip and an external single chip microcomputer, directly designs a low-power non-sequential logic circuit in the uninterrupted power region of the micro-processing unit to be used as a power management unit, and controls a resistor-capacitor sequential circuit outside the micro-processing unit to generate a plurality of on/off signals so that a plurality of voltage adjusting units provide or stop providing a plurality of power voltages to the power management unit according to a specific time sequence, thereby meeting the requirements of a plurality of power domains (power domains) and power on/power off according to a specific time sequence. In addition, the non-sequential logic circuit does not need a crystal oscillator as sequential control operation, only performs simple logic judgment and control output, is not easy to be influenced by sequential drift or short burst (glitch), and has the advantages of low power consumption and high reliability. Furthermore, at least a portion of the power management system is part of the overall micro-processing unit system, and at least a portion of the power management system and other circuit elements may be integrated into a single chip of the micro-processing unit system.
Referring to fig. 1, fig. 1 is a block diagram of a power management system according to an embodiment of the invention. The power management system 1 includes a resistor-capacitor timing circuit 100, a plurality of voltage adjusting units (implemented by dc-dc converters 102, 104, 106 and low dropout regulators 108, 110, 112), a battery 118, a power management unit 120, diodes 114, 116 and a power on/off unit push_b. The power management unit 120 can be implemented as a micro-processing unit, i.e. the power management system 1 itself can be part of a micro-processing unit system, so that no external single chip or external power management chip is required.
The power management unit 120 is designed with non-sequential logic circuits 122 in the uninterruptible power region. The non-sequential logic circuit 122 is electrically connected to the power on/off unit push_b to receive the power on/off signal TR generated by the power on/off unit push_b. In the embodiment of the present invention, the power on/off signal TR refers to a signal for turning on or off the power management system 1. For example, in the on state, when the power on/off signal TR changes from high to low (for example, changes to the ground voltage GND), the power on/off signal TR is used to turn off the power management system 1; in the off state, when the power on/off signal TR changes from high to low, the power on/off signal TR is used to turn on the power management system 1. When the power on/off signal TR is a pulse signal generated by a level change, the power management unit 120 records the status information of the power management system 1 to indicate that the power management system 1 is in the off state or the on state. It should be noted that the power on/off signal TR may also be designed to turn on the power management system 1 at a high level and turn off the power management system 1 at a low level, and no additional status information is recorded.
The non-sequential logic circuit 122 is electrically connected to the rc sequential circuit 100, and generates a power control signal CTPW to the rc sequential circuit 100 upon receiving the power on/off signal TR. In one embodiment, when the power on/off signal TR is a pulse signal generated by a level change, the non-sequential logic circuit 122 generates the power control signal CTPW according to the state information and the power on/off signal TR. In addition, the non-sequential logic circuit 122 is disposed in the uninterruptible power region, and thus receives a normally-on (always-on) supply voltage.
The RC timing circuit 100 is electrically connected to the DC converters 102, 104, 106 and the LDO 108, 110, 112. Upon receiving the power control signal CTPW, the dc-dc converters 102, 104, 106 and the low dropout regulators 108, 110, 112 are turned on/off according to a specific timing sequence. For example, in the on state, the dc-dc converters 102, 104, 106 and the low dropout voltage regulators 108, 110, 112 are turned off sequentially to achieve the power down requirement according to the specific time sequence; and, in the power-on state, the dc-dc converters 102, 104, 106 and the low dropout voltage regulators 108, 110, 112 are turned on sequentially to achieve the power-on requirement according to the specific timing. The specific timing is determined according to the resistance values of the plurality of resistors and the capacitance values of the plurality of capacitors in the resistor-capacitor timing circuit 100.
The dc-dc converters 102, 104, 106 and the low dropout regulators 108, 110, 112 receive the input voltage VIN, and supply the power supply voltages VDD1, VDD2, VDD3, AVDD1, AVDD2 and AVDD3 to the power management unit 120 when turned on, and stop supplying the power supply voltages VDD1, VDD2, VDD3, AVDD1, AVDD2 and AVDD3 to the power management unit 120 when turned off, respectively. The specific timing of the dc-dc converters 102, 104, 106 and the low dropout voltage regulators 108, 110, 112 being turned on and off may be the dc-dc converters 102, 104, 106 and the low dropout voltage regulators 108, 110, 112 in sequence, but the invention is not limited thereto.
Since the normally open power supply voltage (here, the power supply voltage AVDD 3) needs to be provided to the power management unit 120, a battery 118 is generally configured to provide the normally open power supply voltage to the power management unit 120 in the off state, and to provide the normally open power supply voltage to the power management unit 120 by the low dropout regulator 112 in the on state. Therefore, diodes 114, 116 need to be configured to isolate battery 118 from low drop-out voltage regulator 112. In this embodiment, the input terminal of the diode 114 is electrically connected to the output terminal of the LDO 112, the input terminal of the diode 116 is electrically connected to the battery 118, and the output terminals of the diodes 114, 116 are electrically connected to each other and the power management unit 120.
Incidentally, when the power on/off signal TR is an example of a pulse signal generated due to a level change, the power on/off unit push_b may be a one-click PUSH switch. However, the power on/off unit push_b is not limited thereto, and in other possible embodiments, a rotary switch, a non-click PUSH switch, a combination of a remote control receiving module and a remote controller, or the like may be used. In summary, the implementation of the power on/off unit push_b is not intended to limit the present invention. Furthermore, at least a portion of the components of the power management system 1 may be part of the micro-processing unit system and integrated into a single chip of the micro-processing unit system. In addition, in fig. 1, all the voltage adjusting units can be controlled by the on/off signal, but in other embodiments, only a part of the voltage adjusting units can be controlled by the on/off signal, and other voltage adjusting units are not controlled by the on/off signal and are directly turned on when power is turned on. For example, only the dc-dc converters 102, 104, 106 are controlled to turn on/off, but the low dropout regulators 108, 110, 112 are not controlled to turn on/off.
Next, referring to fig. 1 and fig. 2, fig. 2 is a block diagram of a power management unit implemented by a microprocessor according to an embodiment of the invention. The power management unit 120 is implemented as a microprocessor and therefore includes a central processing unit 130, non-sequential logic 122 in an uninterruptible power region 128, a controller 124, and a status register 126. The controller 124 is electrically connected to the cpu 130 and the non-sequential logic circuit 122, and is configured to receive a normally-open power supply voltage (herein, a power supply voltage AVVD3 is taken as an example). The status register 126 is electrically connected to the controller 124 and the non-sequential logic circuit 122, and is used for receiving the normally-open power voltage and receiving and storing status information of the power management system 1. The controller 124 is controlled by the cpu 130 and is used for obtaining the state information temporarily stored in the state register 126. The controller 124 generates a status signal to the non-sequential logic circuit 122 according to the status information, and the non-sequential logic circuit 122 generates an output power control signal CTPW and status information according to the status signal and the power on/off signal TR. The status information outputted from the non-sequential logic circuit 122 is further used to update the status information temporarily stored in the status register 126, and the updating and reading of the status information in the status register 126 is controlled by the controller 124.
Referring to fig. 1 and fig. 3, fig. 3 is a schematic circuit diagram of a resistor-capacitor timing circuit according to an embodiment of the invention. The rc timing circuit 100 corresponds to the embodiment of fig. 1 and includes a total of 6 rc charge-discharge cells 1002-1012. Each of the rc charge-discharge units 1002 to 1012 includes a resistor R1, a capacitor C1, and a buffer output stage implemented by two inverters, one of which is composed of transistors P1, N1 and the other of which is composed of transistors P2, N2. It is to be noted that the buffer output stage may be unnecessary and thus removable. In addition, the products of the resistor R1 and the capacitor C1 of each of the resistive-capacitive charge-discharge cells 1002 to 1012 are different from each other, for example, the resistance values of the resistor R1 of each of the resistive-capacitive charge-discharge cells 1002 to 1012 are different from each other, and the capacitance values of the capacitor C1 of each of the resistive-capacitive charge-discharge cells 1002 to 1012 are different from each other.
In each of the resistance-capacitance charge-discharge units 1002 to 1012, one end of the resistance R1 receives the power supply control signal CTPW, the other end of the resistance R1 is electrically connected to the buffer output stage and one end of the capacitance C1, and the other end of the capacitance C1 is electrically connected to a low voltage, for example, the ground voltage GND.
The resistance R1 of each of the resistive-capacitive charge-discharge cells 1002 to 1012 may be the same or different from each other, or the capacitance C1 of each of the resistive-capacitive charge-discharge cells 1002 to 1012 may be the same or different from each other, so long as the product of the resistance R1 and the capacitance C1 of each of the resistive-capacitive charge-discharge cells 1002 to 1012 is different in design. Since the product of the resistor R1 and the capacitor C1 of each of the rc charge-discharge units 1002 to 1012 is different, the time taken for the output voltages of the rc charge-discharge units 1002 to 1012 to change from high to low is different, so that the dc-dc converters 102, 104, 106 and the low-dropout regulators 108, 110, 112 can be turned on/off at a specific timing.
In summary, the present invention designs non-sequential logic circuit directly in the uninterrupted power region of the micro-processing unit system to achieve simple system up-down power management function, and adds the system power management function directly in the uninterrupted power region of the system, which not only saves external power supply cost, but also uses non-sequential power control signal to determine up-down power control, thereby reducing logic error caused by sequential drift or short burst of sequential logic and improving system reliability to the highest.
It is understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this application and scope of the appended claims.
Claims (10)
1. A power management system, the power management comprising:
the power management unit is a micro-processing unit comprising a non-sequential logic circuit, wherein the non-sequential logic circuit is used for receiving a power on/off signal and generating and outputting a power control signal according to the power on/off signal; and
the resistor-capacitor time sequence circuit is electrically connected with the non-time sequence logic circuit and is used for generating a plurality of on/off signals to a plurality of voltage adjustment units according to the power supply control signals according to a specific time sequence so as to turn on/off the voltage adjustment units according to the specific time sequence, wherein the voltage adjustment units are used for respectively generating a plurality of power supply voltages to the power supply management unit according to input voltages, and the non-time sequence logic circuit receives normally-open power supply voltages.
2. The power management system of claim 1, wherein the voltage adjustment unit comprises at least one dc-dc converter and/or at least one low dropout voltage regulator.
3. The power management system of claim 2, wherein the power management system further comprises:
the plurality of voltage adjustment units, wherein one specific voltage adjustment unit of the plurality of voltage adjustment units is used for providing the normally open power supply voltage when being started;
a battery electrically connected to the power management unit and configured to provide a battery voltage as the normally-open power supply voltage when the specific voltage adjustment unit is turned off;
the first diode is provided with a first input end and a first output end, wherein the first input end is electrically connected with the battery, and the first output end is electrically connected with the power management unit; and
the second diode is provided with a second input end and a second output end, wherein the second input end is electrically connected with the specific voltage adjusting unit, and the second output end is electrically connected with the power management unit and the first output end.
4. The power management system of claim 1, wherein the resistor-capacitor timing circuit comprises:
a plurality of resistors, wherein a first terminal of each of the plurality of resistors receives the power control signal; and
a plurality of capacitors, wherein a first end of each of the plurality of capacitors is electrically connected to a second end of the corresponding resistor and the corresponding voltage adjustment unit, and a second end of each of the plurality of capacitors is electrically connected to a low voltage.
5. The power management system of claim 1, wherein the power management unit further comprises:
a central processing unit;
the controller is electrically connected with the central processing unit and the non-time sequence logic circuit and is used for receiving the normally-open power supply voltage; and
the state register is electrically connected with the controller and the non-time sequence logic circuit and is used for receiving the normally-open power supply voltage and receiving and storing state information of the power supply management system;
the controller is controlled by the central processing unit and is used for acquiring the state information temporarily stored in the state register, generating a state signal to the non-time sequence logic circuit according to the state information, and generating and outputting the power control signal and the state information by the non-time sequence logic circuit according to the state signal and the power on/off signal.
6. The power management system of claim 1, wherein when the power management system is in a power-off state, the power control signal causes the rc timing circuit to generate the on/off signal at the specific timing for causing the voltage adjustment unit to be turned on at the specific timing when the non-timing logic circuit receives the power on/off signal.
7. The power management system of claim 1, wherein when the power management system is in an on state, the power control signal causes the rc timing circuit to generate the on/off signal at the specific timing for the voltage adjustment unit to be turned off at the specific timing when the non-timing logic circuit receives the power on/off signal.
8. A power management unit, characterized by a microprocessor unit for receiving a plurality of power supply voltages output from a plurality of voltage adjustment units in a power management system, comprising:
a central processing unit;
a non-sequential logic circuit for receiving a normally open power supply voltage;
the controller is electrically connected with the central processing unit and the non-time sequence logic circuit and is used for receiving the normally-open power supply voltage; and
the state register is electrically connected with the controller and the non-time sequence logic circuit and is used for receiving the normally-open power supply voltage and receiving and storing state information of the power supply management system;
the controller is controlled by the central processing unit and is used for acquiring the state information temporarily stored in the state register, the controller generates a state signal to the non-time sequence logic circuit according to the state information, and the non-time sequence logic circuit generates and outputs a power supply control signal and the state information according to the state signal and a power supply on/off signal, wherein the power supply control signal is used for enabling the resistance capacitance time sequence circuit to generate a plurality of on/off signals to the voltage adjusting unit according to a specific time sequence so as to turn on/off the voltage adjusting unit according to the specific time sequence.
9. The power management unit of claim 8, wherein when the power management system is in a power-off state, the power control signal causes the rc timing circuit to generate the on/off signal at the specific timing for causing the voltage adjustment unit to be turned on at the specific timing when the non-timing logic circuit receives the power on/off signal.
10. The power management unit of claim 8, wherein when the power management system is in an on state, the power control signal causes the rc timing circuit to generate the plurality of on/off signals according to the specific timing when the non-timing logic circuit receives the power on/off signal for causing the voltage adjustment unit to be turned off according to the specific timing.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW111133903A TWI840943B (en) | 2022-09-07 | 2022-09-07 | Power management system and unit |
| TW111133903 | 2022-09-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117674588A true CN117674588A (en) | 2024-03-08 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211639694.4A Pending CN117674588A (en) | 2022-09-07 | 2022-12-20 | Power management system and unit |
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| CN (1) | CN117674588A (en) |
| TW (1) | TWI840943B (en) |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6801028B2 (en) * | 2002-11-14 | 2004-10-05 | Fyre Storm, Inc. | Phase locked looped based digital pulse converter |
| US7498694B2 (en) * | 2006-04-12 | 2009-03-03 | 02Micro International Ltd. | Power management system with multiple power sources |
| CN111429845A (en) * | 2020-04-30 | 2020-07-17 | 京东方科技集团股份有限公司 | Power management integrated circuit, driving method, circuit board and display device |
| US11658570B2 (en) * | 2020-09-01 | 2023-05-23 | Intel Corporation | Seamless non-linear voltage regulation control to linear control apparatus and method |
| US11165430B1 (en) * | 2020-12-21 | 2021-11-02 | Kepler Computing Inc. | Majority logic gate based sequential circuit |
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- 2022-09-07 TW TW111133903A patent/TWI840943B/en active
- 2022-12-20 CN CN202211639694.4A patent/CN117674588A/en active Pending
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| TW202412431A (en) | 2024-03-16 |
| TWI840943B (en) | 2024-05-01 |
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