CN211653694U - Chip and method for manufacturing the same - Google Patents
Chip and method for manufacturing the same Download PDFInfo
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- CN211653694U CN211653694U CN202020643178.9U CN202020643178U CN211653694U CN 211653694 U CN211653694 U CN 211653694U CN 202020643178 U CN202020643178 U CN 202020643178U CN 211653694 U CN211653694 U CN 211653694U
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Abstract
The utility model relates to a chip, which comprises a clock generator module used for generating clock signals; the enabling and mode selecting module is used for providing an OE signal as an input signal, and if the OE signal is high level, the logic output is in a high resistance state; if the OE signal is suspended or at a low level, the logic output is in a normal state; after determining that an OE signal is suspended or is at a low level, if an external clock module working mode is selected, the RSET pin is externally connected with a pull-up resistor to an input voltage end of the chip; if the internal clock module working mode is selected, the RSET pin is externally connected with a pull-down resistor to the ground end of the chip; the logic generator module is used for outputting fixed time sequence logic according to the working mode of the internal clock module or the working mode of the external clock module; the utility model provides a chip selects outside clock input or internal clock to take place the source through the configuration of outside pin, simple structure, and the low power dissipation improves product stability and reduces the hardware cost.
Description
Technical Field
The utility model belongs to the technical field of the electron, concretely relates to chip.
Background
With the rapid development of electronic information technology and the continuous improvement of manufacturing level in the background of industrialization and informatization, Radio Frequency Identification (RFID) technology is considered as one of the most promising IT technologies in the 21 st century as a combination of wireless communication and automatic Identification technologies, and is widely applied in many fields. The RFID tag reader/writer usually reads information such as an ID number of an RFID tag in a radio frequency field according to an air interface protocol in the prior art. The passive electronic tag is convenient to install and use because the battery does not need to be replaced, and the application scene is wider than that of an active electronic tag.
In the related art, in an automatic train number identification system, along with the development of a passive electronic tag, the stability and reliability of the tag are increasingly required. At present, a tag is built through multiple devices, is relatively complex and unstable, and is high in power consumption, large starting current is needed, and hardware cost is high.
SUMMERY OF THE UTILITY MODEL
In view of this, the utility model aims at overcoming the not enough of prior art, provide a chip to solve among the prior art chip product complicacy, unstable, the consumption is high and with high costs problem.
In order to realize the above purpose, the utility model adopts the following technical scheme: a chip, comprising:
a clock generator module for generating a clock signal; the clock generator module comprises an internal clock module and an external clock module;
the enabling and mode selecting module is used for providing an OE signal as an input signal, and if the OE signal is in a high level, the logic output is in a high resistance state; if the OE signal is suspended or at a low level, the logic output is in a normal state; after determining that the OE signal is suspended or at a low level, if an external clock module working mode is selected, connecting a pull-up resistor to an input voltage end of the chip externally by the RSET pin; if the internal clock module working mode is selected, the RSET pin is externally connected with a pull-down resistor to the ground end of the chip;
and the logic generator module is used for outputting fixed sequential logic according to the working mode of the internal clock module or the working mode of the external clock module.
Further, the method also comprises the following steps:
and the clock switching module is used for switching the internal clock module and the external clock module according to the working mode selected by the enabling and mode selecting module.
Further, the clock generator module includes:
the RC oscillating circuit is used for setting the oscillating frequency of the clock signal;
the RC oscillating circuit comprises an oscillating current source and a reference resistor, wherein the reference resistor is a pull-down resistor externally connected with an RSET pin and used for setting clock frequency;
and the clock stabilizing circuit is used for outputting after the clock frequency is stabilized.
Further, the internal clock module operation modes include:
the reference module is used for establishing reference current/voltage to drive the clock generator module to work;
one end of the reference module is connected with the clock generator module, and the other end of the reference module is connected with the enabling and mode selecting module.
Further, the external clock module operation mode includes:
the CLKIN pin is arranged on a chip and is used as a clock input source;
the CLKIN pin inputs a clock signal into the logic generator module.
Further, the method also comprises the following steps:
the trimming module is used for correcting the RC oscillating circuit in real time to output stable clock frequency;
the trimming module is connected with the logic generator.
Further, the method also comprises the following steps:
a plurality of ESD protection modules for preventing the chip from being broken down or damaged by static electricity;
the ESD protection module is arranged at a pin inlet and a pin outlet of the chip.
Further, the method also comprises the following steps:
and the power supply management module is used for providing input voltage for the chip.
Further, the power management module includes: the voltage comparison module, the low-dropout voltage stabilizing module and the reset module;
the voltage comparison module is used for comparing the input voltage with a first preset voltage and a second preset voltage;
the low dropout voltage regulator module is used for increasing the voltage range of the input voltage when the input voltage is greater than a first preset voltage;
the reset module is used for resetting when the input voltage is smaller than a second preset voltage.
Further, the method also comprises the following steps:
the voltage limiting module is used for outputting the voltage limited by the voltage output by the power management module;
the power supply voltage detection module is used for monitoring the voltage value of the voltage limiting module and outputting the voltage value when the voltage value output by the voltage limiting module is greater than the set starting voltage;
one end of the power supply voltage detection circuit is connected with the voltage limiting module, and the other end of the power supply voltage detection circuit is connected with the logic generator module.
The utility model adopts the above technical scheme, the beneficial effect that can reach includes:
the utility model provides a chip, which comprises a clock generator module used for generating clock signals; the enabling and mode selecting module is used for providing an OE signal as an input signal, and if the OE signal is high level, the logic output is in a high resistance state; if the OE signal is suspended or at a low level, the logic output is in a normal state; after determining that an OE signal is suspended or is at a low level, if an external clock module working mode is selected, the RSET pin is externally connected with a pull-up resistor to an input voltage end of the chip; if the internal clock module working mode is selected, the RSET pin is externally connected with a pull-down resistor to the ground end of the chip; the logic generator module is used for outputting fixed time sequence logic according to the working mode of the internal clock module or the working mode of the external clock module; the utility model provides a chip selects outside clock input or internal clock to take place the source through the configuration of outside pin, simple structure, and the low power dissipation improves product stability and reduces the hardware cost.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a chip according to the present invention;
fig. 2 is a schematic diagram of a working flow of the chip of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be described in detail below. It is to be understood that the embodiments described are only some embodiments of the invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
A specific chip provided in the embodiment of the present application is described below with reference to the drawings.
As shown in fig. 1, the chip provided in the embodiment of the present application includes,
a clock generator module for generating a clock signal; the clock generator module comprises an internal clock module and an external clock module;
the enabling and mode selecting module is used for providing an OE signal as an input signal, and if the OE signal is in a high level, the logic output is in a high resistance state; if the OE signal is suspended or at a low level, the logic output is in a normal state; after determining that the OE signal is suspended or at a low level, if an external clock module working mode is selected, connecting a pull-up resistor to an input voltage end of the chip externally by the RSET pin; if the internal clock module working mode is selected, the RSET pin is externally connected with a pull-down resistor to the ground end of the chip;
and the logic generator module is used for outputting fixed sequential logic according to the working mode of the internal clock module or the working mode of the external clock module.
The working principle of the chip is as follows: as shown in fig. 2, the chip is provided with an OE pin and an RSET pin, the ENABLE and mode selection module ENABLE provides an OE signal through the OE pin, and the OE signal is firstly used as an input signal to control the logic output state: when the OE signal is suspended or at a low level, the logic output is in a normal state, and when the OE signal is at a high level, the logic output is in a high-resistance state; after determining that the OE signal is suspended or at a low level, selecting an internal clock module working mode or an external clock module working mode through an RSET pin, and if the external clock module working mode is selected, externally connecting a pull-up resistor to an input voltage end of the chip through the RSET pin; if the internal clock module working mode is selected, the RSET pin is externally connected with a pull-down resistor to the ground end of the chip;
the RSET pin, one of the functions is as a part of the internal clock module, and the other function is as a control terminal for clock switching ENABLE, that is, the RSET pin is used as a clock selection terminal: when the external pull-down resistor of RSET is grounded, the working mode of the internal clock module is selected, and the resistance value of the resistor can determine the frequency generated by the internal clock module; when RSET is pulled high, an external clock module working mode is selected, and a clock signal is input through a CLKIN pin and is used as a clock source of the whole chip. After the working mode is selected, the logic generator module is triggered by the external clock module or the internal clock module to generate fixed time sequence output, and the logic generator module can drive SPI slave devices with the same time sequence. In the application, the CS is always kept at the low level after being converted from the high level to the low level, and the SCK always exists, so that the logic generator module can continuously and continuously read.
The chip provided by the application can continuously read the special chip of the EEPROM, supports a standard SPI communication protocol, can realize the selection of external clock input or an internal high-precision clock generation source through the configuration of an external pin RSET, and has a wide working voltage range of 1.7-5.5V; low power consumption: the external clock is 5uA, 3.3V, and the internal clock is 12uA, 3.3V.
As shown in fig. 1, pins CS, CLKIN, SCK, SI, GND, OE, REST, VCC are provided on the chip;
the CS is used for providing a chip selection signal;
CLKIN is used for external clock input, and when the internal clock is selected, the internal of the chip is pulled down;
the SCK is used for providing a clock signal;
the SI is used for providing MOSI signals;
GND is chip ground;
OE is chip enable, and CS, SCK and SI are in high resistance state when OE is high level;
REST is a clock selection end, when an external resistor is pulled up, an external clock source is selected, when the external resistor is grounded, an internal clock is selected, and clock frequency is set;
VCC is the chip power supply.
In some embodiments, further comprising:
and the clock switching module is used for switching the internal clock module and the external clock module according to the working mode selected by the enabling and mode selecting module.
Preferably, the clock generator module includes:
the RC oscillating circuit is used for setting the oscillating frequency of the clock signal;
the RC oscillating circuit comprises an oscillating current source and a reference resistor, wherein the reference resistor is a pull-down resistor externally connected with an RSET pin and used for setting clock frequency;
and the clock stabilizing circuit is used for outputting after the clock frequency is stabilized.
Specifically, the RC oscillating circuit sets an oscillating frequency of the clock signal and outputs the clock frequency, and the RC oscillating circuit further includes an external RSET resistor and an internal adjustable capacitor. The reference resistor in the RC oscillation circuit is placed outside the chip, so that the frequency output precision and stability can be obviously improved, and meanwhile, the clock generator module also comprises a clock stabilizing circuit which is provided for the logic generator module after the clock is stabilized.
In some embodiments, the internal clock module operating modes include:
the reference module is used for establishing reference current/voltage to drive the clock generator module to work;
one end of the reference module is connected with the clock generator module, and the other end of the reference module is connected with the enabling and mode selecting module.
Specifically, the reference module REF is enabled only in the internal clock module operating mode, and its main function is to establish a reference current/voltage and drive the internal clock module OSC to operate; EN is used as an enabling switch signal of the reference module, and when EN is equal to 0, the module does not work; ref _ OK provides a reference OK signal for the subsequent stage circuit; LV is the internal low dropout regulator module LDO output voltage, provides stable power supply for other circuits, and when VCC is lower than 2.25V (typical value), LV is VCC, and when VCC >2.25V, LV is 2.25V.
Preferably, the external clock module operation modes include:
the CLKIN pin is arranged on a chip and is used as a clock input source;
the CLKIN pin inputs a clock signal into the logic generator module.
When an external clock module is selected, a clock signal is input to the logic generator module through the CLKIN pin.
Preferably, the chip provided by the present application further includes:
the trimming module is used for correcting the RC oscillating circuit in real time to output stable oscillating frequency;
the trimming module is connected with the logic generator.
Specifically, the trimming module can correct the internal capacitance circuit of the chip in real time, so that stable clock frequency output is generated.
Preferably, the method further comprises the following steps:
and the ESD protection modules are used for preventing the chip from being broken down or damaged by static electricity.
The ESD protection module is arranged at a pin inlet and a pin outlet of the chip.
In the present application, as shown in fig. 1, the chip includes a plurality of pins, and each pin is provided with an ESD protection module to prevent the chip from being damaged or broken by static electricity when the chip is connected to another electronic device.
In some embodiments, further comprising:
and the power supply management module is used for providing input voltage for the chip.
Preferably, the power management module includes: the voltage comparison module, the low-dropout voltage stabilizing module and the reset module;
the voltage comparison module is used for comparing the input voltage with a first preset voltage and a second preset voltage;
the low dropout voltage regulator module is used for increasing the voltage range of the input voltage when the input voltage is greater than a first preset voltage;
the reset module is used for resetting when the input voltage is smaller than a second preset voltage.
The comparator module is used for selecting whether an internal low dropout regulator (LDO) module is used, the range of input voltage can be greatly improved by increasing the LDO module, but power consumption can be increased, the LDO module is not selected when the input voltage is less than a first preset voltage of 2.25V, at the moment, the input voltage directly provides voltage to each module in the chip, the LDO module is selected when the input voltage is more than the first preset voltage of 2.25V, and the voltage of each module in the chip is provided by the LDO module;
the reset module is realized according to the input voltage, when the input voltage is more than 1.75V, the chip starts to work and outputs a logic time sequence; when the input voltage is less than the second preset voltage by 1.45V, the chip is reset, and only when the voltage is more than 1.75V again, the logic sequence is output again.
Preferably, the chip further comprises:
the voltage limiting module is used for outputting the voltage limited by the voltage output by the power management module;
the power supply voltage detection module is used for monitoring the voltage value of the voltage limiting module and outputting the voltage value when the voltage value output by the voltage limiting module is greater than the set starting voltage;
one end of the power supply voltage detection circuit is connected with the voltage limiting module, and the other end of the power supply voltage detection circuit is connected with the logic generator module.
To sum up, the utility model provides a chip, the utility model discloses a clock generator module, enable and mode selection module and logic generator module, the utility model provides a chip selects outside clock input or inside clock to take place the source through outside pin configuration, supports standard SPI communication, has realized simple structure, and low power dissipation has improved product stability and has reduced the hardware cost.
The above description is only for the specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto, and any person skilled in the art can easily think of the changes or substitutions within the technical scope of the present invention, and all should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A chip, comprising:
a clock generator module for generating a clock signal; the clock generator module comprises an internal clock module and an external clock module;
the enabling and mode selecting module is used for providing an OE signal as an input signal, and if the OE signal is in a high level, the logic output is in a high resistance state; if the OE signal is suspended or at a low level, the logic output is in a normal state; after determining that the OE signal is suspended or at a low level, if an external clock module working mode is selected, connecting a pull-up resistor to an input voltage end of the chip externally by the RSET pin; if the internal clock module working mode is selected, the RSET pin is externally connected with a pull-down resistor to the ground end of the chip;
and the logic generator module is used for outputting fixed sequential logic according to the working mode of the internal clock module or the working mode of the external clock module.
2. The chip of claim 1, further comprising:
and the clock switching module is used for switching the internal clock module and the external clock module according to the working mode selected by the enabling and mode selecting module.
3. The chip of claim 1, wherein the clock generator module comprises:
the RC oscillating circuit is used for setting the oscillating frequency of the clock signal;
the RC oscillating circuit comprises an oscillating current source and a reference resistor, wherein the reference resistor is a pull-down resistor externally connected with an RSET pin and used for setting clock frequency;
and the clock stabilizing circuit is used for outputting after the clock frequency is stabilized.
4. The chip of claim 1, wherein the internal clock module operating mode comprises:
the reference module is used for establishing reference current/voltage to drive the clock generator module to work;
one end of the reference module is connected with the clock generator module, and the other end of the reference module is connected with the enabling and mode selecting module.
5. The chip of claim 1, wherein the external clock module operating mode comprises:
the CLKIN pin is arranged on a chip and is used as a clock input source;
the CLKIN pin inputs a clock signal into the logic generator module.
6. The chip of claim 3, further comprising:
the trimming module is used for correcting the RC oscillating circuit in real time to output stable clock frequency;
the trimming module is connected with the logic generator.
7. The chip of claim 1, further comprising:
a plurality of ESD protection modules for preventing the chip from being broken down or damaged by static electricity;
the ESD protection module is arranged at a pin inlet and a pin outlet of the chip.
8. The chip of claim 7, further comprising:
and the power supply management module is used for providing input voltage for the chip.
9. The chip of claim 8, wherein the power management module comprises: the voltage comparison module, the low-dropout voltage stabilizing module and the reset module;
the voltage comparison module is used for comparing the input voltage with a first preset voltage and a second preset voltage;
the low dropout voltage regulator module is used for increasing the voltage range of the input voltage when the input voltage is greater than a first preset voltage;
the reset module is used for resetting when the input voltage is smaller than a second preset voltage.
10. The chip of claim 9, further comprising:
the voltage limiting module is used for outputting the voltage limited by the voltage output by the power management module;
the power supply voltage detection module is used for monitoring the voltage value of the voltage limiting module and outputting the voltage value when the voltage value output by the voltage limiting module is greater than the set starting voltage;
one end of the power supply voltage detection circuit is connected with the voltage limiting module, and the other end of the power supply voltage detection circuit is connected with the logic generator module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020643178.9U CN211653694U (en) | 2020-04-24 | 2020-04-24 | Chip and method for manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020643178.9U CN211653694U (en) | 2020-04-24 | 2020-04-24 | Chip and method for manufacturing the same |
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| Publication Number | Publication Date |
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| CN211653694U true CN211653694U (en) | 2020-10-09 |
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| CN202020643178.9U Active CN211653694U (en) | 2020-04-24 | 2020-04-24 | Chip and method for manufacturing the same |
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| CN (1) | CN211653694U (en) |
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