CN117673048A

CN117673048A - Semiconductor structure and forming method thereof

Info

Publication number: CN117673048A
Application number: CN202211016693.4A
Authority: CN
Inventors: 王晓东; 王西宁; 钱蔚宏; 邬庆
Original assignee: Semiconductor Manufacturing International Shanghai Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp
Priority date: 2022-08-24
Filing date: 2022-08-24
Publication date: 2024-03-08

Abstract

A semiconductor structure and a method of forming the same, the structure comprising: the shielding structure comprises a plurality of first metal wires which extend along a first direction and are arranged in parallel along a second direction, part of the first metal wires and the rest of the first metal wires are respectively grounded, and the first direction is perpendicular to the second direction; the protection ring surrounds the shielding structure, and an opening is formed in the protection ring and used for dividing the protection ring into protection semi-rings which are spaced along a first direction, part of the first metal wires and the rest of the first metal wires are respectively and electrically connected with the spaced protection semi-rings, and the protection ring is grounded. The invention is beneficial to improving the working performance of the semiconductor structure.

Description

Semiconductor structure and forming method thereof

Technical Field

Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.

Background

In Integrated Circuits (ICs), such as CMOS Radio Frequency Integrated Circuits (RFICs), sensing devices are an important electrical device whose performance parameters directly affect the performance of the integrated circuit. Inductive devices in integrated circuits are mostly planar inductances, such as planar spiral inductances. Compared with the traditional wire-wound inductor, the planar inductor has the advantages of low cost, easiness in integration, low noise, low power consumption and the like, and the planar inductor has higher compatibility with the existing integrated circuit process.

An important indicator of how good an inductive device performs is the quality factor (Q), which is higher, the better the performance of the inductive device is characterized.

Disclosure of Invention

The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, and improves the working performance of the semiconductor structure.

To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: the shielding structure comprises a plurality of first metal wires which extend along a first direction and are arranged in parallel along a second direction, part of the first metal wires and the rest of the first metal wires are respectively grounded, and the first direction is perpendicular to the second direction; the protection ring surrounds the shielding structure, and an opening is formed in the protection ring and used for dividing the protection ring into protection semi-rings which are spaced along a first direction, part of the first metal wires and the rest of the first metal wires are respectively and electrically connected with the spaced protection semi-rings, and the protection ring is grounded.

The embodiment of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: forming a shielding structure and a protection ring surrounding the shielding structure, wherein the protection ring is grounded; the shielding structure comprises a plurality of first metal wires which extend along a first direction and are arranged in parallel along a second direction, openings are formed in the protection ring and are used for dividing the protection ring into protection semi-rings which are spaced along the first direction, part of the first metal wires and the rest of the first metal wires are respectively and electrically connected with the spaced protection semi-rings, and the first direction is perpendicular to the second direction.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

in the semiconductor structure provided by the embodiment of the invention, the shielding structure comprises a plurality of first metal wires extending along the first direction and arranged in parallel along the second direction, part of the first metal wires and the rest of the first metal wires are respectively and electrically connected with the spaced protection semi-rings, and the protection rings are grounded; compared with the scheme that all the first metal wires are electrically connected with the same protection semi-ring, the scheme has the advantages that part of the first metal wires and the rest of the first metal wires are respectively electrically connected with the protection semi-rings at intervals, so that the part of the first metal wires are connected in series with the corresponding protection semi-rings, the rest of the first metal wires are connected in parallel with the corresponding protection semi-rings after being connected in series, the resistance of the substrate formed by the shielding structure and the protection rings is favorably increased, and therefore, in the working process of the semiconductor structure, the induction signals generated in the substrate by devices above the substrate are reduced, the substrate loss is further reduced, and the working performance of the semiconductor structure is improved.

In the forming method provided by the embodiment of the invention, the shielding structure comprises a plurality of first metal wires extending along a first direction and arranged in parallel along a second direction, and openings are formed in the protection ring and are used for dividing the protection ring into protection semi-rings spaced along the first direction, and part of the first metal wires and the rest of the first metal wires are respectively and electrically connected with the spaced protection semi-rings; compared with the scheme that all the first metal wires are electrically connected with the same protection semi-ring, the scheme has the advantages that part of the first metal wires and the rest of the first metal wires are respectively electrically connected with the protection semi-rings at intervals, so that the part of the first metal wires are connected in series with the corresponding protection semi-rings, the rest of the first metal wires are connected in parallel with the corresponding protection semi-rings after being connected in series, the resistance of the substrate formed by the shielding structure and the protection rings is favorably increased, and therefore, in the working process of the semiconductor structure, the induction signals generated in the substrate by devices above the substrate are reduced, the substrate loss is further reduced, and the working performance of the semiconductor structure is improved.

Drawings

FIGS. 1-2 are schematic diagrams of a semiconductor structure;

FIGS. 3-6 are schematic diagrams illustrating an embodiment of a semiconductor structure according to the present invention;

fig. 7 to 9 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Detailed Description

As known from the background art, the current device has poor working performance. The reason for the poor working performance of the current devices is analyzed by combining a semiconductor structure.

Fig. 1 to 2 are schematic structural views of a semiconductor structure, and fig. 2 is a partially enlarged top view of the dashed line circle in fig. 1.

The semiconductor structure includes: the shielding structure 10 includes a plurality of first metal lines 21 extending in a first direction (as shown in an X direction in fig. 1) and arranged in parallel in a second direction (as shown in a Y direction in fig. 1), and second metal lines 22 located above the first metal lines 21, the second metal lines 22 extending in the second direction, all of the first metal lines 21 being electrically connected to the second metal lines 22, the shielding structure further including an active region 11 located below the first metal lines 21, and a gate structure 12 located on the active region 11, the active region 11 and the gate structure 12 constituting a plurality of cells 20 extending in the first direction and arranged in parallel in the second direction, the cells 20 being located below the first metal lines 21 and in one-to-one correspondence with the first metal lines 21, the plurality of active regions 11 extending in the first direction and being spaced apart, the plurality of gate structures 12 extending across the active region 11 in the second direction and being arranged in parallel in the first direction, the gate structure 12 being electrically connected to the corresponding first metal lines 21 in the upper direction, the first direction being perpendicular to the second direction; a guard ring 30 surrounding the shielding structure 10, the guard ring 30 having an opening (not shown) therein for dividing the guard ring into guard half rings 31 spaced apart in a first direction, the second metal wire 22 being electrically connected to one of the guard half rings 31, the guard ring 30 being grounded; the coil device 50 is located above the shielding structure 10, and the projection of the coil device 50 onto the surface of the shielding structure 10 is located in the area where the shielding structure 10 is located.

All the first metal wires 21 are electrically connected with the same protection half ring 31, and then the resistance of the substrate formed by the shielding structure and the protection ring is that the protection half ring 31 is connected with the other protection half ring 31 in parallel after being connected with all the first metal wires 21 in series, so that the resistance of the substrate is easy to be smaller, and in the working process of the semiconductor structure, the induction signal generated in the substrate by the coil device 50 above the substrate is easy to be larger, further the substrate loss is increased, and the working performance of the semiconductor structure is influenced.

In order to solve the technical problem, an embodiment of the present invention provides a semiconductor structure, including: the shielding structure comprises a plurality of first metal wires which extend along a first direction and are arranged in parallel along a second direction, part of the first metal wires and the rest of the first metal wires are respectively grounded, and the first direction is perpendicular to the second direction; the protection ring surrounds the shielding structure, and an opening is formed in the protection ring and used for dividing the protection ring into protection semi-rings which are spaced along a first direction, part of the first metal wires and the rest of the first metal wires are respectively and electrically connected with the spaced protection semi-rings, and the protection ring is grounded.

Compared with the scheme that all the first metal wires are electrically connected with the same protection semi-ring, the scheme has the advantages that part of the first metal wires and the rest of the first metal wires are respectively electrically connected with the protection semi-rings at intervals, so that the part of the first metal wires are connected in series with the corresponding protection semi-rings, the rest of the first metal wires are connected in parallel with the corresponding protection semi-rings after being connected in series, the resistance of the substrate formed by the shielding structure and the protection rings is favorably increased, and therefore, in the working process of the semiconductor structure, the induction signals generated in the substrate by devices above the substrate are reduced, the substrate loss is further reduced, and the working performance of the semiconductor structure is improved.

In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.

Fig. 3-6 are schematic structural diagrams of an embodiment of a semiconductor structure according to the present invention.

Referring to fig. 3 to 6 in combination, fig. 3 is a top view of a semiconductor structure, fig. 4 is a top view of a coil device not shown for clarity of illustration, fig. 5 is an enlarged partial top view of a broken line circle in fig. 4, and fig. 6 is a Q-value graph of the present embodiment, the semiconductor structure includes: the shielding structure 100 includes a plurality of first metal lines 210 extending along a first direction (shown as X direction in fig. 3) and arranged in parallel along a second direction (shown as Y direction in fig. 3), wherein a part of the first metal lines 210 and the rest of the first metal lines 210 are respectively grounded, and the first direction is perpendicular to the second direction; the guard ring 300 surrounds the shielding structure 100, and an opening (not shown) is formed in the guard ring 300 for dividing the guard ring 300 into guard half rings 310 spaced apart along the first direction, and a portion of the first metal line 210 and the remaining portion of the first metal line 210 are electrically connected to the spaced apart guard half rings 310, respectively, so that the guard ring 300 is grounded.

In integrated circuits, such as CMOS radio frequency integrated circuits, sensing devices are an important electrical device whose performance parameters directly affect the performance of the integrated circuit. A Substrate of shield structure 100 and guard ring 300 is typically formed under the sensing device in the integrated circuit to isolate the sensing device from the Substrate and reduce Substrate Loss (substrateloss).

In integrated circuits, an important indicator of how well a sensing device performs is the quality factor (Q), which is higher, the better the performance of the sensing device is characterized. One important factor affecting the quality factor of the sensing device is substrate loss at high frequencies, which correspondingly increases the quality factor of the sensing device.

Specifically, the shielding structure 100 is a patterned ground shield (Pattern Ground Shield, PGS) structure.

The shielding structure 100 is used to shield the electric field lines and the induced magnetic field lines of the inductive device such that most of the electric field lines and the induced magnetic field lines generated by the inductive device terminate in the shielding structure 100 without entering the substrate, thereby reducing substrate losses.

The plurality of first metal lines 210 serve to ground the shielding structure 100, and ground noise current generated in the shielding structure 100 by grounding the shielding structure 100.

Compared with the scheme that all the first metal wires are electrically connected with the same protection half ring, the scheme electrically connects part of the first metal wires 210 and the rest of the first metal wires 210 with the spaced protection half rings 310 respectively, so that part of the first metal wires 210 are connected in series with the corresponding protection half rings 310 and the rest of the first metal wires 210 are connected in parallel after being connected in series with the corresponding protection half rings 310, which is beneficial to increasing the resistance of the substrate formed by the shielding structure 100 and the protection ring 300, thereby reducing the induction signals generated in the substrate by devices above the substrate in the working process of the semiconductor structure, further reducing the substrate loss and improving the working performance of the semiconductor structure.

In this embodiment, half of the first metal lines 210 are grounded respectively to the rest half of the first metal lines 210.

Half of the first metal wires 210 are grounded respectively with the rest half of the first metal wires 210, so that half of the first metal wires 210 are connected in series with the corresponding protection half rings 310, and the rest half of the first metal wires 210 are connected in parallel with the corresponding protection half rings 310 after being connected in series, so that the resistance of the substrate formed by the shielding structure 100 and the guard rings 300 reaches the maximum value as much as possible, thereby further reducing the induction signals generated in the substrate by devices above the substrate during the working process of the semiconductor structure, further reducing the substrate loss, and improving the working performance of the semiconductor structure.

In this embodiment, the material of the first metal line 210 includes Cu, W, al, ti or TiN.

In this embodiment, the shielding structure 100 further includes a second metal wire 220 and a third metal wire 230 above the first metal wire 210, the second metal wire 220 and the third metal wire 230 extend along the second direction and are arranged in parallel along the first direction, the second metal wire 220 is electrically connected with a portion of the first metal wire 210, the third metal wire 230 is electrically connected with the remaining portion of the first metal wire 210, and the second metal wire 220 and the third metal wire 230 are respectively electrically connected with the spaced protection half rings 310.

The second metal line 220 is used to ground a portion of the first metal line 210, and the third metal line 230 is used to ground the remaining portion of the first metal line 210.

Specifically, in the present embodiment, the second metal line 220 is electrically connected to one half of the first metal lines 210, and the third metal line 230 is electrically connected to the other half of the first metal lines 210.

In this embodiment, the second metal line 220 and the third metal line 230 are the same layer metal line.

Specifically, in the present embodiment, the first metal line 210 and the second metal line 220 or the third metal line 230 are electrically connected through the contact hole structure 240.

In this embodiment, the material of the contact hole structure 240 includes Cu, W, al, ti or TiN.

In this embodiment, the first metal wire 210 is divided into a portion of the first metal wire 210 and the remaining portion of the first metal wire 210 along the second direction, the electrical connection between the second metal wire 220 and the protection half ring 310 is used as a first connection 220a, the electrical connection between the third metal wire 230 and the protection half ring 310 is used as a second connection 230a, the second metal wire 220 is electrically connected with the portion of the first metal wire 210 far from the first connection 220a, and the third metal wire 230 is electrically connected with the portion of the first metal wire 210 far from the second connection 230 a.

The second metal wire 220 is electrically connected with a part of the first metal wire 210 far from the first connection point 220a, which is favorable for increasing the resistance of the part of the first metal wire 210 far from the first connection point 220a connected in series with the protection half ring 310, and the third metal wire 230 is electrically connected with a part of the first metal wire 210 far from the second connection point 230a, which is favorable for increasing the resistance of the part of the first metal wire 210 far from the second connection point 230a connected in series with the protection half ring 310, and the resistance of the part of the first metal wire 210 far from the first connection point 220a connected in series with the protection half ring 310 and then connected in parallel after being connected in series with the protection half ring 310, so that in the working process of the semiconductor structure, the induction signals generated by devices above the substrate are favorable for reducing the substrate loss, and the working performance of the semiconductor structure is improved.

It should be noted that, in the first direction, the distance between the second metal line 220 and the third metal line 230 should not be too large or too small. If the distance between the second metal wire 220 and the third metal wire 230 is too large, the resistance of the serial protection half ring 310 is small in the part of the first metal wire 210 and the corresponding protection half ring 310 which are connected in series through the second metal wire 220, and correspondingly, the resistance of the serial protection half ring 310 is small in the rest part of the first metal wire 210 and the corresponding protection half ring 310 which are connected in series through the third metal wire 230, so that the overall resistance of the parallel substrates is small, and in the working process of the semiconductor structure, the induction signals generated in the substrates by devices above the substrates are difficult to reduce, so that the substrate loss is increased, and the working performance of the semiconductor structure is affected; if the distance between the second metal line 220 and the third metal line 230 is too small, the difficulty of the process for forming the second metal line 220 and the third metal line 230 is increased, which affects the formation of the semiconductor structure. For this reason, in the present embodiment, the distance between the second metal line 220 and the third metal line 230 is 1 μm to 50 μm along the first direction.

In this embodiment, the material of the second metal line 220 and the third metal line 230 includes Cu, W, al, ti or TiN.

Specifically, in the present embodiment, the first metal line 210, the second metal line 220 and the third metal line 230 are formed by using a back-end process, the first metal line 210 is the first metal line (M1) in the back-end process, and the second metal line 220 and the third metal line 230 are the second metal line (M2) in the back-end process.

In the present embodiment, the first, second and third metal lines 210, 220 and 230 are formed by using a back-end process, so that modification of the existing process can be reduced and process efficiency of forming the first, second and third metal lines 210, 220 and 230 can be improved.

In this embodiment, the shape of the shielding structure 100 is octagonal, which is beneficial to making the shielding structure 100 uniformly shield the electric field lines and the induced magnetic field lines of the induction device.

In other embodiments, the shape of the shielding structure may also be triangular, square or circular.

In this embodiment, the shielding structure 100 further includes: the active region 110 located under the first metal line 210, and the gate structure 120 located on the active region 110, wherein the active region 110 and the gate structure 120 form a plurality of cells 200 extending along a first direction and arranged in parallel along a second direction, the cells 200 are located under the first metal line 210 and correspond to the first metal line 210 one by one, the plurality of active regions 110 extend along the first direction and are spaced apart, and the plurality of gate structures 120 extend across the active region 110 along the second direction and are arranged in parallel along the first direction, and the gate structure 120 is electrically connected with the corresponding first metal line 210 above.

In the actual process of forming the semiconductor structure, the semiconductor structure and the CMOS transistor are usually integrated on the same wafer, so that the semiconductor structure and the CMOS transistor are formed in the same manufacturing process, and meanwhile, the substrate of the semiconductor structure adopts the same structure of the CMOS transistor, which is beneficial to improving the flatness of the whole wafer.

In this embodiment, in the process of manufacturing the CMOS transistor, a fin field effect transistor is introduced, the active region 110 is a fin portion for providing a channel of the fin field effect transistor, and the gate structure 120 is used for controlling on and off of the channel of the fin field effect transistor. Accordingly, the active region 110 and the gate structure 120 of the semiconductor structure can be formed simultaneously during the process of forming the fin field effect transistor. In other embodiments, fully-enclosed (GAA) transistors may also be incorporated, and the respective active regions may also be one or more longitudinally-spaced channel layers. In other embodiments, planar transistors may also be incorporated, and the corresponding active regions may also be planar channels.

In this embodiment, all the active regions 110 and the gate structures 120 are grounded, so as to achieve the shielding effect of the patterned grounding shielding structure.

In this embodiment, the material of the active region 110 is silicon. In other embodiments, the material of the active region may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.

The type of gate structure 120 depends on the actual requirements of the finfet. In practical technology, the fin field effect transistor uses a high-k Gate dielectric material instead of a conventional silicon dioxide Gate dielectric material and uses Metal as a Gate electrode, so in this embodiment, the Gate structure 120 of the semiconductor structure is a Metal Gate structure (Metal Gate). In other embodiments, the gate structure of the semiconductor structure may also be a polysilicon gate structure.

It should be noted that, in the Process of manufacturing the CMOS transistor, in order to ensure that there is a sufficient Process Window (Process Window), the shapes and pattern densities of the active region 110 and the gate structure 120 need to satisfy the design rule. Therefore, in this embodiment, by introducing the active region 110 and the gate structure 120 into the substrate of the semiconductor structure, not only the formation of the semiconductor structure can be ensured, but also the pattern density and shape of the substrate can meet the design rule of the fin field effect transistor, which is correspondingly beneficial to improving the compatibility of the manufacturing processes of the semiconductor structure and the CMOS transistor.

Furthermore, by introducing the striped fins and the gate structure across the fins, it is also advantageous to reduce the eddy current area, and correspondingly reduce the eddy currents generated by the shielding structure 100 during operation, compared to semiconductor devices having planar substrates (i.e., compared to semiconductor devices having overlapping active layers and gate structures), thereby reducing substrate losses and reducing the Q-value of the inductive device.

The guard ring 300 serves to ground noise current generated in the shielding structure 100.

In this embodiment, the guard ring 300 is octagonal, so that the guard ring 300 has a relatively uniform signal suppression effect.

In other embodiments, the guard ring may also be triangular, square, or circular in shape.

In this embodiment, the material of the guard ring 300 includes Cu, W, al, ti or TiN.

Specifically, in the present embodiment, the guard ring 300 is formed by a metal line in the same layer as the first metal line 210 in the shielding structure 100, and a metal line in the same layer as the second metal line 220 and the third metal line 230 in the shielding structure 100.

In this embodiment, the semiconductor structure further includes: the coil device 500 is located above the shielding structure 100, and the projection of the coil device 500 onto the shielding structure 100 is located in the area where the shielding structure 100 is located.

The coil device 500 is the induction device.

In an integrated circuit, such as a CMOS radio frequency integrated circuit, the coil device 500 is an important electrical device, whose performance parameters directly affect the performance of the integrated circuit, and an important indicator of how good the performance of the coil device 500 is the quality factor (Q), which is a higher quality factor, which characterizes the better performance of the coil device 500. Among these, an important factor affecting the quality factor of the coil device 500 is the substrate loss at high frequencies. A shielding structure 100 and guard ring 300 are typically formed under the coil device 500 in the integrated circuit to isolate the coil device 500 from the substrate, reducing substrate loss.

In this embodiment, the shielding structure 100 and the guard ring 300 are disposed below the coil device 500 (e.g. inductor), and the shielding structure 100 is used to shield the electric field lines and the induced magnetic field lines of the induction device, so that most of the electric field lines and the induced magnetic field lines generated by the coil device 500 are terminated in the shielding structure 100 and do not enter the substrate, thereby reducing substrate loss and correspondingly increasing the Q value of the coil device 500.

As shown in fig. 6, the horizontal axis represents frequency, the vertical axis represents Q value, curve 1 represents a Q value curve of a semiconductor structure using the shielding structure 100 according to the embodiment of the present invention, where the sensing device is in different frequencies, and curve 2 represents a Q value curve of a semiconductor structure using a conventional shielding structure, where the sensing device is in different frequencies, and the Q value of the sensing device is significantly improved in the semiconductor structure using the shielding structure 100 according to the embodiment of the present invention.

In this embodiment, the sensing device is a radio frequency passive device.

The radio frequency passive device is usually in a high-frequency state in the working process, so that the effect of improving the Q value of the radio frequency passive device is better by adopting the semiconductor structure of the embodiment.

In this embodiment, the sensing device includes an input end, a metal body layer, and an output end, where the metal body layer extends from the input end to the output end in a spiral ring shape; projection of the metal body layer onto the surface of the shielding structure 100 is in the region of the shielding structure 100.

Specifically, in this embodiment, the sensing device is an inductor. Specifically, the sensing device is a planar differential inductor, and the number of spiral rings extending from the metal body layer is at least 1. In other embodiments, the inductive device may also be other electronic devices capable of generating a magnetic field and forming eddy currents within the substrate, such as planar spiral inductors, transformers, balun transformers, or the like.

The present invention also provides a method for forming a semiconductor structure, and referring to fig. 7 to 9, schematic structural diagrams corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention are provided.

Referring to fig. 7 to 8 in combination, fig. 7 is a top view of an embodiment of a method for forming a semiconductor structure according to the present invention, and fig. 8 is a partially enlarged top view of a broken line of fig. 7, forming a shielding structure 101 and a guard ring 301 surrounding the shielding structure 101, where the guard ring 301 is grounded; the shielding structure 101 includes a plurality of first metal wires 211 extending along a first direction (shown as X direction in fig. 7) and arranged in parallel along a second direction (shown as Y direction in fig. 7), the guard ring 301 has openings therein for dividing the guard ring 301 into guard half rings 311 spaced apart along the first direction, and part of the first metal wires 211 and the rest of the first metal wires 211 are electrically connected to the spaced apart guard half rings 311, respectively, wherein the first direction is perpendicular to the second direction.

In integrated circuits, such as CMOS radio frequency integrated circuits, sensing devices are an important electrical device whose performance parameters directly affect the performance of the integrated circuit. A Substrate of shield structure 101 and guard ring 301 is typically formed under the sensing device in the integrated circuit to isolate the sensing device from the Substrate and reduce Substrate Loss (substrateloss).

Specifically, the shielding structure 101 is a patterned ground shield (Pattern Ground Shield, PGS) structure.

The shielding structure 101 is used to shield the electric field lines and the induced magnetic field lines of the inductive device such that most of the electric field lines and the induced magnetic field lines generated by the inductive device terminate in the shielding structure 101 without entering the substrate, thereby reducing substrate losses.

The plurality of first metal lines 211 are used to ground the shielding structure 101, and noise current generated in the shielding structure 101 is grounded by grounding the shielding structure 101.

Compared with the scheme that all the first metal wires are electrically connected with the same protection half ring, the scheme has the advantages that part of the first metal wires 211 and the rest of the first metal wires 211 are respectively electrically connected with the spaced protection half rings 311, so that part of the first metal wires 211 are connected with the corresponding protection half rings 311 in series, and the rest of the first metal wires 211 are connected with the corresponding protection half rings 311 in parallel after being connected with the corresponding protection half rings 311 in series, the resistance of the substrate formed by the shielding structure 101 and the protection ring 301 is favorably increased, and therefore, in the working process of the semiconductor structure, induction signals generated in the substrate by devices above the substrate are reduced, the substrate loss is further reduced, and the working performance of the semiconductor structure is improved.

In the step of forming the shielding structure 101 and the guard ring 301 in this embodiment, one half of the first metal lines 211 and the other half of the first metal lines 211 are grounded respectively.

Half of the first metal wires 211 are grounded respectively with the rest half of the first metal wires 211, so that half of the first metal wires 211 are connected in series with the corresponding protection half rings 311, and the rest half of the first metal wires 211 are connected in parallel with the corresponding protection half rings 311 after being connected in series, so that the resistance of the substrate formed by the shielding structure 101 and the guard rings 301 reaches the maximum value as much as possible, thereby further reducing the induction signals generated in the substrate by devices above the substrate during the working process of the semiconductor structure, further reducing the substrate loss, and improving the working performance of the semiconductor structure.

In this embodiment, the material of the first metal line 211 includes Cu, W, al, ti or TiN.

In this embodiment, the step of forming the shielding structure 101 further includes: a first connection structure (not shown) and a second connection structure (not shown) are formed over the first metal line 211, the first connection structure including a first contact hole structure 241 on top of the first metal line 211 and a second metal line 221 on top of the first contact hole structure 241, the second connection structure including a second contact hole structure 251 on top of the first metal line 211 and a third metal line 231 on top of the second contact hole structure 251, the second metal line 221 extending in a second direction and being arranged in parallel in the first direction with the third metal line 231, the second metal line 221 being electrically connected with one of the guard half rings 311 through the first contact hole structure 241, the third metal line 231 being electrically connected with the other guard half ring 311 spaced apart through the second contact hole structure 251.

The second metal line 221 is used to ground a portion of the first metal line 211, and the third metal line 231 is used to ground the remaining portion of the first metal line 211.

Specifically, in the present embodiment, the second metal line 221 is electrically connected to one half of the first metal lines 211, and the third metal line 231 is electrically connected to the other half of the first metal lines 211.

In this embodiment, the second metal line 221 and the third metal line 231 are the same layer metal line.

In this embodiment, the material of the second metal line 221 and the third metal line 231 includes Cu, W, al, ti or TiN.

In this embodiment, the material of the first contact hole structure 241 and the second contact hole structure 251 includes Cu, W, al, ti or TiN.

Specifically, in the present embodiment, the first metal line 211, the second metal line 221 and the third metal line 231 are formed by using a back-end process, the first metal line 211 is the first metal line (M1) in the back-end process, and the second metal line 221 and the third metal line 231 are the second metal line (M2) in the back-end process.

In the present embodiment, the first, second and third metal lines 211, 221 and 231 are formed using a back-end process, so that modifications to the existing process can be reduced and the process efficiency of forming the first, second and third metal lines 211, 221 and 231 can be improved.

It should be noted that, in the first direction, the distance between the second metal line 221 and the third metal line 231 should not be too large or too small. If the distance between the second metal line 221 and the third metal line 231 is too large, the resistance of the serial protection half ring 311 is small in the part of the first metal line 211 and the corresponding protection half ring 311 which are connected in series through the second metal line 221, and correspondingly, the resistance of the serial protection half ring 311 is small in the rest part of the first metal line 211 and the corresponding protection half ring 311 which are connected in series through the third metal line 231, so that the overall resistance of the parallel substrates is small, and in the working process of the semiconductor structure, the induction signals generated in the substrates by devices above the substrates are difficult to reduce, so that the substrate loss is increased, and the working performance of the semiconductor structure is affected; if the distance between the second metal line 221 and the third metal line 231 is too small, the difficulty of the process for forming the second metal line 221 and the third metal line 231 is easily increased, which affects the formation of the semiconductor structure. For this reason, in the present embodiment, the distance between the second metal line 221 and the third metal line 231 is 1 μm to 50 μm along the first direction.

In the step of forming the first metal line 211, the first metal line 211 is divided into a portion of the first metal line 211 and the remaining portion of the first metal line 211 along the second direction; in the step of forming the second metal line 221 and the third metal line 231, the electrical connection between the second metal line 221 and the protection half ring 311 is used as a first connection 221a, the electrical connection between the third metal line 231 and the protection half ring 311 is used as a second connection 231a, the second metal line 221 is electrically connected with a portion of the first metal line 211 far from the first connection 221a, and the third metal line 231 is electrically connected with a portion of the first metal line 211 far from the second connection 231 a.

The second metal line 221 is electrically connected with a part of the first metal line 211 far from the first connection part 221a, which is favorable for increasing the resistance of the part of the first metal line 211 far from the first connection part 221a connected with the protection semi-ring 311 in series, the third metal line 231 is electrically connected with a part of the first metal line 211 far from the second connection part 231a, which is favorable for increasing the resistance of the part of the first metal line 211 far from the second connection part 231a connected with the protection semi-ring 311 in series, and the resistance of the part of the first metal line 211 far from the second connection part 231a connected with the protection semi-ring 311 connected in parallel after being connected with the part of the first metal line 211 far from the second connection part 231a connected with the protection semi-ring 311 in series, so that in the working process of the semiconductor structure, the induction signals generated by devices above the substrate in the substrate are favorable for reducing the substrate loss and the working performance of the semiconductor structure are improved.

In this embodiment, the shape of the shielding structure 101 is octagonal, which is beneficial to making the shielding structure 101 uniformly shield the electric field lines and the induced magnetic field lines of the induction device.

In this embodiment, the step of forming the shielding structure 111 further includes: before forming the first metal line 211, forming an active region 111 and a gate structure 121 on the active region 111, wherein the active region 111 and the gate structure 121 form a plurality of units 211 extending along a first direction and arranged in parallel along a second direction, the units 211 are located below the first metal line 211 and correspond to the first metal line 211 one by one, the plurality of active regions 111 extend along the first direction and are spaced apart, and the plurality of gate structures 121 extend across the active region 111 along the second direction and are arranged in parallel along the first direction; in the step of forming the first metal line 211, the first metal line 211 is electrically connected to the corresponding gate structure 121 below.

In this embodiment, in the process of manufacturing the CMOS transistor, a fin field effect transistor is introduced, the active region 111 is a fin portion for providing a channel of the fin field effect transistor, and the gate structure 121 is used for controlling on and off of the channel of the fin field effect transistor. Accordingly, the active region 111 and the gate structure 121 of the semiconductor structure can be simultaneously formed during a process of forming the fin field effect transistor. In other embodiments, fully-enclosed (GAA) transistors may also be incorporated, and the respective active regions may also be one or more longitudinally-spaced channel layers. In other embodiments, planar transistors may also be incorporated, and the corresponding active regions may also be planar channels.

In this embodiment, all the active regions 111 and the gate structures 121 are grounded, so as to achieve the shielding effect of the patterned grounding shielding structure.

In this embodiment, the material of the active region 111 is silicon. In other embodiments, the material of the active region may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.

The type of gate structure 121 depends on the actual requirements of the finfet. In practical technology, the fin field effect transistor uses a high-k Gate dielectric material instead of a conventional silicon dioxide Gate dielectric material and uses Metal as a Gate electrode, so in this embodiment, the Gate structure 121 of the semiconductor structure is a Metal Gate structure (Metal Gate). In other embodiments, the gate structure of the semiconductor structure may also be a polysilicon gate structure.

In the Process of manufacturing the CMOS transistor, the shapes and pattern densities of the active region 111 and the gate structure 121 need to satisfy the design rule in order to ensure a sufficient Process Window (Process Window). Therefore, in this embodiment, by introducing the active region 111 and the gate structure 121 into the substrate of the semiconductor structure, not only the formation of the semiconductor structure can be ensured, but also the pattern density and shape of the substrate can meet the design rule of the fin field effect transistor, which is correspondingly beneficial to improving the compatibility of the manufacturing processes of the semiconductor structure and the CMOS transistor.

Furthermore, by introducing a fin in the shape of a bar and a gate structure across the fin, it is also advantageous to reduce the eddy current area, and correspondingly reduce the eddy currents generated by the shielding structure 101 during operation, compared to a semiconductor device with a planar base (i.e. compared to a semiconductor device with an active layer and a gate structure that overlap), thereby reducing the substrate loss and thus the Q-value of the sensing device.

The guard ring 301 is used to ground noise currents generated in the shielding structure 101.

In this embodiment, the shape of the guard ring 301 is octagonal, so that the guard ring 301 has a relatively uniform signal suppression effect.

In this embodiment, the material of the guard ring 301 includes Cu, W, al, ti or TiN.

Specifically, in the step of forming the first metal line 211, the same-layer metal line is further formed in the region of the guard ring 301, and in the step of forming the second metal line 221 and the third metal line 231, the same-layer metal line is further formed in the region of the guard ring 301, and the guard ring 301 is formed by the metal line in the same layer as the first metal line 211 in the shielding structure 101 and the metal line in the same layer as the second metal line 221 and the third metal line 231 in the shielding structure 101.

Referring to fig. 9, after forming the shielding structure 101 and the guard ring 301, the forming method further includes: a coil device 501 is formed over the shielding structure 101, and a projection of the coil device 501 onto the shielding structure 101 is located in an area where the shielding structure 101 is located.

The coil device 501 is the induction device.

In an integrated circuit, such as a CMOS radio frequency integrated circuit, the coil device 501 is an important electrical device, whose performance parameters directly affect the performance of the integrated circuit, and an important indicator of how good the performance of the coil device 501 is the quality factor (Q), which is a higher quality factor, which characterizes the better performance of the coil device 501. Among these, an important factor affecting the quality factor of the coil device 501 is the substrate loss at high frequencies. A shielding structure 101 and a guard ring 301 are typically formed under the coil device 501 in the integrated circuit to isolate the coil device 501 from the substrate, reducing substrate loss.

In this embodiment, the shielding structure 101 and the guard ring 301 are disposed below the coil device 501 (e.g. inductor), and the shielding structure 101 is used to shield the electric field lines and the induced magnetic field lines of the induction device, so that most of the electric field lines and the induced magnetic field lines generated by the coil device 501 terminate in the shielding structure 101 and do not enter the substrate, thereby reducing substrate loss and correspondingly increasing the Q value of the coil device 501.

In this embodiment, the sensing device is a radio frequency passive device.

In this embodiment, the sensing device includes an input end, a metal body layer, and an output end, where the metal body layer extends from the input end to the output end in a spiral ring shape; projection of the metal body layer onto the surface of the shielding structure 101 is in the region of the shielding structure 101.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims

1. A semiconductor structure, comprising:

the shielding structure comprises a plurality of first metal wires which extend along a first direction and are arranged in parallel along a second direction, part of the first metal wires are grounded respectively with the rest of the first metal wires, and the first direction is perpendicular to the second direction;

and the protection ring surrounds the shielding structure, an opening is formed in the protection ring and is used for dividing the protection ring into protection semi-rings spaced along the first direction, part of the first metal wires and the rest of the first metal wires are respectively and electrically connected with the spaced protection semi-rings, and the protection ring is grounded.

2. The semiconductor structure of claim 1, wherein one half of the first metal lines in the shielding structure are grounded respectively to the remaining half of the first metal lines.

3. The semiconductor structure of claim 1, wherein the shielding structure further comprises a second metal line and a third metal line located above the first metal line, the second metal line and the third metal line extending in the second direction and being arranged in parallel in the first direction, the second metal line being electrically connected to a portion of the first metal line, the third metal line being electrically connected to the remaining portion of the first metal line, the second metal line and the third metal line being electrically connected to the spaced apart guard half rings, respectively.

4. The semiconductor structure of claim 3, wherein the first wire is divided into a portion of the first wire and a remaining portion of the first wire along the second direction, the second wire is electrically connected to the guard half ring as a first connection, the third wire is electrically connected to the guard half ring as a second connection, the second wire is electrically connected to a portion of the first wire remote from the first connection, and the third wire is electrically connected to a portion of the first wire remote from the second connection.

5. The semiconductor structure of claim 3, wherein a spacing of the second metal line from the third metal line along the first direction is 1 μm to 50 μm.

6. The semiconductor structure of claim 1, wherein the shielding structure further comprises: the active area and the gate structure are arranged on the active area, the active area and the gate structure form a plurality of units which extend along the first direction and are arranged in parallel along the second direction, the units are arranged below the first metal line and correspond to the first metal line one by one, in the units, a plurality of active areas extend along the first direction and are spaced apart, a plurality of gate structures extend across the active area along the second direction and are arranged in parallel along the first direction, and the gate structures are electrically connected with the first metal lines corresponding to the upper parts.

7. The semiconductor structure of any one of claims 1-6, further comprising: and the coil device is positioned above the shielding structure, and the projection of the coil device on the surface of the shielding structure is positioned in the area where the shielding structure is positioned.

8. The semiconductor structure of claim 7, wherein the coil device comprises an inductor.

9. A method of forming a semiconductor structure, comprising:

forming a shielding structure and a protection ring surrounding the shielding structure, wherein the protection ring is grounded;

the shielding structure comprises a plurality of first metal wires which extend along a first direction and are arranged in parallel along a second direction, openings are formed in the protection rings and are used for dividing the protection rings into protection semi-rings which are spaced along the first direction, part of the first metal wires and the rest of the first metal wires are electrically connected with the protection semi-rings which are spaced apart from each other respectively, and the first direction is perpendicular to the second direction.

10. The method of forming a semiconductor structure of claim 9, wherein in the step of forming the shielding structure and guard ring, one half of the first metal lines are electrically connected to the guard ring half spaced apart from the remaining half of the first metal lines, respectively.

11. The method of forming a semiconductor structure of claim 9, wherein the step of forming the shielding structure further comprises: and forming a first connection structure and a second connection structure above the first metal wire, wherein the first connection structure comprises a first contact hole structure positioned at the top of the first metal wire and a second metal wire positioned at the top of the first contact hole structure, the second connection structure comprises a second contact hole structure positioned at the top of the first metal wire and a third metal wire positioned at the top of the second contact hole structure, the second metal wire and the third metal wire extend along the second direction and are arranged in parallel along the first direction, the second metal wire is electrically connected with one protection half ring through the first contact hole structure, and the third metal wire is electrically connected with the other spaced protection half ring through the second contact hole structure.

12. The method of forming a semiconductor structure of claim 11, wherein in the step of forming the first metal line, the first metal line is divided into a portion of the first metal line and the remaining portion of the first metal line along the second direction;

in the step of forming the second metal wire and the third metal wire, the electric connection part of the second metal wire and the protection semi-ring is used as a first connection part, the electric connection part of the third metal wire and the protection semi-ring is used as a second connection part, the second metal wire is electrically connected with a part of the first metal wire far away from the first connection part, and the third metal wire is electrically connected with a part of the first metal wire far away from the second connection part.

13. The method of forming a semiconductor structure of claim 9, wherein the step of forming the shielding structure further comprises: forming an active region and a gate structure on the active region before forming the first metal line, wherein the active region and the gate structure form a plurality of units which extend along the first direction and are arranged in parallel along the second direction, the units are positioned below the first metal line and correspond to the first metal line one by one, and in the units, a plurality of active regions extend along the first direction and are spaced apart, and a plurality of gate structures extend across the active region along the second direction and are arranged in parallel along the first direction;

in the step of forming the first metal line, the first metal line is electrically connected with the corresponding gate structure below.

14. The method of forming a semiconductor structure according to any one of claims 9 to 13, wherein after forming the shield structure and guard ring, the method further comprises: a coil device is formed over the shielding structure, with a projection of the coil device onto a surface of the shielding structure being located in an area where the shielding structure is located.

15. The method of forming a semiconductor structure of claim 14, wherein the coil device comprises an inductor.