CN117059609A

CN117059609A - Semiconductor device, forming method thereof and semiconductor structure

Info

Publication number: CN117059609A
Application number: CN202210486297.1A
Authority: CN
Inventors: 王晓东; 王西宁; 钱蔚宏; 朱赛亚
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Shenzhen Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Shenzhen Corp
Priority date: 2022-05-06
Filing date: 2022-05-06
Publication date: 2023-11-14

Abstract

A semiconductor device, a method of forming the same, and a semiconductor structure, the device including: a substrate including a shielding region, and a protection region surrounding the shielding region; the shielding structure is positioned on the substrate of the shielding area; a bottom guard ring on the substrate of the guard region and surrounding the shielding structure and for grounding, the shielding structure electrically connected to the bottom guard ring, the bottom guard ring comprising: the first conductive layers are positioned on the substrate of the protection area, extend along a first direction and are arranged in parallel along a second direction, form a shape surrounding the shielding area, and the first direction is perpendicular to the second direction; the second conductive layers are positioned on the substrate of the protection area, extend along the second direction and are arranged in parallel along the first direction, form a shape surrounding the shielding area, and each second conductive layer penetrates through the first conductive layers of the area along the second direction and is electrically connected with the first conductive layers. The invention is beneficial to improving the performance of the device.

Description

Semiconductor device, forming method thereof and semiconductor structure

Technical Field

The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a semiconductor device, a forming method thereof and a semiconductor structure.

Background

In Integrated Circuits (ICs), such as CMOS Radio Frequency Integrated Circuits (RFICs), sensing devices are an important electrical device whose performance parameters directly affect the performance of the integrated circuit. Inductive devices in integrated circuits are mostly planar inductances, such as planar spiral inductances. Compared with the traditional wire-wound inductor, the planar inductor has the advantages of low cost, easiness in integration, low noise, low power consumption and the like, and the planar inductor has higher compatibility with the existing integrated circuit process.

An important indicator of how good an inductive device performs is the quality factor (Q), which is higher, the better the performance of the inductive device is characterized. Among them, an important factor affecting the quality factor of the sensing device is Substrate Loss (Substrate Loss) at high frequencies. The quality factor of the inductive device is thus generally improved by a method that reduces substrate loss.

Disclosure of Invention

The embodiment of the invention solves the problem of providing a method for forming a photoelectric sensor, which improves the photosensitive performance of the photoelectric sensor.

To solve the above problems, an embodiment of the present invention provides a semiconductor device including: a substrate including a shielding region, and a protection region surrounding the shielding region; a shielding structure positioned on the substrate of the shielding region; a bottom guard ring on the substrate of the guard region and surrounding the shielding structure, the bottom guard ring for grounding, the shielding structure electrically connected to the bottom guard ring, the bottom guard ring comprising: the first conductive layers are positioned on the substrate of the protection area, extend along a first direction and are arranged in parallel along a second direction, the first conductive layers form a shape surrounding the shielding area, and the first direction is perpendicular to the second direction; the second conductive layers are located on the substrate of the protection area, extend along the second direction and are arranged in parallel along the first direction, the second conductive layers form a shape surrounding the shielding area, and each second conductive layer penetrates through the first conductive layers of the area along the second direction and is electrically connected with the first conductive layers.

The embodiment of the invention also provides a method for forming the semiconductor device, which comprises the following steps: providing a substrate comprising a shielding region and a protection region surrounding the shielding region; forming a shielding structure on a substrate of the shielding region; forming a bottom guard ring on the substrate of the guard region surrounding the shield region, the step of forming the bottom guard ring comprising: and forming a plurality of crisscross first conductive layers and second conductive layers on the substrate of the protection area, wherein the first conductive layers extend along a first direction and are arranged in parallel along a second direction, the first conductive layers form a shape surrounding the shielding area, the second conductive layers extend along the second direction and are arranged in parallel along the first direction, the second conductive layers form a shape surrounding the shielding area, and each second conductive layer penetrates through the first conductive layers in the area along the second direction and is electrically connected with the first conductive layers, wherein the bottom protection ring is used for grounding, and the shielding structure is electrically connected with the bottom protection ring.

The embodiment of the invention also provides a semiconductor structure, which comprises: an induction device; the semiconductor device provided by the embodiment of the invention is positioned below the sensing device.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

in the semiconductor device provided by the embodiment of the invention, each second conductive layer penetrates through the plurality of first conductive layers in the area along the second direction and is electrically connected with the plurality of first conductive layers, and the plurality of first conductive layers and the plurality of second conductive layers form a bottom protection ring; in the embodiment of the invention, the first conductive layer and the second conductive layer on the same layer form the bottom protection ring, so that the closed-loop bottom protection ring can be formed, the protection capability of the shielding region is improved, the signal leakage is restrained, the probability of signal loss of a device surrounded by the bottom protection ring is reduced, and the performance of the device is improved.

Drawings

Fig. 1 is a schematic structural view of a semiconductor device;

fig. 2 to 4 are schematic structural views of another semiconductor device;

fig. 5 to 7 are schematic structural views of an embodiment of a semiconductor device according to the present invention;

fig. 8 to 14 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor device according to the present invention;

FIG. 15 is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

Fig. 16 is a graph of the performance of the sensing device of the present invention when the semiconductor structure is in operation.

Detailed Description

As known from the background art, the signal loss problem of the device surrounded by the protection ring is larger at present, and it is difficult to improve the performance of the device.

Now, two kinds of semiconductor devices are combined, and the reason why it is difficult to improve the performance of the devices at present is analyzed.

Fig. 1 is a schematic structural view of a semiconductor device.

Referring to fig. 1, a semiconductor device includes: a substrate including a shielding region 40b, and a protection region 40a surrounding the shielding region 40 b; a shielding structure on the substrate of the shielding region 40 b; and a guard ring 40 on the substrate of the guard region 40a, the guard ring 40 being electrically connected to the shielding structure, the guard ring 40 being grounded.

In integrated circuits, such as CMOS radio frequency integrated circuits, sensing devices are an important electrical device whose performance parameters directly affect the performance of the integrated circuit. Inductive devices in integrated circuits are mostly planar inductances, such as planar spiral inductances. Compared with the traditional wire-wound inductor, the planar inductor has the advantages of low cost, easiness in integration, low noise, low power consumption and the like, and the planar inductor has higher compatibility with the existing integrated circuit process.

An important indicator of how good an inductive device performs is the quality factor, which is higher, the better the performance of the inductive device is characterized. One important factor affecting the quality factor of the sensing device is the signal loss problem of the sensing device. One way to reduce signal loss is to surround the shielding structure with a grounded guard ring 40, so as to inhibit signal leakage and reduce signal loss of the sensing device.

In the semiconductor device, the guard ring 40 is shaped to surround the shielding region 40b, and the guard ring 40 is generally shaped like an octagon or a circle, which can present a surrounding pattern, and as the feature size of the integrated circuit is continuously reduced, it is difficult to form a metal line with any shape (e.g. octagon or circle) due to exposure limitation, design rule limitation, etc., and it is difficult to adapt to the current process of continuously reducing the feature size of the integrated circuit by using the continuous metal line around the guard ring 40 in fig. 1.

Referring to fig. 2 to 4 in combination, there is a schematic structural view of another semiconductor device, in which fig. 2 is a top view of the other semiconductor device, fig. 3 is an enlarged schematic partial view of a region a in fig. 2, and fig. 4 is a sectional view of fig. 3 (a) in the CC direction.

Referring to fig. 2 to 4 in combination, a semiconductor device includes: a substrate 10 including a shielding region 10b, and a protection region 10a surrounding the shielding region 10 b; a shielding structure 30 on the substrate 10 of the shielding region 10 b; a plurality of first metal lines 21 on the substrate 10 of the protection region 10a, the plurality of first metal lines 21 extending in a first direction (shown as X direction in fig. 3) and being arranged in parallel in a second direction (shown as Y direction in fig. 3), the plurality of first metal lines 21 forming a shape surrounding the shielding region 10b, the first direction being perpendicular to the second direction; and second metal lines 22 located on the first metal lines 21, the plurality of second metal lines 22 extending in the second direction and being arranged in parallel in the first direction, the plurality of second metal lines 22 forming a shape surrounding the shielding region 10b, each second metal line 22 crossing the plurality of first metal lines 21 in the second direction and being electrically connected to the plurality of first metal lines 21 in the region, the plurality of first metal lines 21 and the plurality of second metal lines 22 forming a guard ring 20, the guard ring 20 being for grounding, the shielding structure 30 being electrically connected to the guard ring 20.

For clarity of illustration, fig. 3 (a) is a schematic enlarged view of a region a in fig. 2, fig. 3 (b) is a schematic view of the first metal line 21 in fig. 3 (a), and fig. 3 (c) is a schematic view of the second metal line 22 in fig. 3 (a).

The first metal lines 21 extend along a first direction, and the second metal lines 22 extend along a second direction, which is suitable for the current process of continuously decreasing the feature size of the integrated circuit. However, as shown in fig. 4, it has been found that, if the guard ring 20 is formed of the first metal line 21 and the second metal line 22 having the upper and lower layer structures, the first metal line 21 or the second metal line 22 does not have a closed structure in the same layer, so that the protection capability of the shielding region is insufficient in each layer, it is difficult to suppress signal leakage, and it is easy to cause signal loss of the device surrounded by the guard ring 20, which affects the performance of the device, especially, for the sensing device, and it is difficult to improve the quality factor of the device.

In order to solve the technical problem, an embodiment of the present invention provides a semiconductor device, including: a substrate including a shielding region, and a protection region surrounding the shielding region; the shielding structure is positioned on the substrate of the shielding area; a bottom guard ring on the substrate of the guard region and surrounding the shielding structure, the bottom guard ring being for grounding, the shielding structure being electrically connected to the bottom guard ring, the bottom guard ring comprising: the first conductive layers are positioned on the substrate of the protection area, extend along a first direction and are arranged in parallel along a second direction, form a shape surrounding the shielding area, and the first direction is perpendicular to the second direction; the second conductive layers are positioned on the substrate of the protection area, extend along the second direction and are arranged in parallel along the first direction, form a shape surrounding the shielding area, and each second conductive layer penetrates through the first conductive layers of the area along the second direction and is electrically connected with the first conductive layers.

In the semiconductor device provided by the embodiment of the invention, the first conductive layer and the second conductive layer on the same layer form the bottom protection ring, so that the closed-loop bottom protection ring can be formed, the protection capability of the shielding region is improved, the signal leakage is restrained, the probability of signal loss of the device surrounded by the bottom protection ring is reduced, and the performance of the device is improved.

In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.

Referring to fig. 5 to 7, schematic structural views of an embodiment of the semiconductor device of the present invention are shown.

Referring to fig. 5 to 7 in combination, fig. 5 is a plan view of a semiconductor device, fig. 6 is a partially enlarged schematic view of a region B in fig. 5, fig. 7 (a) is a cross-sectional view in a DD direction of fig. 6, and fig. 7 (B) is a cross-sectional view in an EE direction of fig. 6, the semiconductor device including: a substrate 100 including a shielding region 100b, and a protection region 100a surrounding the shielding region 100 b; a shielding structure 300 on the substrate 100 of the shielding region 100 b; a bottom guard ring 200 on the substrate 100 of the guard region 100a and surrounding the shielding structure 300, the bottom guard ring 200 being for grounding, the shielding structure 300 being electrically connected to the bottom guard ring 200, the bottom guard ring 200 comprising: a plurality of first conductive layers 210 disposed on the substrate 100 of the protection region 100a, wherein the plurality of first conductive layers 210 extend along a first direction (shown as X direction in fig. 6) and are arranged in parallel along a second direction (shown as Y direction in fig. 6), and the plurality of first conductive layers 210 form a shape surrounding the shielding region 100b, and the first direction is perpendicular to the second direction; the plurality of second conductive layers 220 are disposed on the substrate 100 of the protection region 100a, the plurality of second conductive layers 220 extend along the second direction and are arranged in parallel along the first direction, the plurality of second conductive layers 220 form a shape surrounding the shielding region 100b, and each of the plurality of second conductive layers 220 penetrates through the plurality of first conductive layers 210 in the region along the second direction and is electrically connected with the plurality of first conductive layers 210.

In integrated circuits, such as CMOS radio frequency integrated circuits, sensing devices are an important electrical device whose performance parameters directly affect the performance of the integrated circuit. Semiconductor devices are typically formed under the sensing devices in the integrated circuit to isolate the sensing devices from the substrate, reducing substrate loss.

The substrate 100 provides a process operation basis for a formation process of a semiconductor device, wherein the substrate 100 of the shielding region 100b provides a process operation basis for a formation process of a shielding structure, and the substrate 100 of the protection region 100a provides a process operation basis for a formation process of a bottom Guard Ring (GR).

In this embodiment, the substrate 100 includes a substrate 160, discrete channel protruding portions 110 located on the substrate 160, and a gate structure 130 crossing the channel protruding portions 110 and covering part of the top and part of the side walls of the channel protruding portions 110, wherein the channel protruding portions 110 on both sides of the gate structure 130 are further formed with source-drain doped layers 120, the channel protruding portions 110 extend along a second direction and are arranged in parallel along the first direction, and the gate structure 130 extends along the first direction and is arranged in parallel along the second direction.

In the actual process of forming the semiconductor device, the semiconductor device and the CMOS transistor are usually integrated on the same wafer, so that the semiconductor device and the CMOS transistor are formed in the same manufacturing process, and meanwhile, the substrate of the semiconductor device adopts the same structure as the CMOS transistor, which is beneficial to improving the flatness of the whole wafer.

In this embodiment, the substrate 160 is a silicon substrate. In other embodiments, the substrate may be a germanium substrate, a silicon carbide substrate, a gallium arsenide substrate, or an indium gallium substrate, and the substrate may be a silicon on insulator substrate or a germanium on insulator substrate. The material of the substrate may be a material suitable for process requirements or easy integration.

In this embodiment, in the process of manufacturing the CMOS transistor, a fin field effect transistor is introduced, the channel protruding portion 110 is a fin portion for providing a channel of the fin field effect transistor, and the gate structure 130 is used for controlling the on and off of the channel of the fin field effect transistor. Accordingly, the channel protrusion 110 and the gate structure 130 of the semiconductor device can be simultaneously formed during a process of forming the fin field effect transistor. In other embodiments, a fully-enclosed (GAA) transistor may also be incorporated, and the corresponding channel protrusions may also be one or more longitudinally-spaced channel layers.

In this embodiment, the material of the channel protruding portion 110 is the same as the material of the substrate 160, and the material of the channel protruding portion 110 is silicon.

The type of gate structure 130 depends on the actual requirements of the finfet. In practical technology, the fin field effect transistor uses a high-k Gate dielectric material instead of a conventional silicon dioxide Gate dielectric material and uses Metal as a Gate electrode, so in this embodiment, the Gate structure 130 of the semiconductor device is a Metal Gate structure (Metal Gate). In other embodiments, the gate structure of the semiconductor device may also be a polysilicon gate structure.

In this embodiment, the source-drain doped layer 120 of the semiconductor device is formed during the formation of the fin field effect transistor, so the doping type of the source-drain doped layer 120 may be N-type or P-type.

In this embodiment, the channel protruding portions 110 extend along the second direction and are arranged in parallel along the first direction, the gate structures 130 extend along the first direction and are arranged in parallel along the second direction, and accordingly, the first conductive layers 210 can extend along the first direction and are arranged in parallel along the second direction according to the direction of the gate structures 130, and the second conductive layers 220 extend along the second direction and are arranged in parallel along the first direction according to the direction of the channel protruding portions 110.

In this embodiment, the semiconductor device further includes: dielectric layer 140 covers substrate 100. Dielectric layer 140 serves to isolate adjacent devices from each other and also serves to provide a process basis for the formation of first conductive layer 210 and second conductive layer 220. In this embodiment, the material of the dielectric layer 140 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

In integrated circuits, an important indicator of how well a sensing device performs is the quality factor (Q), which is higher, the better the performance of the sensing device is characterized. Among them, an important factor affecting the quality factor of the sensing device is Substrate Loss (Substrate Loss) at high frequencies.

In this embodiment, the semiconductor device is disposed below the sensing device (e.g. inductor), and the shielding structure 300 is used to shield the electric field lines and the magnetic field lines of the sensing device, so that most of the electric field lines and the magnetic field lines generated by the sensing device terminate in the shielding structure 300 and do not enter the substrate 160, thereby reducing the loss of the substrate 160 and correspondingly improving the quality factor of the sensing device. Specifically, the shielding structure 300 is a patterned ground shield (Pattern Ground Shield, PGS) structure.

In the present embodiment, noise current generated in the shielding structure 300 is grounded by grounding the shielding structure 300.

In this embodiment, the shielding structure 300 includes a plurality of shielding layers, and by employing the plurality of shielding layers, coupling capacitance and coupling inductance between the shielding layers and the substrate 100 are effectively reduced. The two adjacent shielding layers are electrically connected with each other and are grounded, so that noise current generated by the upper shielding layer can be transmitted to the lower shielding layer until the transmission is grounded when the induction device works, and noise crosstalk (cross talk noise) can be restrained. In this embodiment, the material of the shielding structure 300 is a conductive material, and the conductive material includes Cu, W, or Al.

The first conductive layer 210 is used to constitute the bottom guard ring 200, and the first conductive layer 210 is used to constitute the shape of the bottom guard ring 200 by arrangement.

In this embodiment, the first conductive layer 210 includes a source-drain plug layer, which is located on top of the source-drain doped layer 120 and spans the plurality of channel protrusions 110, and covers a portion of the top of the source-drain doped layer 120.

In this embodiment, the source-drain plug layer is used as the first conductive layer 210, so that the first conductive layer 210 can be formed by using a process of forming the source-drain plug layer in the formation process of the fin field effect transistor, thereby reducing modification to the existing process and improving the process efficiency of forming the first conductive layer 210.

In this embodiment, the first conductive layer 210 is located in the dielectric layer 140 on top of the substrate 100, and specifically, the first conductive layer 210 is located in the dielectric layer 140 on top of the source/drain doped layer 120.

In this embodiment, the plurality of first conductive layers 210 form an octagon with a ring shape surrounding the shielding region 100 b.

In this embodiment, the first conductive layer 210 is configured to form the shape of the bottom protection ring 200 by arrangement, and accordingly, the shape of the bottom protection ring 200 is made to be octagonal, so that the suppression effect of the bottom protection ring 200 on signals is relatively uniform, and the shape of the bottom protection ring 200 surrounding the shielding structure 300 is made to be octagonal, so that the shielding structure 300 is beneficial to uniformly shielding the electric field lines and the induced magnetic field lines of the induction device.

In other embodiments, the shape of the plurality of first conductive layers forming the surrounding shielding region may also be triangular, square or circular.

In this embodiment, the material of the first conductive layer 210 is a conductive material, and the conductive material may be Cu, W or Al.

The second conductive layer 220 is used to penetrate the first conductive layer 210 in the region, electrically connect the first conductive layers 210 in the region, and also jointly form the bottom protection ring 200 with the first conductive layer 210.

In this embodiment, the first conductive layer 210 and the second conductive layer 220 of the same layer form the bottom protection ring 200, so that the closed-loop bottom protection ring 200 can be formed, thereby improving the protection capability of the shielding region 100b, being beneficial to inhibiting signal leakage, reducing the probability of signal loss of the device surrounded by the bottom protection ring 200, and further being beneficial to improving the performance of the device.

In this embodiment, the second conductive layer 220 includes a gate plug layer disposed on top of the gate structures 130 and crossing over the plurality of gate structures 130, and the gate plug layer covers a portion of the top of the gate structures 130. In this embodiment, the gate plug layer is used as the second conductive layer 220, so that the second conductive layer 220 can be formed by using a process of forming the gate plug layer in the process of forming the fin field effect transistor, thereby reducing modification to the existing process and improving the process efficiency of forming the second conductive layer 220.

In this embodiment, the second conductive layer 220 is located in the dielectric layer 140 on top of the substrate 100, and in particular, the second conductive layer 220 is located in the dielectric layer 140 on top of the gate structure 130. In this embodiment, the material of the second conductive layer 220 is a conductive material, and the conductive material may be Cu, W or Al.

It should be noted that, the second conductive layer 220 is electrically connected to the first conductive layer 210, so as to simplify the process steps of forming the first conductive layer 210 and the second conductive layer 220 and reduce the process cost, the first conductive layer 210 and the second conductive layer 220 are formed in the same process step; accordingly, the first conductive layer 210 and the second conductive layer 220 are integrally formed.

The bottom guard ring 200 surrounds the shielding structure 300 and is electrically connected to the shielding structure 300 such that the bottom guard ring 200 serves to ground noise current generated in the shielding structure 300. Specifically, in the present embodiment, the bottom guard ring 200 is electrically connected to the shielding structure 300 through radial interconnect lines.

Accordingly, in this embodiment, the first conductive layer 210 and the second conductive layer 220 of the same layer form the bottom protection ring 200, which can form the closed-loop bottom protection ring 200, so as to be beneficial to inhibiting signal leakage, thereby being beneficial to reducing the probability of signal loss of the sensing device, and further being beneficial to improving the Q value of the sensing device. Meanwhile, the first conductive layer 210 and the second conductive layer 220 of the same layer form the bottom guard ring 200, and can also adapt to the rules such as exposure limitation and design rule limitation, so as to adapt to the current process of continuously reducing the feature size of the integrated circuit.

In the present embodiment, the width d1 of the bottom protection ring 200 in the radial direction is not too large or too small. If the width d1 of the bottom guard ring 200 in the radial direction is too large, the number of the first conductive layers 210 and the second conductive layers 220 for constituting the bottom guard ring 200 is too large, which tends to increase the complexity of the process of forming the bottom guard ring 200 and also tends to cause unnecessary waste; if the width d1 of the bottom guard ring 200 in the radial direction is too small, the number of the first conductive layers 210 and the second conductive layers 220 used to form the bottom guard ring 200 is too small and the size is also small, which easily affects the electrical connection performance of the first conductive layers 210 and the second conductive layers 220, thereby affecting the protection of the bottom guard ring 200 and the suppression of signals by the bottom guard ring 200. For this reason, in the present embodiment, the width d1 of the bottom guard ring 200 in the radial direction is 1 μm to 10 μm.

In this embodiment, the inner diameter d2 of the bottom protection ring 200 is not too large or too small. If the inner diameter d2 of the bottom guard ring 200 is too large, it is easy to cause an excessively large occupied area of the semiconductor device, thereby causing unnecessary area waste; if the inner diameter d2 of the bottom guard ring 200 is too small, the area of the shielding region 100b surrounded by the bottom guard ring 200 is too small, which easily causes process difficulties in forming the shielding structure 300, thereby affecting the formation of the semiconductor device. For this reason, in the present embodiment, the inner diameter d2 of the bottom guard ring 200 is 10um to 300um.

In this embodiment, the bottom guard ring 200 has a plurality of equally spaced first openings 100c, and the first openings 100c divide the bottom guard ring 200 into a plurality of cells isolated from each other.

Accordingly, the shielding structure 300 surrounded by the bottom guard ring 200 also has a plurality of equally spaced second openings, which divide the shielding structure 300 into a plurality of cells isolated from each other, wherein the second openings are in communication with the first openings 100 c.

By dividing the bottom guard ring 200 and the shielding structure 300 into a plurality of units isolated from each other, the resistance of the bottom guard ring 200 and the shielding structure 300 is reduced, thereby reducing the parasitic resistance of the bottom guard ring 200 and the shielding structure 300 and further improving the Q value of the induction device; and the bottom protection ring 200 and the shielding structure 300 are divided into a plurality of units which are isolated from each other, so that the eddy current formed in the bottom protection ring 200 and the shielding structure 300 by the induction current generated in the bottom protection ring 200 and the shielding structure 300 by the magnetic field generated by the induction device can be effectively restrained, the energy loss of the bottom protection ring 200 and the shielding structure 300 to the induction device is reduced, and the Q value of the induction device is further improved.

The greater the number of the first openings 100c, the better the effect of improving the Q value of the sensing device. However, if the number of the first openings 100c is too large, an excessive number of induced magnetic field lines may be caused to enter the substrate 160 through the first openings 100c, and instead the shielding effect of the shielding structure 300 may be reduced. For this reason, in the present embodiment, the number of the first openings 100c is two to eight.

Specifically, as shown in fig. 5, the number of the first openings 100c is two, the first openings 100c are disposed opposite to each other in the radial direction, and the two first openings 100c divide the bottom protection ring 200 into two units that are bilaterally symmetrical. Setting the number of the first openings 100c to two can also preferably reduce the energy loss of the bottom guard ring 200 and the shielding structure 300 to the sensing device, so as to improve the Q value of the sensing device.

Referring to fig. 7, the semiconductor device further includes: a top guard ring on top of the bottom guard ring 200 and electrically connected to the bottom guard ring 200, the top guard ring comprising: a plurality of first metal lines 410 formed on the bottom guard ring 200, the first metal lines 410 extending in the second direction and being arranged in parallel in the first direction, the plurality of first metal lines 410 forming a shape surrounding the shielding region 100 b; the plurality of second metal lines 420 formed on the first metal lines 410, the second metal lines 420 extending in the first direction and being arranged in parallel in the second direction, the plurality of second metal lines 420 forming a shape surrounding the shielding region 100b, each of the second metal lines 420 crossing the plurality of first metal lines 410 in the first direction and being electrically connected to the plurality of first metal lines 410.

In this embodiment, the first metal line 410 and the second metal line 420 form a top guard ring stacked on the bottom guard ring 200, which is beneficial to enhancing the protection capability of the bottom guard ring 200 to the shielding region 100b, and is beneficial to further suppressing signal leakage, so that the proportion of signal leakage of the device surrounded by the bottom guard ring 200 is beneficial to further reducing, and further improving the performance of the device.

Fig. 8 to 14 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor device according to the present invention.

Referring to fig. 8 and 9 in combination, fig. 8 is a top view of the substrate, and fig. 9 is a cross-sectional view of region B in fig. 8, providing a substrate 101 including a shielding region 101B, and a protection region 101a surrounding the shielding region 101B.

The substrate 101 provides a process operation basis for a formation process of the semiconductor device, wherein the substrate 101 of the shielding region 101b provides a process operation basis for a formation process of the shielding structure, and the substrate 101 of the protection region 101a provides a process operation basis for a formation process of the bottom guard ring.

In this embodiment, the base 101 includes a substrate 161, discrete channel protruding portions 111 located on the substrate 161, and a gate structure 131 crossing the channel protruding portions 111 and covering part of the top and part of the side walls of the channel protruding portions 111, wherein the channel protruding portions 111 on both sides of the gate structure 131 are further formed with an active drain doped layer 121, the channel protruding portions 111 extend in a second direction (as shown in a Y direction in fig. 8) and are arranged in parallel in a first direction (as shown in an X direction in fig. 8), and the gate structure 131 extends in the first direction and is arranged in parallel in the second direction.

In this embodiment, the substrate 161 is a silicon substrate. In other embodiments, the substrate may be a germanium substrate, a silicon carbide substrate, a gallium arsenide substrate, or an indium gallium substrate, and the substrate may be a silicon on insulator substrate or a germanium on insulator substrate. The material of the substrate may be a material suitable for process requirements or easy integration.

In this embodiment, in the process of manufacturing the CMOS transistor, a fin field effect transistor is introduced, the channel protruding portion 111 is a fin portion for providing a channel of the fin field effect transistor, and the gate structure 131 is used for controlling the on and off of the channel of the fin field effect transistor. Accordingly, the channel protrusion 111 and the gate structure 131 of the semiconductor device can be simultaneously formed during a process of forming the fin field effect transistor. In other embodiments, a fully-enclosed transistor may also be incorporated, and the corresponding channel bosses may also be one or more longitudinally-spaced channel layers.

In this embodiment, the material of the channel protruding portion 111 is the same as that of the substrate 161, and the material of the channel protruding portion 111 is silicon.

The type of gate structure 131 depends on the actual requirements of the finfet. In practical technology, the fin field effect transistor uses a high-k gate dielectric material to replace the conventional silicon dioxide gate dielectric material and uses metal as the gate electrode, so in this embodiment, the gate structure 131 of the semiconductor device is a metal gate structure. In other embodiments, the gate structure of the semiconductor device may also be a polysilicon gate structure.

In this embodiment, the source-drain doped layer 121 of the semiconductor device is formed during the formation of the fin field effect transistor, so the doping type of the source-drain doped layer 121 may be N-type or P-type.

In this embodiment, the channel protruding portions 111 extend along the second direction and are arranged in parallel along the first direction, the gate structures 131 extend along the first direction and are arranged in parallel along the second direction, and accordingly, the first conductive layers 210 can extend along the first direction and are arranged in parallel along the second direction according to the direction of the gate structures 131, and the second conductive layers 220 extend along the second direction and are arranged in parallel along the first direction according to the direction of the channel protruding portions 111.

Referring to fig. 9 to 13 in combination, a shielding structure 301 is formed on the substrate 101 of the shielding region 101 b.

In integrated circuits, an important indicator of how well an inductive device performs is the quality factor, which is higher, the better the performance of the inductive device is characterized. One important factor affecting the quality factor of the inductive device is the substrate loss at high frequencies.

In this embodiment, the semiconductor device is disposed below an induction device (e.g. an inductor), and the shielding structure 301 is used for shielding electric field lines and induction magnetic field lines of the induction device, so that most of the electric field lines and induction magnetic field lines generated by the induction device terminate in the shielding structure 301 and cannot enter the substrate 161, thereby reducing the loss of the substrate 161 and correspondingly improving the quality factor of the induction device. Specifically, the shielding structure 301 is a patterned ground shielding structure.

In the present embodiment, noise current generated in the shielding structure 301 is grounded by grounding the shielding structure 301.

In this embodiment, the shielding structure 301 includes a plurality of shielding layers, and by employing the plurality of shielding layers, the coupling capacitance and the coupling inductance between the shielding layers and the substrate 100 are effectively reduced. The two adjacent shielding layers are electrically connected with each other and are grounded, so that noise current generated by the upper shielding layer can be transmitted to the lower shielding layer until the next shielding layer is grounded when the induction device works, and noise crosstalk can be restrained. In this embodiment, the material of the shielding structure 301 is a conductive material, and the conductive material includes Cu, W, or Al.

With continued reference to fig. 9-13, forming a bottom guard ring 201 surrounding the shielding region 100b on the substrate 101 of the guard region 101a, the step of forming the bottom guard ring 291 includes: a plurality of first conductive layers 211 and second conductive layers 221 are formed on the substrate 101 of the protection region 101a in a crisscross manner, the plurality of first conductive layers 211 extend along a first direction and are arranged in parallel along a second direction, the plurality of first conductive layers 211 form a shape surrounding the shielding region 100b, the plurality of second conductive layers 221 extend along the second direction and are arranged in parallel along the first direction, the plurality of second conductive layers 221 form a shape surrounding the shielding region 100b, each second conductive layer 221 penetrates through the plurality of first conductive layers 211 of the region in the second direction and is electrically connected with the plurality of first conductive layers 211, wherein the bottom guard ring 201 is used for grounding, and the shielding structure 301 is electrically connected with the bottom guard ring 201.

In this embodiment, the first conductive layer 211 and the second conductive layer 221 of the same layer form the bottom protection ring 201, so that the closed-loop bottom protection ring 201 can be formed, thereby improving the protection capability of the shielding region 101b, being beneficial to inhibiting signal leakage, reducing the probability of signal loss of the device surrounded by the bottom protection ring 201, and further being beneficial to improving the performance of the device. Meanwhile, the first conductive layer 211 and the second conductive layer 221 of the same layer form the bottom guard ring 201, which can also adapt to the rules such as exposure limitation and design rule limitation, so as to adapt to the current process of continuously reducing the feature size of the integrated circuit.

Specifically, the embodiment is beneficial to reducing the probability of signal loss of the sensing device, and further beneficial to improving the Q value of the sensing device.

Referring to fig. 11 to 13 in combination, fig. 11 is a top view of the semiconductor device, fig. 12 is a partially enlarged schematic view of a region B in fig. 11, fig. 13 (a) is a cross-sectional view of fig. 12 along a DD direction, and fig. 13 (B) is a cross-sectional view of fig. 12 along an EE direction, in which the first conductive layer 211 includes a source-drain plug layer on top of the source-drain doped layer 121 and crossing over the plurality of channel protrusions 111, and the source-drain plug layer 121 covers a portion of the top of the source-drain doped layer 121.

The first conductive layer 211 is used to constitute the bottom guard ring 201, and the first conductive layer 211 is used to constitute the shape of the bottom guard ring 201 by arrangement.

In this embodiment, the source-drain plug layer is used as the first conductive layer 211, so that the source-drain plug layer can be formed in the formation process of the fin field effect transistor, thereby reducing the modification to the existing process and improving the process efficiency of forming the first conductive layer 211.

In this embodiment, the plurality of first conductive layers 211 form an octagon with a ring shape surrounding the shielding region 101 b.

In this embodiment, the first conductive layer 211 is configured to form the shape of the bottom protection ring 201 by arrangement, accordingly, the shape of the bottom protection ring 201 is made to be octagonal, so that the suppression effect of the bottom protection ring 201 on signals is relatively uniform, and the shape of the bottom protection ring 201 surrounding the shielding structure 301 is also made to be octagonal, so that the shielding structure 301 is beneficial to uniformly shielding the electric field lines and the induced magnetic field lines of the induction device.

In this embodiment, the material of the first conductive layer 211 is a conductive material, and the conductive material may be Cu, W or Al.

With continued reference to fig. 11-13, in this embodiment, the second conductive layer 221 includes a gate plug layer on top of the gate structures 130 and across the plurality of gate structures 130, the gate plug layer covering a portion of the top of the gate structures 130.

The second conductive layer 221 is used to penetrate the first conductive layer 211 in the region, electrically connect the first conductive layer 211 in the region, and also form the bottom guard ring 201 together with the first conductive layer 211.

In this embodiment, the gate plug layer is used as the second conductive layer 221, so that the gate plug layer can be formed in the forming process of the fin field effect transistor, thereby reducing the modification of the existing process and improving the process efficiency of forming the second conductive layer 221.

In this embodiment, the material of the second conductive layer 221 is a conductive material, and the conductive material may be Cu, W or Al.

The bottom guard ring 201 surrounds the shielding structure 301 and is electrically connected to the shielding structure 301, so that the bottom guard ring 201 serves to ground noise current generated in the shielding structure 301.

Specifically, in the present embodiment, the bottom guard ring 201 is electrically connected to the shielding structure 301 through a radial interconnect line.

In the present embodiment, the width d1 of the bottom guard ring 201 in the radial direction is not too large or too small. If the width d1 of the bottom guard ring 201 in the radial direction is too large, the number of the first conductive layers 211 and the second conductive layers 221 for constituting the bottom guard ring 201 is too large, which tends to increase the complexity of the process of forming the bottom guard ring 201 and also tends to cause unnecessary waste; if the width d1 of the bottom guard ring 201 in the radial direction is too small, the number of the first conductive layers 211 and the second conductive layers 221 constituting the bottom guard ring 201 is too small and the size is also small, so that the electrical connection performance of the first conductive layers 211 and the second conductive layers 221 is easily affected, thereby affecting the protection effect of the bottom guard ring 201 and the suppression effect of the bottom guard ring 201 on signals. For this reason, in the present embodiment, the width d1 of the bottom guard ring 201 in the radial direction is 1 μm to 10 μm.

In this embodiment, the inner diameter d2 of the bottom guard ring 201 is not too large or too small. If the inner diameter d2 of the bottom guard ring 201 is too large, it is easy to cause an excessively large occupied area of the semiconductor device, thereby causing unnecessary area waste; if the inner diameter d2 of the bottom guard ring 201 is too small, the area of the shielding region 101b surrounded by the bottom guard ring 201 is too small, which easily causes process difficulties in forming the shielding structure 301, thereby affecting the formation of the semiconductor device. For this reason, in the present embodiment, the inner diameter d2 of the bottom guard ring 201 is 10um to 300um.

In this embodiment, the bottom guard ring 201 has a plurality of equally spaced first openings 101c, and the first openings 101c divide the bottom guard ring 201 into a plurality of cells isolated from each other.

Accordingly, the shielding structure 301 surrounded by the bottom guard ring 201 also has a plurality of equally spaced second openings, which divide the shielding structure 301 into a plurality of cells isolated from each other, wherein the second openings are in communication with the first openings 101 c.

By dividing the bottom guard ring 201 and the shielding structure 301 into a plurality of units isolated from each other, the resistance of the bottom guard ring 201 and the shielding structure 301 is reduced, so that parasitic resistance of the bottom guard ring 201 and the shielding structure 301 is reduced, and the Q value of the induction device is improved; and the bottom protection ring 201 and the shielding structure 301 are divided into a plurality of units which are isolated from each other, so that eddy currents formed in the bottom protection ring 201 and the shielding structure 301 by induced currents generated in the bottom protection ring 201 and the shielding structure 301 by a magnetic field generated by an induction device can be effectively restrained, energy loss of the bottom protection ring 201 and the shielding structure 301 to the induction device is reduced, and the Q value of the induction device is further improved.

The greater the number of the first openings 101c, the better the effect of improving the Q value of the sensing device. However, if the number of the first openings 101c is too large, it may cause too many induced magnetic field lines to enter the substrate 160 through the first openings 101c, which may rather reduce the shielding effect of the shielding structure 301. For this reason, in the present embodiment, the number of the first openings 101c is two to eight.

Specifically, as shown in fig. 11, the number of the first openings 101c is two, the first openings 101c are disposed opposite to each other in the radial direction, and the two first openings 101c divide the bottom guard ring 201 into two units that are bilaterally symmetrical. Setting the number of the first openings 101c to two can also reduce the energy loss of the bottom guard ring 201 and the shielding structure 301 to the sensing device better, so as to improve the Q value of the sensing device.

Specifically, referring to fig. 9, the step of forming the plurality of first conductive layers 211 and the second conductive layers 221 crisscrossed on the substrate 101 of the protection region 101a includes: a dielectric layer 141 is formed overlying the substrate 101.

Dielectric layer 141 serves to isolate adjacent devices and also serves to provide a process basis for the formation of first conductive layer 211 and second conductive layer 221.

In this embodiment, the material of the dielectric layer 141 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

Referring to fig. 10, a plurality of first trenches 212 are formed in the dielectric layer 141 of the protection region 101a, the plurality of first trenches 212 extending in a first direction and being arranged in parallel in a second direction, the plurality of first trenches 212 constituting a shape surrounding the shielding region 101 b.

The first trench 212 is used to provide a spatial location for forming the first conductive layer 211.

Specifically, the first trench 212 exposes a portion of the top of the source drain doped layer 121.

In this embodiment, the first trench 212 is formed using a dry etching process.

The dry etching process has the characteristic of anisotropic etching, so that the etching is more directional by selecting the dry etching process, which is beneficial to improving the accuracy of the opening size of the first trench 212.

With continued reference to fig. 10, a plurality of second trenches 222 are formed in the dielectric layer 141 of the protection region 101a, the plurality of second trenches 222 extending in the second direction and being arranged in parallel in the first direction, the plurality of second trenches 222 forming a shape surrounding the shielding region 101b, each second trench 222 penetrating the plurality of first trenches 212 of the region in the second direction and communicating with the plurality of first trenches 212.

The second trench 222 is used to provide a spatial location for forming the second conductive layer 221.

Specifically, the second trench 222 exposes a portion of the top of the gate structure 131.

In this embodiment, the second trench 222 is formed by a dry etching process.

The dry etching process has the characteristic of anisotropic etching, so that the etching is more directional by selecting the dry etching process, which is beneficial to improving the dimensional accuracy of the opening of the second trench 222.

Referring to fig. 13, the first trench 212 is filled, forming a first conductive layer 211 located in the first trench 212; the second trench 222 is filled, and a second conductive layer 221 is formed in the second trench 222.

In this embodiment, the first conductive layer 211 is located in the dielectric layer 141 on top of the substrate 101, specifically, the first conductive layer 211 is located in the dielectric layer 141 on top of the source-drain doped layer 121; the second conductive layer 221 is located in the dielectric layer 141 on top of the substrate 101, in particular, the second conductive layer 221 is located in the dielectric layer 141 on top of the gate structure 130.

In this embodiment, the first trench 212 and the second trench 222 are filled in the same step.

In the same step, the first trench 212 and the second trench 222 are filled, so that the process steps of forming the first conductive layer 211 and the second conductive layer 221 are simplified, the process cost is reduced, and correspondingly, the first conductive layer 211 and the second conductive layer 221 are in an integrated structure.

Referring to fig. 14, after forming the bottom guard ring 200, further includes: a top guard ring is formed over the bottom guard ring 201, the top guard ring electrically connected to the bottom guard ring 201, the top guard ring comprising: a plurality of first metal lines 411 formed on the bottom guard ring 200, the first metal lines 411 extending in the second direction and being arranged in parallel in the first direction, the plurality of first metal lines 411 constituting a shape surrounding the shielding region 101 b; a plurality of second metal lines 421 are formed on the first metal lines 411, the second metal lines 421 extending in the first direction and being arranged in parallel in the second direction, the plurality of second metal lines 421 forming a shape surrounding the shielding region 101b, each of the second metal lines 421 crossing the plurality of first metal lines 411 in the first direction and being electrically connected to the plurality of first metal lines 411.

In this embodiment, the first metal line 411 and the second metal line 421 form a top guard ring stacked on the bottom guard ring 201, which is beneficial to enhancing the protection capability of the bottom guard ring 201 to the shielding region 101b, and is beneficial to further suppressing signal leakage, so that the proportion of signal leakage of the device surrounded by the bottom guard ring 201 is further reduced, and the performance of the device is further improved.

Specifically, a back-end process is used to form the first metal line 411 and the second metal line 421, where the first metal line 411 is the first metal line (M1) in the back-end process, and the second metal line 421 is the second metal line (M2) in the back-end process.

Fig. 15 is a schematic structural view of an embodiment of the semiconductor structure of the present invention, and fig. 16 is a performance diagram of the sensing device when the semiconductor structure of the present invention is in operation.

Referring to fig. 15, the semiconductor structure includes: an induction device 500; the semiconductor device provided by the embodiment of the invention is positioned below the sensing device 500.

In an integrated circuit, such as a CMOS radio frequency integrated circuit, the sensing device 500 is an important electrical device, whose performance parameters directly affect the performance of the integrated circuit, and an important indicator of how good the sensing device 500 performs is the quality factor (Q), which is the higher the quality factor, the better the performance of the sensing device 500. One important factor affecting the quality factor of the inductive device 500 is substrate loss at high frequencies, among others. A semiconductor device is typically formed under the sensing device 500 in the integrated circuit to isolate the sensing device 500 from the substrate, reducing substrate loss.

In this embodiment, the first conductive layer and the second conductive layer of the same layer form the bottom protection ring 200, so that the closed-loop bottom protection ring 200 can be formed, thereby improving the protection capability of the shielding region 100b, being beneficial to inhibiting signal leakage, reducing the probability of signal loss of the device surrounded by the bottom protection ring 200, and further being beneficial to improving the performance of the device.

Specifically, the first conductive layer and the second conductive layer of the same layer form the bottom protection ring 200, so that the closed-loop bottom protection ring 200 can be formed, which is beneficial to inhibiting signal leakage, thereby being beneficial to reducing the probability of signal loss of the sensing device 500 and further beneficial to improving the Q value of the sensing device 500.

As shown in fig. 16, the horizontal axis represents frequency, the vertical axis represents Q value, curve 1 represents a Q value curve of the sensing device in different frequencies in the semiconductor structure using the conventional guard ring, and curve 2 represents a Q value curve of the sensing device in different frequencies in the semiconductor structure using the bottom guard ring 200 in the embodiment of the present invention, and the Q value of the sensing device is significantly improved in the semiconductor structure using the bottom guard ring 200 in the embodiment of the present invention.

In this embodiment, the semiconductor device is disposed below the sensing device 500 (e.g. inductor), and the shielding structure 300 is used for shielding the electric field lines and the magnetic field lines of the sensing device, so that most of the electric field lines and the magnetic field lines generated by the sensing device 500 terminate in the shielding structure 300 and cannot enter the substrate, thereby reducing substrate loss and correspondingly increasing the Q value of the sensing device 500.

In this embodiment, the sensing device 500 is a radio frequency passive device.

The radio frequency passive device is usually in a high-frequency state in the working process, so that the effect of improving the Q value of the radio frequency passive device is better by adopting the semiconductor structure of the embodiment.

In this embodiment, the sensing device 500 includes an input end, a metal body layer and an output end, where the metal body layer extends from the input end to the output end in a spiral ring shape; projection of the metal body layer onto the substrate surface is in a shielded region 100b of the substrate.

Specifically, in the present embodiment, the sensing device 500 is an inductor. Specifically, the inductive device 500 is a planar differential inductor, and the number of spiral loops that the metal body layer extends over is at least 1. In other embodiments, the inductive device may also be other electronic devices capable of generating a magnetic field and forming eddy currents within the substrate, such as planar spiral inductors, transformers, balun transformers, or the like.

Projection of the metal body layer onto the substrate surface is in the shielding region 100b of the substrate, thereby achieving shielding of the shielding structure 300 from electric and induced magnetic field lines in the metal body layer.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims

1. A semiconductor device, comprising:

a substrate including a shielding region, and a protection region surrounding the shielding region;

a shielding structure positioned on the substrate of the shielding region;

a bottom guard ring on the substrate of the guard region and surrounding the shielding structure, the bottom guard ring for grounding, the shielding structure electrically connected to the bottom guard ring, the bottom guard ring comprising:

the first conductive layers are positioned on the substrate of the protection area, extend along a first direction and are arranged in parallel along a second direction, the first conductive layers form a shape surrounding the shielding area, and the first direction is perpendicular to the second direction;

the second conductive layers are located on the substrate of the protection area, extend along the second direction and are arranged in parallel along the first direction, the second conductive layers form a shape surrounding the shielding area, and each second conductive layer penetrates through the first conductive layers of the area along the second direction and is electrically connected with the first conductive layers.

2. The semiconductor device of claim 1, wherein the base comprises a substrate, discrete channel bumps on the substrate, and a gate structure spanning the channel bumps and covering a portion of the top and a portion of the sidewalls of the channel bumps, the channel bumps on both sides of the gate structure further having source-drain doped layers formed therein, the channel bumps extending in the second direction and being arranged in parallel along the first direction, the gate structure extending in the first direction and being arranged in parallel along the second direction;

The first conductive layer comprises a source-drain plug layer, which is positioned at the top of the source-drain doped layer and spans across the plurality of channel bulges, and covers part of the top of the source-drain doped layer;

the second conductive layer includes a gate plug layer on top of the gate structure and crossing over a plurality of the gate structures, the gate plug layer covering a portion of the top of the gate structures.

3. The semiconductor device according to claim 1 or 2, wherein the semiconductor device further comprises: a dielectric layer covering the substrate;

the first conductive layer and the second conductive layer are both positioned in a dielectric layer on the top of the substrate.

4. The semiconductor device according to claim 2, wherein the semiconductor device further comprises: a top guard ring on top of and electrically connected to the bottom guard ring, the top guard ring comprising:

a plurality of first metal wires positioned on the bottom guard ring, the first metal wires extending along the second direction and being arranged in parallel along the first direction, the plurality of first metal wires forming a shape surrounding the shielding region;

and a plurality of second metal wires positioned on the first metal wires, wherein the second metal wires extend along the first direction and are arranged in parallel along the second direction, the second metal wires form a shape surrounding the shielding region, and each second metal wire spans the plurality of first metal wires in the area along the first direction and is electrically connected with the plurality of first metal wires.

5. The semiconductor device according to claim 1, wherein a width of the bottom guard ring in a radial direction is 1 μm to 10 μm.

6. The semiconductor device of claim 1, wherein an inner diameter dimension of the bottom guard ring is 10um to 300um.

7. The semiconductor device according to claim 1, wherein a plurality of the first conductive layers constitute an octagon, a triangle, a square, or a circle having a ring shape surrounding the shielding region.

8. The semiconductor device of claim 1, wherein the bottom guard ring has a plurality of equally spaced apart first openings dividing the bottom guard ring into a plurality of cells isolated from each other.

9. The semiconductor device of claim 1, wherein the shielding structure has a plurality of equally spaced apart second openings dividing the shielding structure into a plurality of cells isolated from each other.

10. The semiconductor device according to claim 8, wherein the number of the first openings is two to eight.

11. The semiconductor device according to claim 1, wherein the first conductive layer and the second conductive layer are of unitary construction.

12. A method of forming a semiconductor device, comprising:

providing a substrate comprising a shielding region and a protection region surrounding the shielding region;

forming a shielding structure on a substrate of the shielding region;

forming a bottom guard ring on the substrate of the guard region surrounding the shield region, the step of forming the bottom guard ring comprising: and forming a plurality of crisscross first conductive layers and second conductive layers on the substrate of the protection area, wherein the first conductive layers extend along a first direction and are arranged in parallel along a second direction, the first conductive layers form a shape surrounding the shielding area, the second conductive layers extend along the second direction and are arranged in parallel along the first direction, the second conductive layers form a shape surrounding the shielding area, and each second conductive layer penetrates through the first conductive layers in the area along the second direction and is electrically connected with the first conductive layers, wherein the bottom protection ring is used for grounding, and the shielding structure is electrically connected with the bottom protection ring.

13. The method of forming a semiconductor device of claim 12, wherein the base comprises a substrate, discrete channel bumps on the substrate, and a gate structure spanning the channel bumps and covering a portion of a top and a portion of a sidewall of the channel bumps, the channel bumps on both sides of the gate structure further having source-drain doped layers formed therein, the channel bumps extending in the second direction and being arranged in parallel in the first direction, the gate structure extending in the first direction and being arranged in parallel in the second direction;

14. The method of forming a semiconductor device according to claim 12 or 13, wherein the step of forming a plurality of first conductive layers and second conductive layers crisscrossed on the substrate of the protection region comprises: forming a dielectric layer covering the substrate;

forming a plurality of first grooves in the dielectric layer of the protection area, wherein the first grooves extend along a first direction and are arranged in parallel along a second direction, and the first grooves form a shape surrounding the shielding area;

forming a plurality of second grooves in the dielectric layer of the protection area, wherein the second grooves extend along the second direction and are arranged in parallel along the first direction, the second grooves form a shape surrounding the shielding area, and each second groove penetrates through the first grooves of the area along the second direction and is communicated with the first grooves;

Filling the first groove to form a first conductive layer in the first groove;

and filling the second groove to form a second conductive layer in the second groove.

15. The method of forming a semiconductor device according to claim 14, wherein the first trench and the second trench are filled in a same step.

16. The method of forming a semiconductor device according to claim 12, wherein the method of forming a semiconductor device further comprises: after forming the bottom guard ring, forming a top guard ring on the bottom guard ring, the top guard ring electrically connected to the bottom guard ring, the top guard ring comprising:

a plurality of first metal wires formed on the bottom guard ring, the first metal wires extending in the second direction and being arranged in parallel in the first direction, the plurality of first metal wires forming a shape surrounding the shielding region;

and the second metal wires are formed on the first metal wires, extend along the first direction and are arranged in parallel along the second direction, the second metal wires form a shape surrounding the shielding region, and each second metal wire spans the first metal wires in the area along the first direction and is electrically connected with the first metal wires.

17. A semiconductor structure, comprising:

an induction device;

a semiconductor device as claimed in any one of claims 1 to 11, which is located below the sensing device.

18. The semiconductor structure of claim 17, wherein the inductive device is a radio frequency passive device.

19. The semiconductor structure of claim 17, wherein the sensing device comprises an input, a metal body layer, and an output, the metal body layer extending in a spiral loop from the input to the output;

the projection of the metal body layer on the surface of the substrate is in a shielding area of the substrate.