CN117672818A

CN117672818A - Chip product preparation method and system

Info

Publication number: CN117672818A
Application number: CN202211058895.5A
Authority: CN
Inventors: 张文龙; 胡晶晶; 李渊
Original assignee: Tencent Technology Shenzhen Co Ltd
Current assignee: Tencent Technology Shenzhen Co Ltd
Priority date: 2022-08-30
Filing date: 2022-08-30
Publication date: 2024-03-08

Abstract

The application relates to a chip product preparation method and a chip product preparation system, and relates to the technical field of micro-nano processing. The method comprises the following steps: coating a first photoresist on the first chip product with the first deposition layer to obtain a first photoresist layer covering the first chip product; preparing a first circuit structure composed of a deposition material in a first deposition layer based on the first photoresist layer; performing conversion treatment based on the residual first photoresist in the first photoresist layer to obtain a second photoresist layer; the second photoresist layer has a characteristic of being soluble in a developing solution; preparing a third photoresist layer over the second photoresist layer; carrying out photoetching development treatment on the appointed position on the first chip product, and removing the photoresist of the second photoresist layer and the third photoresist layer at the appointed position; preparing a second deposition layer at a designated location; and cleaning the residual photoresist in the second photoresist layer and the third photoresist layer to obtain a second chip product.

Description

Chip product preparation method and system

Technical Field

The application relates to the technical field of micro-nano processing, in particular to a chip product preparation method and system.

Background

The etch-deposition-strip process is a process commonly used in micro-nano processing techniques for the fabrication of circuit structures in chips.

In the related art, a complete etch-deposition-stripping process may include two rounds of material deposition-photoresist coating-photolithographic development-etching-photoresist cleaning steps; the complete fabrication of a chip typically involves multiple etch-deposition-stripping processes.

Then, in the chip production and manufacturing, excessive photoresist spin coating and cleaning processes can have negative effects on the chip finished product, affecting the chip performance.

Disclosure of Invention

The embodiment of the application provides a chip product preparation method and a chip product preparation system, which can improve the performance of the chip product.

In one aspect, a method of preparing a chip product is provided, the method comprising:

coating a first photoresist on a first chip product with a first deposition layer to obtain a first photoresist layer covering the first chip product;

preparing a first circuit structure composed of a deposition material in the first deposition layer based on the first photoresist layer;

performing conversion treatment based on the first photoresist remained in the first photoresist layer to obtain a second photoresist layer; the second photoresist layer has a characteristic of being soluble in a developing solution;

Preparing a third photoresist layer over the second photoresist layer;

carrying out photoetching development treatment on the appointed position on the first chip product, and removing the photoresist of the second photoresist layer and the third photoresist layer at the appointed position;

preparing a second deposition layer at the designated location;

and cleaning the residual photoresist in the second photoresist layer and the third photoresist layer to obtain a second chip product.

In yet another aspect, a chip product preparation system is provided, the system comprising: a gumming machine, a photoetching machine, an etching machine, an evaporation machine and a cleaning machine;

the glue spreader is used for coating a first photoresist on a first chip product with a first deposition layer to obtain a first photoresist layer covering the first chip product;

the photoetching machine and the etching machine are used for preparing a first circuit structure formed by deposition materials in the first deposition layer based on the first photoresist layer;

the glue coater and the photoetching machine are used for carrying out conversion treatment based on the residual first photoresist in the first photoresist layer to obtain a second photoresist layer; the second photoresist layer has a characteristic of being soluble in a developing solution;

The glue spreader is used for preparing a third photoresist layer above the second photoresist layer;

the photoetching machine is used for carrying out photoetching development treatment on the appointed position on the first chip product and removing the photoresist of the second photoresist layer and the third photoresist layer at the appointed position;

the evaporator is used for preparing a second deposition layer at the appointed position;

and the cleaning machine is used for cleaning the residual photoresist in the second photoresist layer and the third photoresist layer to obtain a second chip product.

In a possible implementation manner, the glue coater and the photoetching machine are used for uniformly mixing the first photoresist and the second photoresist remained in the first photoresist layer to obtain the second photoresist layer.

In a possible implementation manner, the lithography machine is configured to perform flood exposure processing on the first photoresist remaining in the first photoresist layer;

the glue spreader is used for coating the second photoresist layer on the first photoresist layer; and uniformly mixing the second photoresist with the first photoresist to obtain the second photoresist layer.

In a possible implementation manner, the glue spreader is configured to physically mix the second photoresist with the first photoresist uniformly to obtain the second photoresist layer.

In one possible implementation, the physical means includes at least one of the following means:

rotating the first chip product;

and, standing the first chip product.

In one possible implementation manner, the manner of the flood exposure process includes:

ultraviolet exposure or laser direct writing.

In one possible implementation, the second photoresist is a non-photosensitive photoresist.

In one possible implementation, the second photoresist is a lift-off photoresist.

In a possible implementation, the glue spreader is further configured to bake the second photoresist layer at a soft bake temperature before preparing a third photoresist layer over the second photoresist layer.

In one possible implementation, the soft bake temperature is 80 to 200 degrees celsius.

In one possible implementation, the developing time for performing the photolithographic developing process on the specified location on the first chip product is 60 to 120 seconds.

In a possible implementation manner, the photoetching machine is used for carrying out photoetching development treatment on the position, corresponding to the pattern of the first circuit structure, in the first photoresist layer so as to remove the first photoresist at the position of the pattern of the first circuit structure;

and the etching machine is used for carrying out etching treatment on the position of the pattern of the first circuit structure to obtain the first circuit structure.

In one possible implementation, the second chip product is a superconducting quantum chip; or the second chip product is a semi-finished product of the superconducting quantum chip.

The beneficial effects that technical scheme that this application embodiment provided include at least:

after the first circuit structure is prepared by a photoetching development mode based on the first photoresist layer, the first photoresist layer is not directly cleaned, but is subjected to conversion treatment to obtain a second photoresist layer which is soluble in a developing solution, and then a third photoresist layer is prepared on the second photoresist layer.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.

FIG. 1 is a schematic flow diagram of an etch-deposition-stripping process according to the present application;

FIG. 2 is a method flow diagram illustrating a method of manufacturing a chip product according to an exemplary embodiment of the present application;

FIG. 3 is a schematic diagram of a chip product manufacturing process according to the embodiment of FIG. 2;

FIG. 4 is a method flow diagram illustrating a method of manufacturing a chip product according to an exemplary embodiment of the present application;

FIG. 5 is a flow chart of the preparation of a chip product according to the embodiment shown in FIG. 4;

FIGS. 6 and 7 illustrate schematic views of undercut structures involved in the embodiment of FIG. 4;

fig. 8 is a schematic diagram of a josephson junction fabrication system shown in an exemplary embodiment of the present application;

fig. 9 is a schematic diagram of a scenario of application of the solution provided in one embodiment of the present application.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as detailed in the accompanying claims.

Exposure & development: a micro-nano processing technology mainly relates to ultraviolet lithography, namely, coating photoresist on the surface of a substrate sample, then irradiating ultraviolet light on the surface of the substrate through a mask, changing the property of the part of the photoresist irradiated by the light by utilizing photochemical reaction, and then dissolving the area which reacts with the light into a specific solution to achieve the purpose of making a specific pattern on the substrate.

Undercut (undercut): the photoresist structure is characterized in that the bottom of the photoresist is wider than the top, the side wall is gradually expanded outwards from the top to the bottom, the cross section of the photoresist is in a positive trapezoid shape, and the photoresist also can be in a convex shape after the process improvement. The structure is commonly used for stripping technology in the micro-nano processing field.

Etching: a micromachining process uses dry (other) and wet (liquid) etching of metals or other materials to form desired structures.

Sacrificial layer: in the lift-off technique, in order to lift off the deposited material in the undefined region, a photoresist is applied to the substrate in the undefined region; when the photoresist is stripped, the photoresist layer is dissolved in a specific solution, and meanwhile, the material deposited on the photoresist layer is stripped, namely the sacrificial layer.

Release adhesive (LOR): glue that does not react with light is commonly used for sacrificial layers in lift-off processes.

Stripping: the lift-off technology (lift-off technology) refers to that after a photoresist (photoresist) is coated, exposed and developed on a substrate, a photoresist film with a certain pattern is used as a mask, required materials such as metal and the like are deposited on a glued substrate by evaporation and other methods, then the photoresist is removed, simultaneously, the non-required materials on the glue film are peeled off together, and finally only the material structure with the original pattern is left on the substrate.

Superconducting chip: the chip is prepared by using a superconducting material and works below the superconducting transition temperature.

Under-bump Metal (UBM) layer: a buffer layer for connecting the pads to the circuit. In the superconducting chip, since a common circuit material (such as aluminum Al) and a welding spot (such as indium In) can form an alloy, the alloy becomes brittle at low temperature and the stability is reduced, a UBM layer is used for isolating, so that the direct contact between the Al and the In is prevented.

Two Level System (TLS): is a system which is easy to influence the quantum performance of the chip and exists on the superconducting quantum chip, and is mainly introduced in the process steps, and hydrogen ions and the like of organic matters are main sources of the system.

Referring to fig. 1, a schematic flow chart of an etching-deposition-stripping process according to the present application is shown. As shown in fig. 1, in one implementation, the etch-deposition-stripping process may be performed as follows:

S11, depositing a bottom layer material on the substrate.

S12, coating a first photoresist.

S13, performing exposure processing.

And S14, after development, obtaining an etching area of the bottom layer material.

S15, etching the bottom layer material to form the circuit structure.

S16, stripping photoresist.

S17, coating a second photoresist.

S18, performing exposure processing.

And S19, after development, obtaining a region where the second layer material is deposited.

S110, depositing a second layer of material.

S111, removing photoresist and stripping to obtain a required chip product.

The process of stripping photoresist by desmear may have an effect on the circuitry or substrate of the chip product. For example, there are josephson junctions and other quantum devices on the superconducting quantum chip, these devices are very sensitive to local environments, and the introduction of some ions (such as hydrogen ions commonly found in photoresist organics) or chemical bonds can generate a "Two Level System (TLS)", and these TLS and josephson junctions and other quantum devices produce effects such as coupling, which can significantly reduce the quality factor and other properties of the superconducting quantum chip.

Generally, the fabrication of superconducting quantum chips involves multiple etching-deposition-stripping processes. For example, the processing flow of the three-dimensional superconducting quantum chip is divided into a bottom circuit-UBM layer-junction-welding spot-flip chip, wherein etching and stripping are considered to introduce a great number of photoetching, developing, depositing and stripping processes, repeated spin-coating photoresist and photoresist stripping and cleaning with solution such as isopropanol are considered to continuously accumulate substances such as hydrogen ions and the like on the chip, and the performance of the chip is greatly influenced.

For example, taking a preparation flow of an underlying circuit and a UBM layer in a superconducting quantum chip as an example, the preparation flow includes: depositing material on the substrate, developing by photoresist uniformity to define the position and shape of the UBM layer, depositing material as the UBM layer, stripping by photoresist removal, developing by photoresist uniformity to define a bottom circuit structure, etching to obtain a bottom circuit, and stripping by photoresist removal. The above processes involve two photoresist homogenizing, photoetching, developing, depositing and photoresist removing processes, wherein the plurality of photoresist homogenizing, developing and photoresist removing processes can introduce unavoidable ion-level pollution on the surface of the chip.

Based on the above, the application provides a combination process, which shortens the etching-depositing-stripping three-step process to one step, saves the cost and can improve the chip performance.

Referring to fig. 2, a method flowchart of a chip product manufacturing method according to an exemplary embodiment of the present application is shown. As shown in fig. 2, the method may include the steps of:

in step 201, a first photoresist layer is coated on a first chip product having a first deposition layer to obtain a first photoresist layer covering the first chip product.

Alternatively, material deposition may be performed on the substrate in advance, resulting in the first chip product having the first deposition layer described above.

Optionally, other finished circuit structures may be included in the first chip product in addition to the first deposited layer. For example, the first chip product may further include other circuit structures located under the first deposition layer or outside the area where the first deposition layer is located.

For example, please refer to fig. 3, which illustrates a schematic diagram of a chip product preparation process according to an embodiment of the present application. As shown in part (a) of fig. 3, a first photoresist layer may be first spin coated on a first chip product having a first deposition layer by a spin coater.

Step 202, based on a first photoresist layer, preparing a first circuit structure composed of a deposition material in a first deposition layer.

In the embodiment of the application, after the first circuit structure formed by the deposition material in the first deposition layer is prepared, the first photoresist layer is not directly cleaned, but residual first photoresist is remained.

As shown in part (b) of fig. 3, the first circuit structure composed of the deposition material in the first deposition layer may be prepared by photolithography-development-etching.

Step 203, performing conversion treatment based on the residual first photoresist in the first photoresist layer to obtain a second photoresist layer; the second photoresist layer has a characteristic of being soluble in a developer.

In this embodiment of the present application, the conversion treatment based on the residual first photoresist in the first photoresist layer may refer to preparing the second photoresist layer fused with the first photoresist without removing the first photoresist.

That is, after the conversion treatment is performed based on the residual first photoresist in the first photoresist layer, a new second photoresist layer is present on the first chip product, where the new second photoresist layer includes the residual first photoresist in the original first photoresist layer.

The second photoresist layer has a characteristic of being soluble in a developing solution, which means that the second photoresist layer can be dissolved in the developing solution without being exposed again.

In an embodiment of the present application, the second photoresist layer may cover the first circuit structure in the first chip product and other portions except the first circuit structure.

As shown in part (c) of fig. 3, in the embodiment of the present application, the first photoresist layer that is insoluble in the developing solution and covers only the residual first photoresist of the first circuit structure may be converted into the second photoresist layer that covers the entire first chip product, and the second photoresist layer may be soluble in the developing solution.

A third photoresist layer is prepared over the second photoresist layer, step 204.

As shown in part (d) of fig. 3, a third photoresist layer may be spin coated over the second photoresist layer by a spin coater.

And 205, performing photoetching development processing on the appointed position on the first chip product, and removing the photoresist of the second photoresist layer and the third photoresist layer at the appointed position.

In the embodiment of the application, the photoresist of the second photoresist layer at the designated position and the photoresist of the third photoresist layer at the designated position can be removed by means of photoetching development.

In this embodiment of the present application, since the second photoresist layer has a characteristic of being soluble in a developing solution, during the process of performing photolithography development on the third photoresist layer, the photoresist in the second photoresist layer in the developing region is removed in addition to the photoresist in the third photoresist layer.

As shown in part (e) of fig. 3, the photoresist at the corresponding designated position in the third photoresist layer is removed by exposing and developing the third photoresist layer at the designated position by means of photolithography and developing; meanwhile, since the second photoresist layer is dissolved in the developing solution, the photoresist at the position corresponding to the designated position in the third photoresist layer is also removed in the photolithography developing process.

At step 206, a second deposited layer is prepared at the designated location.

As shown in part (f) of fig. 3, the second deposition layer may be prepared at a designated location by evaporating the first chip product.

And step 207, cleaning the residual photoresist in the second photoresist layer and the third photoresist layer to obtain a second chip product.

After photoresist stripping and cleaning the first chip product with the second deposition layer deposited, a second chip product with a second circuit structure and a second deposition layer can be obtained, as shown in part (g) of fig. 3.

In summary, according to the scheme shown in the embodiment of the present application, after the first circuit structure is prepared by using the photolithography developing method based on the first photoresist layer, the first photoresist layer is not directly cleaned, but is subjected to conversion treatment to obtain a second photoresist layer soluble in a developing solution, and then a third photoresist layer is prepared on the second photoresist layer.

In addition, the scheme disclosed by the embodiment of the application reduces the process steps and improves the yield and the processing preparation efficiency.

Referring to fig. 4, a method flowchart of a chip product manufacturing method according to an exemplary embodiment of the present application is shown. As shown in fig. 4, the method may include the steps of:

in step 401, a first photoresist layer is coated on a first chip product having a first deposition layer to obtain a first photoresist layer covering the first chip product.

The first chip product may be a semi-finished product of a superconducting quantum chip.

Alternatively, the first chip product may be a semi-finished product of a conventional chip.

In this embodiment of the present application, the first deposition layer may be prepared in advance on the first chip product, and then the first photoresist layer may be obtained by spin-coating the first photoresist on the first chip product by using a photoresist homogenizer.

Step 402, based on a first photoresist layer, a first circuit structure is prepared that is comprised of deposited material in a first deposited layer.

In one possible implementation manner, the step of preparing the first circuit structure formed by the deposition material in the first deposition layer based on the first photoresist layer may include:

Performing photoetching development treatment on the position, corresponding to the pattern of the first circuit structure, in the first photoresist layer to remove the first photoresist at the position of the pattern of the first circuit structure;

and etching the position of the pattern of the first circuit structure to obtain the first circuit structure.

In an exemplary scheme of this embodiment of the present application, an area on the first photoresist layer corresponding to the first circuit structure may be exposed by a photolithography machine, then cleaned by a developing solution, to obtain a pattern on the first photoresist layer corresponding to the first circuit structure, and then etched by an etching machine, where, due to the existence of the first photoresist layer, the deposition material on the area on the first photoresist layer corresponding to the pattern area of the first circuit structure (i.e. the area where the first deposition layer is exposed) may be removed, and the deposition material on other portions may not be affected, thereby obtaining the first circuit structure.

And step 403, uniformly mixing the first photoresist and the second photoresist remained in the first photoresist layer to obtain a second photoresist layer.

In this embodiment, after etching the exposed portion of the first deposition layer, the first photoresist layer is not directly removed, but a new photoresist (i.e., the second photoresist) is introduced and uniformly mixed with the remaining first photoresist.

In one possible implementation, the process of uniformly mixing the first photoresist remaining in the first photoresist layer with the second photoresist layer to obtain the second photoresist layer may include:

performing flood exposure treatment on the residual first photoresist in the first photoresist layer;

coating a second photoresist layer over the first photoresist layer;

and uniformly mixing the second photoresist with the first photoresist to obtain a second photoresist layer.

The first photoresist after the flood exposure has the characteristic of being mutually soluble with the second photoresist, so that the second photoresist and the first photoresist can be mutually soluble after the second photoresist is coated on the first photoresist after the flood exposure, and the second photoresist is obtained.

In one possible implementation, the step of uniformly mixing the second photoresist with the first photoresist to obtain the second photoresist layer may include:

and uniformly mixing the second photoresist with the first photoresist in a physical mode to obtain a second photoresist layer.

In the embodiment of the application, in order to avoid affecting the photoresist or the chip product in the process of uniformly mixing the second photoresist with the first photoresist, the second photoresist may be uniformly mixed with the first photoresist by a physical manner.

rotating the first chip product;

and standing the first chip product.

In the embodiment of the application, the first chip product after the second photoresist is coated may be rotated, for example, rotated at a high speed, to uniformly mix the second photoresist with the first photoresist.

Alternatively, the first chip product after the second photoresist is coated may be left for a period of time to wait for the second photoresist to be uniformly mixed with the first photoresist, and then the next operation is performed.

Still alternatively, the first chip product after the second photoresist may be rotated, and then the first chip product may be left to stand for a period of time to wait for the second photoresist to be uniformly mixed with the first photoresist.

Or, the first chip product after the second photoresist is first kept stand for a period of time, and then the first chip product is rotated, so that the second photoresist and the first photoresist are uniformly mixed.

In one possible implementation manner, the manner of the flood exposure processing includes:

ultraviolet exposure or laser direct writing.

In one possible implementation, the second photoresist is a lift-off photoresist LOR.

A third photoresist layer is prepared over the second photoresist layer, step 404.

In this embodiment, the third photoresist layer may be coated (e.g., spin coated) on the second photoresist layer by a photoresist leveler.

In one possible implementation, the second photoresist layer may also be baked at a soft bake temperature before the third photoresist layer is prepared over the second photoresist layer.

In this embodiment of the present application, after the first photoresist and the second photoresist are uniformly mixed to obtain the second photoresist layer, in order to ensure the supportability of the second photoresist layer, soft baking treatment may be performed on the second photoresist layer.

In one possible implementation, the soft bake temperature may be 80 to 200 degrees celsius.

In one possible implementation manner, after the third photoresist layer is prepared, the third photoresist layer may be further subjected to a film fixing process, for example, a film fixing process is performed on the third photoresist layer by using a thermal baking manner.

And 405, performing photoetching development processing on the appointed position on the first chip product, and removing the photoresist of the second photoresist layer and the third photoresist layer at the appointed position.

In one possible implementation, the development time for the photolithographic development process is 60 to 120 seconds for the specified location on the first chip product.

After the specified position is subjected to photoetching development, the photoresist in the third photoresist layer corresponding to the photoetching pattern area is soluble in the developing solution, and meanwhile, since the second photoresist layer is also soluble in the developing solution, the third photoresist in the photoetching pattern area and the mixed photoresist in the second photoresist layer are dissolved in the developing solution during photoetching development, so that a substrate below the second photoresist layer or an existing circuit structure (such as the second circuit structure) is exposed.

Wherein the second photoresist layer is entirely soluble in the developing solution unlike the partial region of the third photoresist layer, so that the more the photoresist is dissolved by the developing solution, the less the photoresist is dissolved by the developing solution, at the position of the lower layer, in the second photoresist layer, when the developing is performed.

The photoresist of the dissolved part in the second photoresist layer can be controlled by the development time, and the longer the development time is, the more the photoresist is dissolved in the second photoresist layer, otherwise, the shorter the development time is, the less the photoresist is dissolved in the second photoresist layer.

Alternatively, in order to match the pattern of the subsequent deposited material run with the pattern on the third photoresist layer, a suitable development time may be set so that the third photoresist layer and the remainder of the second photoresist layer may constitute an undercut structure.

Alternatively, the above development time may be set to 60 to 120 seconds.

Step 406, a second deposition layer is prepared at the designated location.

In the embodiment of the application, the deposition material can be evaporated on the first chip product by an evaporator, so as to obtain the second deposition layer deposited on the substrate or the existing circuit structure at the designated position. The deposition material of the second deposition layer may be the same as or different from the deposition material of the first deposition layer.

And step 407, cleaning the residual photoresist in the second photoresist layer and the third photoresist layer to obtain a second chip product.

In an embodiment of the present application, the second chip product may be a superconducting quantum chip; alternatively, the second chip product may be a semifinished product of the superconducting quantum chip.

For example, taking flip-chip superconducting quantum chip preparation as an example, the scheme shown in the embodiment of the application can be used for replacing any one or more etching-depositing-stripping processes in the superconducting quantum chip preparation process.

For example, please refer to fig. 5, which illustrates a flowchart of a chip product preparation process according to an embodiment of the present application. As shown in fig. 5, the above-mentioned chip product preparation process may include the following steps:

and S51, depositing a bottom layer (to be etched) material on the cleaned substrate.

In this step, the above-mentioned material deposition may be physical film deposition or chemical film deposition.

And S52, coating a first photoresist on the bottom layer material and performing first baking.

In this step, the first photoresist layer is a positive photoresist, and the first baking temperature is a soft baking temperature of the first photoresist layer, for example, may be 80 to 200 ℃.

S53, performing first exposure on the first photoresist to define a pattern of the etched structure.

In this step, the above exposure may be ultraviolet exposure or laser direct writing.

And S54, performing first development on the product obtained in the step S53 to obtain a product with a photoresist structure.

In this step, the developing solution used for the development is the developing solution of the first photoresist.

And S55, etching the product obtained in the step S54 to form a circuit structure on the bottom layer material.

In this step, the etching may be wet etching or dry etching.

S56, performing flood exposure treatment on the residual first photoresist, and changing the solubility of the photoresist in the developing solution.

In this step, the above-mentioned flood exposure may be ultraviolet exposure or laser direct writing.

And S57, coating a second photoresist on the product obtained in the step S56, and utilizing the solubility of the second photoresist solvent to the first photoresist after flood exposure to enable the second photoresist solvent and the first photoresist to generate mutual dissolution reaction.

In this step, the second photoresist is a photoresist that is not photosensitive, and may be, for example, a LOR-releasing photoresist.

And S58, performing a second baking after the first photoresist and the second photoresist are fully and uniformly mutually dissolved through a physical method.

In this step, the above-mentioned physical method may be high-speed rotation or standing; the second baking temperature is a soft baking temperature of the second photoresist, and may be, for example, a temperature in the range of 80 to 200 ℃.

And S59, coating a third photoresist on the product obtained in the S58, and performing third baking.

In this step, the third photoresist may be a positive photoresist or a negative photoresist, and the third baking temperature may be a soft baking temperature of the third photoresist, for example, a temperature in the range of 80 to 200 ℃.

S510, carrying out exposure treatment on the product obtained in S59, and defining the position and shape of the material to be deposited.

In this step, the exposure may be ultraviolet exposure or laser direct writing.

S511, developing the product, dissolving the third photoresist exposure area, enabling the first and second miscible photoresists to react with the developing solution, and forming undercut structures with different sizes by controlling the developing time.

In this step, the developing solution is the developing solution of the third photoresist, and LOR can be dissolved at the same time; the size of the undercut structure may be controlled by adjusting the development time, for example, 60 to 120 seconds may be selected.

S512, performing fourth baking on the product obtained in S511 to finish the hardening treatment, and then performing material deposition.

In this step, the fourth baking temperature is a hardening temperature of the third photoresist, for example, the fourth baking temperature may be in the range of 90 to 120 ℃, and the time may be selected to be 60 to 120 seconds.

S513, stripping photoresist from the product obtained in the S512, and stripping the first photoresist, the second photoresist and the third photoresist at one time to obtain a final chip product.

In this step, the photoresist stripping process may use an organic solution as a photoresist stripping solution, and may be, for example, a solution of methylpyrrolidone, isopropyl alcohol, acetone, or the like.

The scheme has the following characteristics:

1) The prolonged flood exposure thoroughly converts the first photoresist into a sacrificial layer. The feature is that the first photoresist is exposed for a long time, so that after the photoresist is fully reflected by light, the photoresist is thoroughly converted into a sacrificial layer which is soluble in developing solution and is easy to be mutually dissolved with solvents of other photoresists.

2) And coating a second photoresist on the fully exposed first photoresist, and changing the first photoresist and the second photoresist into a layer of photoresist by a physical method. The feature is that on the basis of the full exposure of the first photoresist, the second photoresist is directly coated by utilizing the property that the first photoresist is easily dissolved in photoresist solvent, so that the first photoresist and the second photoresist are mixed to become a layer of photoresist to serve as a sacrificial layer. The second photoresist is usually a stripping photoresist such as LOR, and is characterized in that the second photoresist can be dissolved in a developing solution without reacting with light, and the solvent of the second photoresist is not mutually dissolved with the third photoresist.

3) Based on the existing photoresist, the photoresist structure containing undercut can be formed on the sample without introducing a photoresist removing process. On samples of existing photoresist structures, conventional practice typically requires removal of the photoresist, spin coating of the LOR, and spin coating of the photoresist to produce undercut photoresist structures for lift-off, which introduces additional opportunities for primary organic solution to contact the sample. The method has the characteristics that the step of process can be reduced to realize the processing of high-performance (superconducting quantum) chip samples. For example, please refer to fig. 6 and 7, which illustrate schematic views of undercut structures according to embodiments of the present application. As shown in fig. 6 and fig. 7, by controlling a reasonable development time when the third photoresist layer is subjected to photolithography development according to the scheme in the embodiment of the present application, an undercut structure may be formed in the development area.

4) The chip produced by the scheme can be a superconducting quantum chip.

By the scheme shown in the embodiment of the application, the following effects can be achieved:

1) The LOR and the photoresist fully reacted with the light are dissolved into a layer by utilizing the solubility change of the photoresist after the reaction with the light, and an undercut structure is formed by exposure and development, so that stripping after material deposition is facilitated;

2) The pollution of ions, chemical dangling bonds and the like to the chip in the process steps is reduced, the density of a two-energy-level system is reduced, and the performance of the chip (quanta) is improved;

3) The process steps are reduced, and the efficiency and yield of chip preparation are improved.

FIG. 8 illustrates a schematic diagram of a chip-product manufacturing system, which may be implemented as a production line device, as illustrated in an exemplary embodiment of the present application; as shown in fig. 8, the chip product preparation system includes: a coater 801, a photolithography machine 802, an etcher 803, an evaporation machine 804, and a cleaning machine 805;

the glue spreader 801 is configured to apply a first photoresist on a first chip product having a first deposition layer, to obtain a first photoresist layer covering the first chip product;

the lithography machine 802 and the etching machine 803 are used for preparing a first circuit structure formed by deposition materials in the first deposition layer based on the first photoresist layer;

the coater 801 and the photo-etching machine 802 are configured to perform a conversion process based on the first photoresist remaining in the first photoresist layer, so as to obtain a second photoresist layer; the second photoresist layer has a characteristic of being soluble in a developing solution;

the coater 801 is configured to prepare a third photoresist layer over the second photoresist layer;

The photo-etching machine 802 is configured to perform photo-etching development on a specified position on the first chip product, and remove the photoresist of the second photoresist layer and the third photoresist layer at the specified position;

the evaporator 804 is used for preparing a second deposition layer at the designated position;

the cleaning machine 805 is configured to clean the residual photoresist in the second photoresist layer and the third photoresist layer to obtain a second chip product.

the coater 801 is used for coating the second photoresist on the first photoresist layer; and uniformly mixing the second photoresist with the first photoresist to obtain the second photoresist layer.

In a possible implementation manner, the glue spreader 801 is configured to physically mix the second photoresist with the first photoresist uniformly to obtain the second photoresist layer.

rotating the first chip product;

and, standing the first chip product.

ultraviolet exposure or laser direct writing.

In one possible implementation, the coater 801 is further configured to bake the second photoresist layer at a soft bake temperature prior to preparing a third photoresist layer over the second photoresist layer.

In a possible implementation manner, the lithography machine 802 is configured to perform a lithography development process on a position in the first photoresist layer corresponding to the pattern of the first circuit structure, so as to remove the first photoresist at the position of the pattern of the first circuit structure;

The etcher 803 is configured to perform etching processing on the position of the pattern of the first circuit structure, so as to obtain the first circuit structure.

Optionally, the system further includes a control chip, which may be electrically connected to at least one of the coater 801, the photolithography machine 802, the etcher 803, the evaporation machine 804, and the cleaning machine 805, respectively, for controlling the coater 801, the photolithography machine 802, the etcher 803, the evaporation machine 804, and the cleaning machine 805, and so on.

Optionally, the production line apparatus further includes a power supply for supplying power to the electrical devices such as the control chip, the coater 801, the photolithography machine 802, the etcher 803, the evaporation machine 804, and the cleaning machine 805.

Alternatively, the machines may be spatially coupled by a conveyor or the movement of the preparation between the machines may be accomplished based on a robotic arm.

Optionally, the production line device further comprises a memory, the memory being operable to store at least one computer instruction, the processor executing the at least one computer instruction to cause the production line device to perform the qubit assembly preparation method described above.

Please refer to fig. 9, which illustrates a schematic diagram of a scenario of application of the solution provided in an embodiment of the present application. As shown in fig. 9, the application scenario may be a superconducting quantum computing platform, and the application scenario includes: a quantum computing device 91, a dilution refrigerator 92, a control device 93 and a computer 94.

Quantum computing device 91 is a circuit that acts on physical qubits, and quantum computing device 91 may be implemented as a quantum chip, such as a superconducting quantum chip at about absolute zero. The quantum chip can be prepared by the scheme shown in the embodiment of the application. Dilution refrigerator 92 is used to provide an absolute zero environment for the superconducting quantum chip.

The control device 93 is used for controlling the quantum computing device 91, and the computer 94 is used for controlling the control device 93. For example, the written quantum program is compiled into instructions by software in the computer 94 and sent to the control device 93 (e.g., an electronic/microwave control system), and the control device 93 converts the instructions into electronic/microwave control signals and inputs the electronic/microwave control signals to the dilution refrigerator 92 to control superconducting quantum bits at a temperature of less than 10 mK. The read process is reversed and the read waveform is delivered to quantum computing device 91.

Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.

It is to be understood that the present application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims

1. A method of manufacturing a chip product, the method comprising:

preparing a third photoresist layer over the second photoresist layer;

preparing a second deposition layer at the designated location;

2. The method of claim 1, wherein the converting based on the first photoresist remaining in the first photoresist layer to obtain a second photoresist layer comprises:

and uniformly mixing the first photoresist and the second photoresist which are remained in the first photoresist layer to obtain the second photoresist layer.

3. The method of claim 2, wherein the uniformly mixing the first photoresist remaining in the first photoresist layer with a second photoresist to obtain the second photoresist layer comprises:

performing flood exposure treatment on the first photoresist remained in the first photoresist layer;

coating the second photoresist layer over the first photoresist layer;

and uniformly mixing the second photoresist with the first photoresist to obtain the second photoresist layer.

4. The method of claim 3, wherein said uniformly mixing said second photoresist with said first photoresist to obtain said second photoresist layer comprises:

and uniformly mixing the second photoresist with the first photoresist in a physical way to obtain the second photoresist layer.

5. The method of claim 4, wherein the physical means comprises at least one of:

rotating the first chip product;

and, standing the first chip product.

6. A method according to claim 3, wherein the flood exposure process is performed by:

ultraviolet exposure or laser direct writing.

7. The method of any of claims 2 to 6, wherein the second photoresist is a non-photosensitive photoresist.

8. The method of claim 7, wherein the second photoresist is a lift-off photoresist.

9. The method of any of claims 2 to 6, wherein prior to preparing a third photoresist layer over the second photoresist layer, the method further comprises:

and baking the second photoresist layer at a soft baking temperature.

10. The method of claim 9, wherein the soft bake temperature is 80 to 200 degrees celsius.

11. The method of claim 1, wherein the developing time for performing a photolithographic developing process on the specified location on the first chip product is 60 to 120 seconds.

12. The method of claim 1, wherein preparing a first circuit structure comprised of deposited material in the first deposited layer based on the first photoresist layer, comprises:

13. The method of claim 1, wherein the second chip product is a superconducting quantum chip; or the second chip product is a semi-finished product of the superconducting quantum chip.

14. A chip product preparation system, the system comprising: a gumming machine, a photoetching machine, an etching machine, an evaporation machine and a cleaning machine;

15. The system of claim 14, wherein the coater and the lithography machine are configured to uniformly mix the first photoresist remaining in the first photoresist layer with a second photoresist to obtain the second photoresist layer.