JPH10223501A - Method of forming resist pattern and manufacture of semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique for forming a highly accurate pattern on a semiconductor wafer, using a chemical amplification type reactive resist. SOLUTION: Immediately after exposing a chemical amplification type reactive resist 2 applied to a semiconductor wafer 1, the wafer is left in a vacuum so as to have a residual resist solvent 9 diffused which is contained in this resist 2 in the thickness direction of the resist 2. The wafer 1 is baked at a low temp. of 90 deg.C or less to minimize the lateral diffusion of a catalyst 4, thereby reacting the catalyst 4. This improves the resolution of the reactive type resist 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to an exposure technique,
In particular, the present invention relates to a technique effective when applied to a photolithography technique for forming a predetermined resist pattern on a semiconductor wafer.

[0002]

2. Description of the Related Art In a photolithography process, layout information from a design is transferred to a resist applied on a semiconductor wafer through a photomask (or reticle), and a resist pattern is formed through a development process.
The film to be etched formed on the semiconductor wafer is processed using the resist pattern as a mask.

Usually, a negative resist or a positive resist is used as a resist material, but practical resist materials satisfying high sensitivity, high resolution and high dry etching resistance are scarce. For this reason, for example, a method of creating a resist pattern by using an additional process together, such as a multilayer resist method, has been developed.
There are problems such as a decrease in throughput and investment in dedicated equipment.

Therefore, development of a resist material utilizing a new chemical reaction is being promoted. Among them, a chemically amplified resist material utilizing a catalytic reaction (hereinafter referred to as a chemically amplified reaction resist) has the above required performance. Satisfied,
Since it is possible to realize a single-layer resist process, it is regarded as a promising new resist material.

For the chemically amplified reaction resist, see, for example, “Recent Technology Course” 199, published by Realize.
April 3rd, p8.

[0006]

However, the present inventors have found the following problems in developing the chemically amplified reaction resist.

That is, conventionally, a catalyst such as acid (H ⁺ ) is generated in a chemically amplified reaction resist by exposure to form a latent image of a resist pattern, and then a bake for reacting the catalyst is performed on a semiconductor wafer. It has been subjected to.

When exposure is performed using a single wavelength with a reduction projection exposure apparatus, a standing wave is generated in a chemically amplified reaction resist. Since this standing wave can be mitigated by diffusing the catalyst in the thickness direction of the chemically amplified reaction resist, the standing wave is at least 90 ° C. for diffusing the catalyst in the thickness direction of the chemically amplified reaction resist after exposure. Must be applied to the semiconductor wafer. For this reason, the temperature of the bake applied to the semiconductor wafer to react the catalyst is 90
１１０110 ° C.

However, as shown in FIG. 5, since the thermal diffusion of the catalyst 4 is isotropic, when the above-described baking is performed on the semiconductor wafer 1, the baking is performed not only in the thickness direction of the chemically amplified reaction resist 2 but also in the lateral direction. Also, the diffusion of the catalyst 4 progresses, and the catalyst 4 diffuses to the unexposed region.
Resolution is degraded.

An object of the present invention is to provide a technique capable of forming a highly accurate resist pattern on a semiconductor wafer using a chemically amplified reaction resist.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0012]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, in the method of forming a resist pattern according to the present invention, a chemically amplified reaction resist is applied to the surface of a film to be etched on a semiconductor wafer, and then radiation is irradiated to the chemically amplified reaction resist via a photomask. A catalyst is generated thereby to form a latent image of the resist pattern, and then the semiconductor wafer is left in a vacuum to volatilize the remaining resist solvent in the chemically amplified reaction resist and to remove the catalyst from the chemically amplified reaction resist. It is diffused anisotropically in the thickness direction. Subsequently, the semiconductor wafer is subjected to a low-temperature bake to react the catalyst in the chemically amplified reaction resist, and then the semiconductor wafer is subjected to a development process.

According to the above means, the catalyst can be anisotropically diffused in the thickness direction of the chemically amplified reaction resist using the residual resist solvent as a carrier by leaving the semiconductor wafer in a vacuum. Thereafter, a bake applied to the semiconductor wafer to react the catalyst can be performed at a low temperature that can minimize isotropic thermal diffusion of the catalyst. Therefore, it is possible to suppress the lateral diffusion of the catalyst and obtain a chemically amplified reaction resist having high resolution.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In all the drawings for describing the embodiments, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

A method for forming a resist pattern according to an embodiment of the present invention will be described with reference to steps 100 to 110 shown in FIG. 1 and a cross-sectional view of main parts of a semiconductor substrate shown in FIG.

First, a foreign matter on the front surface or the back surface of the semiconductor wafer 1 is removed, and a resist pre-treatment is performed to enhance the adhesion of the developed resist pattern to the semiconductor wafer 1 (step 100).

Next, the chemically amplified reaction resist 2 is uniformly applied on the semiconductor wafer 1 on which the application pretreatment has been completed by a spin coating method (Step 101).
In this method, the semiconductor wafer 1 is placed on a spin chuck, and the chemically amplified reaction resist 2 is scattered by centrifugal force to form the chemically amplified reaction resist 2 on the surface of the semiconductor wafer 1. In order to increase the amount of the resist solvent in the resist 2, a low-viscosity chemically amplified reaction resist 2 of 5 to 15 mpa · s is applied on the semiconductor wafer 1 by low-speed rotation of 2000 rpm or less.

Next, in order to volatilize the resist solvent contained in the chemically amplified reaction resist 2 immediately after the application and stabilize the photochemical reaction at the time of exposure, for example, the semiconductor wafer 1 is prebaked using a hot plate. (Step 102). Even if prebaking is performed, about 10% of the resist solvent remains in the chemically amplified reaction resist 2.

Next, as shown in FIG. 2A, after setting the semiconductor wafer 1 together with a predetermined photomask 3 in a reduction projection exposure apparatus, accurate positioning is performed, and then radiation, for example, ultraviolet light, The chemically amplified reaction resist 2 is exposed by irradiating a mask pattern by irradiating a line or a laser beam for a certain time (step 103), and the exposed region of the chemically amplified reaction resist 2 is exposed to a catalyst 4, for example, acid (H ⁺ ). Generate.

Next, immediately after the exposure, the semiconductor wafer 1 is transferred onto the stage 7 in the chamber 6 of the vacuum apparatus 5 shown in FIG. By leaving the semiconductor wafer 1,
All the remaining resist solvent 9 contained in the chemically amplified reaction resist 2 is volatilized (step 104). At this time, FIG.
As shown in (b), the residual resist solvent 9 volatilized in the thickness direction of the chemically amplified reaction resist 2 is used as a carrier.
The catalyst 4 in the chemically amplified reaction resist 2 generated by the exposure can be diffused in the thickness direction of the chemically amplified reaction resist 2. Thereafter, the semiconductor wafer 1 is transferred onto a stage 11 of a baking apparatus 10 shown in FIG. 3B, and a low-temperature bake of 90 ° C. or less is performed on the semiconductor wafer 1 by heating a heater 12 provided on the stage 11. The catalyst in the chemically amplified reaction resist 2 is reacted (step 105).

Next, a developing solution is dropped on the surface of the semiconductor wafer 1 to build up using surface tension, and after a developing process for a predetermined time, rinsing with pure water and rotary drying are continuously performed ( Step 106). Thereby, a resist pattern is formed on the semiconductor wafer 1.

Subsequently, the semiconductor wafer 1 is baked at about 120 ° C. and dried completely, and the adhesion of the chemically amplified reaction resist 2 to the semiconductor wafer 1 is improved (Step 107).

Next, the external appearance of the semiconductor wafer 1 is inspected with a metallographic microscope (Step 108), and furthermore, the dimension measurement and the alignment inspection of the resist pattern formed on the chemically amplified reaction resist 2 are performed (Steps 109 and 110). ).

Next, a brief description will be given of a photo-etching step using a resist pattern provided on the semiconductor wafer 1 by the above-described forming method. The photoetching process is classified into a photolithography process for forming a resist pattern on a semiconductor wafer, an etching process for processing a film to be etched using the resist pattern, and a resist removing process for removing the resist pattern.

First, after a film 13 to be etched is deposited on the semiconductor wafer 1, a resist pattern is formed on the film 13 to be etched (photolithography step). Here, the method for forming a resist pattern according to the present invention is used.

Next, using the resist pattern as a mask, the film 13 to be etched is processed by, for example, a dry etching method (etching step).

Next, after inspecting the external appearance of the semiconductor wafer 1, the unnecessary resist pattern is peeled off from the semiconductor wafer 1 by an asher treatment method in which the resist pattern is ashed by oxidizing plasma. Thereafter, a cleaning process is performed to remove metal ions and minute foreign matters on the surface of the semiconductor wafer 1 that cannot be completely removed by the asher process attached in the etching process (resist removing process).

Finally, the appearance of the semiconductor wafer 1 is inspected with a metallographic microscope to complete the photo-etching step of the semiconductor wafer 1 in order to detect the appearance defect early and to prevent the contaminated semiconductor wafer 1 from being sent to the next step. .

As described above, according to the present embodiment, after exposure, the semiconductor wafer 1 is left in a vacuum to allow the catalyst 4 to react with the chemical amplification reaction using the residual resist solvent 9 in the chemically amplified reaction resist 2 as a carrier. After the resist 2 is diffused in the thickness direction, the catalyst 4 is reacted by subjecting the semiconductor wafer 1 to a low-temperature bake, so that the thermal diffusion of the catalyst 4 in the lateral direction can be minimized. The resolution of the reaction resist 2 can be improved. Further, by volatilizing the residual resist solvent 9 in the chemically amplified reaction resist 2 immediately after the exposure, it is possible to suppress a change in the resist dimension due to the diffusion of the catalyst 4 depending on the standing time after the exposure.

In this embodiment, after exposure, the semiconductor wafer 1 is left in a vacuum, and then the semiconductor wafer 1 is baked at a low temperature to react the catalyst 4.
A low-temperature bake may be applied to the semiconductor wafer 1 in vacuum immediately after exposure using the vacuum bake apparatus 14 shown in FIG.
In this case, the same effect can be obtained.

That is, immediately after the exposure, the stage 1 provided with the heater 12 in the chamber 6 of the vacuum baking device 14
The semiconductor wafer 1 is transferred onto the substrate 1 and evacuated by a vacuum pump 8 to perform low-temperature baking in a chamber 6 maintained in a vacuum. At this time, simultaneously with the reaction of the catalyst 4, the catalyst 4 is diffused in the thickness direction of the chemically amplified reaction resist 2 by using the residual resist solvent 9 in the chemically amplified reaction resist 2 as a carrier. Thermal diffusion can be minimized, and the resolution of the chemically amplified reaction resist 2 can be improved.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

[0035]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the present invention, the resolution of a chemically amplified reaction resist formed on a semiconductor wafer can be increased, so that a highly accurate resist pattern can be formed.

[Brief description of the drawings]

FIG. 1 is a process diagram illustrating a method for forming a resist pattern according to an embodiment of the present invention.

FIG. 2A is a cross-sectional view of a main part of a semiconductor substrate for explaining generation of a catalyst in a chemically amplified reaction resist, and FIG.

3A is a schematic cross-sectional view of a main part of a vacuum device, and FIG. 3B is a schematic diagram of a bake device. FIG.

FIG. 4 is a sectional view of a main part showing a schematic view of a vacuum baking apparatus.

FIG. 5 is a cross-sectional view of a main part of a semiconductor substrate for explaining diffusion of a catalyst in a conventional chemically amplified reaction resist.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 2 Chemically amplified reaction resist 3 Photomask 4 Catalyst 5 Vacuum device 6 Chamber 7 Stage 8 Vacuum pump 9 Residual resist solvent 10 Bake device 11 Stage 12 Heater 13 Film to be etched 14 Vacuum bake device 15 Mask substrate 16 Light shielding unit

Claims (8)

[Claims] A step of applying a chemically amplified reaction resist on a surface of a film to be etched on a semiconductor wafer; and irradiating the chemically amplified reaction resist with radiation through a photomask to generate a catalyst. Forming a latent image of a pattern on the chemically amplified reaction resist, and volatilizing a residual resist solvent in the chemically amplified reaction resist and anisotropically moving the catalyst in a thickness direction of the chemically amplified reaction resist. Diffusing, and reacting the catalyst in the chemically amplified reaction resist,
Performing a development process on the semiconductor wafer. 2. The method of forming a resist pattern according to claim 1, wherein the semiconductor wafer is left in a vacuum to volatilize a remaining resist solvent in the chemically amplified reaction resist and to remove the catalyst. A method for forming a resist pattern, characterized in that the resist is diffused anisotropically in the thickness direction of a chemically amplified reaction resist. 3. The method of forming a resist pattern according to claim 1, wherein said catalyst in said chemically amplified reaction resist is reacted by subjecting said semiconductor wafer to a low-temperature bake. Formation method. 4. The method of forming a resist pattern according to claim 1, wherein the semiconductor wafer is subjected to a low-temperature bake in a vacuum to volatilize a residual resist solvent in the chemically amplified reaction resist and to form the catalyst. Is anisotropically diffused in the thickness direction of the chemically amplified reaction resist,
A method for forming a resist pattern, comprising simultaneously reacting the catalyst in the chemically amplified reaction resist. 5. The method for forming a resist pattern according to claim 3, wherein the temperature of the low-temperature bake is 90 ° C.
A method for forming a resist pattern, comprising: 6. The method for forming a resist pattern according to claim 1, wherein said chemically amplified reaction resist has an initial viscosity of 5 to 15 mpa · s and a rotation speed of 2,000 rpm.
A method of forming a resist pattern, wherein the chemically amplified reaction resist is applied to the surface of the film to be etched on the semiconductor wafer by the following spin coating method. 7. The method for forming a resist pattern according to claim 1, wherein said radiation is an ultraviolet ray, an electron beam or a laser beam. 8. A step of applying a chemically amplified reaction resist on the surface of a film to be etched on a semiconductor wafer, and irradiating the chemically amplified reaction resist with radiation through a photomask to generate a catalyst, Forming a latent image of a pattern on the chemically amplified reaction resist, and volatilizing a residual resist solvent in the chemically amplified reaction resist and anisotropically moving the catalyst in a thickness direction of the chemically amplified reaction resist. Diffusing, and reacting the catalyst in the chemically amplified reaction resist,
A method for manufacturing a semiconductor integrated circuit device, comprising processing the film to be etched on the semiconductor wafer using a resist pattern formed by the step of performing a development process on the semiconductor wafer as a mask.